phb 55n03lta logic level fet

PHP/PHB/PHD55N03LTATrenchMOS™ Logic Level FETRev. 04 — 4 September 2002 Product data

1. Description

N-channel logic level field-effect power transistor in a plastic package usingTrenchMOS™ technology.

Product availability:

PHP55N03LTA in a SOT78 (TO-220AB)

PHB55N03LTA in a SOT404 (D2-PAK)

PHD55N03LTA in a SOT428 (D-PAK).

2. Features

Low on-state resistance

Fast switching.

3. Applications

Computer motherboard high frequency DC to DC converters.

4. Pinning information

[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.

Table 1: Pinning - SOT78, SOT404, SOT428 simplified outlines and symbol

Pin Description Simplified outline Symbol

1 gate (g)

SOT78 (TO-220AB) SOT404 (D2-PAK) SOT428 (D-PAK)

2 drain (d) [1]

3 source (s)

mb mounting base,connected to drain (d)

MBK1061 2

mb

3

1 3

2

MBK116

mb

MBK091Top view

1 3

mb

2 s

d

g

MBB076

Philips Semiconductors PHP/PHB/PHD55N03LTATrenchMOS™ Logic Level FET

5. Quick reference data

6. Limiting values

Table 2: Quick reference data

Symbol Parameter Conditions Typ Max Unit

VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 175 °C - 25 V

ID drain current (DC) Tmb = 25 °C; VGS = 5 V - 55 A

Ptot total power dissipation Tmb = 25 °C - 85 W

Tj junction temperature - 175 °C

RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C 11 14 mΩ

VGS = 5 V; ID = 25 A; Tj = 25 °C 15 18 mΩ

Table 3: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 175 °C - 25 V

VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 25 V

ID drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 - 55 A

Tmb = 100 °C; VGS = 5 V; Figure 2 - 38 A

VGS gate-source voltage - ±20 V

IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 220 A

Ptot total power dissipation Tmb = 25 °C; Figure 1 - 85 W

Tstg storage temperature −55 +175 °C

Tj junction temperature −55 +175 °C

Source-drain diode

IS source (diode forward) current (DC) Tmb = 25 °C - 55 A

ISM peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs - 220 A

Avalanche ruggedness

EDS(AL)S non-repetitive drain-sourceavalanche energy

unclamped inductive load; ID = 25 A;tp = 0.1 ms; VDD = 15 V; RGS = 50 Ω;VGS = 5V; starting Tj = 25 °C

- 60 mJ

Product data Rev. 04 — 4 September 2002 2 of 14

9397 750 10143 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.


Fig 1. Normalized total power dissipation as afunction of mounting base temperature.

Fig 2. Normalized continuous drain current as afunction of mounting base temperature.

Tmb = 25 °C; IDM is single pulse.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03aa16

0

40

80

120

0 50 100 150 200Tmb (°C)

Pder(%)

03aa24

0

40

80

120

0 50 100 150 200Tmb (°C)

Ider(%)

Pder

Ptot

Ptot 25 C°( )

---------------------- 100%×= I der

I D

ID 25 C°( )

------------------- 100%×=

03ae64

1

10

102

103

1 10 102VDS (V)

ID(A)

DC

100 ms

10 ms

Limit RDSon = VDS / ID

1 ms

tp = 10 µs

100 µs




7. Thermal characteristics

7.1 Transient thermal impedance

Table 4: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to mounting base Figure 4 - - 1.75 K/W

Rth(j-a) thermal resistance from junction to ambient

SOT78 vertical in still air - 60 - K/W

SOT428 SOT428 minimum footprint;mounted on a PCB

- 75 - K/W

SOT404 and SOT428 SOT404 minimum footprint;mounted on a PCB

- 50 - K/W

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

03ae63

10-2

10-1

1

10

10-5 10-4 10-3 10-2 10-1 1tp (s)

Zth(j-mb)(K/W)

single pulse

δ = 0.5

0.2

0.1

0.05

0.02

tp

tp

T

P

t

Tδ =




8. Characteristics

Table 5: CharacteristicsTj = 25 °C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V

Tj = 25 °C 25 - - V

Tj = −55 °C 22 - - V

VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9

Tj = 25 °C 1 1.5 2 V

Tj = 175 °C 0.5 - - V

Tj = −55 °C - - 2.3 V

IDSS drain-source leakage current VDS = 25 V; VGS = 0 V

Tj = 25 °C - 0.05 10 µA

Tj = 175 °C - - 500 µA

IGSS gate-source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA

RDSon drain-source on-state resistance VGS = 5 V; ID = 25 A; Figure 7 and 8

Tj = 25 °C - 15 18 mΩ

Tj = 175 °C - 25.5 30.6 mΩ

VGS = 10 V; ID = 25 A

Tj = 25 °C - 11 14 mΩ

Dynamic characteristics

gfs forward transconductance VDS = 25 V; ID = 25 A - 32 - S

Qg(tot) total gate charge ID = 55 A; VDD = 15 V; VGS = 5 V; Figure 13 - 20 - nC

Qgs gate-source charge - 8 - nC

Qgd gate-drain (Miller) charge - 7 - nC

Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 - 950 - pF

Coss output capacitance - 340 - pF

Crss reverse transfer capacitance - 230 - pF

td(on) turn-on delay time VDD = 15 V; ID = 55 A; VGS = 10 V; RG = 5 Ω - 8 15 ns

tr rise time - 45 80 ns

td(off) turn-off delay time - 45 80 ns

tf fall time - 40 60 ns

Source-drain diode

VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 - 0.95 1.2 V

IS = 55 A; VGS = 0 V - 1.2 - V




Tj = 25 °C Tj = 25 °C and 175 °C; VDS > ID x RDSon

Fig 5. Output characteristics: drain current as afunction of drain-source voltage; typical values.

Fig 6. Transfer characteristics: drain current as afunction of gate-source voltage; typical values.

Tj = 25 °C

Fig 7. Drain-source on-state resistance as a functionof drain current; typical values.

Fig 8. Normalized drain-source on-state resistancefactor as a function of junction temperature.

03ae65

0

20

40

60

0 0.5 1 1.5 2VDS (V)

ID(A)

3 V

5 VTj = 25 °C

VGS = 2.5 V

10 V

3.5 V

4 V4.5 V

03ae67

0

20

40

60

0 1 2 3 4 5VGS (V)

ID(A)

VDS > ID x RDSon

Tj = 25 °C 175 °C

03ae66

0

0.01

0.02

0.03

0 20 40 60ID (A)

RDSon(Ω)

4.5 V

VGS = 4 VTj = 25 °C

5V

10 V

03ad57

0

0.5

1

1.5

2

-60 0 60 120 180Tj (°C)

a

aRDSon

RDSon 25 C°( )----------------------------=




ID = 1 mA; VDS = VGS Tj = 25 °C; VDS = 5 V

Fig 9. Gate-source threshold voltage as a function ofjunction temperature.

Fig 10. Sub-threshold drain current as a function ofgate-source voltage.

VGS = 0 V; f = 1 MHz

Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.

03aa33

0

0.5

1

1.5

2

2.5

-60 0 60 120 180Tj (°C)

VGS(th)(V)

max

typ

min

03aa36

10-6

10-5

10-4

10-3

10-2

10-1

0 1 2 3VGS (V)

ID(A)

maxtypmin

03ae70

102

103

104

10-1 1 10 102VDS (V)

C(pF)

Ciss

Coss

Crss




Tj = 25 °C and 175 °C; VGS = 0 V ID = 55 A; VDD = 15 V

Fig 12. Source (diode forward) current as a function ofsource-drain (diode forward) voltage; typicalvalues.

Fig 13. Gate-source voltage as a function of gatecharge; typical values.

03ae69

0

20

40

60

0 0.3 0.6 0.9 1.2VSD (V)

IS(A)

Tj = 25 °C175 °C

VGS = 0 V

03ae71

0

2

4

6

8

10

0 10 20 30 40QG (nC)

VGS(V)

ID = 55 A

Tj = 25 °C

VDD = 15 V




9. Package outline

Fig 14. SOT78 (TO-220AB).

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

SOT78 SC-463-lead TO-220AB

D

D1

q

p

L

1 2 3

L1(1)

b1

e e

b

0 5 10 mm

scale

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78

DIMENSIONS (mm are the original dimensions)

AE

A1

c

Note

1. Terminals in this zone are not tinned.

Q

L2

UNIT A1 b1 D1 e p

mm 2.54

q QA b Dc L2max.

3.0 3.83.6

15.013.5

3.302.79

3.02.7

2.62.2

0.70.4

15.815.2

0.90.7

1.31.0

4.54.1

1.391.27

6.45.9

10.39.7

L1(1)E L

00-09-0701-02-16

mountingbase




Fig 15. SOT404 (D2-PAK)

UNIT A



IEC JEDEC EIAJ

mm

A1 D1D

max.E e Lp HD Qc

2.54 2.602.20

15.8014.80

2.902.10

11 1.601.20

10.309.70

4.504.10

1.401.27

0.850.60

0.640.46

b


SOT404

0 2.5 5 mm

scale

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads(one lead cropped) SOT404

e e

E

b

D1

HD

D

Q

Lp

c

A1

A

1 3

2

mountingbase

99-06-2501-02-12




Fig 16. SOT428 (D-PAK)



IEC JEDEC JEITA

SOT428 TO-252 SC-6399-09-1301-12-11

0 10 20 mm

scale

Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads(one lead cropped) SOT428

E

b2 E1

w AMb cb1

L1L

1 3

2

D

D1

HE

L2

Note

1. Measured from heatsink back to lead.

e1

e

A A2

A

A1

y

seating plane

mountingbase

A1(1) Db E1E HE w

ymax.

A2 b2b1 cD1

min.e e1

L1min.

L2LAUNIT


0.2 0.2mm 2.382.22

0.650.45

0.930.73

0.890.71

1.10.9

5.465.26

0.40.2

6.225.98

4.814.45

2.285 4.57 10.49.6

0.5 0.90.5

6.736.47

4.0 2.952.55




10. Revision history

Table 6: Revision history

Rev Date CPCN Description

04 20020904 - Product data (9397 750 10143)

Modifications:

• Changes to Table 3 “Limiting values”

– EDS(AL)S correction of typographical error in test conditions

– IDS(AL)S entry removed

03 20020221 - Product data (9397 750 09288)

02 20010801 - Product data (9397 750 08642)

01 20010330 - Product data (9397 750 08149)





Contact informationFor additional information, please visit http://www.semiconductors.philips.com .For sales office addresses, send e-mail to: [email protected] . Fax: +31 40 27 24825

11. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet atURL http://www.semiconductors.philips.com.

12. Definitions

Short-form specification — The data in a short-form specification isextracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance withthe Absolute Maximum Rating System (IEC 60134). Stress above one ormore of the limiting values may cause permanent damage to the device.These are stress ratings only and operation of the device at these or at anyother conditions above those given in the Characteristics sections of thespecification is not implied. Exposure to limiting values for extended periodsmay affect device reliability.

Application information — Applications that are described herein for anyof these products are for illustrative purposes only. Philips Semiconductorsmake no representation or warranty that such applications will be suitable forthe specified use without further testing or modification.

13. Disclaimers

Life support — These products are not designed for use in life supportappliances, devices, or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductorscustomers using or selling these products for use in such applications do soat their own risk and agree to fully indemnify Philips Semiconductors for anydamages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right tomake changes, without notice, in the products, including circuits, standardcells, and/or software, described or contained herein in order to improvedesign and/or performance. Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys nolicence or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products arefree from patent, copyright, or mask work right infringement, unless otherwisespecified.

14. Trademarks

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

Data sheet status [1] Product status [2] Definition

Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductorsreserves the right to change the specification in any manner without notice.

Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at alater date. Philips Semiconductors reserves the right to change the specification without notice, in order toimprove the design and supply the best possible product.

Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right tomake changes at any time in order to improve the design, manufacturing and supply. Changes will becommunicated according to the Customer Product/Process Change Notification (CPCN) procedureSNW-SQ-650A.





© Koninklijke Philips Electronics N.V. 2002.Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the priorwritten consent of the copyright owner.

The information presented in this document does not form part of any quotation orcontract, is believed to be accurate and reliable and may be changed without notice. Noliability will be accepted by the publisher for any consequence of its use. Publicationthereof does not convey nor imply any license under patent- or other industrial orintellectual property rights.

Date of release: 4 September 2002 Document order number: 9397 750 10143

Contents


1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pinning information . . . . . . . . . . . . . . . . . . . . . . 15 Quick reference data . . . . . . . . . . . . . . . . . . . . . 26 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Thermal characteristics . . . . . . . . . . . . . . . . . . . 47.1 Transient thermal impedance . . . . . . . . . . . . . . 48 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 910 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 1211 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 1312 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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phb 55n03lta logic level fet

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