physical ip development on finfet – there’s nothing planar … · 2019-10-11 · finfet...
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![Page 1: Physical IP Development On FinFET – There’s Nothing Planar … · 2019-10-11 · FinFET Advantages & Considerations ... “A 500mV to 1.0V 128Kb SRAM in Sub 20nm Bulk-FinFET using](https://reader035.vdocument.in/reader035/viewer/2022062604/5fb775e731c0da0c390d5df6/html5/thumbnails/1.jpg)
© 2014 Synopsys, Inc. All rights reserved. 1
Navraj Nandra March 25th 2014
Physical IP Development On FinFET – There’s Nothing Planar About It!
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Logic libraries Embedded SRAMS Interface IP
– USB PHY – DDR PHY – PCI Express PHY – HDMI PHY – MIPI PHY – SERDES
Physical IP
DIBL = Drain Induced Barrier Lowering EM = Electromigration SCE = Short Channel Effects RDR = Restricted Design Rules DPT = Double Patterning Technology NBTI / PBTI = Negative (Positive) Bias Temperature Instability PODE = Poly Over Diffusion Edge PDK = Process Design Kit PPA = Power, Performance, Area
Acronyms
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Power, performance & area must be met regardless of the semiconductor technology
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Agenda
Introducing FinFET Devices
FinFETs On Physical IP
New Design Methodology
Summary
Confidential
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FinFET Transistor Characteristics Output Curves: Voltage (V), Current (I)
Fin=1
Fin=12
Lg=7-nm
Lg=40-nm Fin=1 FinFET
Control through Gate length Number of Fins
W/2
Planar W
Fin=2
FinFET Gate Length
Number of Fins
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FinFET Advantages & Considerations Improved Characteristics; Impacts Circuit Design
Advantages Lower leakage Less variability Lower voltage
Sour
ce
Dra
in
Fin Width
Fin Height
Gate Length
Pfin
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FinFET Advantages & Considerations Improved Characteristics; Impacts Circuit Design
Considerations Quantized widths No body biasing Higher parasitics Aging
Sour
ce
Dra
in
Fin Width
Fin Height
Gate Length
Pfin
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Key Points – FinFET Technology
• Better control of short channel effects • Improves gate control to suppress leakage current • Reduces process‐induced variability below 32-nm
FinFET technology is now in production
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Agenda
Introducing FinFET Devices
FinFETs On Physical IP
Design Methodology
Summary
Confidential
![Page 10: Physical IP Development On FinFET – There’s Nothing Planar … · 2019-10-11 · FinFET Advantages & Considerations ... “A 500mV to 1.0V 128Kb SRAM in Sub 20nm Bulk-FinFET using](https://reader035.vdocument.in/reader035/viewer/2022062604/5fb775e731c0da0c390d5df6/html5/thumbnails/10.jpg)
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FinFET Impact On Physical IP
FinFET impact below M1 Circuit optimization
High level view…
Physical IP • Logic libraries • Embedded SRAMS • Interface IP
DPT impacts M2/M3 Routing
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FinFET Logic Libraries Highlights
• Faster than planar; lower leakage & dynamic power – Lower leakage enables lower VTH – Lower VTH enables lower VDD – Lower VDD leads to lower dynamic power: Pd= fCV2
• Higher drive for same silicon area – Effective transistor width of 9T FinFET cell is close to
12T planar cell
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FinFET Challenges
• ‘Quantized width’ challenge • Lonely FinFETs Degrade performance Increase variability
• EM a concern at chip level • Further challenges: Layout compaction Routability
In Logic Libraries
S D G
STI
Lonely FinFET
Lonely FinFET is not stressed Driving current drops
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New Design Styles
• Cell height / width multiple of Fin /gate pitch • Power rail width and layout dictated by special rules • DPT rules prevent use of M1 at the chip level • PODE addresses lonely FinFET effect
In Logic Libraries
Gate Pitch
Fin Pitch
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FinFET SRAMs Highlights
• Higher performance, lower leakage
• Good static noise margin at low Vdd
• Operates at lower Vdd
Guard ring strap
Precharge & equilazer
Pass gate
Pull ups
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FinFET SRAMS Challenges
Body Effect Quantization
Source: Jong-Ho Lee Seoul National University Thesis
Static noise margin or bigger bitcell Write margin issues
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Solutions: Read/Write Assist Schemes In Embedded SRAMS
Prashant Dubey et. al., “A 500mV to 1.0V 128Kb SRAM in Sub 20nm Bulk-FinFET using auto-adjustable write assist”, 27th IEEE International VLSI Design Conf. 2014
• Reliability Aware Negative Bitline Solution • Programmable Assist Solution is key
At least four techniques published in 2014: TSMC, Samsung, Renesas and Synopsys
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Detect Defects In FinFET Transistors
Resistive shorts between Fins
Resistive opens on Fins
In Embedded SRAMS
Step 1. Defect injection & fault modeling Step 2. Test sequence & optimal PVT Step 3. Test algorithm synthesis Step 4. FinFET Enhanced SMS 5*
New addressing mechanisms Fully programmable background patterns Programmable test operations Stress conditions
*Synopsys Star Memory System
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Impact On Circuit Schematics Interface IP
• Key parameters: gm, gd, Ft, Fmax, matching, noise
• PMOS/NMOS drive strength
• Device matching better
• W/L mapped to L and # fins
• New designs needed for high speed blocks
• Aging simulation is important
gm/gds of bulk and FinFET
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Impact On Layout Interface IP
• Smaller devices get hot
• New tools for EM and IR
• High speed divider causes self heating
• DRC complex
• Metal stack has impact
• Need full RCC simulations
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Key Points – FinFETs on Physical IP
Logic Libraries • Short (7.5T) libraries will be key to achieving highest density, lowest power • PODE addresses lonely FinFET effect
Embedded SRAMS • New assist circuitry helps with low Vdd, body bias and 𝜷 quantization • Synopsys developed flow to detect defects in FinFET cells
Interface IP • Create optimized FinFET schematics by including process info. (inc. NBTI) • Start layout earlier in the design process; new modeling in .lib files • In order to meet PPA, new architectures to be developed
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Agenda
Introducing FinFET Devices
FinFETs On Physical IP
Advanced Design Methodology
Summary
Confidential
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The Need The Solution
DDR4, LPDDR4 Higher I/O speeds using single-ended interface USB 3.0 Must support all 4 speeds Meet electrical compliance PCI Express 8 Gb/s but support new low power modes
The Solution: Advanced Silicon Design Methodology
IP S
pecs
M
arke
t
Physical IP Scales (area, power) without performance degradation Aggressive schedules Supports design on an early PDK SOC Works on first instantiation in SoC
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Process Qualification Vehicle
• Timing Structures – Inverter, NAND and NOR Oscillators – Multiple capacitive & metal loads, multiple Vts – Preferred height, #fingers, P/N ratios, #fins
• Power Structures (Vt/Channel) Chains of Inverter for dynamic & static power
• Layout effects: Lonely FinFET, WPE, Endcap, Body Effect, NBTI/End of Life
Monitor / evaluate speed, leakage, parasitic R, C, random & systematic variability & lithography induced variability effects
Device Aging
Logic Macro
Ringo
HDRF2SP
HDSP
HSRF1P
PLL
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CAD Flow
Example 1: Density Viewer
Actual Max density =
54.2%
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Silicon Success: USB 2.0 PHY; 6 Gb/s SERDES
Key USB Test Results
USB 2.0
USB 3.0
Eye Diagrams Pass Pass
ATE Tests Pass Pass
Functional Pass Pass
USB passed logo certification; FinFET designed for power, area
USB PHY 28-nm FinFET % savings
2.0 Macro Area 0.38 mm2 0.19 mm2 50%
2.0 HS Power 56 mW 46 mW 18%
3.0 Macro Area 0.77 mm2 0.43 mm2 44%
3.0 SS Power 84 mW 66 mW 21%
Note: Specific area and power figures are process dependent
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Key Points – Design Methodology
In order to meet: • Time-to-market requirements • Early (changing) PDK • Next protocol generation, improvement in PPA • Silicon success on first instantiation in SoC
Investment in an advanced design methodology is paramount
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Agenda
Introducing FinFET Devices
FinFETs On Physical IP
Design Methodology
Summary
Confidential
![Page 28: Physical IP Development On FinFET – There’s Nothing Planar … · 2019-10-11 · FinFET Advantages & Considerations ... “A 500mV to 1.0V 128Kb SRAM in Sub 20nm Bulk-FinFET using](https://reader035.vdocument.in/reader035/viewer/2022062604/5fb775e731c0da0c390d5df6/html5/thumbnails/28.jpg)
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Summary
• FinFET advantages to Physical IP Improved electrical and technology parameters yielding significant
performance advantages
• New design approaches can handle limitations: – Assist circuits, high voltage tolerance – Redesign (when necessary) to meet PPA
• Advanced design methodology ensures silicon success on first instantiation
• Synopsys provides silicon proven FinFET Physical IP
There’s nothing planar about FinFET’s