CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive.

Typically CISC chips have a large amount of different and complex instructions. The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instruction set, which provides programmers with assembly instructions to do a lot with short programs.For instance Intel and AMD CPU's are based on CISC architectures.Pronounced sisk, and stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture

Pronounced risk, and stands for Reduced Instruction Set Computer. RISC chips evolved around the mid-1980 as a reaction at CISC chips. The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions. Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructionsother advantage of RISC is that - more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce.

It's easier to write powerful optimized compilers, since fewer instructions exist.

So simply say: RISC and CISC are growing to each other .RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips.

CISCRISC Emphasis on hardwareEmphasis on software Includes multi-clockcomplex instructionsSingle-clock,reduced instruction only Memory-to-memory:"LOAD" and "STORE"incorporated in instructionsRegister to register:"LOAD" and "STORE"are independent instructions Small code sizes,high cycles per secondLow cycles per secondlarge code sizes Transistors used for storingcomplex instructionsregistersSpends more transistors on memory

Processor ArchitecturePrincetonPrinceton provided Von Neumann architecture where common memory space are used for storing program and data. Memory unit is responsible for arbitrary access to memory space between reading instructions and passing data back and forth with processor and its internal registers. Advantages: simple memory interfacing and management.

Princeton architecture block diagramprogram ROMVariable RAMStack RAMmemory interface unitProcessor and built-in registersinstruction decodeDataAddCtrl

Harvard proposes a design that used separate memory banks for program storage, the processor stack, and variable RAM.Advantage: execute instruction in fewer cycles than Von Neumann

Harvard architecture block diagramprogram ROMVariable RAMPC StackProcessor and built-in registersinstruction decodeDataAddCtrlDataAddCtrl

Microcontroller primarily differ from a microprocessor in the areas of built-in peripheral features. These features could include memory device selection, timers, interrupt controllers, DMA, and IO devices like serial ports.

PIC architecture is a Harvard architectureThe Harvard Architecture

Feature of Harvard architectureNear all instructions are single instruction word instructionsOnly one fetch per instructionInstruction fetch and execute are pipelined so you can operate at near clock rate instructions per second2 separate busesOne for instructions and one for data

Microcode is a layer of hardware-level instructions or data structures involved in the implementation of higher level machine code instructions in central processing units, and in the implementation of the internal logic of many channel controllers, disk controllers, network interface controllers, network processors, graphics processing units, and other hardware.It resides in special high-speed memory and translates machine instructions into sequences of detailed circuit-level operations.

It helps separate the machine instructions from the underlying electronics so that instructions can be designed and altered more freely.

It also makes it feasible to build complex multi-step instructions while still reducing the complexity of the electronic circuitry compared to other methods.

Writing microcode is often called microprogramming and the microcode in a particular processor implementation is sometimes called a microprogram.

Modern microcode is normally written by an engineer during the processor design phase and stored in a ROM (read-only memory) or PLA (programmable logic array)[1] structure, or a combination of bothmachines also exist which have some (or all) microcode stored in SRAM or flash memoryComplex digital processors may also employ more than one (possibly microcode based) control unit in order to delegate sub-tasks which must be performed (more or less) asynchronously in parallel.

Microcode is generally not visible or changeable by a normal programmer, not even by an assembly programmer.

Unlike machine code which often retains some compatibility among different processors in a family, microcode only runs on the exact electronic circuitry for which it is designed, as it constitutes an inherent part of the particular processor design itself.

Some hardware vendors, especially IBM, use the term as a synonym for firmware, so that all code in a device, whether microcode or machine code, is termed microcode (such as in a hard drive for instance, which typically contains both)A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction.

Some CISC processors include instructions that can take a very long time to execute.

Such variations interfere with both interrupt latency and, what is far more important in modern systems, pipelining.

When designing a new processor, a hardwired control RISC has these advantages over microcoded CISC:

Programming has largely moved away from assembly level, so it's no longer worthwhile to provide complex instructions for productivity reasons.

Simpler instruction sets allow direct execution by hardware, avoiding the performance penalty of microcoded execution. Complex microcoded instructions may require many clock cycles which vary, and are difficult to pipeline for increased performance.Many RISC and VLIW processors are designed to execute every instruction (as long as it is in the cache) in a single cycle

A hardwired processor uses the bit pattern of the instruction to access specific logic gates (possibly unique to the instruction) that are executed as a combinatorial circuit to carry out the instruction.The instruction loaded into the instruction holding register is used to initiate a specific portion of the execution logic that carries out all the functions of the instruction.

The 8-bit PIC microcontroller is divided into following four categories on the basis of internal architecture:1. Base Line PIC2. Mid-Range PIC3. Enhanced Mid-Range PIC4. PIC18Base Line PICBase Line PICs are the least complex PIC microcontrollers. These microcontrollers work on 12-bit instruction architecture which means that the word size of instruction sets are of 12 bits for these controllers. These are smallest and cheapest PICs, available with 6 to 40 pin packaging. The small size and low cost of Base Line PIC replaced the traditional ICs like 555, logic gates etc. in industries.

Mid-Range PICMid-Range PICs are based on 14-bit instruction architecture and are able to work up to 20 MHz speed. These controllers are available with 8 to 64 pin packaging. These microcontrollers are available with different peripherals like ADC, PWM, Op-Amps and different communication protocols like USART, SPI, I2C (TWI), etc. which make them widely usable microcontrollers not only for industry but for hobbyists as well.Enhanced Mid-Range PICThese controllers are enhanced version of Mid-Range core. This range of controllers provides additional performance, greater flash memory and high speed at very low power consumption. This range of PIC also includes multiple peripherals and supports protocols like USART, SPI, I2C and so on.PIC18PIC18 range is based on 16-bit instruction architecture incorporating advanced RISC architecture which makes it highest performer among the all 8-bit PIC families. The PIC18 range is integrated with new age communication protocols like USB, CAN, LIN, Ethernet (TCP/IP protocol) to communicate with local and/or internet based networks. This range also supports the connectivity of Human Interface Devices like touch panels etc.

*MIPS stand for Millions of Instructions per Second

Base LineMid-RangeEnhanced Mid-RangePIC18No. of Pins6-408-648-6418-100Program MemoryUp to 3 KBUp to 14 KBUp to 28 KBUp to 128 KBData MemoryUp to 134 BytesUp to 368 BytesUp to 1.5 KBUp to 4 KBInstruction Length12-bit14-bit14-bit16-bitNo. of instruction set33354983Speed5 MIPS*5 MIPS8 MIPSUp to 16 MIPSFeature Comparator 8-bit ADC Data MemoryInternal OscillatorIn addition of baseline SPI I2C UART PWM 10-bit ADC OP-AmpsIn addition of Mid-range High Performance Multiple communication peripherals In addition of Enhanced Mid-range CAN LIN USB Ethernet 12-bit ADCFamiliesPIC10,PIC12, PIC16PIC12, PIC16PIC12F1XXX, PIC16F1XXXPIC18

Memory variations:The PIC microcontrollers are available with different memory options which are mask ROM, EPROM and flash memory. They are denoted with different symbols as given in the following table:The letter L is included in controllers name to denote extended voltage range controllers. For example, PIC16LFxxx (Operating voltage 2.0-6.0 volts).

SymbolMemory TypeExampleCEPROMPIC16CxxxCRMask ROMPIC16CRxxxFFlash memoryPIC16Fxxx

Program Memory (ROM)ExternalInternalData Memory (RAM)DirectIndirectSFRs

The question may arise that if PIC16 are called 8-bit microcontrollers, then what about them being based on 14-bit instructions set. PIC16 is an 8-bit microcontroller this statement means that the CPU core can receive/transmit or process a maximum of 8-bit data at a time.The data memory is interfaced with 8-bit bus and program memory is interfaced with 16-bit busMemory of the PIC16F87x divided into 3 types of memories: Program Memory - A memory that contains the program(which we had written), after we've burned it. As a reminder, Program Counter executes commands stored in the program memory, one after the other. Data Memory This is RAM memory type, which contains a special registers like SFR (Special Faction Register) and GPR (General Purpose Register). The variables that we store in the Data Memory during the program are deleted after we turn of the micro. These two memories have separated data buses, which makes the access to each one of them very easy. Data EEPROM (Electrically Erasable Programmable Read-Only Memory) - A memory that allows storing the variables as a result of burning the written program.

The EEPROM data memory is readable and writable during normal operation (full VDD range).This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory.These registers are: EECON1 EECON2 EEDATA EEADR

EEDATA holds the 8-bit data for read/writeEEADR holds the address of the EEPROM location being accessed. The 8-bit EEADR register can access up to 256 locations of Data EEPROM.EECON1 contains the control bits, while EECON2 is the register used to initiate the read/write.When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory.

The program memory space is the maximum size of application that can be loaded intothe microcontroller and contains all the code that is executed in an application alongwith the initial values for the variables used in the application.Program memory is not generally changed during program execution, and the application code is stored in it using custom chip programming equipment.Program memory is known by a number of different names, including control storeand firmware (as well as some permutations of these names). The name really isnt important, as long as you understand that this memory space is used to store the application software.

Program Memory OrganizationThe PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory. Accessing a location above the physically implemented address will cause a wraparound.The RESET vector is at 0000h and the interrupt vector is at 0004h.

Program counter:-The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC) are not readable, but are indirectly writable through the PCLATH register.

Program counter and stackProgram Counter Program counter (PC) is a 13-bit register that contains the address of the instruction being executed. It is physically carried out as a combination of a 5-bit register PCLATH for the five higher bits of the address, and the 8-bit register PCL for the lower 8 bits of the address. By its incrementing or change (i.e. in case of jumps) microcontroller executes program instructions step-by-step.For example, the program memory for the 14-bit core microcontroller has a limit of 8K words, and each word contains a single 14-bit wide instruction. The program memory is divided into 1, 2, or 4 pages of 2K words each. The microcontroller uses its data memory (Register file) to move among the pages. The PCLATH register is used to select which page the next execution branch will go to. When a GOTO or CALL instruction is executed, PCLATH is used to select the page branched to. When the PCL is modified by user code, PCLATH is used with PCL to form the full PC address of the next instruction to be executed.

As you can see on this diagram, Page 0 contains the Reset vector at location 0(0000h). After a reset, code execution begins at the reset vector . Little useful code can be placed at the start of Program Memory if interrupts are used.When an interrupt occurs during code execution, the next instruction address to be fetched (whatever it is) is saved to the stack and execution branches to the interrupt vector at location 4. Often, instructions to load PCLATH and a GOTO at this location will cause execution to branch to somewhere else in memory.Alternatively, servicing the interrupt can begin at this vector location.

STACKThe PIC16F87X family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either pro-gram or data space and the stack pointer is not readable or writable.The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch.The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution.

A reserved area of memory used to keep track of a program's internal operations, including functions, return addresses, passed parameters, etc. A stack isusually maintained as a "last in, first out" (LIFO) data structure, so that the last item added to the structure is the first item used.Sometimes is useful to have a region of memory for temporary storage , which does not have to be allocated as named variables. When you use subroutines and interrupts it will be essential to have such a storage region.Such region is called a StackWhen you PUT something ONTO the stack (PUSH onto the stack), the SP is decremented before the item is placed on the stack. When you take something OFF of the stack (PULL from the stack), the SP is incremented after the item is pulled from the stack.PIC16F84 has a 13-bit stack with 8 levels, or in other words, a group of 8 memory locations, 13 bits wide, with special purpose. Its basic role is to keep the value of program counter after a jump from the main program to an address of a subprogram . In order for a program to know how to go back to the point where it started from, it has to return the value of a program counter from a stack.

The variable memory available in an embedded microcontroller consists of a fairlysmall amount of RAM (random-access memory), which is used for the temporary storage of data. Variable memory is volatile, which means that its values will be lost when power is removed from the microcontroller. The processor addressing modes , were primarily referring to accessing the variable memory of a microcontroller.The nonvolatile data memory provides long-term storage of information even whenpower is lost. Typical information stored in this memory includes data logging information for later transmittal to another device, calibration data for different peripherals, and IP address information for networked devices.

The first 32 bytes in each bank are reserved for Special Function Registers. Someof these Special Function Registers (SFR) appear in all banks such as the STATUSand File Select Register (FSR) . Some addresses in these sections have no SFR andare not implemented.Some PIC micro devices have a shared data memory region. This memory is sharedacross all banks. In other words, the same memory location within a bank can beaccessed in all banks without having to select a different bank. If it is present, thisshared memory is usually the last 16 bytes of each bank.Labels for variables in the shared memory region should be declared only once, in any bank, but will be available in all banks.When direct addressing is used, the RP1 and RP0 bits in the STATUS register selectthe desired bank for direct memory access. Within each bank, 7 bits of addressingselect 1 of 128 addresses. Therefore, in a microcontroller with 4 banks of datamemory, 9 bits are required to uniquely address any data memory location.

When indirect addressing is used, the IRP bit is used to select either Banks 0 and 1,or Banks 2 and 3 for indirect addressing. The FSR register provides the remaining 8 bits of address data.