pic part2 architecture

8/10/2019 PIC Part2 Architecture

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Chapter 2

CPU architecture and Instruction Set


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CpE 112 : Klinkhachorn

PIC Architecture

RISC-Like Features

Harvard architecture

Instruction pipelining

Register file conceptSingle-cycle instruction

All instructions single-word

LWI (Long Word Instruction)

Reduced instruction set


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4/43CpE 112 : Klinkhachorn

Harvard Architecture

CPU

Memory

(Data)

Input Output

Different program anddata bus widths are

possible

Memory(Program) Uses two separate

memory space forinstruction and data.

Increases throughput



Harvard Architecture



Pipelining of Instructions



Pipelining of Instructions (Cont.)



Architecture - x12

ProgramBusProgramProgramBusBus

Clock/CounterClock/Counter

T0CKIT0CKI

I/O PortsI/O Ports

PortsPorts

MuxMux

Indirect DataAddress

Indirect DataIndirect DataAddressAddress

STATUS RegSTATUSSTATUS RegReg

FSRFSRFSR

RAM AddrRAMRAMAddrAddr

InstructionInstructionDecode &Decode &ControlControl

TimingTimingGenerationGeneration

MCLRMCLR

OSC1OSC2OSC1OSC1OSC2OSC2

Direct AddrDirectDirectAddrAddr AddrAddrMuxMux

Instruction

Reg

InstructionInstruction

RegReg

ProgramCounterProgramProgram

CounterCounter

STACK1STACK1

STACK2STACK2

WW RegReg

ALUALUALU

384x12to

2048x12

384x12384x12toto

2048x122048x12

24x8to

73x8

24x824x8toto

73x873x8

WatchdogWatchdogTimerTimer

PowerPower--ononResetReset

DeviceDevice RstRstTimerTimer

RAMRAMFile

RegistersFileFile

RegistersRegisters

DataBusDataDataBusBus

ROMEPROM

ROMROMEPROMEPROM

ProgramMemoryProgramProgramMemoryMemory

*From Microchip Seminar 2000



PIC16C508/509

$1.00

For OTP



PIC12C5XX



Architecture - x14

ProgramProgramBusBus

ROMEPROM

FLASHProgramMemory

Clock/CounterClock/Counter

T0CKI

I/O PortsI/O Ports

PortsPorts

Peripheral(s)Peripheral(s)

RAMFile

Registers

Data BusData Bus

Mux

InstructionDecode &Control

TimingGeneration

OSC1OSC1OSC2OSC2

WatchdogTimer

Power-onReset

OSC Start-upTimer

MCLRMCLRBrown-out

Reset

DirectDirectAddrAddr

Addr MuxInstruction Reg

ProgramCounter

STACK1

STACK8

W Reg

ALU

In-CircuitDebugger

Low VoltProgram

36x836x8toto

368x8368x8

Interrupts

Indirect DataIndirect DataAddressAddress

STATUS Reg

RAMRAMAddrAddr

FSR




PIC16C71X


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Architecture - x16

SYSTEMINTERFACE

BUS

SYSTEMINTERFACE

BUS

DATA LATCH

PROGRAMMEMORY

(EPROM/ROM)Up to 16K words

TABLE PTRTABLE PTR

STACK

16 X 16

STACK

16 X 16

PCH PCLPCH PCL

PCLATHPCLATH

TABLE LATCH TABLE LATCH ROM LATCH ROM LATCH

LITERALLITERAL

INSTRUCTIONDECODER

INSTRUCTION

DECODER

CONTROL

OUTPUTS

IR LATCH IR LATCH

8

8

8

WREG WREG BITOPBITOP

ALU

SHIFTER

IR BUS

DATA BUS

BSRIR BUS

4 3

IR

Q1, Q2,Q3, Q4

16

16

13

DECODERDECODER

BSRBSR

12

Peripherals

IR

16

8 x 8 mult

PRODH PRODLPRODH PRODL

DATARAMUp to

1536 bytes

DATARAMUp to

1536 bytes

Ports

FSR0\FSR1

Clock Generator

Power On Reset

Watchdog Timer

OSC Startup Timer

Test Mode Select

OSC1, OSC2

VDD, VSS

MCLR/VPP

TEST

CHIP_RESETAND OTHERCONTROLS

SIGNALS



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PIC17C4X


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PIC17C4X


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Architecture - x16 Enhanced

Instruction

Register

Program Memory

(up to 2M Bytes)

Table Pointer

Inc/dec logic

PCLATU PCLATH

PCU PCH PCL

2121

5 8 8 Data RAM(up to

4K Bytes)

PORTS PERIPHERALSAddress

12 (2)

FSR0

FSR1

FSR2

12

BSR

4

PRODH PRODL

8 x 8

Multiply

8

8

ALU

8

8

831 Level Stack

Program Counter

TABLELATCH

Add ress

8

12

BIT OP WREG

8

Instruction

Decodeand

Control

Instruction

Decodeand

Control

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Timing Generation

4X PLL

Brown-out

Reset

OSC2/CLK0

OSC1/CLK1

T1OS1

T1OSO

MCLR VDD,VSS*From Microchip Seminar 2000


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PIC18CXXX


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PIC18CXXX


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Mid-Range PIC

16F877


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PIC16F87X28/40-pin 8-Bit CMOS FLASH Microcontrollers

Microcontroller Core Features:

High-performance RISC CPU Only 35 single word instructions to learn

All single cycle instructions except for program branches which are two cycle

Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle

Up to 8K x 14 words of FLASH Program Memory Up to 368 x 8 bytes of Data Memory (RAM)

Up to 256 x 8 bytes of EEPROM data memory

Pinout compatible to the PIC16C73B/74B/76/77

Interrupt capability (up to 14 sources)

Eight level deep hardware stack

Direct, indirect and relative addressing modes

Power-on Reset (POR)

Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)


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PIC16F87X (Cont.)28/40-pin 8-Bit CMOS FLASH Microcontrollers

Microcontroller Core Features: Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

Programmable code-protection

Power saving SLEEP mode

Selectable oscillator options

Low-power, high-speed CMOS FLASH/EEPROM technology

Fully static design

In-Circuit Serial Programming (ICSP) via two pins

Single 5V In-Circuit Serial Programming capability

In-Circuit Debugging via two pins

Processor read/write access to program memory

Wide operating voltage range: 2.0V to 5.5V

High Sink/Source Current: 25 mA

Commercial and Industrial temperature ranges

Low-power consumption:

< 2 mA typical @ 5V, 4 MHz

20 uA typical @ 3V, 32 kHz< 1 uA typical standby current


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PIC16F87X (Cont.)28/40-pin 8-Bit CMOS FLASH Microcontrollers

Peripheral Features:

Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with prescaler

Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

Two Capture, Compare, PWM modules

Capture is 16-bit, max. resolution is 12.5 ns

Compare is 16-bit, max. resolution is 200 ns

PWM max. resolution is 10-bit

10-bit multi-channel Analog-to-Digital converter

Synchronous Serial Port (SSP) with SPI (Master Mode) and I2C (Master/Slave)

Universal Synchronous Asynchronous ReceiverTransmitter (USART/SCI) Parallel Slave Port (PSP) 8-bits wide, with external RD/, WR/ and CS/ controls

Brown-out detection circuitry for Brown-out Reset (BOR)


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PIC16F877


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PIC16F87X Key Features


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Program Memory (PIC16X/17X)

Reset vector

0x000

Interrupt vector

0x004

Memory Top 0x3ff (1K)

0x7ff (2K)

0xfff (4K) 0x1fff (8k)

Program Counter

13 bits Jump to Main

Jump to ISR

0x000

0x004

Tables

0x0ff

Main Program

AndISR

Memory Top


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Program CounterAccessing Program Memory

Program

Counter

01012

Ignored bits 2K (11-bit address range)

PIC2K Program

Memory

Program

Counter

01012

Ignored bits 4K (12-bit address range)

PIC4K Program

Memory


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Program CounterAccessing Program Memory: Call/Goto Instruction

Call/GotoInstruction

Program

Counter

01012

11-bit address range

01013

Call

PCLATH 0

0

Program Memory

PCLATH, 3=0

PCLATH, 3=1

0x000

0x7ff

2KParts

0x800

0xfff

4K

Parts

PCLATH Program Counter Latch

4 3


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Data Memory (Register File)An instruction can access data (register file)

via an addressTwo type of register file

General purpose register file RAM (8 bit data bus)

Special-purpose register file

Input/Output ports Control/Status registers

A/D, Timer, etc.


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Data Memory OrganizationPartitioned into multiple banks

Each bank extends up to 0x7f (128 bytes)

Bits RP1 and RP0 (status register bit 6:5) are

the bank select bits

Status Register (0x03, 0x83, 0x103, 0x183)6 5

RP1 RP0

= 00!!!! Bank 0= 00!!!! Bank 1

= 00!!!! Bank 2

= 00!!!! Bank 3


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Register File Structure (16F87X)

RAM

(96 bytes)

0x00

0x1f

0x7f

0x20

Special purposeregisters(32 bytes)

Bank 0(128 bytes)

0x80

0x9f

0xff

0xa0


Bank 1(128 bytes)

RAM(80 bytes)

0xef

0xf0

0x100(180) Special purposeregisters(16 bytes)

Bank 2(3)(128 bytes)

RAM

(80 bytes)

Accesses70h-7fh

0x10f(18f)0x110(190)

0x11f(19f)RAM

(16 bytes)

0x120(1a0)

0x16f(1ef)

0x170(1f0)0x17f(1ff)Accesses70h-7fh


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PIC16F87X Special File Registers

RAM

(96 bytes)

0x00

0x1f

0x7f

0x20


Bank 0(128 bytes)


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PIC16F87X Special File Registers


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PIC16XXX Instruction Set


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PIC General Format for Instruction

OPCODE f(File #)d067813

Byte-Oriented file register operations

d = 0 for desination Wd = 1 for destination f

f = 7-bit file register address

OPCODE f(File #)0671013

Bit-Oriented file register operations

b = 3-bit address

f = 7-bit file register address

9

b(Bit#)

Examples:movf Temp,W; W=Temp

addwf Temp,f ;Temp=Temp+W

Examples:

bcf PORTB,2 ; clear bit 2 of PORTB

btfsc Temp,0; skip if bit 0=0


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PIC General Format for Instruction

OPCODE k(literal)07813

Literal and Control Operation

k = 8-bit immediate value

OPCODE k(literal)0101113

CALL and GOTO Instructions

k = 11-bit immediate value (address)

Examples:movlw 5; Load 5 to W

addlw 10; Add 10 to W

Examples:

goto Taks1; jump to Task1

call Sub1; call sub1


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Direct Addressing Mode

Op code

0613

7 bit addressRP1 RP0

9 bit effective address

Data Memory

0x000

0x1ff

Byte/Bit oriented instruction


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Indirect Addressing ModeIndirect access memory location via FSR

(File Select Register) through INDF register

07IRPFSR register

Bank Select

Bank 0 Bank 1 Bank 2 Bank 3

0x00

0x7f

0x80

0xff

0x100

0x17f

0x180

0x1ff

Example: Clear RAM usingindirect addressing

movlw 0x20 ;Init ptrmovwf FSR ;to RAM

Next clrf INDF ;clear RAMincf FSR ;inc. ptrbtfss FSR,4 ;all done?

goto Next ;No, clear next

Continue

: ; Yes, continue

Status Reg.

07


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CPU Registers W (Working Register)

Serves a function similar to Accumulator

FSR (File Select Register) Address 0x04,0x84,0x104,0x184

Indirect data memory address pointer INDF (Address 0x00, 0x80, 0x100, 0x180)

Addressing this location uses contents of FSR to address datamemory (not a physical register)

PCL (Address 0x02, 0x82, 0x102, 0x182) Program Counters(PC) Least Significant Byte

PCLATH (Address 0x0a, 0x8a, 0x10a, 0x18a)

Write Buffer for the upper 5 bits of the PC

07

13 bit PC


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CPU Registers (Cont.)STATUS (address 0x03,0x83,0x103,0x183)

IRP: Register bank select bit (Indirect addressing)1 = Bank 2,3 (0x100 0x1ff)

0 = Bank 0,1 (0x00 0xff)

RP1, RP0:Register bank select bits (direct addressing)11 = Bank 3 (0x180-0x1ff)10 = Bank 2 (0x100-0x17f)

01 = Bank 1 (0x80-0xff)

00 = Bank 0 (0x00-0x7f)

TO:Time-out bit

PD:Power-down bitZ:Zero bit

DC:Digit carry/borrow bit (from 4th low order bit)

C:Carry/borrow bit

07


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PIC16F87X STACK

.

..

Stack Level 1Stack Level 2

Stack Level 8

PCCALL, RETURN

RETFIE, RETLW

pic part2 architecture

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