pic18 serial communication

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PIC18 MICROCONTROLLER { Serial Communication Protocol}Mohamad Fauzi Zakaria

http://fkee.uthm.edu.my/mfauzi

Basic Serial Communication2

Communication Method

SYNCHRONOUS ASYNCHRONOUS1 2

SYNCHRONOUS ASYNCHRONOUS

transfers a transfers a single transfers a BLOCK

of data at a time

gBYTE

at a time

useSEPARATE CLOCK

has NOSEPARATE CLOCK SEPARATE CLOCK

and DATA LINE SEPARATE CLOCK

accompanying the data

3 January, 2011mfauzi

Basic Serial Communication3

Data Transmission


PART 14

UART

PART

UART


RS232 StandardRS232 Standard5

Was set by the Electronics Industries Association (EIA) in 1960, before the advent of TTL logic family.before the advent of TTL logic family.

Therefore, logic 1 is represented by “-3 to -25V”, and logic 0 is “+3 to +25V”+25V .

Two types of RS232 pins: DB-25 and DB-9. Most important pins are Tx Rx and groundTx, Rx, and ground.

To interface with PIC, we need line driver such as MAX232 (need it ) MAX233 ( it )capacitors) or MAX233 (no capacitors).


UART>>PIC18 and PC-RS232

6


UART REGISTER>>PIC18F4550 UART REGISTER

7

Normal USART has 7 major registers:

TXSTA (Transmit status and control register)TXSTA (Transmit status and control register)

RCSTA (Receive status and control register)

BAUDCON (Baud rate control)

SPBRG (serial port baud rate generator)

TXREG (Transfer register BUFFER)

RCREG (Receive register BUFFER)RCREG (Receive register BUFFER)

PIR1 (peripheral interrupt request register 1)


EUSARTEUSART8

The Enhanced USART module implements additional features, including:including:

automatic baud rate detection and calibration

automatic wake up on Sync Break receptionautomatic wake-up on Sync Break reception

12-bit Break character transmit.

These make it ideally suited for use in Local Interconnect Network ybus (LIN bus) systems.


PINs ConfigurationPINs Configuration9

In order to configure RC6/TX/CK and RC7/RX/DT/SDO as an EUSART:RC7/RX/DT/SDO as an EUSART:

bit SPEN (RCSTA<7>) must be set (= 1)

bit TRISC<7> must be set (= 1)

bit TRISC<6> must be set (= 1)bit TRISC<6> must be set (= 1)

Note: The EUSART control will automatically reconfigure the pin from input to output as g p p pneeded.


TXSTATXSTA10

TRANSMIT STATUS AND CONTROL REGISTER


RCSTARCSTA11

RECEIVE STATUS AND CONTROL REGISTER


BAUDCONBAUDCON12

BAUD RATE CONTROL REGISTER


Baud Rate Generator (BRG)Baud Rate Generator (BRG)13

By default, the BRG operates in 8-bit mode.

S tti th BRG16 bit (BAUDCON 3 ) l t 16 bit Setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode.


Calculating the Baud Rate ErrorCalculating the Baud Rate Error14


ASYNCHRONOUS TRANSMITTERASYNCHRONOUS TRANSMITTER15


To set up an

ASYNCHRONOUS TRANSMITTER16

1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate., q ,

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.3. If the signal from the TX pin is to be inverted, set the TXCKP bit.3. If the signal from the TX pin is to be inverted, set the TXCKP bit.4. If interrupts are desired, set enable bit TXIE.5 If 9-bit transmission is desired set transmit bit TX9 Can be used as 5. If 9 bit transmission is desired, set transmit bit TX9. Can be used as

address/data bit.6. Enable the transmission by setting bit TXEN which will also set bit TXIF.6. Enable the transmission by setting bit TXEN which will also set bit TXIF.7. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.8 Load data to the TXREG register (starts transmission)8. Load data to the TXREG register (starts transmission).9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register

(INTCON<7:6>) are set.(INTCON 7:6 ) are set.

ASYNCHRONOUS RECEIVERASYNCHRONOUS RECEIVER 17


To set up an

ASYNCHRONOUS RECEIVER18

1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate., q ,

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.3. If the signal at the RX pin is to be inverted, set the RXDTP bit.4. If interrupts are desired, set enable bit RCIE.5. If 9-bit reception is desired, set bit RX9.

Enable the reception by setting bit CREN6. Enable the reception by setting bit CREN.7. Flag bit, RCIF, will be set when reception is complete and an interrupt will be

generated if enable bit RCIE was setgenerated if enable bit, RCIE, was set.8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error

occurred during reception.9. Read the 8-bit received data by reading the RCREG register.10. If any error occurred, clear the error by clearing enable bit CREN.

If i i t t th t th GIE d PEIE bit i th INTCON i t 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.

Example 1Example 119


USART FUNCTION LIBRARYUSART FUNCTION LIBRARY20


Example 2Example 221


PART 222

SPI

PART

SPI


MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE

23

Is a serial interface, useful for communicating with other peripheral or microcontroller devices or microcontroller devices.

These peripheral devices may be serial EEPROMs, shift registers, di l d i A/D t t display drivers, A/D converters, etc.

The MSSP module can operate in one of two modes:Serial Peripheral Interface (SPI)

Inter-Integrated Circuit (I2C)

The I2C interface supports the following modes in hardware:Master mode

Multi-Master mode

Slave mode


MSSP Control RegistersMSSP Control Registers24

has three associated registers:

a status register (SSPSTAT) a status register (SSPSTAT)

control registers (SSPCON1 and SSPCON2).

The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode.


SPI PinsSPI Pins25

To accomplish communication, typically three pins are used:used:

Serial Data Out (SDO) – RC7/RX/DT/SDO

Serial Data In (SDI) – RB0/AN12/INT0/FLT0/SDI/SDA

Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL( )

Additi ll f th i b d h i Sl Additionally, a fourth pin may be used when in a Slave mode of operation:

Slave Select (SS) – RA5/AN4/SS/HLVDIN/C2OUT

SPISPI 26

BlockBlock Diagramg


SPI RegistersSPI Registers27

The MSSP module has four registers for SPI mode operation These are:operation. These are:

MSSP Status Register (SSPSTAT)MSSP Control Register 1 (SSPCON1)Serial Receive/Transmit Buffer Register (SSPBUF)Serial Receive/Transmit Buffer Register (SSPBUF)MSSP Shift Register (SSPSR) – Not directly accessible

SSPSTATSSPSTAT28

MSSP STATUS REGISTER


SSPCON1SSPCON129

MSSP CONTROL REGISTER 1


Enabling SPIEnabling SPI30

To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. must be set.

To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit the SSPCON registers and then set the SSPEN bit.

This configures the SDI, SDO, SCK and SS pins as serial port pins.

Pi t b h th i l t f tiPins to behave as the serial port function:SDI is automatically controlled by the SPI module

SDO must have TRISC<7> bit cleared

SCK (Master mode) must have TRISB<1> bit clearedSCK (Slave mode) must have TRISB<1> bit set

SS must have TRISA<5> bit set

Typical ConnectionTypical Connection31

SPI MODE WAVEFORM(MASTER)

32

SPI Function LibrarySPI Function Library33

PART 334

I2C

PART 3

I2C


Inter-Integrated Circuit (I2C)Inter-Integrated Circuit (I2C)35

Two advantages I2C:

1. I2C needs only two wires (SCL and SDA)(SCL and SDA).

2 I2C supports multi-master2. I C supports multi master.


Data TransmissionData Transmission36

I2C is Half-Duplex data transmissionI2C is Half-Duplex data transmission.

Data is transmitted with the MSB first Data is transmitted with the MSB first.

Th I2C b i d i d f th th d t t i i dThe I2C bus is designed for the three-data transmission speed:Low Speed: The data can be transmitted from 0 to 100 kbps.

SFast Speed: The data can be transmitted up to 400 kbps.

High-Speed: The data can be transmitted up to 3.4 Mbps.


I2C in PIC18F4550I2C in PIC18F455037

The I2C module implements the standard mode specifications as well as 7-bit and 10-bit addressing.well as 7 bit and 10 bit addressing.

Two pins are used for data transfer:Serial clock (SCL) RB1/SCLSerial clock (SCL) – RB1/SCL

Serial data (SDA) – RB0/SDA

Th t fi th i i t th h th The user must configure these pins as inputs through the TRISB<1:0> bits.


I2C Registers in PIC18F4520I2C Registers in PIC18F452038

The MSSP module has six registers for I2C operation.

These are:These are:MSSP Control Register 1 (SSPCON1)

MSSP Control Register 2 (SSPCON2)MSSP Control Register 2 (SSPCON2)

MSSP Status Register (SSPSTAT)

Serial Receive/Transmit Buffer Register (SSPBUF)Serial Receive/Transmit Buffer Register (SSPBUF)

MSSP Shift Register (SSPSR) – Not directly accessible

MSSP Address Register (SSPADD)MSSP Address Register (SSPADD)


I2C MODE BLOCK DIAGRAMI2C MODE BLOCK DIAGRAM39

Note:

SLAVE MODESSPADD register holds the slave SSPADD register holds the slave device address.

MASTER MODEMASTER MODEThe lower seven bits of SSPADD act as the Baud Rate Generator reload

lvalue.


40


41


42


43


OperationOperation44

The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>).bit, SSPEN (SSPCON 5 ).

The SSPCON1 register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected:

I2C Master mode clock = FOSC/(4 x (SSPADD + 1))I2C Master mode, clock = FOSC/(4 x (SSPADD + 1)).

I2C Slave mode (7-bit address).

I2C Slave mode (10 bit address)I2C Slave mode (10-bit address).

I2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled.

I2C Slave mode (10 bit address) with Start and Stop bit interrupts enabledI2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled.

I2C Firmware Controlled Master mode, slave is Idle.


OperationOperation45

Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits.

To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pinsprovided externally to the SCL and SDA pins.


I2C DATA TRANSFERI2C DATA TRANSFER46


I2C DATA TRANSFERI2C DATA TRANSFER47


Master ModeMaster Mode48

Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits.

To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pinsprovided externally to the SCL and SDA pins.


ConfigurationConfiguration49

1. SSPSTAT = ?;SSPADD ? //B d R t2. SSPADD = ?; //Baud Rate

3. SSPCON1 = ?;4. SSPCON2 = ?;5 SSPCON1bits SSPEN= 1; 5. SSPCON1bits.SSPEN= 1; 6. TRISCbits.TRISC3 = 1;7. TRISCbits.TRISC4 = 1;


I2C Function LibraryI2C Function Library50

pic18 serial communication

Documents

asynchronous

clearing bit

mssp shift

setting bit

desired baud

ensure proper

mssp status

i2c slave