pic18f2480/2580/4480/4580 data sheetww1.microchip.com/downloads/en/devicedoc/39637d.pdf ·...

2009 Microchip Technology Inc. DS39637D

PIC18F2480/2580/4480/4580Data Sheet

28/40/44-PinEnhanced Flash Microcontrollers

with ECAN Technology, 10-Bit A/Dand nanoWatt Technology

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

DS39637D-page 2

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

2009 Microchip Technology Inc.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

PIC18F2480/2580/4480/458028/40/44-Pin Enhanced Flash Microcontrollers with

ECAN Technology, 10-Bit A/D and nanoWatt Technology

Power-Managed Modes: Run: CPU on, Peripherals on Idle: CPU off, Peripherals on Sleep: CPU off, Peripherals off Idle mode Currents Down to 6.1 A Typical Sleep mode Current Down to 0.2 A Typical Timer1 Oscillator: 1 A, 32 kHz, 2V Watchdog Timer: 1.7 A Two-Speed Oscillator Start-up

Flexible Oscillator Structure: Four Crystal modes, up to 40 MHz 4x Phase Lock Loop (PLL) Available for Crystal

and Internal Oscillators) Two External RC modes, up to 4 MHz Two External Clock modes, up to 40 MHz Internal Oscillator Block:

- Fast wake from Sleep and Idle, 1 s typical- 8 user-selectable frequencies, from 31 kHz to 8 MHz- Provides a complete range of clock speeds,

from 31 kHz to 32 MHz when used with PLL- User-tunable to compensate for frequency drift

Secondary Oscillator using Timer1 @ 32 kHz Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock stops

Special Microcontroller Features: C Compiler Optimized Architecture with Optional

Extended Instruction Set 100,000 Erase/Write Cycle Enhanced Flash

Program Memory Typical 1,000,000 Erase/Write Cycle Data EEPROM

Memory Typical Flash/Data EEPROM Retention: > 40 Years Self-Programmable under Software Control Priority Levels for Interrupts 8 x 8 Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s Single-Supply 5V In-Circuit Serial

Programming (ICSP) via Two Pins In-Circuit Debug (ICD) via Two Pins Wide Operating Voltage Range: 2.0V to 5.5V

Peripheral Highlights: High-Current Sink/Source 25 mA/25 mA Three External Interrupts One Capture/Compare/PWM (CCP) module Enhanced Capture/Compare/PWM (ECCP) module

(40/44-pin devices only):- One, two or four PWM outputs- Selectable polarity- Programmable dead time- Auto-shutdown and auto-restart

Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I2C Master and Slave modes

Enhanced Addressable USART module- Supports RS-485, RS-232 and LIN/J2602- RS-232 operation using internal oscillator

block- Auto-wake-up on Start bit- Auto-Baud Detect

10-Bit, up to 11-Channel Analog-to-Digital Converter (A/D) module, up to 100 ksps- Auto-acquisition capability- Conversion available during Sleep

Dual Analog Comparators with Input Multiplexing

ECAN Technology Module Features: Message Bit Rates up to 1 Mbps Conforms to CAN 2.0B Active Specification Fully Backward Compatible with PIC18XXX8 CAN

modules Three Modes of Operation:

- Legacy, Enhanced Legacy, FIFO Three Dedicated Transmit Buffers with Prioritization Two Dedicated Receive Buffers Six Programmable Receive/Transmit Buffers Three Full 29-Bit Acceptance Masks 16 Full 29-Bit Acceptance Filters w/Dynamic

Association DeviceNet Data Byte Filter Support Automatic Remote Frame Handling Advanced Error Management Features

DeviceProgram Memory Data Memory

I/O 10-BitA/D (ch)CCP/ECCP(PWM)

MSSP

EUSA

RT

Comp. Timers8/16-bitFlash(bytes)

# Single-WordInstructions

SRAM(bytes)

EEPROM(bytes) SPI

MasterI2C

PIC18F2480 16K 8192 768 256 25 8 1/0 Y Y 1 0 1/3PIC18F2580 32K 16384 1536 256 25 8 1/0 Y Y 1 0 1/3PIC18F4480 16K 8192 768 256 36 11 1/1 Y Y 1 2 1/3PIC18F4580 32K 16384 1536 256 36 11 1/1 Y Y 1 2 1/3

2009 Microchip Technology Inc. DS39637D-page 3

PIC18F2480/2580/4480/4580

Pin Diagrams

RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/KBI0/AN9RB3/CANRXRB2/INT2/CANTXRB1/INT1/AN8RB0/INT0/FLT0/AN10VDDVSSRD7/PSP7/P1DRD6/PSP6/P1CRD5/PSP5/P1BRD4/PSP4/ECCP1/P1ARC7/RX/DTRC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3/C2IN-RD2/PSP2/C2IN+

MCLR/VPP/RE3RA0/AN0/CVREF

RA1/AN1RA2/AN2/VREF-RA3/AN3/VREF+

RA4/T0CKIRA5/AN4/SS/HLVDIN

RE0/RD/AN5RE1/WR/AN6/C1OUTRE2/CS/AN7/C2OUT

VDDVSS

OSC1/CLKI/RA7OSC2/CLKO/RA6

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1

RC3/SCK/SCLRD0/PSP0/C1IN+RD1/PSP1/C1IN-

1234567891011121314151617181920

4039383736353433323130292827262524232221

PIC

18F4

480

40-Pin PDIP

PIC

18F4

580

PIC

18F2

480

1011

23456

1

87

9

121314 15

1617181920

232425262728

2221

MCLR/VPP/RE3RA0/AN0RA1/AN1

RA2/AN2/VREF-RA3/AN3/VREF+


VSSOSC1/CLKI/RA7

OSC2/CLKO/RA6RC0/T1OSO/T13CKI

RC1/T1OSIRC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/KBI0/AN9RB3/CANRXRB2/INT2/CANTXRB1/INT1/AN8RB0/INT0/AN10VDDVSSRC7/RX/DTRC6/TX/CKRC5/SDORC4/SDI/SDA

28-Pin SPDIP, SOIC

PIC

18F2

580

28-Pin QFN

10 11

23

6

1

18192021

22

12 13 1415

87

1617

232425262728

9

PIC18F2480

RC

0/T1

OSO

/T13

CK

I

54

RB

7/K

BI3/

PG

DR

B6/

KBI

2/P

GC

RB

5/K

BI1/

PG

MR

B4/

KBI

0/A

N9

RB3/CANRXRB2/INT2/CANTXRB1/INT1/AN8RB0/INT0/AN10VDDVSSRC7/RX/DT

RC

6/TX

/CK

RC

5/S

DO

RC

4/S

DI/S

DA

MC

LR/V

PP/R

E3

RA

0/A

N0

RA

1/A

N1

RA2/AN2/VREF-RA3/AN3/VREF+


VSSOSC1/CLKI/RA7

OSC2/CLKO/RA6

RC

1/T1

OS

IR

C2/

CC

P1

RC

3/S

CK

/SC

L

PIC18F2580

DS39637D-page 4 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580

Pin Diagrams (Continued)

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

PIC18F4480

37

RA

3/A

N3/

VRE

F+R

A2/A

N2/

V RE

F-R

A1/

AN

1R

A0/

AN

0/C

V RE

FM

CLR

/VP

P/R

E3NC

RB

7/K

BI3

/PG

DR

B6/

KB

I2/P

GC

RB

5/KB

I1/P

GM

RB4

/KB

I0/A

N9

NC

RC

6/TX

/CK

RC

5/S

DO

RC

4/S

DI/S

DA

RD

3/P

SP3

/C2I

N-

RD

2/P

SP2

/C2I

N+

RD

1/P

SP1

/C1I

N-

RD

0/P

SP0

/C1I

N+

RC

3/S

CK

/SC

LR

C2/

CC

P1

RC

1/T1

OS

IN

C

NCRC0/T1OSO/T13CKIOSC2/CLKO/RA6OSC1/CLKI/RA7

VSSVDD

RE2/CS/AN7/C2OUTRE1/WR/AN6/C1OUTRE0/RD/AN5RA5/AN4/SS/HLVDINRA4/T0CKI

RC7/RX/DTRD4/PSP4/ECCP1/P1A

RD5/PSP5/P1BRD6/PSP6/P1C

VSSVDD

RB0/INT0/FLT0/AN10RB1/INT1/AN8

RB2/INT2/CANTXRB3/CANRX

44-Pin TQFP

RD7/PSP7/P1D 54

44-Pin QFN(1)

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

PIC18F4480

37

RA

3/A

N3/

VRE

F+R

A2/

AN2/

V RE

F-R

A1/A

N1

RA

0/A

N0/

CVR

EF

MC

LR/V

PP/R

E3

RB

7/KB

I3/P

GD

RB

6/KB

I2/P

GC

RB

5/K

BI1

/PG

MR

B4/

KBI0

/AN

9N

CR

C6/

TX/C

KR

C5/

SD

OR

C4/

SD

I/SD

AR

D3/

PS

P3/

C2I

N-

RD

2/P

SP

2/C

2IN

+R

D1/

PS

P1/

C1I

N-

RD

0/P

SP

0/C

1IN

+R

C3/

SC

K/S

CL

RC

2/C

CP

1R

C1/

T1O

SI

RC

0/T1

OS

O/T

13C

KI

OSC2/CLKO/RA6OSC1/CLKI/RA7VSS

AVDDRE2/CS/AN7/C2OUTRE1/WR/AN6/C1OUTRE0/RD/AN5RA5/AN4/SS/HLVDINRA4/T0CKI

RC7/RX/DT

RD5/PSP5/P1BRD6/PSP6/P1C

VSS

VDDRB0/INT0/FLT0/AN10

RB1/INT1/AN8RB2/INT2/CANTX

RB

3/C

AN

RX

RD7/PSP7/P1D 54 AVSS

VDD

AVDD

PIC18F4580

PIC18F4580

RD4/PSP4/ECCP1/P1A

Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.


PIC18F2480/2580/4480/4580

Table of Contents1.0 Device Overview .......................................................................................................................................................................... 92.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 253.0 Oscillator Configurations ............................................................................................................................................................ 294.0 Power-Managed Modes ............................................................................................................................................................. 395.0 Reset .......................................................................................................................................................................................... 476.0 Memory Organization ................................................................................................................................................................. 677.0 Flash Program Memory............................................................................................................................................................ 1018.0 Data EEPROM Memory ........................................................................................................................................................... 1119.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 11710.0 Interrupts .................................................................................................................................................................................. 11911.0 I/O Ports ................................................................................................................................................................................... 13512.0 Timer0 Module ......................................................................................................................................................................... 15113.0 Timer1 Module ......................................................................................................................................................................... 15514.0 Timer2 Module ......................................................................................................................................................................... 16115.0 Timer3 Module ......................................................................................................................................................................... 16316.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 16717.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 17718.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 19119.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) ....................................................................................... 23120.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 25321.0 Comparator Module.................................................................................................................................................................. 26322.0 Comparator Voltage Reference Module................................................................................................................................... 26923.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 27324.0 ECAN Module........................................................................................................................................................................... 27925.0 Special Features of the CPU.................................................................................................................................................... 34926.0 Instruction Set Summary .......................................................................................................................................................... 36727.0 Development Support............................................................................................................................................................... 41728.0 Electrical Characteristics .......................................................................................................................................................... 42129.0 Packaging Information.............................................................................................................................................................. 459Appendix A: Revision History............................................................................................................................................................. 471Appendix B: Device Differences......................................................................................................................................................... 471Appendix C: Conversion Considerations ........................................................................................................................................... 472Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 472Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 473Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 473The Microchip Web Site ..................................................................................................................................................................... 487Customer Change Notification Service .............................................................................................................................................. 487Customer Support .............................................................................................................................................................................. 487Reader Response .............................................................................................................................................................................. 488PIC18F2480/2580/4480/4580 Product Identification System ............................................................................................................ 489


PIC18F2480/2580/4480/4580

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.We welcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following: Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page) The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (includeliterature number) you are using.

Customer Notification SystemRegister on our web site at www.microchip.com/cn to receive the most current information on all of our products.


PIC18F2480/2580/4480/4580

NOTES:


PIC18F2480/2580/4480/4580

1.0 DEVICE OVERVIEWThis document contains device specific information forthe following devices:

PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580

This family of devices offers the advantages of allPIC18 microcontrollers namely, high computationalperformance at an economical price with the additionof high-endurance, Enhanced Flash programmemory. In addition to these features, thePIC18F2480/2580/4480/4580 family introduces designenhancements that make these microcontrollers alogical choice for many high-performance,power-sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGYAll of the devices in the PIC18F2480/2580/4480/4580family incorporate a range of features that can signifi-cantly reduce power consumption during operation.Key items include:

Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements.

On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their applications software design.

Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 A, respectively.

Extended Instruction Set: In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2480/2580/4480/4580 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2480/2580/4480/4580family offer ten different oscillator options, allowingusers a wide range of choices in developing applicationhardware. These include:

Four Crystal modes, using crystals or ceramic resonators

Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O)

Two External RC Oscillator modes with the same pin options as the External Clock modes

An internal oscillator block which provides an 8 MHz clock (2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O.

A Phase Lock Loop (PLL) frequency multiplier, available to both the high-speed crystal and internal oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz all without using an external crystal or clock circuit.

Besides its availability as a clock source, the internaloscillator block provides a stable reference source thatgives the family additional features for robustoperation:

Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a refer-ence signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.


PIC18F2480/2580/4480/4580

1.2 Other Special Features Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

Self-Programmability: These devices can write to their own program memory spaces under inter-nal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.

Extended Instruction Set: The PIC18F2480/2580/4480/4580 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C.

Enhanced CCP Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select conditions and auto-restart, to reactivate outputs once the condition has cleared.

Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN/J2602 bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement).

10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead.

Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 131 seconds, that is stable across operating voltage and temperature.

1.3 Details on Individual Family Members

Devices in the PIC18F2480/2580/4480/4580 family areavailable in 28-pin (PIC18F2X80) and 40/44-pin(PIC18F4X80) packages. Block diagrams for the twogroups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in sixways:

1. Flash program memory (16 Kbytes forPIC18FX480 devices; 32 Kbytes forPIC18FX580 devices).

2. A/D channels (8 for PIC18F2X80 devices; 11 forPIC18F4X80 devices).

3. I/O ports (3 bidirectional ports and 1 input onlyport on PIC18F2X80 devices; 5 bidirectionalports on PIC18F4X80 devices).

4. CCP and Enhanced CCP implementation(PIC18F2X80 devices have 1 standard CCPmodule; PIC18F4X80 devices have onestandard CCP module and one ECCP module).

5. Parallel Slave Port (present only onPIC18F4X80 devices).

6. PIC18F4X80 devices provide two comparators.

All other features for devices in this family are identical.These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 andTable 1-3.

Like all Microchip PIC18 devices, members of thePIC18F2480/2580/4480/4580 family are available asboth standard and low-voltage devices. Standarddevices with Enhanced Flash memory, designated withan F in the part number (such as PIC18F2580),accommodate an operating VDD range of 4.2V to 5.5V.Low-voltage parts, designated by LF (such asPIC18LF2580), function over an extended VDD rangeof 2.0V to 5.5V.


PIC18F2480/2580/4480/4580

TABLE 1-1: DEVICE FEATURES

Features PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580

Operating Frequency DC 40 MHz DC 40 MHz DC 40 MHz DC 40 MHzProgram Memory (Bytes) 16384 32768 16384 32768Program Memory (Instructions) 8192 16384 8192 16384Data Memory (Bytes) 768 1536 768 1536Data EEPROM Memory (Bytes) 256 256 256 256Interrupt Sources 19 19 20 20I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, ETimers 4 4 4 4Capture/Compare/PWM Modules 1 1 1 1Enhanced Capture/Compare/PWM Modules

0 0 1 1

ECAN Module 1 1 1 1Serial Communications MSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTParallel Communications (PSP) No No Yes Yes10-Bit Analog-to-Digital Module 8 Input Channels 8 Input Channels 11 Input Channels 11 Input ChannelsComparators 0 0 2 2Resets (and Delays) POR, BOR,

RESET Instruction, Stack Full,

Stack Underflow (PWRT, OST),

MCLR (optional),WDT

POR, BOR, RESET Instruction,

Stack Full, Stack Underflow (PWRT, OST),

MCLR (optional),WDT



MCLR (optional),WDT



MCLR (optional),WDT

Programmable High/Low-Voltage Detect

Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes YesInstruction Set 75 Instructions;

83 with Extended Instruction Set

Enabled

75 Instructions; 83 with Extended

Instruction Set Enabled





Packages 28-pin SPDIP28-pin SOIC28-pin QFN

28-pin SPDIP28-pin SOIC28-pin QFN

40-pin PDIP44-pin QFN

44-pin TQFP

40-pin PDIP44-pin QFN

44-pin TQFP


PIC18F2480/2580/4480/4580

FIGURE 1-1: PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM

InstructionDecode &

Control

PORTA

PORTB

PORTC


RB0/INT0/AN10

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0

RB1/INT1/AN8

Data Latch

Data Memory(.7, 1.5 Kbytes)

Address Latch

Data Address12

AccessBSR4 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

88

ALU

Address Latch

Program Memory(16/32 Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

RB2/INT2/CANTXRB3/CANRX

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)

OSC2/CLKO/RA6

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 3.0 Oscillator Configurations for additional information.

RB4/KBI0/AN9RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

EUSARTComparator MSSP 10-Bit ADC

Timer2Timer1 Timer3Timer0

ECCP1

HLVD

CCP1

BOR DataEEPROM

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

8

8Power-up

TimerOscillator

Start-up TimerPower-on

ResetWatchdog

Timer

OSC1(2)

OSC2(2)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

ReferenceBand Gap

VSS

MCLR(1)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

OSC1/CLKI/RA7

ECAN

BITOP

FSR0FSR1FSR2

inc/dec

Address

12

Decode

logic


PIC18F2480/2580/4480/4580

FIGURE 1-2: PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM

InstructionDecode &

Control

Data Address12

AccessBSR4 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

Address Latch

Program Memory(16/32 Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

PORTDRD0/PSP0

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)RE2/CS/AN7/C2OUT

RE0/RD/AN5RE1/WR/AN6/C1OUT

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 3.0 Oscillator Configurations for additional information.

/C1IN+

EUSARTComparator MSSP 10-Bit ADC

Timer2Timer1 Timer3Timer0

CCP1

HLVD

ECCP1

BOR DataEEPROM

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

8

8Power-up

TimerOscillator

Start-up TimerPower-on

ResetWatchdog

Timer

OSC1(2)

OSC2(2)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

ReferenceBand Gap

VSS

MCLR(1)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

RD1/PSP1/C1IN-RD2/PSP2/C2IN+RD3/PSP3/C2IN-

PORTA

PORTB

PORTC


RB0/INT0/FLT0/AN10

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0/CVREF

RB1/INT1/AN8RB2/INT2/CANTXRB3/CANRX

OSC2/CLKO/RA6

RB4/KBI0/AN9RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

OSC1/CLKI/RA7

ECAN

FSR0FSR1FSR2

inc/dec

Address

12

Decode

logic

Data Latch

Data Memory(.7, 1.5 Kbytes)

Address Latch

RD4/PSP4/ECCP1/P1ARD5/PSP5/P1BRD6/PSP6/P1CRD7/PSP7/P1D


PIC18F2480/2580/4480/4580

TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS

Pin NamePin Number

PinType

BufferType DescriptionSPDIP,

SOIC QFN

MCLR/VPP/RE3MCLR

VPPRE3

1 26I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

9 6I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise.External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

10 7O

O

I/O

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C/SMBus input buffer


PIC18F2480/2580/4480/4580

PORTA is a bidirectional I/O port.RA0/AN0

RA0AN0

2 27I/OI

TTLAnalog

Digital I/O.Analog Input 0.

RA1/AN1RA1AN1

3 28I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

4 1I/OII

TTLAnalogAnalog

Digital I/O.Analog Input 2.A/D reference voltage (low) input.

RA3/AN3/VREF+RA3AN3VREF+

5 2I/OII

TTLAnalogAnalog

Digital I/O.Analog Input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4T0CKI

6 3I/OI

TTLST

Digital I/O.Timer0 external clock input.

RA5/AN4/SS/HLVDIN

RA5AN4SSHLVDIN

7 4

I/OIII

TTLAnalog

TTLAnalog

Digital I/O.Analog Input 4. SPI slave select input.High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin NamePin Number

PinType


SOIC QFN



PIC18F2480/2580/4480/4580

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0/ AN10RB0INT0AN10

21 18I/OII

TTLST

Analog

Digital I/O.External Interrupt 0.Analog Input 10.

RB1/INT1/AN8RB1INT1AN8

22 19I/OII

TTLST

Analog

Digital I/O.External Interrupt 1.Analog Input 8.

RB2/INT2/CANTXRB2INT2CANTX

23 20I/OIO

TTLSTTTL

Digital I/O.External Interrupt 2.CAN bus TX.

RB3/CANRXRB3CANRX

24 21I/OI

TTLTTL

Digital I/O.CAN bus RX.

RB4/KBI0/AN9RB4KBI0AN9

25 22I/OII

TTLTTL

Analog

Digital I/O.Interrupt-on-change pin.Analog Input 9.

RB5/KBI1/PGMRB5KBI1PGM

26 23I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

27 24I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGDRB7KBI3PGD

28 25I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.


Pin NamePin Number

PinType


SOIC QFN



PIC18F2480/2580/4480/4580

PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI

RC0T1OSOT13CKI

11 8I/OOI

STST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSIRC1T1OSI

12 9I/OI

STCMOS

Digital I/O.Timer1 oscillator input.

RC2/CCP1RC2CCP1

13 10I/OI/O

STST

Digital I/O.Capture 1 input/Compare 1 output/PWM1 output.

RC3/SCK/SCLRC3SCKSCL

14 11I/OI/OI/O

STSTI2C

Digital I/O.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.

RC4/SDI/SDARC4SDISDA

15 12I/OI

I/O

STSTI2C

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

16 13I/OO

ST

Digital I/O.SPI data out.

RC6/TX/CKRC6TXCK

17 14I/OO

I/O

STST

Digital I/O.EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT).

RC7/RX/DTRC7RXDT

18 15I/OI

I/O

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see related TX/CK).

RE3 See MCLR/VPP/RE3 pin.VSS 8, 19 5, 16 P Ground reference for logic and I/O pins.VDD 20 17 P Positive supply for logic and I/O pins.


Pin NamePin Number

PinType


SOIC QFN



PIC18F2480/2580/4480/4580

TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS

Pin NamePin Number Pin

TypeBufferType DescriptionPDIP QFN TQFP

MCLR/VPP/RE3MCLR

VPPRE3

1 18 18I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

13 32 30I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise.External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

14 33 31O

O

I/O

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.



PIC18F2480/2580/4480/4580

PORTA is a bidirectional I/O port.RA0/AN0/CVREF

RA0AN0CVREF

2 19 19I/OIO

TTLAnalogAnalog

Digital I/O.Analog Input 0.Analog comparator reference output.

RA1/AN1RA1AN1

3 20 20I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

4 21 21I/OII

TTLAnalogAnalog

Digital I/O.Analog Input 2.A/D reference voltage (low) input.

RA3/AN3/VREF+RA3AN3VREF+

5 22 22I/OII

TTLAnalogAnalog

Digital I/O.Analog Input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4T0CKI

6 23 23I/OI

TTLST

Digital I/O.Timer0 external clock input.

RA5/AN4/SS/HLVDIN

RA5AN4SSHLVDIN

7 24 24

I/OIII

TTLAnalog

TTLAnalog

Digital I/O.Analog Input 4.SPI slave select input.High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.RA7 See the OSC1/CLKI/RA7 pin.






PIC18F2480/2580/4480/4580

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0/AN10

RB0INT0FLT0AN10

33 9 8I/OIII

TTLSTST

Analog

Digital I/O.External Interrupt 0.Enhanced PWM Fault input (ECCP1 module).Analog input 10.

RB1/INT1/AN8RB1INT1AN8

34 10 9I/OII

TTLST

Analog

Digital I/O.External Interrupt 1.Analog input 8.

RB2/INT2/CANTXRB2INT2CANTX

35 11 10I/OIO

TTLSTTTL

Digital I/O.External Interrupt 2.CAN bus TX.

RB3/CANRXRB3CANRX

36 12 11I/OI

TTLTTL

Digital I/O.CAN bus RX.

RB4/KBI0/AN9RB4KBI0AN9

37 14 14I/OII

TTLTTL

Analog

Digital I/O.Interrupt-on-change pin.Analog Input 9.

RB5/KBI1/PGMRB5KBI1PGM

38 15 15I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

39 16 16I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programmingclock pin.

RB7/KBI3/PGDRB7KBI3PGD

40 17 17I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programmingdata pin.






PIC18F2480/2580/4480/4580

PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI

RC0T1OSOT13CKI

15 34 32I/OOI

STST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSIRC1T1OSI

16 35 35I/OI

STCMOS

Digital I/O.Timer1 oscillator input.

RC2/CCP1RC2CCP1

17 36 36I/OI/O

STST

Digital I/O.Capture 1 input/Compare 1 output/PWM1 output.

RC3/SCK/SCLRC3SCK

SCL

18 37 37I/OI/O

I/O

STST

I2C

Digital I/O.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.

RC4/SDI/SDARC4SDISDA

23 42 42I/OI

I/O

STSTI2C

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

24 43 43I/OO

ST

Digital I/O.SPI data out.

RC6/TX/CKRC6TXCK

25 44 44I/OO

I/O

STST

Digital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see related RX/DT).

RC7/RX/DTRC7RXDT

26 1 1I/OI

I/O

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see related TX/CK).






PIC18F2480/2580/4480/4580

PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled.

RD0/PSP0/C1IN+RD0PSP0C1IN+

19 38 38I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 1 input (+).

RD1/PSP1/C1IN-RD1PSP1C1IN-

20 39 39I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 1 input (-)

RD2/PSP2/C2IN+RD2PSP2C2IN+

21 40 40I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 2 input (+).

RD3/PSP3/C2IN-RD3PSP3C2IN-

22 41 41I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 2 input (-).

RD4/PSP4/ECCP1/P1A

RD4PSP4ECCP1P1A

27 2 2

I/OI/OI/OO

STTTLSTTTL

Digital I/O.Parallel Slave Port data.Capture 2 input/Compare 2 output/PWM2 output.ECCP1 PWM Output A.

RD5/PSP5/P1BRD5PSP5P1B

28 3 3I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM Output B.

RD6/PSP6/P1CRD6PSP6P1C

29 4 4I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM Output C.

RD7/PSP7/P1DRD7PSP7P1D

30 5 5I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM Output D.






PIC18F2480/2580/4480/4580

PORTE is a bidirectional I/O port.

RE0/RD/AN5RE0RD

AN5

8 25 25I/OI

I

STTTL

Analog

Digital I/O.Read control for Parallel Slave Port (see also WR and CS pins).Analog Input 5.

RE1/WR/AN6/C1OUTRE1WR

AN6C1OUT

9 26 26I/OI

IO

STTTL

AnalogTTL

Digital I/O.Write control for Parallel Slave Port (see CS and RD pins).Analog Input 6.Comparator 1 output.

RE2/CS/AN7/C2OUTRE2CS

AN7C2OUT

10 27 27I/OI

IO

STTTL

AnalogTTL

Digital I/O.Chip select control for Parallel Slave Port (see related RD and WR).Analog Input 7.Comparator 2 output.

RE3 See MCLR/VPP/RE3 pin.VSS 12,

316, 30,

316, 29 P Ground reference for logic and I/O pins.

VDD 11, 32

7, 8, 28, 29

7, 28 P Positive supply for logic and I/O pins.

NC 13 12, 13, 33, 34

No connect.






PIC18F2480/2580/4480/4580

NOTES:


PIC18F2480/2580/4480/4580

2.0 GUIDELINES FOR GETTING STARTED WITH PIC18F MICROCONTROLLERS

2.1 Basic Connection RequirementsGetting started with the PIC18F2480/2580/4480/4580family of 8-bit microcontrollers requires attention to aminimal set of device pin connections beforeproceeding with development.

The following pins must always be connected:

All VDD and VSS pins (see Section 2.2 Power Supply Pins)

All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 Power Supply Pins)

MCLR pin (see Section 2.3 Master Clear (MCLR) Pin)

These pins must also be connected if they are beingused in the end application:

PGC/PGD pins used for In-Circuit Serial Programming (ICSP) and debugging purposes (see Section 2.4 ICSP Pins)

OSCI and OSCO pins when an external oscillator source is used (see Section 2.5 External Oscillator Pins)

Additionally, the following pins may be required:

VREF+/VREF- pins are used when external voltage reference for analog modules is implemented

The minimum mandatory connections are shown inFigure 2-1.

FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS

Note: The AVDD and AVSS pins must always beconnected, regardless of whether any ofthe analog modules are being used.

PIC18FXXXX

VD

D

VS

S

VDD

VSS

VSS

VDD

AVD

D

AVS

S

VD

D

VS

S

C1

R1

VDD

MCLRR2

C2(1)

C3(1)

C4(1)C5(1)

C6(1)

Key (all values are recommendations):C1 through C6: 0.1 F, 20V ceramicR1: 10 kR2: 100 to 470Note 1: The example shown is for a PIC18F device

with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.


PIC18F2480/2580/4480/4580

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORSThe use of decoupling capacitors on every pair ofpower supply pins, such as VDD, VSS, AVDD andAVSS, is required.

Consider the following criteria when using decouplingcapacitors:

Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.

Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm).

Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capaci-tor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F).

Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.

2.2.2 TANK CAPACITORSOn boards with power traces running longer thansix inches in length, it is suggested to use a tank capac-itor for integrated circuits, including microcontrollers, tosupply a local power source. The value of the tankcapacitor should be determined based on the traceresistance that connects the power supply source tothe device, and the maximum current drawn by thedevice in the application. In other words, select the tankcapacitor so that it meets the acceptable voltage sag atthe device. Typical values range from 4.7 F to 47 F.

2.2.3 CONSIDERATIONS WHEN USING BOR

When the Brown-out Reset (BOR) feature is enabled,a sudden change in VDD may result in a spontaneousBOR event. This can happen when the microcontrolleris operating under normal operating conditions, regard-less of what the BOR set point has been programmedto, and even if VDD does not approach the set point.The precipitating factor in these BOR events is a rise orfall in VDD with a slew rate faster than 0.15V/s.

An application that incorporates adequate decouplingbetween the power supplies will not experience suchrapid voltage changes. Additionally, the use of anelectrolytic tank capacitor across VDD and VSS, asdescribed above, will be helpful in preventing high slewrate transitions.

If the application has components that turn on or off,and share the same VDD circuit as the microcontroller,the BOR can be disabled in software by using theSBOREN bit before switching the component. After-wards, allow a small delay before re-enabling the BOR.By doing this, it is ensured that the BOR is disabledduring the interval that might cause high slew ratechanges of VDD.

Note: Not all devices incorporate software BORcontrol. See Section 5.0 Reset fordevice-specific information.


PIC18F2480/2580/4480/4580

2.3 Master Clear (MCLR) PinThe MCLR pin provides two specific devicefunctions: Device Reset, and Device Programmingand Debugging. If programming and debugging arenot required in the end application, a directconnection to VDD may be all that is required. Theaddition of other components, to help increase theapplications resistance to spurious Resets fromvoltage sags, may be beneficial. A typicalconfiguration is shown in Figure 2-1. Other circuitdesigns may be implemented, depending on theapplications requirements.

During programming and debugging, the resistanceand capacitance that can be added to the pin must beconsidered. Device programmers and debuggers drivethe MCLR pin. Consequently, specific voltage levels(VIH and VIL) and fast signal transitions must not beadversely affected. Therefore, specific values of R1and C1 will need to be adjusted based on theapplication and PCB requirements. For example, it isrecommended that the capacitor, C1, be isolated fromthe MCLR pin during programming and debuggingoperations by using a jumper (Figure 2-2). The jumperis replaced for normal run-time operations.

Any components associated with the MCLR pinshould be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS

2.4 ICSP PinsThe PGC and PGD pins are used for In-Circuit SerialProgramming (ICSP) and debugging purposes. Itis recommended to keep the trace length between theICSP connector and the ICSP pins on the device asshort as possible. If the ICSP connector is expected toexperience an ESD event, a series resistor is recom-mended, with the value in the range of a few tens ofohms, not to exceed 100.

Pull-up resistors, series diodes, and capacitors on thePGC and PGD pins are not recommended as they willinterfere with the programmer/debugger communica-tions to the device. If such discrete components are anapplication requirement, they should be removed fromthe circuit during programming and debugging. Alter-natively, refer to the AC/DC characteristics and timingrequirements information in the respective deviceFlash programming specification for information oncapacitive loading limits and pin input voltage high (VIH)and input low (VIL) requirements.

For device emulation, ensure that the CommunicationChannel Select (i.e., PGCx/PGDx pins) programmedinto the device matches the physical connections forthe ICSP to the Microchip debugger/emulator tool.

For more information on available Microchipdevelopment tools connection requirements, refer toSection 27.0 Development Support.

Note 1: R1 10 k is recommended. A suggestedstarting value is 10 k. Ensure that theMCLR pin VIH and VIL specifications are met.

2: R2 470 will limit any current flowing intoMCLR from the external capacitor, C, in theevent of MCLR pin breakdown, due toElectrostatic Discharge (ESD) or ElectricalOverstress (EOS). Ensure that the MCLR pinVIH and VIL specifications are met.

C1

R2R1

VDD

MCLR

PIC18FXXXXJP


PIC18F2480/2580/4480/4580

2.5 External Oscillator PinsMany microcontrollers have options for at least twooscillators: a high-frequency primary oscillator and alow-frequency secondary oscillator (refer toSection 3.0 Oscillator Configurations for details). The oscillator circuit should be placed on the sameside of the board as the device. Place the oscillatorcircuit close to the respective oscillator pins with nomore than 0.5 inch (12 mm) between the circuitcomponents and the pins. The load capacitors shouldbe placed next to the oscillator itself, on the same sideof the board.

Use a grounded copper pour around the oscillator cir-cuit to isolate it from surrounding circuits. Thegrounded copper pour should be routed directly to theMCU ground. Do not run any signal traces or powertraces inside the ground pour. Also, if using a two-sidedboard, avoid any traces on the other side of the boardwhere the crystal is placed.

Layout suggestions are shown in Figure 2-4. In-linepackages may be handled with a single-sided layoutthat completely encompasses the oscillator pins. Withfine-pitch packages, it is not always possible to com-pletely surround the pins and components. A suitablesolution is to tie the broken guard sections to a mirroredground layer. In all cases, the guard trace(s) must bereturned to ground.

In planning the applications routing and I/O assign-ments, ensure that adjacent port pins and other signalsin close proximity to the oscillator are benign (i.e., freeof high frequencies, short rise and fall times, and othersimilar noise).

For additional information and design guidance onoscillator circuits, please refer to these MicrochipApplication Notes, available at the corporate web site(www.microchip.com):

AN826, Crystal Oscillator Basics and Crystal Selection for rfPIC and PICmicro Devices

AN849, Basic PICmicro Oscillator Design AN943, Practical PICmicro Oscillator Analysis

and Design AN949, Making Your Oscillator Work

2.6 Unused I/OsUnused I/O pins should be configured as outputs anddriven to a logic low state. Alternatively, connect a 1 kto 10 k resistor to VSS on unused pins and drive theoutput to logic low.

FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT

GND

`

`

`

OSC1

OSC2

T1OSO

T1OS I

Copper Pour Primary OscillatorCrystal

Timer1 OscillatorCrystal

DEVICE PINS

PrimaryOscillator

C1

C2

T1 Oscillator: C1 T1 Oscillator: C2

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

GND

OSCO

OSCI

Bottom LayerCopper Pour

OscillatorCrystal

Top Layer Copper Pour

C2

C1

DEVICE PINS

(tied to ground)

(tied to ground)


PIC18F2480/2580/4480/4580

3.0 OSCILLATOR CONFIGURATIONS

3.1 Oscillator TypesPIC18F2480/2580/4480/4580 devices can be operatedin ten different oscillator modes. The user can programthe Configuration bits, FOSC, in ConfigurationRegister 1H to select one of these ten modes:

1. LP Low-Power Crystal2. XT Crystal/Resonator3. HS High-Speed Crystal/Resonator4. HSPLL High-Speed Crystal/Resonator

with PLL Enabled5. RC External Resistor/Capacitor with

FOSC/4 Output on RA66. RCIO External Resistor/Capacitor with I/O

on RA67. INTIO1 Internal Oscillator with FOSC/4 Output

on RA6 and I/O on RA78. INTIO2 Internal Oscillator with I/O on RA6

and RA79. EC External Clock with FOSC/4 Output10. ECIO External Clock with I/O on RA6

3.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal orceramic resonator is connected to the OSC1 andOSC2 pins to establish oscillation. Figure 3-1 showsthe pin connections.

The oscillator design requires the use of a parallelresonant crystal.

FIGURE 3-1: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)

TABLE 3-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS

Note: Use of a series resonant crystal may givea frequency out of the crystalmanufacturers specifications.

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz2.0 MHz4.0 MHz

56 pF47 pF33 pF

56 pF47 pF33 pF

HS 8.0 MHz16.0 MHz

27 pF22 pF

27 pF22 pF

Capacitor values are for design guidance only. These capacitors were tested with the resonatorslisted below for basic start-up and operation. Thesevalues are not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes on page 30 for additional information.

Resonators Used:

455 kHz 4.0 MHz2.0 MHz 8.0 MHz

16.0 MHz

Note: When using resonators with frequenciesabove 3.5 MHz, the use of HS mode,rather than XT mode, is recommended.HS mode may be used at any VDD forwhich the controller is rated. If HS isselected, it is possible that the gain of theoscillator will overdrive the resonator.Therefore, a series resistor should beplaced between the OSC2 pin and theresonator. As a good starting point, therecommended value of RS is 330.

Note 1: See Table 3-1 and Table 3-2 for initial values of C1 and C2.

2: A series resistor (RS) may be required for AT strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

To

Logic

PIC18FXXXXRS(2)

Internal


PIC18F2480/2580/4480/4580

TABLE 3-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

An external clock source may also be connected to theOSC1 pin in the HS mode, as shown in Figure 3-2.

FIGURE 3-2: EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION)

3.3 External Clock InputThe EC and ECIO Oscillator modes require an externalclock source to be connected to the OSC1 pin. There isno oscillator start-up time required after a Power-onReset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 3-3 shows the pin connections for the ECOscillator mode.

FIGURE 3-3: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,except that the OSC2 pin becomes an additionalgeneral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6). Figure 3-4 shows the pin connectionsfor the ECIO Oscillator mode.

FIGURE 3-4: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)

Osc Type Crystal Freq

Typical Capacitor Values Tested:

C1 C2

LP 32 kHz 33 pF 33 pF200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pFCapacitor values are for design guidance only. These capacitors were tested with the crystals listedbelow for basic start-up and operation. These valuesare not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes following this table for additionalinformation.

Crystals Used:32 kHz 4 MHz

200 kHz 8 MHz1 MHz 20 MHz

Note 1: Higher capacitance increases the stabilityof the oscillator but also increases thestart-up time.

2: When operating below 3V VDD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use theHS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its owncharacteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.

4: Rs may be required to avoid overdrivingcrystals with low drive level specification.

5: Always verify oscillator performance overthe VDD and temperature range that isexpected for the application.

OSC1

OSC2Open

Clock fromExt. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKOFOSC/4


OSC1/CLKI

I/O (OSC2)RA6



PIC18F2480/2580/4480/4580

3.4 RC OscillatorFor timing insensitive applications, the RC andRCIO device options offer additional cost savings.The actual oscillator frequency is a function of severalfactors:

supply voltage values of the external resistor (REXT) and

capacitor (CEXT) operating temperature

Given the same device, operating voltage and tempera-ture and component values, there will also be unit-to-unitfrequency variations. These are due to factors such as:

normal manufacturing variation difference in lead frame capacitance between

package types (especially for low CEXT values) variations within the tolerance of limits of REXT

and CEXT

In the RC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 3-5 shows how the R/C combination isconnected.

FIGURE 3-5: RC OSCILLATOR MODE

The RCIO Oscillator mode (Figure 3-6) functions likethe RC mode, except that the OSC2 pin becomes anadditional general purpose I/O pin. The I/O pinbecomes bit 6 of PORTA (RA6).

FIGURE 3-6: RCIO OSCILLATOR MODE

3.5 PLL Frequency MultiplierA Phase Locked Loop (PLL) circuit is provided as anoption for users who wish to use a lower frequencyoscillator circuit or to clock the device up to its highestrated frequency from a crystal oscillator. This may beuseful for customers who are concerned with EMI dueto high-frequency crystals or users who require higherclock speeds from an internal oscillator.

3.5.1 HSPLL OSCILLATOR MODEThe HSPLL mode makes use of the HS mode oscillatorfor frequencies up to 10 MHz. A PLL then multiplies theoscillator output frequency by 4 to produce an internalclock frequency up to 40 MHz.

The PLL is only available to the crystal oscillator whenthe FOSC Configuration bits are programmed forHSPLL mode (= 0110).

FIGURE 3-7: PLL BLOCK DIAGRAM (HS MODE)

3.5.2 PLL AND INTOSCThe PLL is also available to the internal oscillator blockin selected oscillator modes. In this configuration, thePLL is enabled in software and generates a clockoutput of up to 32 MHz. The operation of INTOSC withthe PLL is described in Section 3.6.4 PLL in INTOSCModes.

OSC2/CLKO

CEXT

REXT

PIC18FXXXX

OSC1

FOSC/4

InternalClock

VDD

VSS

Recommended values: 3 k REXT 100 kCEXT > 20 pF

CEXT

REXT

PIC18FXXXX

OSC1 InternalClock

VDD

VSS

Recommended values: 3 k REXT 100 kCEXT > 20 pF

I/O (OSC2)RA6

MU

X

VCO

LoopFilter

CrystalOsc

OSC2

OSC1

PLL Enable

FINFOUT

SYSCLK

PhaseComparator

HS Osc Enable

4

(from Configuration Register 1H)

HS Mode


PIC18F2480/2580/4480/4580

3.6 Internal Oscillator BlockThe PIC18F2480/2580/4480/4580 devices include aninternal oscillator block which generates two differentclock signals; either can be used as the micro-controllers clock source. This may eliminate the needfor external oscillator circuits on the OSC1 and/orOSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,which can be used to directly drive the device clock. Italso drives a postscaler, which can provide a range ofclock frequencies from 31 kHz to 4 MHz. The INTOSCoutput is enabled when a clock frequency from 125 kHzto 8 MHz is selected.

The other clock source is the internal RC oscillator(INTRC), which provides a nominal 31 kHz output.INTRC is enabled if it is selected as the device clocksource; it is also enabled automatically when any of thefollowing are enabled:

Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up

These features are discussed in greater detail inSection 25.0 Special Features of the CPU.The clock source frequency (INTOSC direct, INTRCdirect or INTOSC postscaler) is selected by configuringthe IRCF bits of the OSCCON register (Register 3-2).

3.6.1 INTIO MODESUsing the internal oscillator as the clock source elimi-nates the need for up to two external oscillator pins,which can then be used for digital I/O. Two distinctconfigurations are available:

In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output.

In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.

3.6.2 INTOSC OUTPUT FREQUENCYThe internal oscillator block is calibrated at the factoryto produce an INTOSC output frequency of 8.0 MHz.

The INTRC oscillator operates independently of theINTOSC source. Any changes in INTOSC across volt-age and temperature are not necessarily reflected bychanges in INTRC and vice versa.

3.6.3 OSCTUNE REGISTERThe internal oscillators output has been calibrated atthe factory but can be adjusted in the users applica-tion. This is done by writing to the OSCTUNE register(Register 3-1).

When the OSCTUNE register is modified, the INTOSCand INTRC frequencies will begin shifting to the newfrequency. The INTRC clock will reach the newfrequency within 8 clock cycles (approximately8 * 32 s = 256 s). Code execution continues duringthis shift. There is no indication that the shift hasoccurred.

The OSCTUNE register also implements the INTSRCand PLLEN bits, which control certain features of theinternal oscillator block. The INTSRC bit allows usersto select which internal oscillator provides the clocksource when the 31 kHz frequency option is selected.This is covered in greater detail in Section 3.7.1Oscillator Control Register. The PLLEN bit controls the operation of the frequencymultiplier, PLL, in internal oscillator modes.

3.6.4 PLL IN INTOSC MODESThe 4x frequency multiplier can be used with the inter-nal oscillator block to produce faster device clockspeeds than are normally possible with an internaloscillator. When enabled, the PLL produces a clockspeed of up to 32 MHz.

Unlike HSPLL mode, the PLL is controlled throughsoftware. The control bit, PLLEN (OSCTUNE), isused to enable or disable its operation. If PLL isenabled and a Two-Speed Start-up from wake isperformed, execution is delayed until the PLL starts.

The PLL is available when the device is configured touse the internal oscillator block as its primary clocksource (FOSC = 1001 or 1000). Additionally, thePLL will only function when the selected output fre-quency is either 4 MHz or 8 MHz (OSCCON = 111or 110). If both of these conditions are not met, the PLLis disabled.

The PLLEN control bit is only functional in those internaloscillator modes where the PLL is available. In all othermodes, it is forced to 0 and is effectively unavailable.

3.6.5 INTOSC FREQUENCY DRIFTThe factory calibrates the internal oscillator blockoutput (INTOSC) for 8 MHz. However, this frequencymay drift as VDD or temperature changes, which canaffect the controller operation in a variety of ways. It ispossible to adjust the INTOSC frequency by modifyingthe value in the OSCTUNE register. This has no effecton the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when tomake the adjustment, in which direction it should bemade, and in some cases, how large a change isneeded. Three compensation techniques arediscussed in Section 3.6.5.1 Compensating withthe EUSART, Section 3.6.5.2 Compensating withthe Timers and Section 3.6.5.3 Compensatingwith the CCP Module in Capture Mode, but othertechniques may be used.


PIC18F2480/2580/4480/4580

3.6.5.1 Compensating with the EUSART An adjustment may be required when the EUSARTbegins to generate framing errors or receives data witherrors while in Asynchronous mode. Framing errorsindicate that the device clock frequency is too high. Toadjust for this, decrement the value in OSCTUNE toreduce the clock frequency. On the other hand, errorsin data may suggest that the clock speed is too low. Tocompensate, increment OSCTUNE to increase theclock frequency.

3.6.5.2 Compensating with the TimersThis technique compares device clock speed to somereference clock. Two timers may be used; one timer isclocked by the peripheral clock, while the other isclocked by a fixed reference source, such as theTimer1 oscillator.

Both timers are cleared, but the timer clocked by thereference generates interrupts. When an interruptoccurs, the internally clocked timer is read and bothtimers are cleared. If the internally clocked timer value

is greater than expected, then the internal oscillatorblock is running too fast. To adjust for this, decrementthe OSCTUNE register.

3.6.5.3 Compensating with the CCP Module in Capture Mode

A CCP module can use free-running Timer1 (orTimer3), clocked by the internal oscillator block and anexternal event with a known period (i.e., AC powerfrequency). The time of the first event is captured in theCCPRxH:CCPRxL registers and is recorded for uselater. When the second event causes a capture, thetime of the first event is subtracted from the time of thesecond event. Since the period of the external event isknown, the time difference between events can becalculated.

If the measured time is much greater than thecalculated time, the internal oscillator block is runningtoo fast. To compensate, decrement the OSCTUNEregister. If the measured time is much less than thecalculated time, the internal oscillator block is runningtoo slow. To compensate, increment the OSCTUNEregister.

REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)0 = PLL disabled

bit 5 Unimplemented: Read as 0bit 4-0 TUN: Frequency Tuning bits

01111 = Maximum frequency 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency.11111 10000 = Minimum frequency

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as 0. See text for details.


PIC18F2480/2580/4480/4580

3.7 Clock Sources and Oscillator

SwitchingLike previous PIC18 devices, thePIC18F2480/2580/4480/4580 family includes a featurethat allows the device clock source to be switched fromthe main oscillator to an alternate low-frequency clocksource. PIC18F2480/2580/4480/4580 devices offertwo alternate clock sources. When an alternate clocksource is enabled, the various power-managedoperating modes are available.

Essentially, there are three clock sources for thesedevices:

Primary oscillators Secondary oscillators Internal oscillator block

The primary oscillators include the external crystaland resonator modes, the external RC modes, theexternal clock modes and the internal oscillator block.The particular mode is defined by the FOSCConfiguration bits. The details of these modes arecovered earlier in this chapter.

The secondary oscillators are those external sourcesnot connected to the OSC1 or OSC2 pins. Thesesources may continue to operate even after thecontroller is placed in a power-managed mode.

PIC18F2480/2580/4480/4580 devices offer the Timer1oscillator as a secondary oscillator. This oscillator, in allpower-managed modes, is often the time base forfunctions such as a Real-Time Clock (RTC).

Most often, a 32.768 kHz watch crystal is connectedbetween the RC0/T1OSO/T13CKI and RC1/T1OSIpins. Like the LP Oscillator mode circuit, loadingcapacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail inSection 13.3 Timer1 Oscillator.In addition to being a primary clock source, the internaloscillator block is available as a power-managedmode clock source. The INTRC source is also used asthe clock source for several special features, such asthe WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2480/2580/4480/4580devices are shown in Figure 3-8. See Section 25.0Special Features of the CPU for Configurationregister details.

FIGURE 3-8: PIC18F2480/2580/4480/4580 CLOCK DIAGRAM

4 x PLL

FOSC

Secondary Oscillator

T1OSCENEnableOscillator

T1OSO

T1OSI

Clock Source Option for Other Modules

OSC1

OSC2

Sleep

Primary Oscillator

HSPLL, INTOSC/PLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

Pos

tsca

ler

MU

X

MU

X

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON

111

110

101

100

011

010

001

00031 kHz

INTRCSource

InternalOscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON

ClockControl

OSCCON

Source8 MHz

31 kHz (INTRC)

OSCTUNE

01

OSCTUNE

and Two-Speed Start-up


PIC18F2480/2580/4480/4580

3.7.1 OSCILLATOR CONTROL REGISTERThe OSCCON register (Register 3-2) controls severalaspects of the device clocks operation, both infull-power operation and in power-managed modes.

The System Clock Select bits, SCS, select theclock source. The available clock sources are theprimary clock (defined by the FOSC Configura-tion bits), the secondary clock (Timer1 oscillator) andthe internal oscillator block. The clock source changesimmediately after one or more of the bits is written to,following a brief clock transition interval. The SCS bitsare cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits,IRCF, select the frequency output of the internaloscillator block to drive the device clock. The choicesare the INTRC source, the INTOSC source (8 MHz) orone of the frequencies derived from the INTOSC post-scaler (31 kHz to 4 MHz). If the internal oscillator blockis supplying the device clock, changing the states ofthese bits will have an immediate change on the inter-nal oscillators output. On device Resets, the defaultoutput frequency of the internal oscillator block is set at1 MHz.

When an output frequency of 31 kHz is selected(IRCF = 000), users may choose which internaloscillator acts as the source. This is done with theINTSRC bit in the OSCTUNE register (OSCTUNE).Setting this bit selects INTOSC as a 31.25 kHz clocksource by enabling the divide-by-256 output of theINTOSC postscaler. Clearing INTSRC selects INTRC(nominally 31 kHz) as the clock source.

This option allows users to select the tunable and moreprecise INTOSC as a clock source, while maintainingpower savings with a very low clock speed. Regardlessof the setting of INTSRC, INTRC always remains theclock source for features such as the Watchdog Timerand the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clocksource is currently providing the device clock. TheOSTS bit indicates that the Oscillator Start-up Timer(OST) has timed out and the primary clock is providingthe device clock in primary clock modes. The IOFS bitindicates when the internal oscillator block has stabi-lized and is providing the device clock in RC Clockmodes. The T1RUN bit (T1CON) indicates whenthe Timer1 oscillator is providing the device clock insecondary clock modes. In power-managed modes,only one of these three bits will be set at any time. Ifnone of these bits are set, the INTRC is providing theclock or the internal oscillator block has just started andis not yet stable.

The IDLEN bit determines if the device goes into Sleepmode or one of the Idle modes when the SLEEPinstruction is executed.

The use of the flag and control bits in the OSCCONregister is discussed in more detail in Section 4.0Power-Managed Modes.

3.7.2 OSCILLATOR TRANSITIONSPIC18F2480/2580/4480/4580 devices contain circuitryto prevent clock glitches when switching betweenclock sources. A short pause in the device clock occursduring the clock switch. The length of this pause is thesum of two cycles of the old clock source and three tofour cycles of the new clock source. This formulaassumes that the new clock source is stable.

Clock transitions are discussed in greater detail inSection 4.1.2 Entering Power-Managed Modes.

Note 1: The Timer1 oscillator must be enabled toselect the secondary clock source. TheTimer1 oscillator is enabled by setting theT1OSCEN bit in the Timer1 Control regis-ter (T1CON). If the Timer1 oscillator isnot enabled, then any attempt to select asecondary clock source when executing aSLEEP instruction will be ignored.

2: It is recommended that the Timer1oscillator be operating and stable beforeexecuting the SLEEP instruction, or a verylong delay may occur while the Timer1oscillator starts.


PIC18F2480/2580/4480/4580

REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit1 = Device enters Idle mode on SLEEP instruction0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF: Internal Oscillator Frequency Select bits111 = 8 MHz (INTOSC drives clock directly)110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz001 = 125 kHz000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1)

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable and the frequency is provided by one of the RC modes0 = INTOSC frequency is not stable

bit 1-0 SCS: System Clock Select bits1x = Internal oscillator block01 = Timer1 oscillator00 = Primary oscillator

Note 1: Depends on state of the IESO Configuration bit.2: Source selected by the INTSRC bit (OSCTUNE), see text.3: Default output frequency of INTOSC on Reset.


PIC18F2480/2580/4480/4580

3.8 Effects of Power-Managed Modes

on the Various Clock SourcesWhen PRI_IDLE mode is selected, the designatedprimary oscillator continues to run without interruption.For all other power-managed modes, the oscillatorusing the OSC1 pin is disabled. The OSC1 pin (andOSC2 pin, if used by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN andSEC_IDLE), the Timer1 oscillator is operating andproviding the device clock. The Timer1 oscillator mayalso run in all power-managed modes if required toclock Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),the internal oscillator block provides the device clocksource. The 31 kHz INTRC output can be used directlyto provide the clock and may be enabled to supportvarious special features, regardless of thepower-managed mode (see Section 25.2 WatchdogTimer (WDT), Section 25.3 Two-Speed Start-upand Section 25.4 Fail-Safe Clock Monitor for moreinformation on WDT, Two-Speed Start-up and Fail-SafeClock Monitor. The INTOSC output at 8 MHz may beused directly to clock the device or may be divideddown by the postscaler

pic18f2480/2580/4480/4580 data sheetww1.microchip.com/downloads/en/devicedoc/39637d.pdf ·...

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