PipeliningPipelining

By Toan NguyenBy Toan Nguyen

CharacterizeCharacterize Pipelines Pipelines

1)1) Hardware or software implementation – pipelining can be Hardware or software implementation – pipelining can be implemented in either software or hardware. implemented in either software or hardware.

2)2) Large or Small Scale – Stations in a pipeline can range from Large or Small Scale – Stations in a pipeline can range from simplistic to powerful, and a pipeline can range in length from simplistic to powerful, and a pipeline can range in length from short to long.short to long.

3)3) Synchronous or asynchronous flow – A synchronous pipeline Synchronous or asynchronous flow – A synchronous pipeline operates like an assembly line: at a given time, each station is operates like an assembly line: at a given time, each station is processing some amount of information. A asynchronous processing some amount of information. A asynchronous pipeline, allow a station to forward information at any time.pipeline, allow a station to forward information at any time.

4)4) Buffered or unbuffered flow – One stage of pipeline sends data Buffered or unbuffered flow – One stage of pipeline sends data directly to another one or a buffer is place between each pairs directly to another one or a buffer is place between each pairs of stages.of stages.

5)5) Finite Chunks or Continuous Bit Streams – The digital Finite Chunks or Continuous Bit Streams – The digital information that passes though a pipeline can consist of a information that passes though a pipeline can consist of a sequence or small data items or an arbitrarily long bit stream.sequence or small data items or an arbitrarily long bit stream.

6)6) Automatic Data Feed Or Manual Data Feed – Some Automatic Data Feed Or Manual Data Feed – Some implementations of pipelines use a separate mechanism to implementations of pipelines use a separate mechanism to move information, and other implementations require each move information, and other implementations require each stage to participate in moving information.stage to participate in moving information.

What is PipeliningWhat is Pipelining

A technique used in advanced microprocessors A technique used in advanced microprocessors where the microprocessor begins executing a where the microprocessor begins executing a second instruction before the first has been second instruction before the first has been completed.completed.

- A Pipeline is a series of stages, where some work A Pipeline is a series of stages, where some work is done at each stage. The work is not finished is done at each stage. The work is not finished until it has passed through all stages.until it has passed through all stages.

With pipelining, the computer architecture allows With pipelining, the computer architecture allows the next instructions to be fetched while the the next instructions to be fetched while the processor is performing arithmetic operations, processor is performing arithmetic operations, holding them in a buffer close to the processor holding them in a buffer close to the processor until each instruction operation can performed.until each instruction operation can performed.

How Pipelines WorksHow Pipelines Works

The pipeline is divided into segments The pipeline is divided into segments and each segment can execute it and each segment can execute it operation concurrently with the other operation concurrently with the other segments. Once a segment segments. Once a segment completes an operations, it passes completes an operations, it passes the result to the next segment in the the result to the next segment in the pipeline and fetches the next pipeline and fetches the next operations from the preceding operations from the preceding segment.segment.

ExampleExample

Instruction 1 Instruction 2

Instruction 3Instruction 4

X X

XX

Four sample instructions, executed linearly

Four Pipelined Instructions

IF

IF

IF

IF

ID

ID

ID

ID

EX

EX

EX

EX M

M

M

M

W

W

W

W

5

1

1

1

Instructions FetchInstructions Fetch

The instruction Fetch (IF) stage is responsible for The instruction Fetch (IF) stage is responsible for obtaining the requested instruction from memory. obtaining the requested instruction from memory. The instruction and the program counter (which is The instruction and the program counter (which is incremented to the next instruction) are stored in incremented to the next instruction) are stored in the IF/ID pipeline register as temporary storage the IF/ID pipeline register as temporary storage so that may be used in the next stage at the start so that may be used in the next stage at the start of the next clock cycle.of the next clock cycle.

Instruction DecodeInstruction Decode

The Instruction Decode (ID) stage is responsible The Instruction Decode (ID) stage is responsible for decoding the instruction and sending out the for decoding the instruction and sending out the various control lines to the other parts of the various control lines to the other parts of the processor. The instruction is sent to the control processor. The instruction is sent to the control unit where it is decoded and the registers are unit where it is decoded and the registers are fetched from the register file.fetched from the register file.

ExecutionExecution

The Execution (EX) stage is where any The Execution (EX) stage is where any calculations are performed. The main component calculations are performed. The main component in this stage is the ALU. The ALU is made up of in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities.arithmetic, logic and capabilities.

Memory and IOMemory and IO

The Memory and IO (MEM) stage is responsible The Memory and IO (MEM) stage is responsible for storing and loading values to and from for storing and loading values to and from memory. It also responsible for input or output memory. It also responsible for input or output from the processor. If the current instruction is from the processor. If the current instruction is not of Memory or IO type than the result from the not of Memory or IO type than the result from the ALU is passed through to the write back stage.ALU is passed through to the write back stage.

Write BackWrite Back

The Write Back (WB) stage is The Write Back (WB) stage is responsible for writing the result of a responsible for writing the result of a calculation, memory access or input calculation, memory access or input into the register file.into the register file.

Operation TimingsOperation Timings

Estimated timings for each Estimated timings for each of the stages:of the stages:

InstructioInstruction Fetchn Fetch

2ns2ns

InstructioInstruction Decoden Decode

1ns1ns

ExecutionExecution 2ns2ns

Memory Memory and IOand IO

2ns2ns

Write Write BackBack

1ns1ns

Advantages/DisadvantagesAdvantages/Disadvantages

Advantages: Advantages: More efficient use of processorMore efficient use of processor Quicker time of execution of large number of Quicker time of execution of large number of instructionsinstructions

Disadvantages:Disadvantages: Pipelining involves adding hardware to the Pipelining involves adding hardware to the

chipchip Inability to continuously run the pipeline Inability to continuously run the pipeline at full speed because of pipeline hazards at full speed because of pipeline hazards which disrupt the smooth execution of the which disrupt the smooth execution of the pipeline.pipeline.

Pipeline HazardsPipeline Hazards

Data Hazards – an instruction uses the result of Data Hazards – an instruction uses the result of the previous instruction. A hazard occurs exactly the previous instruction. A hazard occurs exactly when an instruction tries to read a register in its when an instruction tries to read a register in its ID stage that an earlier instruction intends to ID stage that an earlier instruction intends to write in its WB stage.write in its WB stage.

Control Hazards – the location of an instruction Control Hazards – the location of an instruction depends on previous instructiondepends on previous instruction

Structural Hazards – two instructions need to Structural Hazards – two instructions need to access the same resourceaccess the same resource

Data HazardsData Hazards

IF

IF

ID

ID EX

EX M

M

WB

WB

ADD R1, R2, R3

SUB R4, R1, R5

Select R2 and R3 for ALU Operations

ADD R2 and R3 STORE SUM IN R1

Select R1 and R5 for ALU Operations

StallingStalling Stalling involves halting the flow of instructions Stalling involves halting the flow of instructions

until the required result is ready to be used. until the required result is ready to be used. However stalling wastes processor time by However stalling wastes processor time by doing nothing while waiting for the result.doing nothing while waiting for the result.

IF

IF

ID

ID EX

EX M

M

WB

WB

ADD R1, R2, R3

SUB R4, R1, R5

IF ID EX M WBSTALL

IF ID EX M WBSTALL

IF ID EX M WBSTALL

Type of PipeliningType of Pipelining Software PipeliningSoftware Pipelining

1) Can Handle Complex Instructions1) Can Handle Complex Instructions

2) Allows programs to be reused2) Allows programs to be reused Hardware PipeliningHardware Pipelining

1) Help designer manage complexity – a 1) Help designer manage complexity – a

complex task can be divided into smaller, complex task can be divided into smaller,

more manageable pieces.more manageable pieces.

2) Hardware pipelining offers higher 2) Hardware pipelining offers higher

performanceperformance

Type of Hardware PipelinesType of Hardware Pipelines Instruction Pipeline - Instruction Pipeline - An An instruction pipeline instruction pipeline is is

very similar to a manufacturing assembly line. very similar to a manufacturing assembly line.

1st stage receives some parts, performs its assembly 1st stage receives some parts, performs its assembly task, and passes the results to the second stage;task, and passes the results to the second stage;

2nd stage takes the partially assembled product from 2nd stage takes the partially assembled product from the first stage, performs its task, and passes its the first stage, performs its task, and passes its work to the third stage; work to the third stage;

3rd stage does its work, passing the results to the last 3rd stage does its work, passing the results to the last stage, which completes the task and outputs its stage, which completes the task and outputs its results. results.

Data Pipeline – data pipeline is designed to pass Data Pipeline – data pipeline is designed to pass data from stage to stage.data from stage to stage.

Instruction Pipelines ConflictInstruction Pipelines Conflict It divided into two categories.It divided into two categories.

Data ConflictsData Conflicts Branch ConflictsBranch Conflicts

When the current instruction changes a register When the current instruction changes a register that the next one needed, data conflicts happens.that the next one needed, data conflicts happens.

When the current instruction make a jump, When the current instruction make a jump, branch conflicts happens.branch conflicts happens.

ReferencesReferences

http://www.cs.sjsu.edu/~lee/cs147/fahttp://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.pptll2003/23147L25Pipelining.ppt

http://murray.newcastle.edu.au/usershttp://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.html#/students/1999/c9311421/pipe.html#s5s5