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Dr.Abhijit RAsatiEEEDepartment,BITS,Pilani

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Placement

solution in reasonable amount of computational time.

ons ruc ve :

Used to obtain initial solutionSequential, deterministic or probabilistic

Iterative :

Simulated annealing, simulated evolution, partitioning based

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Problem statement :

Input:B1,B2,B3Bn are blocks to be placed on chip .The block Bi has height hi&width wiN= N ,N ,N .N are set of nets re resentin interconnections between

different blocks.

Out ut :Q={Q1,Q2,Q3.Qk} represent rectangular empty area allocated for

routing between blocks.L denote the estimated len th of net N .Find iso-oriented rectangle for each blockR={R1,R2.Rn} such that Ri has widthwi& height hi.

rectangles overlap.Total wire length i.e. Li (i=1...m) is minimized.

. . i i=1..mdriven placement).Placement is routable.

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Constructive Algorithm:

IOC method for Initial placement with minimum total routing length:

IOC for each unplaced block is I-0.Where := .O=sum of signal net connectivity to all unplaced blocks.

e oc s w e g es va ue s en se ec e or p acemen .

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Routing Regions in Different Design Styles:

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Initial placement and Rout-ability Analysis : (Global Routing)

Block are placed anywhere such that it should provide 100%routing.After placement if it is found that 100% routing is not possible wema even alter lacement.

A rough wiring analysis is performed for each placement refinementto determine :

.

Total routing length i.e. area occupied by routing

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Grid-graph model:

Each cell is given a vertex

Filled circles: Occupied cellsEmpty circles: Unoccupied cells present at location.Edge weight represents channel capacity.

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Channel intersection model:

Channels are re resented as ed es.Channel intersections and terminals are represented as vertices.Edge weight represents channel capacity.

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Global routing problem:

Input:

Net-list N = {n1, n2, , nm}

A routing graph G(V,E), where V is a set of vertices, and E is a set ofed es

Output: ' ' i X(ej) C(ej) for all ej Ewhere:

ej = individual edgeC(ej) = capacity of edge ejX e = number of wires assin throu h e

The total length of all the steiner trees is minimized.

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Area-Routing:

.Take into account gate area & routing area.

e o a rou ng eng can e es ma e us ng o ow ng eur s calgorithms.

Minimum spanning treeSteiner treeHalf perimeter method -Complete GraphSource to Sink Connection

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Design style specific placement problem :-

u us om:

Standard-cells:

Gate-Arrays :

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Classification of placement Algorithm:

(1) Simulation-Based placement Algorithm:

Simulated Annealin Al orithm

Simulated Evolution Algorithm

-

Sequence-pair Technique

(2) Partitioning-Based placement Algorithm:(Breuers Algorithm)

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(2) Partitioning-Based placement Algorithm:(Breuers Algorithm)

It performs the partitioning of the both i.e.

given circuit and

their simultaneous placement by partitioning layout area.

C={c1,c2,c3.cn} =set of n cut-lines

The order of cut lines which ives minimum routin -len th is thebest order.

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Such reduction of net-cuts in sequential-manner is Greedy-

Approach, may not yield optimal solution.

Useful for standard-cell and gate-arrays.

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Cut oriented min-cut placement :

- .

Easy to implement.Dose not always yield good results. u a e or e unequa s ze oc s.Blocks created by previous cut-line have to partitionedsimultaneously therefore may require more space.

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Quandrature placement procedure:

using horizontal and vertical cut lines.Most popular sequence of cut lines. oc s o equa s ze. eg.

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Bisection placement procedure :

- -

consist of one row.Then Bisected by vertical cut-lines to place all cells/blocks. se or s an ar ce p acemen .Does not guarantee minimization of maximum net cut perchannels .

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Slice-Bisection placement :

First Bisected b horizontal cut-lines until each sub-re ion consistof a row assigned to a component/block.Then Bisected by vertical cut-lines to place all bit-slice in a

.Suitable for circuits which have a high degree of interconnection at

the periphery.

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A Data-Path Compiler:

y: =0;f or bi t - posi t i on: =0 upt o n_bi t s- 1 do begi nx: =0;

f or al l dat a pat h el ement s ( e) do begi ncel l : =sel ect DPEcel l e bi t - osi t i onmakeI nst ance ( cel l , x, y) ;

y: =y + hei ght of ( cel l ) ;

x: =x + wi dt h of ( cel l ) ;end;