planar bulk cmos scaling to the end of the road
TRANSCRIPT
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Planar Bulk CMOS Scaling to the End of the Road
Prof. Tsu‐Jae King LiuElectrical Engineering and Computer Sciences Department
University of California at Berkeley
November 2012
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Outline
• Where We Are Now– The CMOS Power Crisis
• The Road to Now– Recent Advancements in CMOS Technology
• The Road Not (yet) Taken– Evolution of the Planar Bulk MOSFET
• Summary
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The CMOS Power Crisis• As transistor density has increased, the supply voltage (VDD)
has not decreased proportionately.
Source: P. Packan (Intel), 2007 IEDM Short Course
Pow
er D
ensi
ty (
W/c
m2 )
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
0.01 0.1 1Gate Length (μm)
Passive Power Density
Active Power Density
Source: B. Meyerson (IBM) Semico Conf., January 2004
Power Density vs. Gate LengthCMOS Voltage Scaling
Power density now constrains CMOS chip design!
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A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007
Process‐Induced Variations• Sub‐wavelength lithography:
– Resolution enhancement techniques are costly and increase process sensitivity
SiO2 Gate
Source Drain
A. Brown et al., IEEE Trans.Nanotechnology,p. 195, 2002
• Random dopant fluctuations (RDF):– Atomistic effects become
significant in nanoscale FETs
courtesy Mike Rieger (Synopsys, Inc.)• Gate line‐edge roughness:photoresist
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Outline
• Where We Are Now– The CMOS Power Crisis
• The Road to Now– Recent Advancements in CMOS Technology
• The Road Not (yet) Taken– Evolution of the Planar Bulk MOSFET
• Summary
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CMOS Technology Advancement
• The transistor gate length (Lg) has not scaled proportionately with device pitch in recent generations.– Transistor performance has been boosted by other means.
90 nm node 65 nm node 45 nm node 32 nm node
T. Ghani et al., IEDM 2003 K. Mistry et al.,IEDM 2007
P. Packan et al.,IEDM 2009
XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.)
(after S. Tyagi et al., IEDM 2005)
6
strained Sihigh-k/metal gate stack
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Bulk MOSFET Design Optimization
SioxoxSi
oxSi
ox
Si
tttt
/12
oxSiox
Si tt2
Double-Gate FET
Scale length:
Ground-Plane FETStructure: Double-Gate FET
Scale length:
Ground-Plane FETStructure:
SourceDrain
Energy Band Profile:(OFF State)
longer
R.‐H. Yan et al., IEEE Trans. Electron Devices, Vol. 39, pp. 1704‐1710, 1992
• The thickness of the lightly doped channel region, tSi, is a critical design parameter.
• To maximize ION and minimize VTH variation, heavy doping near the surface of the channel region should be avoided. Use a steep retrograde channel doping profile to suppress IOFF
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Carrier Confinement w/o Doping• Inversion charge is confined to be near the surface, by
inserting O partial mono‐layers within the channel region relaxes requirement for thin tSi
• Separation of carrier sub‐bands reduces inter‐band scattering carrier mobility is enhanced
R. J. Mears et al. (Mears Technologies), 2012 Silicon Nanoelectronics Workshop
Inversion‐charge density profile Effective electron mobility
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Solid: regular SiDashed: O-inserted Si
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Outline
• Where We Are Now– The CMOS Power Crisis
• The Road to Now– Recent Advancements in CMOS Technology
• The Road Not (yet) Taken– Evolution of the Planar Bulk MOSFET
• Summary
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log ID
VGSVDD
ION
• The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential.
Body
Gate
Drain
CoxCdep
higher ION/IOFF for fixed VDD, or lower VDD to achieve target ION/IOFFreduced short‐channel effect and drain‐induced barrier lowering:
Source
SourceDrainincreasing VDS
ox
total
CCS
log ID
VGS
decreasing Lgor
increasing VDS IOFF
Key to Lg Scaling: Improved Gate Control
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1.0E+034.0E+002.5E‐011.6E‐021.0E‐03
Current Density (A/cm2)
Lg=20nm, Leff=18nm, EOT = 0.9nm, Vds=0.7V
Narrow MOSFETWSTRIPE = 2Lg = 40 nm
HSTRIPE=5nm
Along the channel:
Across the channel:
Off‐State Leakage Contour Plots
Wide MOSFET
source drain source drain
11
Fringing E‐fields + ground plane good gate control!
TSi=12nmTSi=12nm
Retrograde channel doping (ground plane) is insufficient!
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HSTRIPE=25nm
WSTRIPE=15nm WSTRIPE=12nm WSTRIPE=9nm
Lg=20nm, Leff=18nm, EOT = 0.9nm, Vds=0.7VBulk FinFET Off‐State Leakage
• The FinFET requires a narrow channel region to achieve good gate control. Fin width must be less than 0.6×Lg to well suppress IOFF
• Fin aspect ratio must be >1.5 for good area efficiency Challenging to manufacture!
Across the channel/fin:
1.0E+034.0E+002.5E‐011.6E‐021.0E‐03
Current Density (A/cm2)
Note that doping at the base of the fin is used to suppress sub‐fin leakage between the source and drain regions, not to achieve good gate control.
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TSi=25nm
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Impact of HSTRIPE Variation
• If TSi is fixed, VTH is not sensitive to HSTRIPE variation.
12 13 14 15 160.27
0.30
0.33
0.36
0.39
0.42 TSi = XJ,EXT = HSTRIPE TSi = XJ,EXT = 14nm
V T_LI
N (V)
HSTRIPE (nm)
Lg = 20nm, EOT = 0.9nm, WSTRIPE = 20nm
HSTRIPE (nm)
13
X. Sun (UC Berkeley), Ph.D. thesis
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VTH Adjustment Approaches
• VTH adjustment via TSi tuning provides for less variation, and eliminates the trade‐off with short‐channel control.
DIBL values for each design are
indicated
C. Shin et al., IEEE 2008 Silicon Nanoelectronics Workshop
14
Lg = 20 nmEOT = 0.9 nm
WSTRIPE = 20 nmHSTRIPE = 14 nmWeff = 44 nm
tSi = 14 nmXJ = 14 nm
• VTH of a narrow MOSFET can be adjusted by tuning either the dose (Npeak) or the depth (TSi) of the retrograde doping.
– 200 atomistic simulations were run for each nominal design.
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Segmented Channel MOSFET (SegFET)
• Gate control is enhanced by fringing electric fields!– The channel stripes can be elevated above the vSTI, or a high‐k vSTI dielectric can be used, to further enhance gate control.
B. Ho et al., International Semiconductor Device Research Symposium 2011 15
• Channel region comprises stripes of equal width ≥ Lg, isolated by very shallow trench isolation (vSTI).– vSTI is much shallower than the STI between transistors. Deep source/drain regions and ground plane are not segmented!
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Gate electrode
STI oxideSi
VSTIdielectric
T.‐J. King and V. Moroz, U.S. Patent 7,265,008
1. Start with corrugated substrate
2. Define active areas
3. Fill trenches to formSTI; Implant wells
4. Slightly recess theisolation oxide (optional)
5. Implant channels;Form gate stack
7. Embed/grow epitaxial material in S/D regions
(optional)
8. Dope S/D regions;Form silicide
WSTRIPE
Precise control of channel width is achieved(Layout dependencies, sensitivity to misalignment are reduced) variation in MOSFET performance is reduced
LG
6. Form S/D extensions, then sidewall spacers
SegFET Fabrication Process
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vSTI dielectric
Corrugated Substrate Fabrication(requires 1 mask, which can be used for multiple chip designs)
Silicon
vSTI dielectric
Silicon
Silicon
Si Si Si Si
Silicon
Silicon
3. Selective Epitaxy3. Dielectric Etch‐back
1. Si Etch 1. Dielectric DepositionWSTRIPE ≥ Lg,min
≤ Lg,min
2. Dielectric Deposition
2. Dielectric Etch
17
PROCESS #1: PROCESS #2:
XVSTI > XJ• NOTE: A high-k vSTI
material is beneficial for enhanced gate control
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1st Demonstration of (N‐channel) SegFET
• SegFETs have reduced SCE and comparable area efficiency as conventional planar MOSFETs.
Plan‐View SEM Image XTEM along A‐A’
Measured I‐V Characteristics
18
B. Ho et al., International Semiconductor Device Research Conference 2012
(Currents are normalized to layout width)
(Corrugated Substrate Process #1)
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N‐Channel FET Gate Leakage
• SegFET has lower gate leakage due to reduced transverse E‐field Allows for more aggressive EOT scaling for improved scalability
19
B. Ho et al., International Semiconductor Device Research Conference 2012
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Si1‐xGex P‐Channel SegFET
The SegFET exhibits• higher linear VTH (due to
reduced biaxial strain)• larger drive current per
unit layout width
XTEM along Gate
20
B. Ho et al., Symp. VLSI Technology 2012
(Currents are normalized to layout width)
Hole Mobility
Measured I‐V Characteristics
Short Channel Effect(Corrugated Substrate Process #2)
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P‐Channel FET Gate Capacitance
• SegFET has lower gate capacitance per unit layout area beneficial for lower delay 21
B. Ho et al., to be published
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P‐channel FET Layout Width Dependence
Saturation Threshold Voltage Linear Drive Current
• SegFETs show dramatically reduced narrow width effects.
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B. Ho et al., Symp. VLSI Technology 2012
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• More stress is induced in SegFETMore mobility enhancement• Reduced variation with Weff for SegFET Reduced eff variation
Segmented FET(bulk tri‐gate)
Planar
• SegFET parameters:WSTRIPE = 20nmWSPACING = 20nmHSTRIPE = 10nm
• Lg = 20nm• EOT = 0.9nm• TGATE = 40nm• LSPACER = 20nm
Layout Width Dependence of Strained SiCapping‐layer‐induced strain along the channel
Contact etch stop liner is assumed to be a 30nm‐thick silicon nitride with 2GPa tensile stress
Narrow ChannelWide Channel
Xin Sun Ph.D. thesis, UC Berkeley, 2010 23
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Performance Comparison with FinFET
0
5
10
15
28nm22nm34nm27nm20nm 12nm15nm25nmWSi
LeffLG=20nmLG=25nm
|dV T/d
WSi| (
mV/
nm)
0.0
0.5
1.0
1.5
2.0
28nm22nm18nm34nm27nm21nm
20nm 12nm20nm15nm25nm25nmWSiLeff LG=20nmLG=25nm
Planar bulk Tri-Gate bulk FinFET SOI
Intri
nsic
Del
ay (p
s)
86% reduction
• 3‐D device simulations were performed for MOSFETs designed to achieve minimum intrinsic delay at a given IOFF specification: For LG=25nm, IOFF=8nA/µm For LG=20nm, IOFF=18nA/µm
The SegFET is less sensitive to WSTRIPE variation than the FinFET.
81% reduction
The intrinsic delay advantage of the SegFET increases with scaling.
34% reduction37% reduction
QP Bulk
Xin Sun Ph.D. thesis, UC Berkeley, 2010 24
Planar bulkSegFETSOI FinFET
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Impact of Retrograde Doping Steepness
25
SegFETFinFET
For the SegFET:WSTRIPE = Lg, HSTRIPE = 0.8Lg
For the FinFET:WSTRIPE = 0.6Lg, HSTRIPE = 1.3Lg
The optimal steepness is less aggressive for the SegFET!
X. Sun (UC Berkeley), Ph.D. thesis
• For the SegFET, there is a trade‐off between improved average carrier mobility and improved short‐channel‐effect suppression.
• For the FinFET, the retrograde doping gradient should be as steep as possible to maximize the average carrier mobility.
tox = 9Å, TSi = HSTRIPE, VDD = 0.7V
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Summary• Power density and variability now limit transistor scaling
– Thin‐body MOSFET solutions are revolutionary, introducing new challenges for design and/or manufacturing
• The segmented‐channel bulk MOSFET design offers an evolutionary (low‐cost) pathway to lower VTH and VDD− utilizes conventional (established) IC fabrication techniques− is compatible with all technologies (strained‐Si, high‐k/metal gate stack, advanced doping/anneal) developed for bulk CMOS
− is easily implemented alongside conventional bulk MOSFETs
• The benefits of SegFET technology lower power / higher performance; improved yield / lower cost
will only increase with CMOS technology scaling.26
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Corrugated Substrate TechnologyProcess steps required to form a (partially) corrugated substrate:
– Masked etch (of Si or vSTI dielectric)• Regular line/space pattern + low‐aspect‐ratio features
amenable to spacer lithography to achieve very fine pitch• Mask can generic, i.e. used for multiple chip designs
– vSTI dielectric depositionwhich can be high‐k material (different than STI) for improved gate control
– Etchback (of VSTI dielectric) or selective epitaxy (of channel)• Epitaxial growth of Ge or III‐V directly on Si is facilitated by confinement
Benefits of Corrugated Substrate approach vs. STI‐only approach:Superior CD controlLower parasitic resistance (due to non‐segmented source/drain)Higher stress transfer from embedded source/drain stressors
Superior performance and yield!27
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Broadening the RoadmapB. Ho (UC Berkeley), Ph.D. thesis
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Extend known solutions by 4 yrs
Extend known solutions by >7 years
Extend known solutions by 8 years
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Acknowledgements• Collaborators:
– Dr. Victor Moroz and Dr. Qiang Lu (Synopsys, Inc.)– Dr. Xin Sun (now with IBM Microelectronics)– Dr. Changhwan Shin (now with University of Seoul)– Byron Ho (joining Intel Corp.)– Dr. Nuo Xu (UCB)
• Funding/Support:– Synopsys, Inc.– SRC (Task 1631.001; Graduate Fellowship)– TEL (T. Sako, K. Maekawa, M. Tomoyasu, Y. Akasaka)– AMAT (B.Wood, V.Tran, S.Chopra, Y.Kim, S.Kuppurao, C.‐P.Chang)– Soitec (B.‐Y. Nguyen, O. Bonnin, C. Mazure)
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Additional Information
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SegFET at a Glance• SegFET is a proven transistor design in which the channel region
of a planar bulk MOSFET is segmented to improve gate control.– Conventional CMOS fabrication process, w/ corrugated starting substrate
Not a FinFET: nearly planar, i.e. no high‐aspect‐ratio features Leverages retrograde channel doping to suppress leakage VT can be tuned via body biasing
• The combination of retrograde channel doping and a “tri‐gate” structure provides for superior electrostatic integrity. More scalable than FinFET, Intel’s tri‐gate FET, and gate‐all‐around FET
Easiest approach to extend transistor scaling to sub‐10 nm Lgand/or to adopt new channel materials Requires no process‐tool changes or new materials Requires one additional mask – which can be reused Uses standard bulk MOSFET compact model and EDA tools
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Proof of Concept: Recessed Isolation Oxide
Experiment performed at UMC in early 28nm CMOS technology• Individual logic transistors and 6T‐SRAM arrays fabricated
• ~2500 cell per device‐under‐test (DUT)• Dual‐stress liners for performance enhancement
CMOS front‐end‐of‐line stepsXTEM along gate electrodeSRAM cell plan‐view SEM
cell‐area = 0.149 um2
STI Formation
LDD & Pocket Implants
Well & VT ImplantsSTI Oxide RecessGate Ox./Poly DepositionGate Patterning
Spacer & S/D FormationActivation ProcessSalicidation
C. Shin et al., 2010 ESSDERC
PKT dose split: Standard or Light
0 or 15nm
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Measured Quasi‐Planar CMOS ResultsION statistics IOFF statistics
• Quasi‐planar ION is higher, for comparable IOFF2x increase for NMOS, 4x increase for PMOS
NMOS Pu
ll‐Dow
nPM
OS Pu
ll‐Up
• Quasi‐planar VTHvariation is lower
Saturation VT statistics
C. Shin et al., 2010 ESSDERC
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• The standard bulk MOSFET compact model can well predict quasi‐planar MOSFET performance, including the body effect.
NMOS PMOS
0.0E+00
2.0E-06
4.0E-06
6.0E-06
8.0E-06
1.0E-05
1.2E-05
1.4E-05
-1 -0.8 -0.6 -0.4 -0.2 0
Drain Voltage Vd (V)
PU D
rian
Cur
rent
Id (A
)
Control Vbs=0
Control Vbs=-0.2
RECESS=15nm Vbs=0
RECESS=15nm Vbs=-0.2
0.0E+00
6.0E-06
1.2E-05
1.8E-05
2.4E-05
3.0E-05
3.6E-05
4.2E-05
0 0.2 0.4 0.6 0.8 1Drain Voltage Vd (V)
PG D
rain
Cur
rent
Id (A
)
Control Vbs=0
Control Vbs=0.2
RECESS=15nm Vbs=0
RECESS=15nm Vbs=0.2
Quasi‐Planar
Planar
Quasi‐Planar
Planar
Body Bias Effect and Compact ModelC. Shin et al., 2010 ESSDERC
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Advanced Channel Materials• High‐mobility semiconductor
materials potentially can provide for improved performance:– Ge for PMOS– (In)GaAs for NMOS
J.‐S. Park et al., Appl. Phys. Lett. 90 052113, 2007
Ge on Si
J. Z. Li et al., Appl. Phys. Lett. 91 021114, 2007
GaAs on Si
Si Ge GaAs
Electron mobility (cm2/Vs) 1500 3900 8500
Hole mobility (cm2/Vs) 450 1900 400
Lattice constant (Å) 5.431 5.646 5.653
Band gap (eV) 1.12 0.66 1.424
Dielectric constant 12 16 13
• Selective epitaxial growth directly on Si is facilitated by the use of a corrugated substrate:
35