Capacitors

Second Edition

with On-Chip DecouplingPower Distribution Networks

•

Power Distribution Networks

Capacitors

Second Edition

• •Renatas Jakushokas Mikhail PopovichAndrey V. Mezhiba Selçuk Köse Eby G. Friedman

with On-Chip Decoupling

Springer New York Dordrecht Heidelberg London

All rights reserved. This work may not be translated or copied in whole or in part without the

New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis.

software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are

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Use in connection with any form of information storage and retrieval, electronic adaptation, computer

University of Rochester

USA USA

University of Rochester

USA

USA

Qualcomm IncorporatedSan Diego California

Andrey V. MezhibaIntel CorporationHillsboro OregonUSA

Sel k K e

Mikhail Popovich

Rochester New York

Eby G. Friedman

Renatas Jakushokas

University of Rochester

ISBN 978-1-4419-7870-7 e-ISBN 978-1-4419-7871-4

subject to proprietary rights.

DOI 10.1007/978-1-4419-7871-4

© Springer Science+Business Media, LLC 2011

çu ös

Rochester New York

Rochester New York

To Victoria and Daniel

To Oksana, Elizabeth, and JulieAnn

To Elizabeth

To Leman, Gulsum, and Nurettin

To Laurie, Joseph, and Samuel

Contents

Preface to the Second Edition . . . . . . . . . . . . . . . . . . . . . . . . XIX

Preface to the First Edition . . . . . . . . . . . . . . . . . . . . . . . . . . XXIII

Part I General Background

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Evolution of integrated circuit technology . . . . . . . . . . 71.2 Evolution of design objectives . . . . . . . . . . . . . . . . . . . . . 101.3 The problem of power distribution . . . . . . . . . . . . . . . . 141.4 Deleterious effects of power distribution noise . . . . . . . 20

1.4.1 Signal delay uncertainty . . . . . . . . . . . . . . . . . . . . 211.4.2 On-chip clock jitter . . . . . . . . . . . . . . . . . . . . . . . . 211.4.3 Noise margin degradation . . . . . . . . . . . . . . . . . . . 241.4.4 Degradation of gate oxide reliability . . . . . . . . . . 24

1.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2 Inductive Properties of Electric Circuits . . . . . . . . . . 272.1 Definitions of inductance . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1.1 Field energy definition . . . . . . . . . . . . . . . . . . . . . 282.1.2 Magnetic flux definition . . . . . . . . . . . . . . . . . . . . 302.1.3 Partial inductance . . . . . . . . . . . . . . . . . . . . . . . . . 352.1.4 Net inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

VIII Contents

2.2 Variation of inductance with frequency . . . . . . . . . . . . . 432.2.1 Uniform current density approximation . . . . . . . 442.2.2 Inductance variation mechanisms . . . . . . . . . . . . 452.2.3 Simple circuit model . . . . . . . . . . . . . . . . . . . . . . . 49

2.3 Inductive behavior of circuits . . . . . . . . . . . . . . . . . . . . . 522.4 Inductive properties of on-chip interconnect . . . . . . . . 542.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3 Properties of On-Chip Inductive Current Loops . . . 593.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.2 Dependence of inductance on line length . . . . . . . . . . . 603.3 Inductive coupling between two parallel loop segments 673.4 Application to circuit analysis . . . . . . . . . . . . . . . . . . . . 683.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4 Electromigration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714.1 Physical mechanism of electromigration . . . . . . . . . . . . 724.2 Electromigration-induced mechanical stress . . . . . . . . . 754.3 Steady state limit of electromigration damage . . . . . . . 764.4 Dependence of electromigration lifetime on the line

dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.5 Statistical distribution of electromigration lifetime . . . 814.6 Electromigration lifetime under AC current . . . . . . . . . 824.7 A comparison of aluminum and copper interconnect

technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834.8 Designing for electromigration reliability . . . . . . . . . . . 864.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5 Decoupling Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 895.1 Introduction to decoupling capacitance . . . . . . . . . . . . . 90

5.1.1 Historical retrospective . . . . . . . . . . . . . . . . . . . . . 905.1.2 Decoupling capacitor as a reservoir of charge . . 915.1.3 Practical model of a decoupling capacitor . . . . . 93

5.2 Impedance of power distribution system withdecoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.2.1 Target impedance of a power distribution

system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.2.2 Antiresonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005.2.3 Hydraulic analogy of hierarchical placement of

decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . 104

Contents IX

5.3 Intrinsic vs intentional on-chip decoupling capacitance 1095.3.1 Intrinsic decoupling capacitance . . . . . . . . . . . . . 1105.3.2 Intentional decoupling capacitance . . . . . . . . . . . 114

5.4 Types of on-chip decoupling capacitors . . . . . . . . . . . . . 1165.4.1 Polysilicon-insulator-polysilicon (PIP)

capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175.4.2 MOS capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195.4.3 Metal-insulator-metal (MIM) capacitors . . . . . . 1275.4.4 Lateral flux capacitors . . . . . . . . . . . . . . . . . . . . . . 1295.4.5 Comparison of on-chip decoupling capacitors . . 133

5.5 On-chip switching voltage regulator . . . . . . . . . . . . . . . 1355.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6 Scaling Trends of On-Chip Power DistributionNoise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396.1 Scaling models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406.2 Interconnect characteristics . . . . . . . . . . . . . . . . . . . . . . . 142

6.2.1 Global interconnect characteristics . . . . . . . . . . . 1446.2.2 Scaling of the grid inductance . . . . . . . . . . . . . . . 1446.2.3 Flip-chip packaging characteristics . . . . . . . . . . . 1456.2.4 Impact of on-chip capacitance . . . . . . . . . . . . . . . 147

6.3 Model of power supply noise . . . . . . . . . . . . . . . . . . . . . . 1486.4 Power supply noise scaling . . . . . . . . . . . . . . . . . . . . . . . 150

6.4.1 Analysis of constant metal thickness scenario . . 1506.4.2 Analysis of the scaled metal thickness scenario 1516.4.3 ITRS scaling of power noise . . . . . . . . . . . . . . . . . 153

6.5 Implications of noise scaling . . . . . . . . . . . . . . . . . . . . . . 1576.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Part II Design of Power Systems

8 High Performance Power Distribution Systems . . . . 1658.1 Physical structure of a power distribution system . . . . 1668.2 Circuit model of a power distribution system . . . . . . . 1678.3 Output impedance of a power distribution system . . . 1708.4 A power distribution system with a decoupling

capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

X Contents

8.4.1 Impedance characteristics . . . . . . . . . . . . . . . . . . . 1738.4.2 Limitations of a single-tier decoupling scheme . 177

8.5 Hierarchical placement of decoupling capacitance . . . . 1798.6 Resonance in power distribution networks . . . . . . . . . . 1868.7 Full impedance compensation . . . . . . . . . . . . . . . . . . . . . 1928.8 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948.9 Design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

8.9.1 Inductance of the decoupling capacitors . . . . . . 1978.9.2 Interconnect inductance . . . . . . . . . . . . . . . . . . . . 198

8.10 Limitations of the one-dimensional circuit model . . . . 1998.11 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

9 On-Chip Power Distribution Networks . . . . . . . . . . . . 2039.1 Styles of on-chip power distribution networks . . . . . . . 204

9.1.1 Basic structure of on-chip power distributionnetworks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

9.1.2 Improving the impedance characteristics ofon-chip power distribution networks . . . . . . . . . . 209

9.1.3 Evolution of power distribution networks inAlpha microprocessors . . . . . . . . . . . . . . . . . . . . . 210

9.2 Die-package interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2129.3 Other considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2179.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

10 Computer-Aided Design and Analysis . . . . . . . . . . . . . 22110.1 Design flow for on-chip power distribution networks . 22210.2 Linear analysis of power distribution networks . . . . . . 22710.3 Modeling power distribution networks . . . . . . . . . . . . . 22910.4 Characterizing the power current requirements of

on-chip circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23610.5 Numerical methods for analyzing power distribution

networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23810.6 Allocation of on-chip decoupling capacitors . . . . . . . . . 245

10.6.1 Charge-based allocation methodology . . . . . . . . 24710.6.2 Allocation strategy based on the excessive noise

amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24810.6.3 Allocation strategy based on excessive charge . 249

10.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Contents XI

11 Closed-Form Expressions for Fast IR Drop Analysis 25311.1 Background of FAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25411.2 Analytic IR drop analysis . . . . . . . . . . . . . . . . . . . . . . . . 256

11.2.1 One power supply and one current load . . . . . . . 25711.2.2 One power supply and multiple current loads . . 25911.2.3 Multiple power supplies and one current load . . 26011.2.4 Multiple power supplies and multiple current

loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26311.3 Locality in power grid analysis . . . . . . . . . . . . . . . . . . . . 265

11.3.1 Principle of spatial locality in a power grid . . . . 26511.3.2 Effect of spatial locality on computational

complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26911.3.3 Exploiting spatial locality in FAIR . . . . . . . . . . . 27011.3.4 Error correction windows . . . . . . . . . . . . . . . . . . . 271

11.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27211.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

12 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Part III Noise in Power Distribution Networks

13 Inductive Properties of On-Chip Power DistributionGrids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28513.1 Power transmission circuit . . . . . . . . . . . . . . . . . . . . . . . . 28513.2 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28813.3 Grid types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28813.4 Inductance versus line width . . . . . . . . . . . . . . . . . . . . . . 29313.5 Dependence of inductance on grid type . . . . . . . . . . . . 294

13.5.1 Non-interdigitated versus interdigitated grids . . 29413.5.2 Paired versus interdigitated grids . . . . . . . . . . . . 295

13.6 Dependence of Inductance on grid dimensions . . . . . . . 29613.6.1 Dependence of inductance on grid width . . . . . . 29613.6.2 Dependence of inductance on grid length . . . . . 29813.6.3 Sheet inductance of power grids . . . . . . . . . . . . . 29813.6.4 Efficient computation of grid inductance . . . . . . 299

13.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

XII Contents

14 Variation of Grid Inductance with Frequency . . . . . 30314.1 Analysis approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30314.2 Discussion of inductance variation . . . . . . . . . . . . . . . . . 305

14.2.1 Circuit models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30514.2.2 Analysis of inductance variation . . . . . . . . . . . . . 308

14.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

15 Inductance/Area/Resistance Tradeoffs . . . . . . . . . . . . 31315.1 Inductance vs. resistance tradeoff under a constant grid

area constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31315.2 Inductance vs. area tradeoff under a constant grid

resistance constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31815.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

16 Inductance Model of Interdigitated Power andGround Distribution Networks . . . . . . . . . . . . . . . . . . . . 32316.1 Basic four-pair structure . . . . . . . . . . . . . . . . . . . . . . . . . 32416.2 Power and ground distribution network with a large

number of interdigitated pairs . . . . . . . . . . . . . . . . . . . . 32516.3 Comparison and discussion . . . . . . . . . . . . . . . . . . . . . . . 33016.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

17 On-Chip Power Noise Reduction Techniques . . . . . . 33717.1 Ground noise reduction through an additional low noise

on-chip ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33917.2 Dependence of ground bounce reduction on system

parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34117.2.1 Physical separation between noisy and noise

sensitive circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 34217.2.2 Frequency and capacitance variations . . . . . . . . 34317.2.3 Impedance of an additional ground path . . . . . . 345

17.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

18 Noise Issues in On-Chip Power DistributionNetworks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34918.1 Scaling effects in chip-package resonance . . . . . . . . . . . 35018.2 Propagation of power distribution noise . . . . . . . . . . . . 35218.3 Local inductive behavior . . . . . . . . . . . . . . . . . . . . . . . . . 35518.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Contents XIII

19 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Part IV Placement of On-Chip Decoupling Capacitance

20 Effective Radii of On-Chip Decoupling Capacitors 36720.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36920.2 Effective radius of on-chip decoupling capacitor based

on target impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37120.3 Estimation of required on-chip decoupling capacitance 373

20.3.1 Dominant resistive noise . . . . . . . . . . . . . . . . . . . . 37420.3.2 Dominant inductive noise . . . . . . . . . . . . . . . . . . . 37520.3.3 Critical line length . . . . . . . . . . . . . . . . . . . . . . . . . 378

20.4 Effective radius as determined by charge time . . . . . . . 38020.5 Design methodology for placing on-chip decoupling

capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38620.6 Model of on-chip power distribution network . . . . . . . . 38620.7 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38920.8 Design implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39520.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

21 Efficient Placement of Distributed On-ChipDecoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39921.1 Technology constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 40021.2 Placing on-chip decoupling capacitors in nanoscale ICs 40121.3 Design of a distributed on-chip decoupling capacitor

network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40421.4 Design tradeoffs in a distributed on-chip decoupling

capacitor network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40921.4.1 Dependence of system parameters on R1 . . . . . . 41021.4.2 Minimum C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41121.4.3 Minimum total budgeted on-chip decoupling

capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41221.5 Design methodology for a system of distributed on-chip

decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41421.6 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41721.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

XIV Contents

22 Simultaneous Co-Design of Distributed On-ChipPower Supplies and Decoupling Capacitors . . . . . . . . 42322.1 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42522.2 Simultaneous power supply and decoupling capacitor

placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42622.3 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42822.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

23 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Part V Multi-Layer Power Distribution Networks

24 Impedance Characteristics of Multi-Layer Grids . . 43924.1 Electrical properties of multi-layer grids . . . . . . . . . . . . 441

24.1.1 Impedance characteristics of individual gridlayers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

24.1.2 Impedance characteristics of multi-layer grids . 44424.2 Case study of a two layer grid . . . . . . . . . . . . . . . . . . . . 446

24.2.1 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . 44724.2.2 Inductive coupling between grid layers . . . . . . . . 44724.2.3 Inductive characteristics of a two layer grid . . . 45124.2.4 Resistive characteristics of a two layer grid . . . . 45224.2.5 Variation of impedance with frequency in a two

layer grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45424.3 Design implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45524.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

25 Multi-Layer Interdigitated Power DistributionNetworks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45925.1 Single metal layer characteristics . . . . . . . . . . . . . . . . . . 461

25.1.1 Optimal width for minimum impedance . . . . . . 46325.1.2 Optimal width characteristics . . . . . . . . . . . . . . . 466

25.2 Multi-layer optimization . . . . . . . . . . . . . . . . . . . . . . . . . 46925.2.1 First approach - equal current density . . . . . . . . 47025.2.2 Second approach - minimum impedance . . . . . . 476

25.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47825.3.1 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47825.3.2 Routability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47925.3.3 Fidelity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Contents XV

25.3.4 Critical frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 48325.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

26 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

Part VI Multi-Voltage Power Network Systems

27 Multiple On-Chip Power Supply Systems . . . . . . . . . 49327.1 ICs with multiple power supply voltages . . . . . . . . . . . 494

27.1.1 Multiple power supply voltage techniques . . . . . 49527.1.2 Clustered voltage scaling (CVS) . . . . . . . . . . . . . 49727.1.3 Extended clustered voltage scaling (ECVS) . . . 498

27.2 Challenges in ICs with multiple power supply voltages 49927.2.1 Die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50027.2.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 50027.2.3 Design complexity . . . . . . . . . . . . . . . . . . . . . . . . . 50127.2.4 Placement and routing . . . . . . . . . . . . . . . . . . . . . 501

27.3 Optimum number and magnitude of available powersupply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

27.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

28 On-Chip Power Distribution Grids with MultipleSupply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51128.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51328.2 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51428.3 Power distribution grid with dual supply and dual

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51628.4 Interdigitated grids with DSDG . . . . . . . . . . . . . . . . . . . 519

28.4.1 Type I interdigitated grids with DSDG . . . . . . . 51928.4.2 Type II interdigitated grids with DSDG . . . . . . 521

28.5 Paired grids with DSDG . . . . . . . . . . . . . . . . . . . . . . . . . 52328.5.1 Type I paired grids with DSDG . . . . . . . . . . . . . 52428.5.2 Type II paired grids with DSDG. . . . . . . . . . . . . 525

28.6 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52828.6.1 Interdigitated power distribution grids without

decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . 52928.6.2 Paired power distribution grids without

decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . 536

XVI Contents

28.6.3 Power distribution grids with decouplingcapacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

28.6.4 Dependence of power noise on the switchingfrequency of the current loads . . . . . . . . . . . . . . . 541

28.7 Design implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54428.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

29 Decoupling Capacitors for Multi-Voltage PowerDistribution Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54929.1 Impedance of a power distribution system . . . . . . . . . . 551

29.1.1 Impedance of a power distribution system . . . . 55229.1.2 Antiresonance of parallel capacitors . . . . . . . . . . 55529.1.3 Dependence of impedance on power distribution

system parameters . . . . . . . . . . . . . . . . . . . . . . . . . 55629.2 Case study of the impedance of a power distribution

system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55929.3 Voltage transfer function of power distribution system 564

29.3.1 Voltage transfer function of a power distributionsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

29.3.2 Dependence of voltage transfer function on powerdistribution system parameters . . . . . . . . . . . . . . 566

29.4 Case study of the voltage response of a powerdistribution system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56929.4.1 Overshoot-free magnitude of a voltage transfer

function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57129.4.2 Tradeoff between the magnitude and frequency

range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57329.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

30 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Part VII Final Comments and Supplementary Material

Closing Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Appendices

A Estimate of Initial Optimal Width for InterdigitatedPower/Ground Network . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Contents XVII

B First Optimization Approach for Multi-LayerInterdigitated Power Distribution Network . . . . . . . . 593

C Second Optimization Approach for Multi-LayerInterdigitated Power Distribution Network . . . . . . . . 595

D Mutual Loop Inductance in Fully InterdigitatedPower Distribution Grids with DSDG . . . . . . . . . . . . . 597

E Mutual Loop Inductance in Pseudo-InterdigitatedPower Distribution Grids with DSDG . . . . . . . . . . . . . 599

F Mutual Loop Inductance in Fully Paired PowerDistribution Grids with DSDG . . . . . . . . . . . . . . . . . . . . 601

G Mutual Loop Inductance in Pseudo-Paired PowerDistribution Grids with DSDG . . . . . . . . . . . . . . . . . . . . 603

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

About the Authors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

1

Preface to the Second Edition

The first planar circuit was fabricated by Fairchild Semiconductor Com-pany in 1959. Since then, the evolution of the integrated circuit hasprogressed, now providing billions of transistors on a single monolithicsubstrate. These integrated circuits are an integral and nearly essentialpart of our modern life. The power consumed by a typical 20×20 mm2

microprocessor is in the range of several hundreds of watts, makingintegrated circuits one of the highest power consumers per unit area.With such a high rate of power consumption, the problem of deliveringpower on-chip has become a fundamental issue. The focus of this bookis on distributing power within high performance integrated circuits.

In 2004, the book titled Power Distribution Networks in High SpeedIntegrated Circuits by A. V. Mezhiba and E. G. Friedman was publishedto describe, for the first time in book form, the design and analysis ofpower distribution networks within integrated circuits. The book de-scribed different aspects of on-chip power distribution networks, start-ing with a general introduction and ending with a discussion of var-ious design tradeoffs in on-chip power distribution networks. Later,the important and highly relevant topic of decoupling capacitance wasadded to this book. Due to the significant change in size and focus,the book was released in 2008 as a new first edition with a new ti-tle, Power Distribution Networks with On-Chip Decoupling Capacitorsby M. Popovich, A. V. Mezhiba, and E. G. Friedman. Since this re-vised book was published, new design and analysis challenges in on-chippower networks have emerged.

The rapidly evolving field of integrated circuits has required aninnovative perspective on on-chip power generation and distribution,shifting the authors’ research focus to these new challenges. Updating

XX Preface to the Second Edition

knowledge on chip-based power distribution networks is the primarypurpose for publishing a second edition of Power Distribution Networkswith On-Chip Decoupling Capacitors. Focus is placed on complexity is-sues related to power distribution networks, developing novel designmethodologies and providing solutions for specific design and analysisissues. In this second edition, the authors have revised and updated pre-viously published chapters and added four new chapters to the book.This second edition has also been partitioned into sub-areas (calledParts) to provide a more intuitive flow to the reader.

The organization of the book is now separated into seven parts.A general background, introducing power networks, inductive prop-erties, electromigration, and decoupling capacitance within integratedcircuits, is provided in Part I (Chapters 1 to 7). In Part II (Chapters 8to 12), the design of on-chip power distribution networks is discussed.Since noise within the power grid is a primary design constraint, thisissue is reviewed in Part III (Chapters 13 to 19). In Part IV (Chap-ters 20 to 23), the primary issue of placing on-chip decoupling capaci-tors is discussed. Multi-layer power distribution networks are the focusof Part V (Chapters 24 to 26). In Part VI (Chapter 27 to 30), multiplepower supply systems are described. The focus of this part is on thoseintegrated circuits where several on-chip power supplies are required. InPart VII, some concluding comments, the appendices, and additionalinformation are provided.

This revised and updated material is based on recent research byRenatas Jakushokas and Selcuk Kose developed between 2005 and 2010at the University of Rochester during their doctoral studies under thesupervision of Prof. Eby G. Friedman. The emphasis of these newlyadded chapters is on the complexity of power distribution networks.Models for commonly used meshed and interdigitated interconnectstructures are described. These models can be used to accurately andefficiently estimate the resistance and inductance of complex power dis-tribution networks. With these models, on-chip power networks can beefficiently analyzed and designed, greatly enhancing the performanceof the overall integrated circuit.

The book covers a wide spectrum of issues related to on-chip powerdistribution networks. The authors believe that this revised editionprovides the latest information into what is a quickly changing andhighly important topic to both the industrial and academic researchand development communities.

Preface to the Second Edition XXI

Acknowledgments

The authors would like to thank Charles Glaser from Springer for mak-ing this book a reality. The authors are also grateful to Dr. Sankar Basuof the National Science Foundation for his support over many years.We are sincerely thankful to Dr. Emre Salman for endless conversationsand discussions, leading to novel research ideas and solutions.

This research has been supported in part by the National ScienceFoundation under Grant Nos. CCF-0541206, CCF-0811317, and CCF-0829915, grants from the New York State Office of Science, Technol-ogy and Academic Research to the Center for Advanced Technologyin Electronic Imaging Systems, and by grants from Intel Corporation,Eastman Kodak Company, and Freescale Semiconductor Corporation.

Rochester, New York Renatas JakushokasSan Diego, California Mikhail PopovichHillsboro, Oregon Andrey V. MezhibaRochester, New York Selcuk KoseRochester, New York Eby G. Friedman

September 2010

2

Preface to the First Edition

The purpose of this book is to provide insight and intuition into thebehavior and design of power distribution systems with decoupling ca-pacitors for application to high speed integrated circuits. The primaryobjectives are threefold. First, to describe the impedance characteris-tics of the overall power distribution system, from the voltage regula-tor through the printed circuit board and package onto the integratedcircuit to the power terminals of the on-chip circuitry. The second ob-jective of this book is to discuss the inductive characteristics of on-chippower distribution grids and the related circuit behavior of these struc-tures. Finally, the third primary objective is to present design method-ologies for efficiently placing on-chip decoupling capacitors in nanoscaleintegrated circuits.

Technology scaling has been the primary driver behind the amaz-ing performance improvement of integrated circuits over the past sev-eral decades. The speed and integration density of integrated circuitshave dramatically improved. These performance gains, however, havemade distributing power to the on-chip circuitry a difficult task. Highlydense circuitry operating at high clock speeds have increased the dis-tributed current to many tens of amperes, while the noise margin ofthe power supply has shrunk consistent with decreasing power supplylevels. These trends have elevated the problems of power distributionand allocation of the on-chip decoupling capacitors to the forefront ofseveral challenges in developing high performance integrated circuits.

This book is based on the body of research carried out by MikhailPopovich from 2001 to 2007 and Andrey V. Mezhiba from 1998 to2003 at the University of Rochester during their doctoral studies un-der the supervision of Professor Eby G. Friedman. It is apparent to

XXIV Preface to the First Edition

the authors that although various aspects of the power distributionproblem have been addressed in numerous research publications, notext exists that provides a unified focus on power distribution systemsand related design problems. Furthermore, the placement of on-chipdecoupling capacitors has traditionally been treated as an algorithmicoriented problem. A more electrical perspective, both circuit modelsand design techniques, has been used in this book for presenting howto efficiently allocate on-chip decoupling capacitors. The fundamentalobjective of this book is to provide a broad and cohesive treatment ofthese subjects.

Another consequence of higher speed and greater integration den-sity has been the emergence of inductance as a significant factor in thebehavior of on-chip global interconnect structures. Once clock frequen-cies exceeded several hundred megahertz, incorporating on-chip induc-tance into the circuit analysis process became necessary to accuratelydescribe signal delays and waveform characteristics. Although on-chipdecoupling capacitors attenuate high frequency signals in power distri-bution networks, the inductance of the on-chip power interconnect isexpected to become a significant factor in multi-gigahertz digital cir-cuits. An important objective of this book, therefore, is to clarify theeffects of inductance on the impedance characteristics of on-chip powerdistribution grids and to provide an understanding of related circuitbehavior.

The organization of the book is consistent with these primary goals.The first eight chapters provide a general description of distributingpower in integrated circuits with decoupling capacitors. The challengesof power distribution are introduced and the principles of designingpower distribution systems are described. A general background to de-coupling capacitors is presented followed by a discussion of the use of ahierarchy of capacitors to improve the impedance characteristics of thepower network. An overview of related phenomena, such as inductanceand electromigration, is also presented in a tutorial style. The followingseven chapters are dedicated to the impedance characteristics of on-chippower distribution networks. The effect of the interconnect inductanceon the impedance characteristics of on-chip power distribution networksis investigated. The implications of these impedance characteristics oncircuit behavior are also discussed. On-chip power distribution gridsare described, exploiting multiple power supply voltages and multiplegrounds. Techniques and algorithms for the computer-aided design and

Preface to the First Edition XXV

analysis of power distribution networks are also described; however, theemphasis of the book is on developing circuit intuition and understand-ing the electrical principles that govern the design and operation ofpower distribution systems. The remaining five chapters focus on thedesign of a system of on-chip decoupling capacitors. Methodologies fordesigning power distribution grids with on-chip decoupling capacitorsare also presented. These techniques provide a solution for determiningthe location and magnitude of the on-chip decoupling capacitance tomitigate on-chip voltage fluctuations.

Acknowledgments

The authors would like to thank Alex Greene and Katelyn Stanne fromSpringer for their support and assistance. We are particularly thankfulto Bill Joyner and Dale Edwards from the Semiconductor ResearchCorporation, and Marie Burnham, Olin Hartin, and Radu Secareanufrom Freescale Semiconductor Corporation for their continued supportof the research project that culminated in this book. The authors wouldalso like to thank Emre Salman for his corrections and suggestions onimproving the quality of the book. Finally, we are grateful to MichaelSotman and Avinoam Kolodny from Technion — Israel Institute ofTechnology for their collaboration and support.

The original research work presented in this book was made possiblein part by the Semiconductor Research Corporation under ContractNos. 99–TJ–687 and 2004–TJ–1207, the DARPA/ITO under AFRLContract F29601–00–K–0182, the National Science Foundation underContract Nos. CCR–0304574 and CCF–0541206, grants from the NewYork State Office of Science, Technology & Academic Research to theCenter for Advanced Technology in Electronic Imaging Systems, andby grants from Xerox Corporation, IBM Corporation, Lucent Tech-nologies Corporation, Intel Corporation, Eastman Kodak Company,Intrinsix Corporation, Manhattan Routing, and Freescale Semiconduc-tor Corporation.

Rochester, New York Mikhail Popovich and Eby G. FriedmanHillsboro, Oregon Andrey V. Mezhiba

June 2007