CEMC IAB Meeting

May 8-10, 2012

University/Center Confidential

Power Integrity Concepts for High-Speed Design on Multi-

Layer PCBsChulsoon Hwang

Missouri EMC Laboratoryhwangc@mst.edu

PI - 2

● The PDN problem and some preliminaries– What PI design impacts– Design choices– A quick reminder of

circuit element behavior with frequency current physics

● Charge delivery physics for PI design ● Why Ztarget is used – an FPGA example● PDN design – multi-layer PCBs with power layer area

fills● Design flow for package/PCB PI co-design

PI Module – Physics

PI - 3

PDN ProblemHigh-speed, integrated, and mixed electronic system

IC DiePKG

VRM JitterDecap

3D IC

Effect of PDN noise on I/O jitter

IC EMI source model?

Power Distribution Network

Power Distribution Network• VRM• Decoupling capacitors • Power net area fills

PI - 4

Geometry and Inductance Decomposition

GND1GND2

GND3

GND4

GND5

GND6

PWR

Silicon Die

Frequency

|ZPD

N|

CDecapLPCB_EQ CPlane

LPCB_IC

LPCB_IC

Labove

Labove

LPCB_DecapLPCB_Decap

LPCB_Decap

LPCB_Plane

Labove

VDD

Time

Vripple

Voltage

PI - 5

2a. Decoupling capacitors• top• bottom,• beneath IC?

IC

IC pins

Decaps1.Power plane(s)• location in stack• spacing to power

return plane• total area fill• special materials

Effect of other ground/reference

planes?

PWRGND

2b. Decoupling capacitor connection -• PWR/GND via

geometry• Package size

2c. Decoupling capacitor layout• How close to IC?• Shape – ring IC, on

one side?

2a. Decoupling capacitors• value(s)• Number (total C)

3. IC PWR/GND• Number pins• pin pattern• Pitch• on-package decaps

PCB PDN Design Considerations

PI - 6

Reminder – Circuit Model Behavior with Frequency

6

Z

Z Z

Z( )Z dBΩ

( )Z dBΩ

( )Z dBΩ

( )Z dBΩ

PI - 7

Reminder: Current Behavior

Conduction current – carried by electrons

Displacement current – carried bydispl

dEJdt

ε=

condJ Eσ=

+-

Signal

GND

Model with lumped elements if geometry

electrically short

impeded by

admitted by

Current on a line for high-speed data

PI - 8

● The PDN problem and some preliminaries● Charge delivery physics for PI design ● Why Ztarget is used – an FPGA example● PDN design – multi-layer PCBs with power layer area

fills● Design flow for package/PCB PI co-design

PI Module – Physics

PI - 9

switch IC loadICdriver

VDC

GND

CL

VCC

Z0, vp

GND

IC loadICdriver

VCC

VCC

charge

LO to HI

Z0, vp

shoot-thru current

IC loadICdriver

GND

VCC

0 V

discharge

HI to LO

Z0, vp

shoot-thru current

Shoot-thru current (and everything else we can’t account for)

Load charging currentLoad discharge current

Logic Transitions and Current Draw

This charge to support IC switching must be provided by the PDN – package, PCB

PI - 10

Voltage Switching/Dynamic Current Draw Distrubances

Dynamic current on power net causes disturbance and can lead to faulty switching, a source of jitter, and trouble in general

1

0

T1 and T2 are not simultaneous

GND

IC load

ICdriver

VPWR

VCC

charging currentVPWR+VNoise

shoot thru currenta trouble-maker

T1

T2

vL

ist

ilogic

iIC

banks of transistors for the PMOS and NMOS not perfectly synchronized

PI - 11

Bottom decoupling capacitors

ICGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PWR

IC Top decoupling capacitorsLooking from the IC

Decoupling capacitors sharing IC vias

The Objective and Guiding Physics:Conduction Current Path results in Inductance

PI - 12

ICGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PWR

IC Top decoupling capacitorsLooking from the IC

Decoupling capacitors sharing IC vias Bottom decoupling capacitors

The Objective and Guiding Physics:Condution Current Path results in Inductance

PI - 13

Key Point – Current Path and Inductance

ICGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PWR

IC Top decoupling capacitorsLooking from the IC

Decoupling capacitors sharing IC vias

Bottom decoupling capacitors

( )PCB inZ jω−

pkg-to-PWR planes

caps-to-PWR planes

in PWR planes

Four contributions (current path pieces) to the ZPDN inductance

Above PCB to decaps

PI - 14

And a (relatively) Simple ZPDN

The Objective and Guiding Physics:Current Path results in Inductance

10-4 10-2 100

10-2

100

102

Frequency[GHz]

Inpu

t Im

peda

nce

at I

C P

ort [Ω

]

|ZIN|- 17 IC Power Pins

Step1Step2Step3

targetZ

PDNZ

LPCB_EQ

LPCB_IC

Due to viasin PCB connecting package to PCB PDN area fills

LPCB_IC + L due to all parallel paths for decoupling capacitors

1 decap19 decaps43 decaps

( )PDNZ Ω

Engineer LPCB_IC and LPCB_EQ to meet the target impedance

PCB Example (no package or

die here)

increasing parallel paths,decreasing inductance

PI - 15

Ideally for PDN Design

3. THEN the PCB/package PDN ZPDN(jω) can be engineered to meet noise voltage specifications

2. Calculate the dynamic current draw

1. Develop noise voltage specifications for the PCB or at the package connections (specs in TD, but can transform to FD)

( )( ) ( )PDN ICV Z Iω ω ω= ×

• Plane stackup, area fills, materials• Number of decoupling capacitors• Location, pattern, values and package

size of SMT decoupling capacitors

PI - 16

The Reality for Dynamic Current Draw

IIC(jω)

(source)

x

Determining the dynamic current draw is difficult

• Tool – in-house or commercial• Approximate current draw

waveform – pulse width, pulse amplitude, pulse sequence

and then specify Ztarget

( ) ( ){ }1PDN PDNv t F V jω−=( )( ) ( )PDN PDN ICV Z Iω ω ω= ×

0 50 100 150-20

-15

-10

-5

0

5

10

15

Time [ns]

Volta

ge [m

V]

CalculationMeasurement

|ZPDN(jω)|

PI - 17

Engineering |ZPDN(jω)| - the Alternative

Choices for PCB PDN design• Layer stackup, area fill dimensions, and plane separation (maybe)• Number, value, pattern, location (top/bottom), proximity

work at these design decisions with a limited knowledge of IIC(ω)

Select |ZPDN(jω)| to meet noise voltage specifications

( )( ) ( )PDN PDN ICV Z Iω ω ω= ×

The concept of target impedance – not entirely satisfactory, but since the physics are dominated by inductance, there will be a limiting value.

10-4

10-2

10010

-3

10-2

10-1

100

101

102

Frequency[GHz]

Inpu

t Im

peda

nce

at IC

por

t [Ω

]

43 Capacitors

eq planes decouplingC C C= +

highL

EQ high planes Decaps ijL L L L M= + + +

targetZ28 layer PCB design

PI - 18

Key Point – Use Ztarget for Design

● Design choices (related to geometry)

– Layer of power net area fill on PCB (and GND power return)

– Decoupling capacitorswill be driven by achieving a specified Ztarget

• The PDN impedance behavior in frequency is dominated by inductance (with some lumped element resonances) and use design choices to lower inductance in a frequency range corresponding to current path geometry

10-4 10-2 100

10-2

100

102

Frequency[GHz]

Inpu

t Im

peda

nce

at I

C P

ort [Ω

]

|ZIN|- 17 IC Power Pins

Step1Step2Step3

targetZ

IC19 Decoupling capacitors at the top

7 Decoupling capacitors at the Bottom

17 Decoupling capacitors Sharing IC vias

PDNZ

PDNZ

PI - 19

● The PDN problem and some preliminaries● Charge delivery physics for PI design ● PDN design – multi-layer PCBs with power layer area

fills● Design flow for package/PCB PI co-design● an FPGA example

PI Module – Physics

PI - 20

Power Plane and Capacitor Location Matrix

PI - 21

Lhigh – Power Plane Location in Layer Stack

10-4 10-2 10010-4

10-2

100

102

[GHz]

Ω

|Z11| - Bottom Caps - Under the IC

TopMidBottom

Power plane at Top

Power plane Middle

Power plane Bottom

( )PDNZ Ω

Decreasing current path and inductance from package

balls to PDN power layer net

PDNZ

Power layer closest to the IC minimizes IC to power plane inductance. (Recall that jωLPCB_IC is the impedance limit above a few MHz.)

?

LPCB_IC

PI - 22

Capacitor Location – Top, Bottom, at IC

10-4 10-2 10010-4

10-2

100

102

[GHz]

Ω

|Z11|- Top Pwr

Top CapBottom Cap-AwayBottom Cap- Under the IC

PDNZ

10-4 10-2 10010-4

10-2

100

102

[GHz]

Ω

|Z11| - Middle PWR

Top CapBottom Cap-AwayBottom Cap- Under the IC

LPCB_EQ

PDNZ

Capacitors placed on the side closest to the power plane reduces the inductance from the capacitor to power plane and LEQ. The current path length/area is smallest.

LPCB_IC

LPCB_IC

LPCB_EQ

PI - 23

LEQ – Power Plane Location in Layer Stack

LPCB_EQ is also decreasing because the L from the decoupling capacitors to the power planes AND the package balls to the power planes is decreasing

Power planes – top Power planes – mid Power planes – bottom

10-4 10-2 10010-4

10-2

100

102

[GHz]

Ω

|Z11| - Top Cap

TopMidBottom

Power plane at Top

Power plane Middle

Power plane Bottom

PDNZ

LPCB_EQ

LPCB_IC

PI - 24

Key Points

10-4 10-2 100

10-2

100

102

Frequency[GHz]

Inpu

t Im

peda

nce

at IC

Por

t [Ω

]

IN

Circuit Model ResultsMeasurements

● The shape of the ZPDN curve is relatively simple, even though the geometry of the PDN on a multi-layer PCB is complicated

● The current-path physics governing the impedance are dominated by inductance and lumped element resonances above approximately 1 MHz

● The inductance is dominated by the current path – geometry “length/area” (series inductance), and the number of parallel paths (parallel inductance) and this will drive the design approach (“small loops and many loops”)

• Where power layers are located in stackup• Package ball pitch• Decoupling capacitor interconnect

• Number of PWR/GND vias in package• Number of decoupling capacitors

PI - 25

● The PDN problem and some preliminaries● Charge delivery physics for PI design ● PDN design – multi-layer PCBs with power layer area

fills● SMT decoupling● Design flow for package/PCB PI co-design

PI Module – Physics

PI - 26

● Use an array of capacitor values: – This may be the best known approach in the signal integrity

design community– Rationale: to maintain a flat impedance profile below a target

impedance over a wide frequency range– Typically a logarithmically spaced (10, 22, 47, 100, 220, 470nF,

etc.) array of 3 values per decade.

● Use a large capacitor value in the package size– This is less well-known, but an approach in the EMI design

community– Rationale: to keep impedance as low as possible, less emphasis

on a target impedance and a flat profile

Two Approaches for SMT Decoupling

PI - 27

Decoupling Strategy – Geometry

GND (PWR Return)PWR

9 in.

6 in.

t=10 mils.tan δ = 0.02εr=4.5

PI - 28

• Approach A : values of decoupling capacitors logarithmically spaced, i.e. 3 values per decade: 10, 22, 47, 100, etc.

• Approach B : largest values of decoupling available in two package sizes, i.e., 0603 and 0402

• Approach B1 : largest values of decoupling available in one package size, i.e., 0402.

Target Impedance

Both approaches can meet the design specs relative to the target impedance

Approaches for SMT Decoupling ValuesPDNZ

PI - 29

Practices for Mounting SMT Capacitors

best ok poor

Adding trace length, adds inductance to the interconnect:• “loop area” above the planes – Labove• Area between the power and GND return vias vertically

connecting to the PWR planes

PWR via

GND via

PWR current

Return current

Decoupling Capacitor

PWR

d

GND

Labove

practical IC GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

PWR

IC Top decoupling capacitorsLooking from the IC

Decoupling capacitors sharing IC vias

pkg-to-PWR planes

caps-to-PWR planes

in PWR planes

Above PCB to decaps

PI - 30

10-4 10-2 10010-3

10-2

10-1

100

101

102

Frequency[GHz]

Inpu

t Im

peda

nce

at IC

por

t [Ω

]

Step1 - 1 CapacitorStep2 - 19 CapacitorsStep3 - 43 Capactors

eq planes decouplingC C C= +

_PCB ICL

_ _EQ PCB IC planes PCB Decaps ijL L L L M= + + +

Design Geometry, Current Path, and ZPDN

PI - 31

• PWR/GND plane pair nearer to the IC in stackupwill minimize LPCB_IC from package balls to power net area fill (smaller loop)

• PWR/GND plane pairs closely spaced will reduce LPCB_plane.

• Place caps close to the power layer to minimize the inductance from the capacitor to the power net area fill layer, i.e., LPCB_decaps. (minimize the loop)

Design Implications

LPCB_IC

Target Impedance

Minimal possible L

Frequency

CplaneLPCB_EQCdecap

PI - 32

• Placing caps on the underside of PCB opposite package can benefit the design

– if the path(s) from the package to bottom of the PCB is comparable to the pkg/planes/decappath due to mutual inductance of the via grid power pattern

– Unless the pkg/planes/decap path is shorter due to PWR/GND near package in stackup

• Power and ground vias placed adjacent to the caps reduces the inductance in the current return path (or in the bonding pads). (smaller loops)

• Capacitor arrangements that utilize mutual inductance, e.g., doublet, or 3-terminal capacitor, can significantly reduce LPCB_decaps.

• Using a large capacitance value in a given package size can meet the low-frequency target impedance, and inductance can be reduced by adding more capacitors. (many parallel paths)

Design Implications

PI - 33

● The PDN problem and some preliminaries● Charge delivery physics for PI design ● PDN design – multi-layer PCBs with power layer area

fills● Time-domain and frequency domain through a circuit

model● Design flow for package/PCB PI co-design● an FPGA example

PI Module – Physics

PI - 34

Circuit Model for PCB PDN

INLog Z

( )Log Frequency

CDecapLPCB_EQ

CPlane

3f1f

LPCB_IC RPCB_ICGDiel

LPCB_EQ’ CPlane

REQGDiel+ +

Topologically correct behavioral circuit model

LPCB_ICRIC

GDielCPlane

REQCPCB_decap

LpkgCdie

Rdie LPCB_EQ’_ ' _

_ PCB EQ PCB Decap

above PCB Plane

L LL L

=

+ +

LPCB_IC

Based on physics-based circuit model

GND1

GND3PWRGND4

GND6

GND1

PIC_G1

GND3

+- - +PIC_G2

GND4

GND6

PWR LPCB_Plane

LPCB_IC

LPCB_Decap

LPCB_Decap

LPCB_Decap

Labove

LaboveLaboveLabove

Labove

Labove Labove

LPCB_IC LPCB_Decap

LPCB_Decap LPCB_Decap

LPCB_Plane

PI - 35

Vripple Calculation

VDD

Time

VDD voltage ripple/droop

VoltageVoltage ripple specification

…

( )I ω

f ( )Log frequency

( )inLog Z

×

…

( )V ω

f

Voltage ripple mathematical calculation

Time

Voltage1F −

Switching current profile I

Time

I

Frequency

F1F −

Voltage ripple simulation

LPCB_ICRIC

GDielCPlane

REQCPCB_decap

LpkgCdie

Rdie LPCB_EQ’

PI - 36

Voltage Ripple Separation

0 5 10-0.1

-0.05

0

0.05

0.1

Time [ns]

Volta

ge [V

]

0 2 4 6 8 10 12-0.2

-0.1

0

0.1

0.2Voltage Ripple

Time [ns]

Volta

ge [V

] Vripple_spec

Frequency

LPCB_EQCplaneCdecap

_PCB EQL∆||

PDN

Z

Frequency

LPCB_IC

()

PDN

phaseZ

||

PDN

Z

Minimal possible L

0 5 10-0.2

-0.1

0

0.1

0.2

Time [ns]

Volta

ge [V

]

_ _PCB EQ PCB ICL L−

CPCB_IC

PI - 37

• The PDN problem and some preliminaries• Charge delivery physics for PI design • PDN design – multi-layer PCBs with power

layer area fills• Design flow for package/PCB PI co-design• an FPGA example

PI Module – Appendix

PI - 38

A Systematic Approach for Achieving PI

PDNZ

log10f

pkg viasto IC

pkg+ on-pkg decap

PCB viasto pkg

PCB + board

decoupling

low-frequency capacitance

20 dBdecade no on package

decoupling

On-die capacitance

PI - 39

2a. Decoupling capacitors• top• bottom,• beneath IC?

IC

IC pins

Decaps1.Power plane(s)• location in stack• spacing to power

return plane• total area fill• special materials

Effect of other ground/reference

planes?

PWRGND

2b. Decoupling capacitor connection -• PWR/GND via

geometry• Package size

2c. Decoupling capacitor layout• How close to IC?• Shape – ring IC, on

one side?

2a. Decoupling capacitors• value(s)• Number (total C)

3. IC PWR/GND• Number pins• pin pattern• Pitch• on-package decaps

PCB PDN Design Considerations

PI - 40

Design Flow – Package

Package ball pitchdetermines minimum

achievable high-frequency -----

Choose number (and pattern) PWR/GND

vias to meet high-frequency target impedance for

specified PCB power area fill layer* ------ _PCB ICL→

DC power determines minimum number

power interconnects (IR drop, current)

targetZ

* PCB/package co-design step

On-package decapsreduce minimum overall achievable

high-frequency target impedance seen by

IC

SMT C

Trad

e-of

f

log10f

pkg viasto IC

pkg+ on-pkg decap

PCB viasto pkg

PCB + board

decoupling

low-frequency capacitance

no on package decoupling

On-die capacitance

PI - 41

Design Flow – PCB

IC/ASIC PWR/GND pin-out number (and pattern) determines

minimal ------highL→

Choose PWR/GND area fill layer to meet high-frequency target

impedance -------highL→

Peak voltage ripple/droop determines targetZ

Number of decapsand placement

determines -----

to meet EQL→

targetZ

value of decapsdetermines low-frequency

impedance to meet targetZ

10-4

10-2

10010

-3

10-2

10-1

100

101

102

Frequency[GHz]In

put I

mpe

danc

e at

IC p

ort [

Ω]

43 Capacitors

eq planes decouplingC C C= +

highL

EQ high planes DecapsL L L L M= + + +

targetZ28 layer PCB design0 20 40 60 80 100 120 140 160 180

-30

-20

-10

0

10

20

30

Time [ns]

Volta

ge [m

V]

CalculationMeasurement

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