power lecture
DESCRIPTION
Power LectureTRANSCRIPT
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Power Estimation in DigitalCircuits
ECE4420Reading 5.8
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Average Power ConsumptionOver a Clock Period
+-Vdd
Digital Circuits
Isupply
Pswitching =1
Tclk
Vdd
* Isupply
(t)0
Tclk
! dt = fclk Vdd * Isupply(t)0
Tclk
! dt
Average power per clock period
Understand instantaneous power vs.average power concept!
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Power Components
P = fclk
Vdd * Isupply
0
Tclk
! dt
Dynamic Power Static Power
capacitive switching
short circuit power
glitch power
Leakage currentsDC standby power(e.g. pseudo-nmoscircuits)
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Dynamic Power:Capacitive Switching
Due to charging and discharging of capacitors!
Vdd
+-Vinput
RC modelDissipates 1/2CV2 as heat!
Stores 1/2CV2 on cap!
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Dynamic Power:Capacitive Switching
During discharge event cap energy dissipates asheat through resistor!
Vdd
+-Vinput
RC modelDissipates 1/2CV2 as heat!
Cap is initially charge!
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During a single binary transition dissipates 1/2CV2energy as heat!
Dynamic Power:Capacitive Switching
P
dyn=
1
2CV
dd
2 fclk
To reduce power dissipation Reduce capacitance
Reduce supply voltage Reduce clock frequencyNOTE: I will generally just refer to this component asjust the dynamic power.
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Dynamic Power:CapacitiveSwitching
P = a1
2CV
dd
2fclk
P = !
0"1CV
dd
2fclk
Activity factor 2: fraction of clock periods where the output is switching low-to-high
Activity factor 1: fraction of clock periods where output has a binary transition
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Short Circuit Power Dissipation
+-Vdd+-
Vinput
DC voltage source
Pulse input voltage source with finite risetime, Trise
Vtn
Vdd -|Vtp|
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Short Circuit (SC) PowerDissipation
+-Vdd+-
Vinput
VtnVdd -|Vtp|
Vout
VinVtn Vdd -|Vtp|
Both nFET and pFET areconducting when inputvoltage is in the range.Isc
Isc = short circuit =a.k.a crowbar current
Fast rise and fall times (i.e. edge rates) can reduce SC power
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Definition/Causes of Glitches Glitches are caused by having inputs that are not switching
simultaneously. Glitches occur when the output node temporarily has a value
that is not the steady-state value. Example: Consider OUT=AB when going 01->10 the following
could occur if both inputs do not change simultaneously
A
B
OUT
glitch
01 10
Inputs not changing at the same time so glitch can occur!
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Dynamic Power Glitches Glitches can cause significant dynamic power
dissipation because they represent at leasttwo binary transitions per clock period.
Designer should minimize glitches tominimize dynamic power dissipation.
To minimize glitches one must have signalsarrive at roughly the same time.
Designing equal rise and fall times helps tocontrol this because this CAN help tosynchronize signal arrival times.
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Static PowerSubthreshold leakage currents are the dominate source
(also pn junction leakage)
Ileak
!W
L
Ileak
! e"
VTn
kT /q
Ileak
! (1" e
"VDS
kT /q )
high VT (more like dual VT)
Cool transistors (not practical?)
Minimize size of transistors
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Static Power
Ileak
!W
L Ileak
! e"
VTn
kT /q
Ileak
! (1" e
"VDS
kT /q )
Which has more leakage?
2W
4W
2W
2W
2W
2W
Body bias increase VT
VDS is less than inverter
High VDS es Ileak!
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Clock Period/SwitchingAssumption
+-Vdd+-
Vinput
The following slides assume that we have one binarytransition during a clock period (i.e. glitch free).
t=0 t=Tclk t=2Tclk
Vclk(t)
Vinput(t)
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Static Power Measurements inHSPICE
+-Vdd +-Vdd
Static power low output Static power high output
make these DC voltage sources
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Static power low output Static power high output
Static Power Measurements (staticpowertest.sp).option post INGOLD=2.op.lib 'mos.lib' PMOS130nm.lib 'mos.lib' NMOS130nm.param supply = 1.3Vlowoutput 1 0 'supply'Vhighoutput 3 0 'supply*low outputmn 2 1 0 0 n l=0.130u w=2.0ump 2 1 1 1 p l=0.130u w=3.0u*low inputmn2 4 0 0 0 n l=0.130u w=2.0ump2 4 0 3 3 p l=0.130u w=3.0u.end
For this case, I have put in both circuits in one file so I have specified TWO supply voltages!
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If you use the command : hspice staticpowertest.sp > log
The power supplied by each voltage source is in the log file.
Search for the text in log operating point and you will find the datayou require.
(NOTE: In vi use in command mode type /operating point and it will take you to this next occurrence.)
static power measurements ****** operating point information tnom= 25.000 temp= 25.000 ****** ***** operating point status is all simulation time is 0. node =voltage node =voltage node =voltage
+0:1 = 1.300e+00 0:2 = 1.472e-07 0:3 = 1.300e+00 +0:4 = 1.300e+00
**** voltage sources
subckt element 0:vlowoutp 0:vhighout volts 1.300e+00 1.300e+00 current -3.737e-10 -1.440e-11 power 4.858e-10 1.872e-11
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Low-to-High SC Power
+-Vdd+-
Vinput
low-to-high transitions
ISC
For this case the short circuit current can be determined from the nFET.
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High-to-Low SC Power
+-Vdd+-
Vinput
low-to-high transitions
For this case the short circuit current can be determined from the pFET.
ISC
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HSPICE simulation
EscHL
=Vdd
i(mp)dt
0
Tclk
!
EscLH
=Vdd
i(mn)dt
Tclk
2Tclk
!+-Vdd
+-Vinput
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HSPICE Sample CodeShort Circuit Power Measurements
.option post INGOLD=2
.lib 'mos.lib' PMOS130nm
.lib 'mos.lib' NMOS130nm
.param supply = 1.3Vsupply Vdd 0 'supply'Vinput 1 0 pulse (0 'supply' 0 30p 30p 1n 2n)
mn 2 1 0 0 n l=0.130u w=2.0ump 2 1 Vdd Vdd p l=0.130u w=4.0u
Cout 2 0 100f
.tran 1p 3n
**measure the high-to-low transition.measure tran Q_HL integral i(mp) FROM = 0 TO= 1n.measure high_low_SCenergy param = 'supply*Q_HL'
**measure the low-to-high transition.measure tran Q_LH integral i(mn) FROM = 1n TO= 2n.measure Low_to_high_SCenergy param = 'supply*Q_LH'
.end
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Average Binary SwitchingEnergy per Clock Period
+-Vdd+-
Vinput
Etotal _ HL
=Vdd
i(Vdd
)dt0
Tclk
!
Because we are focused on the output, for this calculation we are ignoring energy from Vinput.
Etotal _ LH
=Vdd
i(Vdd
)dtT
clk
2Tclk
!
E total =
Etotal _ HL
+ Etotal _ LH
2
This represents total energy supplied bypower supply during these time intervals!
HL and LH are from theperspective of the output!
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Average Binary SwitchingPower per Clock Period
+-Vdd+-
Vinput
For this calculation we are ignoring energy from Vinput.
P =Etotal
Tclk
E total =
Etotal _ HL
+ Etotal _ LH
2
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HSPICE CodeTotal Power Measurements.option post INGOLD=2
.lib 'mos.lib' PMOS130nm
.lib 'mos.lib' NMOS130nm
.param supply = 1.3
Vsupply Vdd 0 'supply'Vinput 1 0 pulse (0 'supply' 0 30p 30p 1n 2n)
mn 2 1 0 0 n l=0.130u w=2.0ump 2 1 Vdd Vdd p l=0.130u w=4.0u
Cout 2 0 100f IC = supply
.tran 1p 3n
**measure the high-to-low transition.measure tran Q_HL integral i(Vsupply) FROM = 0 TO= 1n.measure high_low_total_energy param = 'supply*Q_HL'
**measure the low-to-high transition.measure tran Q_LH integral i(Vsupply) FROM = 1n TO= 2n.measure Low_to_high_total_energy param = 'supply*Q_LH'
.print tran v(1) v(2)
.end
Note: Thewords in boldare keywords inHSPICE!
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ResultsTotal Energy
Etotal_HL = 5.127fJ Etotal_LH = 0.1851pJ
Short Circuit EnergyESC_HL = 5.690fJ ESC_LH = 3.265fJ
Leakage Power
Plow = 485.8pW Phigh = 18.72pW
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Calculation of DynamicEnergy with HSPICE
E
total _ LH= E
SC _ LH+ E
dyn _ LH+ E
static _ H
E
total _ HL= E
SC _ HL+ E
dyn _ HL+ E
static _ L
You cannot measure the dynamic power directly withHSPICE; however, you can solve for dynamic componentsbecause all OTHER components are known.
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Average Dynamic Binary SwitchingEnergy per Clock Period
Edyn =
Edyn _ HL
+ Edyn _ LH
2
E
dyn _ LH= E
total _ LH! E
SC _ LH! E
static _ H
E
dyn _ HL= E
total _ HL! E
SC _ HL! E
static _ L
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Calculation of DynamicEnergy with HSPICE
E
total _ LH= E
SC _ LH+ E
dyn _ LH+ P
static _ highT
clk
0.1851pJ = 3.265fJ+ Edyn _ LH
+ (18.72pW)1ns
Edyn _ LH
= 181.83fF
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How does this compare to1/2CV2
Edyn _ LH
= 181.83fF
1
2CV
dd
2= 0.5(100fF)(1.3)2 = 84.5fJ
Because we ignored drain areas in the HSPICE simulationthis should be approximately 1/2 Edyn_LH and it is!
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Calculation of DynamicEnergy with HSPICE
5.127fJ = 5.690fJ+ Edyn _ HL
+ (485.8pW)1ns
Edyn _ HL
= !0.563fJ
E
total _ HL= E
SC _ HL+ E
dyn _ HL+ P
lowT
CLK
WHY IS THIS NEGATIVE? This is due to the feedthroughcurrent that is provided by Vinput! (see next page)
This should be much smaller than the 1/2CVdd (and it is!)because the power supply is not providing energy to thecircuit.. The circuit is discharging energy stored incapacitive node!
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Feedthrough Current
Vdd
+-Vinput
feedthrough current = capacitive current from gate to drain!
feedthrough current cause voltage over/undershoot!
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Average Power Calculation
P total =E
total _ LH+ E
total _ HL
2
Ptotal =5.127fJ +185.1fJ
2
1
1e ! 9= 95.11W