Introduction to 8086

Intel 8086 CPU: An IntroductionIntel 8086 CPU: An Introduction

8086 Features•16-bit Arithmetic Logic Unit

•16-bit data bus

•20-bit address bus - 220 = 1,048,576 = 1 meg

•16-bit registers

•Separate units to fetch and execute instructions

8086 Architecture8086 Architecture• The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU).• The BIU fetches instructions, reads and writes data, and computes the 20-bit address.• The EU decodes and executes the instructions using the 16-bit ALU.• The BIU contains the following registers:

IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to construct the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode.

8086 Block Diagram8086 Block Diagram

The EU contains the following 16-bit registers:

AX - the AccumulatorBX - the Base RegisterCX - the Count RegisterDX - the Data Register

SP - the Stack Pointer

BP - the Base Pointer SI - the Source Index RegisterDI - the Destination Register

These are referred to as general-purpose registers, although, as seen by their names, they often have a special-purpose use for some instructions.

The AX, BX, CX, and DX registers can be considered as two 8-bit registers, a High byte and a Low byte. This allows byte operations and compatibility with the previous generation of 8-bit processors, the 8080 and 8085. The 8-bit registers are:

AX --> AH,ALBX --> BH,BLCX --> CH,CLDX --> DH,DL

8086 Architecture [2]8086 Architecture [2]

Default to stack segment

8086 Architecture [3]8086 Architecture [3]

The EU also contains the Flag Register which is a collection of condition bits and control bits. The condition bits are set or cleared by the execution of an instruction. The control bits are set by instructions to control some operation of the CPU.

Bit 0 - CF Carry Flag - Set by carry out of msbBit 2 - PF Parity Flag - Set if result has even parityBit 4 - AF Auxiliary Flag - for BCD arithmeticBit 6 - ZF Zero Flag - Set if result is zeroBit 7 - SF Sign Flag = msb of resultBit 8 - TF Single Step Trap FlagBit 9 - IF Interrupt Enable FlagBit 10 - DF String Instruction Direction FlagBit 11 - OF Overflow Flag

Bits 1, 3, 5, 12-15 are undefined.

Condition flagsCondition flags• CF (carry flag) — addition sets flag if carry out of MSB generate;

subtraction sets flag if borrow needed.

• PF (parity flag) — set to 1 if low-order 8 bits (low order byte) contain even number of 1’s (that is, gives odd parity)

• AF (auxiliary carry flag) — set if carry out of bit 3 during addition or borrow by bit 3 during subtraction. Used exclusively for BCD arithmetic.

• ZF (zero flag) — set to 1 if result is 0; to 0 if result is nonzero

• SF (sign flag) — equal to MSB of result

• OF (overflow flag) — set if overflow occurs (that is, if carry in to MSB is not equal to carry out from MSB)

ExampleExample• CF (carry flag) — carry out of MSB

• PF (parity flag) — set to 1 if low-order 8 bits (low order byte) contain even number of 1’s

• AF (auxiliary carry flag) —carry out of bit 3

• ZF (zero flag) — set to 1 if result is 0; to 0 if result is nonzero

• SF (sign flag) —MSB of result

• OF (overflow flag) — set if carry in to MSB is not equal to carry out from MSB)

0011 0100 1101 1100

+0000 0111 0010 1110

0011 1100 0000 1010

CF = 0

PF = 1

AF = 1

ZF = 0

SF = 0

OF = 0

Example 2Example 2• CF (carry flag) — carry out of MSB• PF (parity flag) — set to 1 if low-

order 8 bits (low order byte) contain even number of 1’s

• AF (auxiliary carry flag) —carry out of bit 3

• ZF (zero flag) — set to 1 if result is 0; to 0 if result is nonzero

• SF (sign flag) —MSB of result• OF (overflow flag) — set if carry in

to MSB is not equal to carry out from MSB)

1111 1111 1110 0101 +1111 1111 1011 00011 1111 1111 1001 0110

CF = 1

PF = 1

AF = 0

ZF = 0

SF = 1

OF = 0

Control flagsControl flags• TF (trap flag) — if set, a trap is executed after each

instruction

• IF (interrupt enable flag) — if set, a maskable interrupt can be recognized by the CPU; otherwise, these interrupts are ignored.

• DF (direction flag) — used by string manipulation instructions; if clear to 0, then process string from low address to high; if set to 1, then process string from high address to low.

8086 Programmer’s Model8086 Programmer’s Model16-bit Registers16-bit Registers

ESCSSSDSIP

AHBHCHDH

ALBLCLDL

SPBP

SIDI

FLAGS

AXBX

CX

DX

Extra SegmentCode Segment

Stack SegmentData SegmentInstruction Pointer

Accumulator

Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register

BIU registers

(20 bit adder)

EU registers

16 bit arithmetic

8086-80286 extended 32bit Model8086-80286 extended 32bit Model

The special uses of general-purpose registers• EAX—Accumulator for operands and results data.

• EBX—Pointer to data in the DS segment.

• ECX—Counter for string and loop operations.

• EDX—I/O pointer.

• ESI—Pointer to data in the segment pointed to by the DS register; source pointer for string operations.

• EDI—Pointer to data (or destination) in the segment pointed to by the ES register;

destination pointer for string operations.

• ESP—Stack pointer (in the SS segment).

• EBP—Pointer to data on the stack (in the SS segment).

8086 internal registers 16 bits (2 bytes each)8086 internal registers 16 bits (2 bytes each)

AX, BX, CX and DX are twobytes wide and each byte can

be accessed separately

These registers are used as memory pointers.

Segment registers are usedas base address for a segment

in the 1 M byte of memory

Segmented MemorySegmented Memory

Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset

li ne

ar a

ddre

sse

s

one segment

Memory Address GenerationMemory Address Generation

• The BIU has a dedicated adder for determining physical memory addresses

Intel

Physical Address (20 Bits)

Adder

Segment Register (16 bits) 0 0 0 0

Offset Value (16 bits)

Example Address CalculationExample Address Calculation

• If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data?

Intel

Offset: 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

2 9

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment:

0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address:

SegmentsSegments

SegmentRegisters

EXTRA

64K DataSegment

64K Code Segment

CODE

STACK

DATA

MEMORY Address 000000H

0FFFFFH

Segments are < or = 64K,can overlap, start at an addressthat ends in 0H.

CS:0

Segment Starting address is segment register value shifted 4 place to the left.

8086 Memory Terminology8086 Memory Terminology

CODE

DATA

STACK

EXTRA

0100H

0B200H

0CF00H

0FF00H

DS:

SS:

ES:

CS:

001000H

0B2000H

0CF000H

0FF000H

10FFFH

0C1FFFH

0DEFFFH

0FFFFFH

000000HSegment Registers

Memory Segments

Segments are < or = 64K and can overlap.Note that the Code segment is < 64K since 0FFFFFH is the highest address.

The Code SegmentThe Code Segment

The offset is the distance in bytes from the start of the segment.The offset is given by the IP for the Code Segment.Instructions are always fetched with using the CS register.

The physical address is also called the absolute address

000000H

Memory

Segment Register

Offset

Physical orAbsolute Address

0

+

CS:

IP

0400H

0056H

4000H

4056H

0400

0056

04056H

CS:IP = 400:56Logical Address

0FFFFFH

Left-shift 4 bits

The Stack SegmentThe Stack Segment

The offset is given by the SP register.The stack is always referenced with respect to the stack segment register.The stack grows toward decreasing memory locations.The SP points to the last or top item on the stack.

PUSH - pre-decrement the SPPOP - post-increment the SP

Memory

Segment Register

Offset

Physical Address

+

SS:

SP

0A00

0100

0A000H

0A100H

0A00 0

010 0

0A100H

SS:SP

000000H

0FFFFFH

The Data SegmentThe Data Segment

Data is usually fetched with respect to the DS register.The effective address (EA) is the offset.The EA depends on the addressing mode.

Memory

Segment Register

Offset

Physical Address

+

DS:

EA

05C0

0050

05C00H

05C50H

05C0 0

0050

05C50H

DS:EA

000000H

0FFFFFH

COMMON SIGNALS  

NAME FUNCTION TYPE

AD15-AD0 Address/ Data Bus Bidirectional, 3 State

A19/S6-A16/S3 Address/Status Output, 3-State

BHE/ S7 Bus High Enable/ Status Output, 3-State

MN/MX Minimum/Maximum Mode Control Input

RD Read Control Output, 3-State

TEST Wait On Test Control Input

READY Wait State Control Input

RESET System Reset Input

NMI Non-Maskable Interrupt Request Input

INTR Interrupt Request Input

CLK System Clock Input

Vcc (+ 5 V ) Input

GND Ground  

MINIMUM MODE SIGNALS (MN/MX = Vcc )  

NAME FUNCTION TYPE

HOLD Hold Request Input

HOLDA Hold Acknowledge Output

WR Write Control Output, 3-State

M / IO Memory/ IO Control Output, 3-State

DT / R Data Transmit / Receive Output, 3-State

DEN Data Enable Output, 3-State

ALE Address Latch Enable Output

INTA Interrupt Acknowledge Output

 

MAXIMUM MODE SIGNALS (MN/MX = GND )  

NAME FUNCTION TYPE

RQ/GT1, RQ/GT0 Request / Grant Bus Access Control Bidirectional

LOCK Bus Priority Lock Control Output, 3-State

S2 - S0 Bus Cycle Status Output, 3-State

QS1 , QS0 Instruction Queue Status Output