predictive evaluation of electrical characteristics of sub-22nm finfet technologies under device...

Microelectronics Reliability 54 (2014) 2319–2324

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Microelectronics Reliability

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Predictive evaluation of electrical characteristics of sub-22 nm FinFETtechnologies under device geometry variations

http://dx.doi.org/10.1016/j.microrel.2014.07.0230026-2714/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author at: Center of Computer Science, Federal University of RioGrande, Av. Itália km8, Rio Grande 96203900, RS, Brazil. Tel.: +55 (51) 82080344;fax: +55 (51) 3308 7308.

E-mail address: [email protected] (C. Meinhardt).

C. Meinhardt a,b,⇑, A.L. Zimpeck b, R.A.L. Reis b

a Center of Computer Science, Federal University of Rio Grande, Av. Itália km8, Rio Grande 96203900, RS, Brazilb Instituto de Informática, Graduate Program in Computer Science (PPGC), Federal University of Rio Grande do Sul, Bento Gonçalves Av. 9500, Porto Alegre 91501970, RS, Brazil

a r t i c l e i n f o a b s t r a c t

Article history:Received 25 June 2014Accepted 8 July 2014Available online 30 July 2014

Keywords:FinFET devicePredictive technologiesVariability

This work evaluates the impact on ION and IOFF currents of variations in process parameters for a set ofpredictive FinFET technologies from 20 nm to 7 nm. The main contribution of the present study is to iden-tify relevant behavioural standards with respect to the use of FinFET technology in digital designs. It is nolonger enough to focus only on the threshold voltage fluctuations in the development of projects and EDAtools considering the FinFET technology. It is necessary that EDA tools and designers evaluate all electri-cal characteristics.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

The integration capacity of digital circuits has increased signif-icantly in the last decades. This elevated integration factor and thetechnology evolution reaching nanometer scale bring new chal-lenges for Ultra Large-Scale Integration (ULSI) designs as agingeffects, high leakage currents and increase in the number of faults.

One of the most undesired behaviour verified in nanoscale tech-nologies is process variability due to sub-wave-length lithographyfabrication. Each circuit may present a different behaviour due tovariability during manufacturing process, generating deviation ofperformance, abnormal power consumption, accelerating circuitdegradation and making the circuit inappropriate for your particu-lar purpose [1].

CMOS bulk is the most used technology in the manufacturing ofintegrated circuits. However, continued MOSFET transistor scalingwill not be trivial because of fundamental material and processtechnology limits [2]. As the transistor size decreases, CMOS bulktransistors increasingly suffer from the undesirable short-channeleffects (SCE) [3]. In the last decade, many researches have studiedthe variability problem associated to CMOS bulk process. For bulkCMOS devices in nanotechnologies, the variation of gate lengthdimensions is the dominant parameter related to threshold voltageand ION deviation due to the random dopants fluctuation (RDF)[4–7].

The ITRS [8] underscores that the use of multi-gate devices willbe required to overcome these obstacles to keep scaling becausethese devices provide better control of short-channel effects, lowerleakage and better yield in CMOS processes [2]. Perfect isolationand high driving capability makes the FinFET advantageous bothfor low power and high-speed applications.

However, there are a number of scaling challenges with FinFETs,as geometric variability, mitigate random dopant fluctuation (RDF),fringe capacitance to contact/facet, low-k spacer, fin and gate fidel-ity (patterning and etch), conformal coverage in gate wrap-arounddevices (Vt tuning), CMP polish challenges and contact resistances[9]. Moreover, fin engineering (balancing height, fin thickness,oxide thickness, and channel length) is essential in minimizingthe leakage current, IOFF, and maximizing the on current, ION [2].

Although CMOS bulk processes are more sensible to processvariability, the effects on the electrical behaviour for sub 22 nmFinFET technology should not be neglected. The main objective ofthis work is to verify the impact on ION and IOFF currents of scalingin a set of predictive FinFET technologies from 20 nm to 7 nm.Thus, it is possible to predict the influence of process variationsin future technology nodes, identifying relevant behavioural stan-dards with respect to the use of FinFET technology in digitaldesigns and highlighting the need of consider all electrical charac-teristics in the development of projects and EDA tools for FinFETtechnology.

Next Section introduces some FinFET properties. The variabilityimpact on FinFET devices is detailed in Section 3. The methodologyutilized in experiments is presented in Section 4 and discussion ofthe results is showed in Section 5. Finally, conclusions are pre-sented in Section 6.

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2. FinFET devices

FinFET (Fin-Shaped Field Effect Transistor) technology ispointed as the main candidate to replace bulk CMOS technologyunder 20 nm. FinFETs are multi-gate devices. Multi-gate devicesprovide a better electric control channel, allowing more efficientreduction of leakage current [2].

The FinFET technology consists of vertical silicon fins whichform the channel region and which connect to source and drainregions at each end. Fig. 1 presents FinFET key geometric parame-ters [10]. The distance between drain and source is the fin length, L.The main characteristics about the fin are the fin height, HFIN, andthe silicon thickness is given by TFIN, also known as fin width, WFIN.

The gate region is wrapped around this vertical fin. MOS chan-nels are formed at the two sidewalls plus top side of the fin. Thisfin-like geometry, where the depletion regions reach from thegates entirely into the body region, implies that no free chargecarriers are available, making the suppression of SCE possible inFinFETs [11].

The threshold voltage of multi-gate devices can be expressed asEq. (1), where QSS represents charge in the gate dielectric, Cox is thegate capacitance, QD is the depletion charge in the channel, fms rep-resents metal–semiconductor workfunction (WF) differencebetween the gate electrode and the semiconductor, ff is the fermipotential which for P-type silicon is given by (2) where NA is accep-tor concentration and ni is intrinsic carrier concentration [12]. Forultrathin body and lightly doped devices the effect of QD and QSS onthreshold voltage, Vt is negligible compared to ff. Further Vin is theadditional surface potential to 2ff that is needed for ultrathin bodydevices to bring enough inversion charges into the channel regionof the transistor to reach threshold point. Therefore, the WF of gateelectrode is the main parameter for threshold voltage determina-tion in case of multi-gate devices [13]. In FinFET technologies, asa result of the shape of active fins, the fin channel is preferred tobe low-doped for minimizing threshold voltage variations relatedto random doping fluctuations (RDF). Thus, in FinFETs, the thresh-old voltage of low-doping channel is mainly set by theworkfunction.

Vt ¼ fms þ 2f f þQ D

Cox� Q SS

Coxþ Vin ð1Þ

ff ¼kTq

lnNA

nið2Þ

Fig. 1. Top view and cross-section of a FinFET 3T [10].

3. FinFET devices under process variability

Some works have investigated the impact on the threshold volt-age and also on the device current IOFF and ION of sources of vari-ability in a 3D FinFET models [14–16]. Gold Standard SimulationsLtd. (GSS) shows that, although the random distribution of dopants(RDD) is a major cause of variability in bulk CMOS technologies,their contribution in FinFET technology is significantly reduceddue to the low doping of the channel [14]. Moreover, the impactdue to line edge roughness (LER) in FinFETs, beyond the effectsof variation in the gate (GER), should also consider the impact ofthese imperfections on the fin edge roughness (FER).

With the introduction of high-k metal gates at the 45 nm tech-nology node, Metal Gate Granularity (MGG) has been identified asan important source of statistical variability. Fluctuations in work-function (WFF) are locally induced due to the polycrystalline nat-ure of the metal lead to surface potential variations [17–19]. WFFis caused by the dependency of metal workfunction on the orienta-tion of its grains, as Fig. 2 illustrates [20]. In the ideal fabricationprocess, metal gates devices have the gates produced with aunique metal uniformly aligned and very small workfunction devi-ation. Nevertheless, in real fabrication process, metal gate devicesare generally produced with metals with different WF randomlyaligned that implies higher WF variation. It has been shown thatthe threshold-voltage fluctuation due to MGG is close to Gaussiandistribution and the standard deviation is almost linearly propor-tional to metal-grain size [17]. Recent researches highlights thestrong influence of WFF in the threshold voltage and mainly, inthe ION and IOFF currents [15].

Thus, gate length (L), fin height (HFIN), fin width (WFIN) and gateworkfunction fluctuation (WFF) parameters are the main sourcesof variability expected for FinFETs [21].

4. Methodology

This work evaluates geometry variations in gate length (L), finheight (HFIN), fin width (WFIN) for a set of predictive FinFET technol-ogies from 20 nm to 7 nm by electrical device simulations [22,23].Also is evaluated the impact of MGG variability on the electricalparameter gate workfunction (WF).

This work adopts two FinFET devices models with differentthreshold voltages: the High Performance (HP) and the LowStandby Power (LSTP) version of the 20 nm, 16 nm, 14 nm, 10 nmand 7 nm PTM-MG models [23]. PTM-MG is developed usingBSIM-CMG model [22], scaling theory of multi-gate devices, phys-ical models and ITRS projections. These models allow us to con-sider predictive models for fully depleted SOI FinFETs. Thereference values from PTM for the gate length (L), fin height (HFIN),fin width (WFIN) and workfunction (WF) for these technologies areshown in Table 1 [23].

Variability was taken by Monte Carlo SPICE simulations with atotal of ten thousand variations for each parameter. Results of ION

Fig. 2. Random alignment of metal in real devices is the main source of WFF. Atright, the ideal metal gate fabrication [20].

Table 1Main parameter of HP and LSTP FinFET devices [23].

Parameter Technology (nm)

20 16 14 10 7

L (nm) 24 20 18 14 11HFIN (nm) 28 26 23 21 18WFIN (nm) 15 12 10 8 6.5

WF HP N 4.38 4.41 4.42 4.42 4.42P 4.80 4.76 4.75 4.75 4.74

WF LSTP N 4.56 4.58 4.60 4.60 4.61P 4.62 4.59 4.57 4.56 4.56

Fig. 3. Density of gate length (L), fin width (WFIN), fins height (HFIN) parametersunder variation and gate workfunction fluctuation (WFF) of a 7 nm LSTP NFET.

C. Meinhardt et al. / Microelectronics Reliability 54 (2014) 2319–2324 2321

and IOFF currents were obtained from simulations for 3r deviationof 10% from nominal values of the geometric parameters gatelength (L), fin height (HFIN), fin width (WFIN) under variation. Forthe electrical parameter WFF the simulations assume initially amore conservative approach with 3r deviation of 3% from nominalvalues because small deviations on WFF have high impact on elec-trical behaviour of FinFET devices. To evaluate this impact factor, a

Table 2Results of nominal ION and IOFF per single fin and ION and IOFF considering geometric variability in gate length (L), fin width (WFIN), fin height (HFIN) and WFF.

Nominal L WFIN HFIN WFF

Mean SD Mean SD Mean SD Mean SD

20 nmHP NFET ION (lA) 88.4 88.4 0.42 88.4 0.43 88.4 1.20 88.4 5.11

IOFF (nA) 6.56 7.11 2.14 6.85 1.53 6.56 0.28 17.1 17.4HP PFET ION (lA) 78.3 78.3 0.38 78.3 0.38 78.3 0.98 78.3 4.99

IOFF (nA) 6.34 6.99 2.35 6.67 1.60 6.34 0.29 19.3 20.9LSTP NFET ION (lA) 51.5 51.5 0.04 51.5 0.31 51.5 0.79 51.5 4.61

IOFF (pA) 6.26 6.78 2.07 6.66 1.75 6.27 0.31 19.4 21.2LSTP PFET ION (lA) 45.9 45.9 0.00 45.9 0.30 45.9 0.67 45.9 4.20

IOFF (pA) 6.22 6.79 2.18 6.64 1.81 6.23 0.32 19.6 21.6

16 nmHP NFET ION (lA) 91.1 91.1 0.14 91.1 0.58 91.1 1.46 88.4 5.11




IOFF (pA) 5.81 6.39 2.04 6.28 1.87 5.81 0.26 18.0 19.7

14 nmHP NFET ION (lA) 94.1 94.1 0.00 94.2 0.63 94.2 1.58 94.2 7.06




IOFF (pA) 157.7 175.3 61.46 5.41 1.69 3458.9 129.74 459.64 491.72

10 nmHP NFET ION (lA) 90.0 90.0 0.05 90.0 0.62 90.0 1.46 90.0 7.44




IOFF (pA) 734.89 801.27 254.78 780.24 205.70 735.33 28.78 2057.6 2166.0

7 nmHP NFET ION (lA) 81.9 82.0 0.10 82.0 0.57 82.0 1.29 82.1 7.63


IOFF (lA) 2.02 2.08 0.43 2.06 0.34 2.02 0.06 2.79 1.91LSTP NFET ION (lA) 35.2 35.2 0.25 35.2 0.42 35.2 0.64 35.4 6.13


IOFF (nA) 3.45 3.70 1.04 3.63 0.86 3.46 0.129 9.53 9.98


second experiment analyses the consequence of different degreesof WFF deviation on ION and IOFF currents. This experiment consid-ers workfunction as a Gaussian distribution with 3r deviation of4–10% from nominal values.

Fig. 4. Distribution of ION for a 7 nm LSTP NFET device under WFF.

Fig. 5. Sub-20 nm 3% of WFF tendency of deviation impact on ION for HP and LSTPdevices.

Fig. 6. HP and LSTP devices average IOFF

The mean (l) and standard deviation (r) are then compared.The normalized standard deviation (r/l) of the metrics was com-pared because it makes possible to compare the variability of theparameter with different means. Simulations were carried out byusing HSPICE.

5. Results and discussion

Table 2 shows the results of ION and IOFF per single fin for NFETand PFET devices in HP and LSTP model for the 5 predictive tech-nologies evaluated. Nominal values are obtained without the pres-ence of any variation source, representing the expected currentvalues for the technologies. This complete set of values offer condi-tion to evaluate although ION suffers with some deviation in thepresence of geometric variability is the IOFF current that presentsthe most significative impact. IOFF mean currents outline the devi-ation from the nominal values for all parameters under variation.

Fig. 3 shows the ION density function for the parameters undervariation in a 7 nm NFET LSTP device. Gate length, fin width andfin height variation have insignificant impact on ION for NFETdevices, lower than 2% of normalized deviation. WF shows smalldensity due to large deviation. The same behaviour is observedfor the ION in the other technologies.

WFF have a large deviation impact on ION both in NFET and PFETdevices, in both technologies LSTP and HP. To highlight this, Fig. 4shows the histogram for 7 nm LSTP NFET devices under WFF, witha mean value of 35.4 lA and standard deviation of 6.13 lA.

NFET devices are more susceptible to WFF, as Fig. 5 illustrated.For NFET devices, this fluctuation increases with the scale reduc-tion, and introduces about 17% of deviation in 7 nm LSTP devices.

Fig. 6 shows the average impact on IOFF of individual parametervariation for NFET and PFET devices in the HP and LSTP process.Gate length and fin width have significant impact on IOFF behav-iour, at the approximated level of 30%. WFF severely impacts theIOFF, especially NFET devices, as Fig. 7 details for all technologies.This impact appears to be decreasing with the technology scaling,mainly for PFET devices, but still high enough to be neglected indigital designs, particularly in low-power applications.

Even considering a low WFF, these results underline the impor-tance of investigating how gate WF affects the predictive nodes ofFinFET technologies. The experiments show that for more than 5%of WFF, the current ION starts to have more than 10% of deviationeven for the 20 nm technology, as shows Fig. 8. This investigationis more alarming about IOFF currents. WFF introduces a large devi-ation from nominal values and brings elevated standard deviation

impact due to parameter variation.

Fig. 7. Impact on IOFF due to 3% of WFF for sub-20 nm HP and LSTP devices.

Fig. 8. WFF factor and the effect on the ION for High Performance NFET devices.

Fig. 9. WFF factor and the effect on the IOFF for High Performance NFET devices.

Fig. 10. Sub-20 nm 10% of WFF tendency of deviation impact on ION for HP and LSTPdevices.

Fig. 11. Sub-20 nm 10% of WFF tendency of deviation impact on IOFF for HP andLSTP devices.

C. Meinhardt et al. / Microelectronics Reliability 54 (2014) 2319–2324 2323

even for small values of WF variability, as it is possible to see inFig. 9.

For a 10% of WFF, circuits in these predictive technologies willhave to deal with about 50% of ION normalized deviation and morethan 100% of IOFF normalized deviation, as Figs. 10 and 11 describesrespectively.

6. Conclusion

These results emphasize that it is no longer enough to focusonly on the threshold voltage fluctuations in the development ofprojects and EDA tools considering the FinFET technology. It is nec-essary that EDA tools and designers evaluate all electrical charac-teristics, especially the variability impact on the IOFF currents.With small feature sizes, low voltages, and complex vector sets,many of these challenges will require new design methodologiesand new EDA tools that should be able to deal with the new fabri-cation process and variability challenges [16].

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