presentation: a fully-integrated 10.5 to 13.5 gbps ... · presentation: a fully-integrated 10.5 to...
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A Fully-Integrated 10.5 to 13.5 Gbps Transceiver in 0.13µm CMOS
Guoqing Miao, Peicheng Ju, Devin Ng, John Khoury, and Kadaba Lakshmikumar
Vitesse Semiconductor CorporationNew Jersey Design Center
(formerly Multilink Technology Corporation)Somerset, NJ, USA
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Outline
• System overview• Transmitter
- VCO- Duo-binary coding and the output buffer
• Receiver- Quadrature VCO- Half-rate binary phase/DC offset detector- High gain input buffer- DC offset cancellation circuit- Data retiming clock phase tuning
• Experimental results• Conclusions
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System Overview
Intended applications:
• SONET OC-192 with 7 – 25 % FEC overhead• 10G Ethernet with added FEC function and 64/66 code rate• SOC integration
E/O
O/E E/O
O/ETX
RX TX
RX
10Gb/s
FECFramerNP
FECFramerNP
32 32
3232
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Transmitter Block Diagram
• Half-rate architecture• Multiplexer uses CML logic for speed > 2.5GHz
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Tx VCO Circuit
• LC oscillator for superior jitter performance• VCO runs at half the data rate• Multiple VCO tuning curves to achieve low KVCO and wide range• Selectable capacitors for coarse tuning, MOS varactors for fine tuning
fosc
Vc
•••
1.2V
Vc
Vbias
CKN CKP
••• •••
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Transmitter Duo-binary Coding
• Duo-binary coding:
Pre-coding: p(k) = p(k-1)⊕x(k),Filtering: y(k) = p(k) + p(k-1)
• Implementation:
Pre-coding before the last 4:1 MUXFiltering in the output buffer
D D
x(k)p(k)
y(k)
Pre-coding Filtering
x(k): NRZ data, D: unit delay
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Transmitter Output Buffer (I)
• Output buffer uses four parallel paths:
For normal NRZ pattern: b0 = b1 = b2 = b3 = x(k)For NRZ with pre-emphasis: b0 = b1 = b2 = x(k), b3 = - x(k-1)For output duo-binary coding: b0 = b1 = p(k), b2 = b3 = p(k-1)
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Transmitter Output Buffer (II)
• Four matched parallel paths• Inductive peaking in each pre-buffer to improve output rise/fall times• 50Ω on chip termination to reduce reflections
1.2VL LR R 50Ω 50Ω
b0(p,n)
b3(p,n)
out(p,n)
•••
Pre-buffer Buffer
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Receiver Block Diagram
Loop II
Loop I
• Half rate dual loop architectureLoop-I for VCO trainingLoop-II for data phase locking and retiming
• High gain input buffer with DC offset compensation• Phase tuning of the data sampling clock (Q)
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Rx Quadrature LC Oscillator
• Two cross-coupled LC tanks to generate quadrature phases• Multiple VCO tuning curves to achieve low KVCO and wide range• Selectable capacitors for coarse tuning, MOS varactors for fine tuning
1.2V 1.2V
VcVc
CKQN CKQPCKIN CKIP
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Binary Phase/DC Offset Detection
increment if 512 occurrences-1 1 1
incrementretard1 1 0
--1 0 1
decrementadvance1 0 0
incrementadvance0 1 1
--0 1 0
decrementretard0 0 1
Decrement if 512 occurrences-0 0 0
DC offsetPhaseA T B
Din(p,n)
A T T BB/A
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Half-Rate Phase Detector Implementation
Din(p,n)
ckip
ckin
ckqn
ckqp
UP1
DN2
D0
D1
UP2
DN1
DCK
Q
DCK
Q
DCK
Q
DCK
Q
• Half-rate Alexander phase detector• Use both edges of In-phase clock to sample the data transition• Use both edges of quadrature clock to sample the data center• Automatic 1-to-2 de-multiplexing• All in CML logic
Din(p,n)
ckip
ckin
ckqn
ckqp
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Data Sampling Clock Phase Tuning
Ckq
op/n
Cki
op/n
Cki
op/n
Di(p,n)
(1) (2)• When Di(p,n) has different rise/fall time(2) is the optimal data sampling point, away from the data center (1)
• α > 0: extra delay to Ckqo(p,n)• α < 0: less delay to Ckqo(p,n)• Digitally controlled α provides +/- 45o tuning range, with 6.4o
step size
Qua
drat
ure
Rx
VC
O
CKI
CKQ
CKIO
CKQO1-α
1+α
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DC Offset Cancellation Circuit
FromPhase Detector
A
T
B
6INC
DEC
Iosp
Iosn
To Input Buffer
OffsetDecoder
DigitalAccumulator
6 Bit I-DAC
• Digital accumulator “integrates” the T bit to measure input DC offset• To save power, the digital accumulator runs at lower frequency• 6 bit current DAC input is thermo-coded to guarantee outputmonotonic
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High Gain Input Buffer (I)
• Ios(p,n): offset cancellation current• Two modes of operation:
with all 4 stages => high gain for high sensitivity with 1st and 4th stages => low gain for low power
• Active shunt peaking for bandwidth extension
Din(p,n) Dout(p,n)G1 G2 G3 G4
Iosp
Iosn
Mode
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High Gain Input Buffer (II)
• Input-referred offset canceled withcurrent-mode DAC via Iosp, Iosn
• NMOS load with active shunt peaking
DC gain ≈
• Equivalent shunt peaking inductance
1
2
)/(
)/(
LW
LW
1
1
1 m
gsg
T
g
g
CRRL
×=≈
ω
VDDL
VDDH
M1A M1B
M2A M2B
RgA RgB
Do(p,n)
Di(p,n)
Iosp Iosn
Vbias
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Die Microphotograph
4mm
4mm
• 0.13µm, 1.2v 8M standard CMOS• Flip-chip layout, wire-bonding package for test chip• On chip 1.5mm T-lines for high speed I/Os• 2.0 x 4.0 mm2 macro size• 118-pin PBGA package
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Transmitter Test Results(I)
NRZ output @ 10.68Gbps,231-1 PRBS pattern
Duo-binary coding @12.5 Gbps,231-1 PRBS pattern
• Slow edges caused by the non-ideal on-chip T-lines and the wire-bond package
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Transmitter Test Results(II)
• Improved output data eyes, the 10G macro is integrated into a XAUI to 10G transceiver in a 400 pin Flip Chip Plastic BGA (FC-PBGA) package
NRZ output @ 10.3Gbps,27-1 PRBS pattern
Duo-binary coding @10.3 Gbps,27-1 PRBS pattern
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Transmitter Test Results(III)
Tx half rate clock jitter:1.2ps rms, 8.4ps p-p jitter @ 5.5GHz
Tx clock spectrumPhase noise:-103dBc/Hz @ 1MHz offset
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Receiver Test Results(I)
Recovered divide-by-4 clock, input 40mV, 231-1 PRBS pattern, 11.0Gbps, 2.46ps rms,12ps p-p jitter
Recovered divide-by-4 clockSpectrum, phase noise:-122dBc/Hz @ 1MHz offset
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Receiver Test Results(II)
Rx jitter tolerance: input 40mV231-1 PRBS pattern, 11.0Gbps10-12 error threshold
Rx input sensitivity: with DC offsetcancellation, 231-1 PRBS pattern,11.0Gbps
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Summary of Experimental Results
0.13µm standard CMOSTechnology
Tx = 450mW, Rx = 550mWPower consumption
1.2V, 1.8VPower supply
8.0 mm2Macro size
700 mV p-p differentialTx output swing
8.9 mUI rmsRx jitter generation (50kHz – 80MHz)
6.7 mUI rmsTx jitter generation (50kHz – 80MHz)
< 15 mV single-endedRx input sensitivity
10.5 ~ 13.5 GbpsSpeed
Experimental resultsParameter
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Conclusions
• A fully integrated 10.5 to 13.5 Gbps transceiver in 0.13µmstandard CMOS has been demonstrated
• Half-rate architecture has been demonstrated for both Tx and Rx
• Tx output duo-binary coding integrated
• A new DC offset cancellation technique is implemented
• Rx achieves < 15mV input sensitivity
• SONET OC-192 compliant performance achieved