problems - university of icelanddaj2/tolvutaekni/appendixa.pdf4) a.14 a number code in which...

724 APPENDIX A • LOGIC CIRCUITS (Corrisponde al cap. 2 - Elementi di logica)

PROBLEMS

A.1 Implement the COINCIDENCE function in sum-of-products form, whereCOINCIDENCE = XOR.

A.2 Prove the following identities by using algebraic manipulation and also by using truthtables.

(a) a ⊕ b ⊕ c = abc + abc + abc + abc

(b) x + wx = x + w

(c) x1x2 + x2x3 + x3x1 = x1x2 + x3x1

Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat ZakyCopyright © 2006 - The McGraw-Hill Companies srl

PROBLEMS 725

A.3 Derive minimal sum-of-products forms for the four 3-variable functions f1, f2, f3, andf4 given in Figure PA.1. Is there more than one minimal form for any of these functions?If so, derive all of them.

x1 x2 x3 f 1 f 2 f 3 f 4

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

1

0

0

1

0

1

1

1

1

1

1

0

0

0

1

d

1

0

1

d

0

1

1

0

1

1

d

d

d

1

0

Figure PA.1 Logic functions forProblem A.3.

A.4 Find the simplest sum-of-products form for the function f using the don’t-care conditiond, where

f = x1(x2x3 + x2x3 + x2x3x4) + x2x4(x3 + x1)

and

d = x1x2(x3x4 + x3x4) + x1x3x4

A.5 Consider the function

f (x1, . . . , x4) = (x1 ⊕ x3) + (x1x3 + x1x3)x4 + x1x2

(a) Use a Karnaugh map to find a minimum cost sum-of-products (SOP) expressionfor f .

(b) Find a minimum cost SOP expression for f , which is the complement of f . Then,complement (using de Morgan’s rule) this SOP expression to find an expression forf . The resulting expression will be in the product-of-sums (POS) form. Compareits cost with the SOP expression derived in Part a. Can you draw any generalconclusions from this result?

A.6 Find a minimum cost implementation of the function f (x1, x2, x3, x4), where f = 1 ifeither one or two of the input variables have the logic value 1. Otherwise, f = 0.

A.7 Figure A.6 defines the 4-bit encoding of BCD digits. Design a circuit that has fourinputs labeled b3, . . . , b0, and an output f , such that f = 1 if the 4-bit input patternis a valid BCD digit; otherwise f = 0. Give a minimum cost implementation of thiscircuit.


726 APPENDIX A • LOGIC CIRCUITS

A.8 Two 2-bit numbers A = a1a0 and B = b1b0 are to be compared by a four-variablefunction f (a1, a0, b1, b0). The function f is to have the value 1 whenever

v(A) ≤ v(B)

where v(X) = x1 × 21 + x0 × 20 for any 2-bit number. Assume that the variables Aand B are such that |v(A) − v(B)| ≤ 2. Synthesize f using as few gates as possible.

A.9 Repeat Problem A.8 for the requirement that f = 1 whenever

v(A) > v(B)

subject to the input constraint

v(A) + v(B) ≤ 4

A.10 Prove that the associative rule does not apply to the NAND operator.

A.11 Implement the following function with no more than six NAND gates, each havingthree inputs.

f = x1x2 + x1x2x3 + x1x2x3x4 + x1x2x3x4

Assume that both true and complemented inputs are available.

A.12 Show how to implement the following function using six or fewer two-input NANDgates. Complemented input variables are not available.

f = x1x2 + x3 + x1x4

A.13 Implement the following function as economically as possible using only NAND gates.Assume that complemented input variables are not available.

f = (x1 + x3)(x2 + x4)

A.14 A number code in which consecutive numbers are represented by binary patterns thatdiffer only in one bit position is called a Gray code. A truth table for a 3-bit Gray codeto binary code converter is shown in Figure PA.2a.

(a) Implement the three functions f1, f2, and f3 using only NAND gates.

(b) A lower-cost network for performing this code conversion can be derived by notingthe following relationships between the input and output variables.

f1 = a

f2 = f1 ⊕ b

f3 = f2 ⊕ c

Using these relationships, specify the contents of a combinational network N that canbe repeated, as shown in Figure PA.2b, to implement the conversion. Compare thetotal number of NAND gates required to implement the conversion in this form to thenumber required in Part a.


PROBLEMS 727

a b c f 1 f 2 f 3

0

0

0

0

1

1

1

1

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

3-bit Gray codeinputs

Binary codeoutputs

N? N? N?

a b c

f 1 f 2 f 3

? (b) Code conversion network

(a) Three-bit Gray code to

? ?

binary code conversion

Figure PA.2 Gray code conversion example for Problem A.14.

A.15 Implement the XOR function using only 4 two-input NAND gates.

A.16 Figure A.37 defines a BCD to seven-segment display decoder. Give an implementationfor this truth table using AND, OR, and NOT gates. Verify that the same functions arecorrectly implemented by the NAND gate circuits shown in the figure.

A.17 In the logic network shown in Figure PA.3, gate 3 fails and produces the logic value 1at its output F1 regardless of the inputs. Redraw the network, making simplifications

f

x4

x3x1

x2

1

2

3

4

6

7

5

8

F1

F2

Figure PA.3 A faulty network.



wherever possible, to obtain a new network that is equivalent to the given faulty networkand that contains as few gates as possible. Repeat this problem, assuming that the faultis at position F2, which is stuck at a logic value 0.

A.18 Figure A.16 shows the structure of a general CMOS circuit. Derive a CMOS circuitthat implements the function

f (x1, . . . , x4) = x1x2 + x3x4

Use as few transistors as possible. (Hint: Consider series/parallel networks of transistors.Note the complementary series and parallel structure of the pull-up and pull-downnetworks in Figures A.17 and A.18.)

A.19 Draw the waveform for the output Q in the JK circuit of Figure A.31, using the inputwaveforms shown in Figure PA.4 and assuming that the flip-flop is initially in the 0 state.

Clock1

0

1J

0

1K

0

Figure PA.4 Input waveforms for a JK flip-flop.

A.20 Derive the truth table for the NAND gate circuit in Figure PA.5. Compare it to the truthtable in Figure A.24b and then verify that the circuit in Figure A.26 is equivalent to thecircuit in Figure A.25a.

Q

Q

A

B

Figure PA.5 NAND latch.

A.21 Compute both the setup time and the hold time in terms of NOR gate delays for thenegative edge-triggered D flip-flop shown in Figure A.29.

A.22 In the circuit of Figure A.27a, replace all NAND gates with NOR gates. Derive atruth table for the resulting circuit. How does this circuit compare with the circuit inFigure A.27a?


PROBLEMS 729

A.23 Figure A.33 shows a shift register network that shifts the data to the right one place ata time under the control of a clock signal. Modify this shift register to make it capableof shifting data either one or two places at a time under the control of the clock and anadditional control input ONE/TWO.

A.24 A 4-bit shift register that has two control inputs — INITIALIZE and RIGHT/LEFT —is required. When INITIALIZE is set to 1, the binary number 1000 should be loadedinto the register independently of the clock input. When INITIALIZE = 0, pulses atthe clock input should rotate this pattern. The pattern rotates right or left when theRIGHT/LEFT input is equal to 1 or 0, respectively. Give a suitable design for thisregister using D flip-flops that have preset and clear inputs as shown in Figure A.32.

A.25 Derive a three-input to eight-output decoder network, with the restriction that the gatesto be used cannot have more than two inputs.

A.26 Figure A.35 shows a 3-bit up counter. A counter that counts in the opposite direction(that is, 7, 6, . . . , 1, 0, 7, . . . ) is called a down counter. A counter capable of counting inboth directions under the control of an UP/DOWN signal is called an up/down counter.Show a logic diagram for a 3-bit up/down counter that can also be preset to any statethrough parallel loading of its flip-flops from an external source. A LOAD/COUNTcontrol is used to determine whether the counter is being loaded or is operating as acounter.

A.27 Figure A.35 shows an asynchronous 3-bit up-counter. Design a 4-bit synchronous up-counter, which counts in the sequence 0, 1, 2, . . . , 15, 0 . . . . Use T flip-flops in yourcircuit. In the synchronous counter all flip-flops have to be able to change their statesat the same time. Hence, the primary clock input has to be connected directly to theclock inputs of all flip-flops.

A.28 A switching function to be implemented is described by the expression

f (x1, x2, x3, x4) = x1x3x4 + x1x3x4 + x2x3x4

(a) Show an implementation of f in terms of an eight-input multiplexer circuit.

(b) Can f be realized with a four-input multiplexer circuit? If so, show how.

A.29 Repeat Problem A.28 for

f (x1, x2, x3, x4) = x1x2x3 + x2x3x4 + x1x4

A.30 (a) What is the total number of distinct functions, f (x1, x2, x3), of three binaryvariables?

(b) How many of these functions are implementable with one PAL circuit of the typeshown in Figure A.43?

(c) What is the smallest change in the circuit in Figure A.43 that should be made toallow any three-variable function to be implemented with a single PAL circuit?

A.31 Consider the PAL circuit in Figure A.43. Suppose that the circuit is modified by addinga fourth input variable, x4, whose uncomplemented and complemented forms can beconnected to all four AND gates in the same way as the variables x1, x2, and x3.



(a) Can this modified PAL be used to implement the function

f = x1x2x3 + x1x2x3 + x1x2x3

If so, show how.

(b) How many functions of three variables cannot be implemented with this PAL?

A.32 Complete the design of the up/down counter in Figure A.47 by using the state assignmentS0 = 10, S1 = 11, S2 = 01, and S3 = 00. How does this design compare with the onegiven in Section A.13.1?

A.33 Design a 2-bit synchronous counter of the general form shown in Figure A.50 thatcounts in the sequence . . . , 0, 3, 1, 2, 0, . . . , using D flip-flops. This circuit has noexternal inputs, and the outputs are the flip-flop values themselves.

A.34 Repeat Problem A.33 for a 3-bit counter that counts in the sequence . . . , 0, 1, 2, 3, 4,5, 0, . . . , taking advantage of the unused count values 6 and 7 as don’t-care conditionsin designing the combinational logic.

A.35 In Section A.13, D flip-flops were used in the design of synchronous sequential circuits.This is the simplest choice in the sense that the logic function values for a D input aredirectly determined by the desired next-state values in the state table. Suppose that JKflip-flops are to be used instead of D flip-flops. Describe, by the construction of a table,how to determine the binary value for each of the J and K inputs for a flip-flop as afunction of each possible required transition from present state to next state for thatflip-flop. (Hint: The table should have four rows, one for each of the transitions 0 → 0,0 → 1, 1 → 0, and 1 → 1; and each J and K entry is to be 0, 1, or “don’t care,” asrequired.) Apply the information in your table to the design of individual combinationallogic functions for each J and K input for each of the two flip-flops of the 2-bit binarycounter of Problem A.33. How does the simplicity of the logic required compare tothat needed for the design of the counter using D flip-flops?

A.36 Repeat Problem A.34 using JK flip-flops instead of D flip-flops. The general procedurefor doing this is provided by the answer to Problem A.35.

A.37 In the vending machine example used in Section A.13.4 to illustrate the finite statemachine model, a single binary output, z, was used to indicate the dispensing of mer-chandise. Change was not provided as an output. The purpose of this problem is toexpand the output to include providing proper change. Assume that the only inputsequences of dimes and quarters are: 10-10-10, 10-25, 25-10, and 25-25. Coincidentwith the last coin input, the outputs to be provided for these sequences are 0, 5, 5, and20, respectively. Use two new binary outputs, z2 and z3, to represent the three distinctoutputs. (This does not correspond directly to coins in use, but it keeps the problemsimple.)

(a) Specify the new state table that incorporates the new outputs.

(b) Develop the logic expressions for the new outputs z2 and z3.

(c) Are there any equivalent states in the new state table?


REFERENCES 731

A.38 Finite state machines can be used to detect the occurrence of certain subsequences inthe sequence of binary inputs applied to the machine. Such machines are called finitestate recognizers. Suppose that a machine is to produce a 1 as its output coincident withthe second 1 in the pattern 011 whenever that subsequence occurs in the input sequenceapplied to the machine.

(a) Draw the state diagram for this machine.

(b) Make a state assignment for the required number of flip-flops and construct theassigned state table, assuming that D flip-flops are to be used.

(c) Derive the logic expressions for the output and the next-state variables.

A.39 Repeat Part a only of Problem A.38 for a machine that is to recognize the occurrenceof either of the subsequences 011 and 010 in the input sequence, including the caseswhere overlap occurs. For example, the input sequence 110101011. . . is to produce theoutput sequence 000010101. . . .


SOLUTIONS - Appendix A – Logic Circuits

A.1. The truth table for the COINCIDENCE function is

x1 x2 COINCIDENCE

0 0 10 1 01 0 01 1 1

COINCIDENCE = x1x2 + x1x2 = (x1 ⊕ x2)

A.2. Proof for identity (a):

(a⊕ b)⊕ c = (a⊕ b)c + (a⊕ b)c

= abc + abc + abc + abc

Proof for identity (b):

x + wx = (x + w)(x + x)

= x + w

Proof for identity (c):

x1x2 + x2x3 + x3x1 = x1x2 + x2x3(x1 + x1) + x3x1

= x1x2 + x1x2x3 + x3x1x2 + x3x1

= x1x2 + x3x1

A.3. Using Karnaugh maps get:

1

1 0

1

1 1

10

0 0 0 1 1 1 1 0

0

1

x1x2x3

A minimum cost expression for f1 is

f1 = x1x2 + x1x2 + x1x3

1


Another expression that has the same cost is

f1 = x1x2 + x1x2 + x2x3

1

1 0

0

1 1

01

0 0 0 1 1 1 1 0

0

1

x1x2x3

The minimum cost expression for f2 is

f2 = x1 + x2x3

d

1 0

d

1 1

10

0 0 0 1 1 1 1 0

0

1

x1x2x3

The minimum cost expression for f3 is

f3 = x1x2 + x1x3

0

d d

d

1 0

11

0 0 0 1 1 1 1 0

0

1

x1x2x3

A minimum cost expression for f4 is

f4 = x2x3 + x2x3


f4 = x2x3 + x1x3

2


A.4. The corresponding Karnaugh map is

0

d 1

d

0 1

11

0

0 0

d

0 1

10

0 0 0 1 1 1 1 0

0 0

0 1

1 1

1 0

x3x4

x1x2

A minimum-cost SOP expression is

f = x2x3 + x1x2 + x1x3


f = x2x3 + x1x2 + x1x4

A.5. The Karnaugh map is

0

1 1

1

1 1

10

1

1 1

1

1 0

11

0 0 0 1 1 1 1 0

0 0

0 1

1 1

1 0

x3x4

x1x2

(a) The minimum-cost SOP expression is

f = x4 + x1x3 + x1x3 + x1x2

(b) The minimum-cost SOP expression for the complement of f is

f = x1x3x4 + x1x2x3x4

Complementing this expression using de Morgan’s rule gives

f = (x1 + x3 + x4)(x1 + x2 + x3 + x4)

3


This expression requires 2 OR gates, one AND gate and 9 inputs to gates, for atotal cost of 12. The SOP expression requires 3 AND gates, one OR gate and 10inputs to gates, for a total cost of 14. The apparent conclusion is that for somefunctions the POS implementation is less expensive than the SOP implementa-tion, and vice versa.

A.6. The corresponding Karnaugh map is

0

1 1

1

1 0

11

1

1 1

0

1 0

00

0 0 0 1 1 1 1 0

0 0

0 1

1 1

1 0

x3x4

x1x2

A minimum-cost SOP expression is

f = x1x2x3 + x2x3x4 + x1x3x4 + x1x2x3 + x1x3x4 + x1x2x4

The minimum-cost POS expression is

f = (x1+x2+x3+x4)(x1+x2+x3)(x1+x2+x4)(x1+x3+x4)(x2+x3+x4)

The cost of the SOP expression is 31, comprising 7 gates and 24 inputs to gates.The cost of the POS expression is 27, comprising 6 gates and 21 inputs. There-fore, the POS expression leads to the minimum-cost implementation.

A.7. The desired function, f , has the value 1 for the rst ten rows of the truth table inFigure A.6. The value of f for the remaining six rows is 0. The correspondingKarnaugh map is

1

1 1

1

1 0

01

1

1 0

0

1 0

01

0 0 0 1

0 0

0 1

1 0

1 1

1 1 1 0b1b0

b3b2

4


Hence, the expressionf = b3 + b1b2

describes the required circuit.

A.8. The comparison function, f , is de ned by the map

1

1 0

0

1 0

d0

d

1 1

1

1 0

11

0 0 0 1 1 1 1 0

0 0

0 1

1 1

1 0

a1a0b1b0

The minimum-cost SOP expression is

f = a1a0 + b1b0 + a0b1 + a1b0 + a1b1

The minimum-cost POS expression is

f = (a1 + b1)(a0 + b1 + b0)(a1 + a0 + b0)

The cost of the SOP expression is 21, comprising 6 gates and 15 inputs to gates.The cost of the POS expression is 15, comprising 4 gates and 11 inputs. Thisdescribes the lowest-cost circuit.

A.9. The comparison function, f , is de ned by the map

0

0 1

1

0 1

11

0

0 0

d

0 d

d0

0 0 0 1 1 1 1 0

0 0

0 1

1 1

1 0

a1a0b1b0

The minimum-cost circuit is speci ed by the expression

f = a1b1 + a0b1b0

5


A.10. The associative rule would require that

(w ↑ y) ↑ z = w ↑ (y ↑ z)

The left-hand side of this expression gives

(w ↑ y) ↑ z = wyz

= wy + z

The right-hand side gives

w ↑ (y ↑ z) = wyz

= w + yz

These expressions do not represent the same function. For example, when w =y = 1 and z = 0, the left hand side is equal to 1 while the right hand side isequal to 0.

A.11 Simplifying the expression for f into

f = x1x2 + x1x2(x3x4 + x3x4)

and manipulating it using de Morgan’s rule, we can get the following circuit:

x1

x2

x3

x4

x4

x3

x1

x2

f

A.12. A possible circuit is

x1

x2

x3x4

fx1

6



x2

x3

x4

f

x1

A.14. (a) The sum-of-products expressions are

f1 = a

f2 = a⊕ b

= ab + ab

f3 = a⊕ b⊕ c

= abc + abc + abc + abc

These AND-OR circuits can be implemented using only NAND gates by a directtransformation as explained in Figure A.8. The expressions for f1, f2 and f3

require 0, 3 and 5 gates, respectively, plus 3 gates to invert the input variables a,b and c.

(b) The general block in Figure PA.2b can be implemented as

Since the leftmost block need not have an input from the left side, the XOR gateis not needed in that block, and input a is wired directly to the output of theblock. Thus, only two XOR gates are needed. They can be implemented with atotal of 8 NAND gates (see Problem A.15).

7


A.15. The required circuit is

x2

x1

x1 x2⊕

A.16. Consider the a function only. The implementation given in Figure A.37 can beseen to be correct by the following argument. The input to the inverter must bea. The 2-level NAND network implements a sum-of-products expression for the0s of the truth table column for a. (See Figure A.8). The 4-input NAND gateaccounts for the input valuation (x1, x2, x3, x4) = (0, 0, 0, 1), and the 3-inputNAND gate accounts for the input valuation (x1, x2, x3, x4) = (0, 1, 0, 0) cou-pled with the “don’t care” entry at (x1, x2, x3, x4) = (1, 1, 0, 0). The remainingfunctions in the given implementation can be veri ed in the same way.

The AND, OR, NOT implementation follows directly via replacement of theindividual NAND gate networks by AND and OR gates as shown in Figure A.8.

A.17. The stuck-at-1 fault at F1 reduces the network to

f

x4

x3x1

x21

6

7

5

8

The stuck-at-0 fault at F2 reduces the network to just a wire that implements

f = x4

8


A.18. As explained in Section A.5.1, in a CMOS circuit the pull-up network imple-ments the function f and the pull-down network implements its complement f .In our case

f = x1x2 + x3x4

andf = (x1 + x2)(x3 + x4)

The term (x1 + x2) is realized as a parallel connection of NMOS transistorsdriven by inputs x1 and x2. Similarly, the term (x3 +x4) is realized as a parallelconnection of NMOS transistors driven by inputs x3 and x4. These two parallelsubcircuits have to be connected in series to realize the product of the two terms.

In the pull-up network, the term x1x2 is realized as a series connection of PMOStransistors driven by inputs x1 and x2. Similarly, the term x3x4 is realized asa series connection of PMOS transistors driven by inputs x3 and x4. A parallelconnection of these subcircuits realizes x1x2 + x3x4.

Therefore, the desired circuit is

x1

x2 x3

x4

f

Vsupply

x2x1

x3 x4

9


A.19. The waveforms are

Clock1

0

1J

0

1K

0

1

0Q

A.20. The truth table for the NAND latch is

A B Q Q

0 0 1 10 1 1 01 0 0 11 1 0/1 1/0

This truth table describes the same behavior as the truth table in Figure A.24b

if we let A = S and B = R. The only difference is when A = B = 0 causing Q = Q= 1, but this input valuation should not be used in an SR latch. The two NANDgates at the input of the circuit in Figure A.26 provide the required inversion ofsignals S and R when Clk = 1.

A.21. Point P3 follows changes at D with 1 gate delay, and point P4 follows changes atD with 2 gate delays. If we assume that both P3 and P4 are to be stable at theircorrect values no later than when the clock goes to 0, then the minimum setuptime is 2 gate delays.

For calculating hold time, the critical case is when P1 is set to 1 as a result of theclock going to 0. This is the case when D = 1 at the clock edge and the ip- opis to be set into the 1 state. The D line must hold for at least 1 gate delay after thetrailing edge of the clock so that the output of gate 2 can get to 1 and maintainthe output of gate 1 at 0 for proper operation. Therefore, the hold time is 1 gatedelay.

10


A.22. Using all NOR gates gives the truth table

Clk D Q(t + 1)

0 0 00 1 11 x Q(t)

Therefore, the circuit is a gated D latch which is set to the value of D inputwhen Clk = 0.

A.23. The modi ed circuit is

D Q

QClock

D Q

Q

D Q

Q

D Q

Q

In

One Two⁄


D Q

Q

Clock

D Q

Q

D Q

Q

D Q

Q

Initialize

P

C C C

Right Left⁄

11


A.25. The 3-input decoder circuit is

3

2

1

0

x1

x2

x3

4

5

6

7

A.26. The up/down counter can be implemented as follows:

T Q

QClock

T Q

Q

T Q

Q

P

C CQ1 Q2 Q3

External source

1

DU /

P P

C

Count Load⁄

12


A.27. A 4-bit synchronous counter can be implemented as

T Q

QClock

T Q

Q

T Q

Q

1Q0 Q1 Q2

T Q

Q

Q3

A.28. (a) The truth table for f implemented using an 8-input multiplexer is

x1 x2 x3 f

0 0 0 10 0 1 00 1 0 x4

0 1 1 01 0 0 x4

1 0 1 x4

1 1 0 01 1 1 x4

(b) The truth table using a 4-input multiplexer is

x3 x4 f

0 0 x2

0 1 x1

1 0 x1

1 1 0

13


A.29. (a) The truth table for f implemented using an 8-input multiplexer is

x1 x2 x3 f

0 0 0 x4

0 0 1 x4

0 1 0 x4

0 1 1 11 0 0 01 0 1 11 1 0 01 1 1 x4

(b) It cannot be done with a single 4-input multiplexer.

A.30. (a) The total number of distinct functions of three binary variables is

223

= 256

(b) Functions that cannot be implemented are those requiring 3 or more productterms in the minimal sum-of-products expression, e.g. x1x2 + x2x3 + x1x3.

(c) Connect all four AND gates to a single OR gate.

A.31. (a) Using the modi ed PAL, f can be implemented as

x1 x2 x3x2x2 x1 x1x3x3

f

x4

(b) Two. They are x1 ⊕ x2 ⊕ x3 and its complement.

14


A.32. In this case the state-assigned table is

Presentstate

Next state Output z

Y2 Y1 Y2 Y1

x 0= x 0=x 1= x 1=

1

1

0

0

0

1

1

0

1

0

0

1

1

1

0

0

0

1

1

0

0

0

1

1

0

0

1

0

0

0

1

0

y2 y1

The next-state and output equations are

Y2 = xy1 + y1x

Y1 = x⊕ y2

z = y2y1

15


A.33. The state table is

Presentstate

S0

S1

S2

S3

S3

S2

S0

S1

Nextstate

The state-assigned table is

Presentstate

Y2 Y1y2 y1

0

0

1

1

0

1

0

1

1

1

0

0

1

0

0

1

Nextstate


Y2 = y2

Y1 = y1y2 + y1y2

z2 = y2

z1 = y1

16



Presentstate

S0

S1

S2

S3

S1

S2

S3

S4

Nextstate

S4

S5

S5

S0


Presentstate

0

0

1

1

0

1

0

1

y1y3 y2

0

0

1

1

0

1

0

1

0

0

0

0

1

1

1

1

0

1

1

0

1

0

1

0

0

0

d

d

1

0

d

d

0

0

0

1

1

0

d

d

Y 1Y 3 Y 2

Nextstate


Y3 = y1y2 + y1y3

Y2 = y1y2 + y1y2y3

Y1 = y1

z3 = y3 z2 = y2 z1 = y1

17


A.35. J and K inputs needed to cause the desired transitions are

Presentstate

0

0

1

1

0

1

0

1

0

1

d

d

d

d

1

0

Nextstate J K

The state-assigned table for the solution in Problem A.33 becomes

Presentstate

0

0

1

1

0

1

0

1

y1y2

1

1

0

0

1

0

0

1

Y 1Y 2

Nextstate

d

d

1

1

1

d

0

d

1

1

d

d

J1J2 K1K2

d

1

d

0

Inputs forJK ip- ops

The next-state equations are

J2 = 1

K2 = 1

J1 = y2

K1 = y2

These equations are simpler than those using D ip- ops, because the toggle fea-ture of JK ip- ops is naturally suitable for implementation of counter circuits.

18


A.36. The state-assigned table is

Presentstate

0

0

1

1

0

1

0

1

y1y3 y2

0

0

1

1

0

1

0

1

0

0

0

0

1

1

1

1

0

1

1

0

1

0

1

0

0

0

d

d

1

0

d

d

0

0

0

1

1

0

d

d

Y 1Y 3 Y 2

Nextstate

d

d

d

d

0

1

d

d

0

1

d

d

0

0

d

d

0

0

0

1

d

d

d

d

J1J3 J2

1

d

1

d

d

1

d

1

1

d

d

d

d

1

d

d

d

d

0

1

d

d

d

d

K1K3 K2

Inputs forJK ip- ops

The next-state equations are

J3 = y1y2

K3 = y1

J2 = y1y3

K2 = y1

J1 = 1

K1 = 1

19


A.37. Let the three outputs be de ned as:

z1 = 1 denotes that mechandise has to be dispensed

z2 = 1 denotes that the change is 20 cents

z3 = 1 denotes that the change is 5 cents

The outputs are speci ed as shown in the following state-assigned table

y2y1

Next state OutputsPresent

statex1x2 00=

0

0

1

1

-

-

-

-

x1x2 01= x1x2 10= x1x2 11= x1x2 00= x1x2 01= x1x2 10= x1x2 11=

Y2Y1 Y2Y1 Y2Y1 Y2Y1

0

1

0

1

0

0

1

1

0

1

0

1

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

0

0

0

0

0

-

-

-

-

S0

S1

S2

S3

z1z3z2

0

0

0

0

0

0

0

0

z1z3z2z1

z3z2z1z3z2

0

0

1

1

0

0

0

0

0

0

0

1

0

1

1

0

0

1

0

1

0

-


Y2 = x1x2y2 + x2y2y1 + x1y2

y1

Y1 = x1x2y1 + (x1 + x2)y2y1

z3 = x2y2y1 + x1y2y1

z2 = x1y2

z1 = (x1 + x2)y2 + x1y1

There are no equivalent states in the table.

20



Presentstate

Next state Output z

x 0= x 0=x 1= x 1=

S0

S1

S2

S1

S1

S1

S0

S2

S0

0

0

0

0

0

1


Presentstate

Next state Output z

Y2 Y1 Y2 Y1

x 0= x 0=x 1= x 1=

0

0

1

1

0

1

0

1

0

0

0

d

1

1

1

d

0

1

0

d

0

0

0

d

0

0

0

d

0

0

1

d

y2 y1


Y2 = xy1

Y1 = x

z = xy2

21



Presentstate

Next state Output z

x 0= x 0=x 1= x 1=

S0

S1

S2

S1

S1

S1

S0

S2

S0

0

0

1

0

0

1


Presentstate

Next state Output z

Y2 Y1 Y2 Y1

x 0= x 0=x 1= x 1=

0

0

1

1

0

1

0

1

0

0

0

d

1

1

1

d

0

1

0

d

0

0

0

d

0

0

1

d

0

0

1

d

y2 y1


Y2 = xy1

Y1 = x

z = y2

22


problems - university of icelanddaj2/tolvutaekni/appendixa.pdf4) a.14 a number code in which...

Documents