process and statistical process controlsstaff.utar.edu.my/limsk/process integration and ic...

UNIVERSITI TUNKU ABDUL RAHMAN

Process

and Statistical process

Controls

Dr. Lim Soo King

03/26/2013

Contents Pages

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Chapter 4 Process and Statistical Process Controls ...................... 95

4.0 Introduction .............................................................................................. 95

4.1 Contamination Control ............................................................................ 95

4.1.1 Source of Contaminant/Particles ...................................................................... 96 4.1.2 Clean Facility ...................................................................................................... 97 4.1.3 Wafer Cleaning .................................................................................................. 99

4.1.4 Gettering ........................................................................................................... 100

4.2 Quality Control ....................................................................................... 100

4.3 ESD Control ............................................................................................ 101

4.3.1 Electrostatic Discharge Protection Circuit Design........................................ 101 4.3.2 Workstation ESD Protection and Prevention Design ................................... 108 4.3.3 People ESD Protection and Prevention Design ............................................. 109

4.4 Statistical Control................................................................................... 109

4.4.1 Establishing Statistical Control Chart for Process Mean ............................ 111

4.4.1.1 Estimating 0 by X and 0 by R /d2 ......................................................................... 111

4.4.1.2 Estimating 0 by X and 0 by s /c4 ............................................................................ 113

4.4.2 Establishing Statistical Control Chart for Process Standard Deviation . 113

4.4.2.1 Using R /d2 Statistics ..................................................................................................... 113

4.4.2.2 Using s /c4 Statistics ....................................................................................................... 114 4.4.3 Establishing Statistical Control Chart for X and R Charts ......................... 115

4.4.4 Special Charts ................................................................................................... 115 4.4.4.1 Pre-Control Chart .......................................................................................................... 116 4.4.4.2 D-NOM Charts ............................................................................................................... 117

4.4.4.3 Standardized X and R Charts .................................................................................... 118

4.5 Process Capability Ratio and Process Capability Index .................... 121

4.5.1 Process Capability Ratio Cp ............................................................................ 121 4.5.2 Process Capability Index Cpk .......................................................................... 123 4.5.3 Taguchi Process Capability Index Cpm .......................................................... 125

4.5.4 Ppk Index ............................................................................................................ 126

Exercises ........................................................................................................ 128

Bibliography ................................................................................................. 130

List of Figure Page

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Figure 4.1: The number of particle and diameter of particle for various classes of

cleanliness ........................................................................................................ 97 Figure 4.2: Cleaning step and composition of RCA solution ............................................. 99 Figure 4.3: The block diagram of a CMOS input circuits ................................................ 101 Figure 4.4: Human Body Model and Machine Model for ESD testing ........................... 102

Figure 4.5: Pictorial view showing damage caused by ESD ............................................ 103 Figure 4.6: Cross sectional view of resistor and clamping diode ..................................... 104 Figure 4.7: ESD protection network of Fig. 4.6 ............................................................... 104 Figure 4.8: Layout of ESD protection network of Fig. 4.7 .............................................. 105 Figure 4.9: I-V characteristics of an n-type diffusion resistor .......................................... 105

Figure 4.10: I-V characteristics of a diode ......................................................................... 106

Figure 4.11: ESD protection network utilizing clamping diode and limiting resistor ....... 106 Figure 4.12: ESD protection network with thick oxide transistor ...................................... 107

Figure 4.13: Gate grounded n-MOSFET characteristic ..................................................... 108 Figure 4.14: ESD protected workstation ............................................................................ 109 Figure 4.15: Data collected for the hermetic lid length at incoming store room ................ 112

Figure 4.16: Statistical control chart of the data shown in Fig. 10.1 using X and R as

estimate .......................................................................................................... 112

Figure 4.17: Statistical control chart of the data shown in Fig. 10.1 using X and s as

estimate .......................................................................................................... 113 Figure 4.18: A pre-control chart ......................................................................................... 116

Figure 4.19: Data for D-NOM chart ................................................................................... 117

Figure 4.20: Data for standardized X and R charts ........................................................... 119

Figure 4.21: Control chart of standardized mean X .......................................................... 120 Figure 4.22: Control chart of standardized range R ........................................................... 120 Figure 4.23: Processes with same Cpk but different Cpm indices ........................................ 126

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Chapter 4

Process and Statistical Process Controls

_____________________________________________

4.0 Introduction

In integrated circuit manufacturing involves design, fabrication, assembly, and

test processes. Besides keeping the facility clean and free-off contamination, the

other aspect is to ensure that each process step conforms to specifications. Thus,

it is necessary to implement quality control scheme. Quality control

monitoring/checking has become an important process and is normally imposed

at the end of certain critical process steps. Besides the quality control at in

process step, quality control procedure is also required to be implemented at the

incoming material inspection stage.

With the quality control in place at critical process steps and at incoming

material acceptance stage, it is also necessary to monitor the process

stability/reliability and process capability of the machine/equipment used to

process the device.

Besides, the aspects of quality control, it is necessary to control static

electricity damage to the integrated circuit by discharging away the static

electricity generated by human being handling the circuit.

In this section, student will learn the methodology to keep the facility

clean, the process of quality and ESD control, and how in process quality

control and incoming control are performed. The concepts of how to establish

statistical process control charts and at the same time learn how use the collect

data to determine the process capability ratio CP and process capability index

CPK of the machine/equipment used for the manufacturing processes. At the last

of learning, the concepts and methods used to determine the reliability of

integrated circuit are studied.

4.1 Contamination Control

In the modern sub-micron integrated circuit fabrication, it requires a multi-

million dollar facility that consists of equipment for various fabrication process

steps, cleaning station, and the source material. Beside the equipment, stations,

materials are people who are the working in the facility.

04 process and Statistical Process Control

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The primary quality requirement for the integrated circuit IC facility is

cleanliness. The facility is subjected to too many sources of contaminant, which

is harmful to device under fabrication. It is a known fact that any contaminant

has a size large enough to cover the active area of a sub-micron device. If such

type contaminant is resided on the active area of the device during fabrication,

the consequence is malfunction of the device. Thus, it is necessary for a modern

integrated circuit fabrication facility to keep the contaminants or particles level

below part per million ppm or part per billion ppb level.

In modern IC facility set-up, it employs three-tiered approaches to control

the particles level and contaminant level, which are clean facility, wafer

cleaning, and gettering. Let’s describe all approaches in the process of learning

this chapter.

4.1.1 Source of Contaminant/Particles

Contaminants/particles are mainly come from people who work in the

fabrication facility, assembly, and test areas, equipment in the facility, air

circulating in the facility, and the supplied materials from external vendor.

Particles contaminant such as dust particle, particle from cosmetic, powder

in the air always present in a distribution of size and shape. However, the most

concern size is between 10nm and 10m. Particle of size 10nm tends to

coagulate into a larger size and if it is larger than 10m, it will fall by gravity on

the surface. Particles of size between 10nm and 10m remain suspend in air for

a long time. Such particle type can be deposited on the surface primary through

two mechanisms, which are Brownian motion and gravitational sedimentation.

The Brownian motion is a random motion that can occasionally bring the

particle and deposit it on the surface.

People typically emits 5-10 millions particles and contaminant per minute

from each cm2 of surface. The particles/contaminants emitted by people are

mainly from exhaled air, skin, and hair etc which consist of dust particle, water,

salt, carbon dioxide, oxygen, and contaminants such as nickel, manganese,

phosphorus etc from powder and cosmetic.

Raw materials such as acid, solvent that brought in from vendor normally

contain contaminants after handling even though they are electronic grade

materials. The contaminants are required to be filtered off before using.


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4.1.2 Clean Facility

Knowing the sources of contaminant, certainly the solution is to eliminate them.

If it cannot be eliminated then control the amount to the acceptable level is

desired.

A modern sub-micron IC fabrication facility normally is built with class

100 or class 10 cleanliness standards. A class X simply means that each cubic

foot of air in the facility has less than X total number of particles of size greater

than 0.5m. In the critical process area such as ion implantation, class 1

cleanliness is required.

Figure 4.1 shows the number of particle versus the diameter of particle

expectation for different class of cleanliness for fabrication of the VLSI

integrated circuit. Take for an example, the class 100 environment, in one cubic

foot of air, the number of particle of size greater than 0.5m should not be more

than 100.

Figure 4.1: The number of particle and diameter of particle for various classes of cleanliness

Since people working in the IC fabrication area are continuously emitting

contaminant particles which mean this source of contaminant cannot be

eliminated. As the result, the particle level in the air will increase. Thus, the

control procedure becomes necessary.

The air in the IC fabrication facility is sucked into the air duct via the vents

mounted either on the wall or on the raise floor of the facility. The air is then


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channel to the ceiling with portion of it is released to the atmosphere, portion of

it is mixed with external filter air. It is then forced through the high efficiency

particulate air HEPA filter residing in the ceiling at the velocity of 50cms-1

before it is released into the facility through vent mounted on the ceiling. The

release and mixing is necessary to maintain the level of oxygen in the facility.

The HEPA filter is composed of thin porous sheets of trafine glass fiber of

diameter less than 1m. Large particles having diameter greater than 1m are

trapped by the filter, while the small particles that can pass through will be stuck

to the filter due to electrostatic charge. Even if the small particles are not

charged, due to work function difference between the particles and filter

materials, eventually they are stuck in the filter. The air after filtered by HEPA

filter normally has cleanliness better than class 1.

People working in the IC fabrication facility required to wear the “bunny

suit”, which covers the body and cloth – the source of contaminant from fabric,

human sweat, and a pair of clean room shoes. The people are also required to

wear face mask to block the particles from the exhaled air getting into the

facility. Before entering into the fabrication facility, people have to be cleaned

by air shower. Air shower will blow away loose particles/contaminant residing

on the cloth and body. Beside all these procedures, people who are working in

the fabrication facility are barred from using cosmetic and powder.

Chemical as such sulfuric acid, hydrogen peroxide, acetone, aqueous

alkaline, etc used for the fabrication process are to be specified as electronic

grade types with level of contaminant control to a specific electronic grade

standard.

Water is an important solvent for cleaning and rinsing purposes. City water

from the tap is too dirty containing too much of contaminants and particles such

as chlorine, heavy metals, silt, bacteria etc and is not suitable for cleaning and

rinsing. De-ionized DI water is normally used. DI water is the highly purified

and filtered water obtained from reverse osmosis process through 0.1nm filter. It

has all traces of ionic, particles, and bacterial contaminants been removed.

Another important parameter of DI water is the resistivity. This parameter

is important because too low the resistivity value means too much the

dissociation of water molecule i.e. too much H+ and OH

- ions, which would

create too much static charge problem on the wafer knowing that static charge

will attract particles and contaminants.


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A basic DI water system can achieve resistivity of 18.0Mohm-cm versus

the theoretical resistivity of pure water at 250C, which is 18.3Mohm-cm, with

fewer than 1.2 colonies of bacteria per milliliter and no particle size larger than

0.25m.

4.1.3 Wafer Cleaning

By nature, there is a layer of native oxide grown on any wafer due to presence

of oxygen in the atmosphere and also due to presence of contaminants such as

wax, resin, greasy film, sodium chloride, copper, and etc. Moreover, each

process steps, inorganic and organic chemicals such as organic photoresist,

hydrochloric acid, developing solution etc are used. The residue of the chemical

has to be cleaned before proceeding to next process step. Thus, it is necessary to

have two types cleaning solution – on for organic material and one for inorganic

materials.

Hydrofluoric acid is used to remove oxide that formed on surface of silicon

wafer. Ammonium hydroxide, sulfuric acid, and hydrogen peroxide are

typically used to remove organic contaminants, whilst hydrogen peroxide and

hydrochloric acid are used to remove metal contaminants. De-ionized DI water

is then used as solvent for cleaning or rinsing. The wafer is finally dried in

nitrogen environment to prevent oxidation and contamination. The right

proportional mixture of the above mentioned solvents are termed as Radio

Corporation of America RCA solution that was developed in 1965. The

solutions are divided into solution clean 1 and solution clean 2. Figure 4.2

shows the eight cleaning steps for cleaning the wafer to remove inorganic,

organic, and native oxide contaminants before actual fabrication process steps

begin. The figure also shows the composition of various solutions and

temperature requirements during cleaning process.

Step Solution Temperature Type of Contaminant to be

removed

1 H2SO4 + H2O2 (4:1) 1200C Organic particle

2 DI water 250C Rinse

3 NH3OH + H2O2 + H2O (1:1:5)

RCA clean 1 80

0C – 90

0C Organic particle


5 HCl + H2O2 + H2O (1:1:6)

RCA clean 2 80

0C – 90

0C Inorganic ion


7 HF + H2O (1:50) 250C Native oxide


Figure 4.2: Cleaning step and composition of RCA solution


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4.1.4 Gettering

Gettering is the third line of control to avoid ionic contaminant reaching the

active region of the integrated circuit after facility cleaning and wafer cleaning.

The active regions of the integrated circuit usually occupy a small fraction of

the volume of wafer. If there are contaminants resided on them, once they are

driven away, the performance of the circuit usually will not be affected because

the concentration of contaminant on the active region is now too low to be

influential.

Getting is a process of getting the unwanted contaminant resided in the

wafer to the non-critical part of wafer such as the backside of the wafer or far

away from the active parts on the top of wafer. The contaminants that are the

most concern which requiring gettering are the heavy transition elements such

as titanium, chromium, mercury, copper etc. They are normally the deep level

contaminants found in silicon wafer due to their high diffusivity coefficient.

The other most concern contaminants are alkali ions such as sodium Na+ and

potassium K+ that usually come from human sweat commonly residing in

dielectric material that can cause threshold shift of the MOSFET.

The processes of gettering consist of three steps. Firstly, the elements to be

gettered must be freed from any trapping sites that they may currently occupy

and made mobile. Secondly, they must diffuse to the gettering site and finally,

they must be trapped.

4.2 Quality Control

Quality control can be divided into two parts, which are in-process quality

monitoring and Incoming Quality Control. In-process quality

monitoring/inspection always helps to check and balance if the device is

manufactured according to the specifications and if the operator processes the

device according to the operational procedure. Normally the samples according

to a specific sampling plan (usually 0.025 AQL sampling plan) are pull from a

process lot/batch at the end of critical process step such as die attach, wire

bonding, initial/final tests at temperature. If there is any failure detected, non-

conformance notice is normally issued to manufacturing line manager for taking

necessary collective actions. After the corrective action has been taken, quality

control personnel will take new samples to check for conformance to

specifications. When conformance is achieved, the particular process is then

released to manufacturing for further processing of device. The failed sample lot

is either re-processed or declared as total reject.


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Let’s take a critical process step, which is wire bonding. After wire

bonding process, the quality control personnel will pull the samples according

to specific quality sampling plan to check the wire loop height and wire bond

strength according to specifications. Besides, he/she also checks if there is

missing wire, bond crack, wrong bonding etc. If there is any non-conformance

detected, stop process notice is issued. The process will only be allowed after

collective action has been taken and the subsequent samples pass the quality

control check/test.

In test operating, the quality control personnel would pick the sample

according to the quality sampling plan to test to see if all selected samples pass

the electrical test specifications. If selected samples fail the sampling plan, the

tested lot is normally re-tested and re-submitted for sampling test.

At incoming inspection, the quality control personnel will pull samples from the

incoming materials like the hermetic package lid to check if the dimensions,

strength of the material etc. meeting the specifications. If the samples fail the

sampling plan, the batch of hermetic lids is return to vendor.

4.3 ESD Control

The input circuit of the device provides electrostatic discharge ESD protection,

level conversion, noise removal, and buffer the input signal. The block diagram

of the input circuit is shown in Fig. 4.3.

Figure 4.3: The block diagram of a CMOS input circuits

4.3.1 Electrostatic Discharge Protection Circuit Design

CMOS integrated device is easily damaged by electrostatic discharge ESD due

to the fragile physical structure of MOS transistor. The gate of MOS transistor


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is capacitive with a thin dielectric, which can be easily punctured by high

voltage. If the electric field across the oxide is more than 1x107V/m, the

tendency of getting damaged oxide is very high. Once the oxide is damaged, the

MOSFET is non-longer function as a switch. There will have leakage resulting

high quiescent current and invalid data will be recorded.

Human body and machine are the major culprits of causing ESD damage to

the device. As the consequence, the Human Body Model HBM and Machine

Model MM are the commonly models used to study and test the susceptibility of

the device by ESD. The HBM and MM models are represented by the RC

network circuits as shown in Fig. 4.4. DUT denotes device under test.

Figure 4.4: Human Body Model and Machine Model for ESD testing

The Charged Device Model CDM is another model usually used to interpret the

discharge of the device package due to accumulation of the charge during

process. The device is usually charged in the air and discharge through a probe

to ground level with the assumption that there is 1.0G resistor connected

between them. There are many other models available such as Field Induction

Model, Floating Induction Model, and Charged Board Model etc.

Let’s illustrate an example of how ESD damage the device by calculating

the amount of current received by a device with static charge of 100V

discharged through a human being. By calculation using the Human Body

Model, the discharge time constant is RC = 100pFx1.5k = 0.15s. The amount

of charge transferred to the device is Q = CV = 100pFx100V = 10nC.

Translating this amount of charge to current, it is as high as s15.0

nC10Q

ti =

66.6mA. If this amount of current is to be discharged through an oxide with

cross sectional area of 0.12m x 0.96m, the current density is equal to

578.1mA/m2. This current-density with a short discharge time of 0.15s can

easily burn the diffusion junction or rapture the oxide.


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Based on this illustration, one way to control the current density is to

increase the discharge time that reducing the peak current. The other way of

course is to distribute this amount of current to be shared by a number of the

protection device so that the current density is reduced to a tolerable level.

Figure 4.5 illustrates a pictorial view of the damage caused by ESD at

channel near the drain of MOS transistor. This damage can be caused by too

high current density that has created high temperature beyond the maximum

allowable junction temperature of the device.

Figure 4.5: Pictorial view showing damage caused by ESD

One of many protective ways to prevent the damage is by designing the input

with current limiting resistor and clamping diode so that excessive charge can

be limited and discharged via diode. This can be achieved by designing the n-

well connecting the bonding pad. The cross-sectional view of the current

limiting resistor and clamping diode is shown in Fig. 4.6. The value of limiting

resistor is usually in between 1.0k to 3.0k.


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Figure 4.6: Cross sectional view of resistor and clamping diode

The design can be viewed as a limited resistor connected to a diode as shown in

Fig. 4.7, where it provides not only the limiting current but also providing the

discharge path for excessive charge whereby the diode will go into breakdown

mode to discharge the excessive charge.

Figure 4.7: ESD protection network of Fig. 4.6

The layout of the ESD protection circuit shown in Fig. 4.7 is shown in Fig. 4.8.


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Figure 4.8: Layout of ESD protection network of Fig. 4.7

The current-voltage characteristics of the resistor and diode used as the

protection for ESD from damaging the input circuits are illustrated respectively

in Fig. 4.9 and Fig. 4.10 respectively.

The current limit for the n-type diffusion resistor is saturation current Isat.

Once the current goes beyond this point, the resistor will incur permanent

damage, which is not recoverable.

Figure 4.9: I-V characteristics of an n-type diffusion resistor

The current limit for the diode is 10-5

A/m. Once the current goes beyond this

point, the diode will incur permanent damage due to thermal breakdown, which


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is not recoverable. Once the static charge subsided, the diode would have

leakage that cannot be acted as ESD protection circuit.

Figure 4.10: I-V characteristics of a diode

Other example showing the topology of the ESD protection networking utilizing

limiting resistor and diode is shown in Fig. 4.11. The resistor R is used to limit

the current. The lower diodes D1 and D2 are used to bypass positive static

electricity charge by mean avalanche breakdown, while the upper diode D3 is

used to bypass negative static electricity by similar mean.

Figure 4.11: ESD protection network utilizing clamping diode and limiting resistor


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If there is positive charge at the input pad, the excessive charge is discharged

via diode D1 and D2 and limiting resistor R. If there is negative charge at the

input pad, the excessive charge is discharged through diode D3 and limiting

resistor R. In both cases there is RC constant that limits the rate of discharge.

This method of ESD protection is limited to 1,000V of static electricity. A better

design utilizing thick oxide punch-through n-MOS transistor together with the

gate grounded p-MOS and n-MOS transistors is shown in Fig. 4.12. This design

can yield protection for more than 3,000V of static electricity. The characteristic

of a gate grounded n-MOS transistor is shown in Fig. 4.13. From the circuit

shown in Fig. 4.12, once would notice that there are more protection circuit for

positive static charge rather than negative charge. The reason being, human

being is net positive charge generator.

Figure 4.12: ESD protection network with thick oxide transistor

The gate grounded n-MOS transistor acted as n+pn

+ diode, whereby positive

static charge causes avalanche breakdown at the n+p junction at drain side. The

breakdown voltage is 9.3 volts as shown in Fig. 4.13. After the breakdown, the

current density is very high and voltage dropped across the channel source is

basically the pn+ junction forward voltage. This phenomenon is termed as

snapback mode. As shown in Fig. 4.13, the current limit is 5.0mA/m. If the

current is larger than the current limit point, thermal breakdown would occur

resulting permanent damage to the gate grounded n-MOS transistor. Gate

grounded p-MOS transistor is used to bypass negative static charge. Similarly

explanation can be used to describe how this type of transistor bypassing the

negative static charge.


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Transistor M1 and M3 are thick oxide transistors, where M1 and M3 are

punch through types. Transistor M2 is the thin oxide type. When there is

positive charge at input pad, the excess charge causes the n-punch through

transistor M1 to go into avalanche breakdown and excess charges are drain to

ground through its shorted source and gate. When there is negative charge at

input pad, the excess charge causes the p-punch through transistor M3 to go into

avalanche breakdown and excess charges are drain to VDD.

Figure 4.13: Gate grounded n-MOSFET characteristic

Although, punch through transistor works fine for discharge excess charge for

protection of inner circuit, it may cause secondary breakdown which can cause

permanent damage to the input protection circuit.

4.3.2 Workstation ESD Protection and Prevention Design

Beside in circuit ESD protection design, it is necessary to design the

workstation such that it protects the integrated circuit being damaged by ESD

and more importance is to prevent generation of statistic charge. A typical ESD

protected workstation is shown in Fig. 4.14.


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Figure 4.14: ESD protected workstation

4.3.3 People ESD Protection and Prevention Design

People working in the area must always be kept at the lowest potential as

possible. It is required to prevent there is potential difference between the

people and the integrated circuit.

The normal way to achieve lowest potential is by grounding the people

who work in the IC manufacturing area with a ground cord connecting the wrist

and the utility ground of the power system.

4.4 Statistical Control

In the aspects to monitor the process stability, it is necessary to set-up statistical

process control chart SPC to monitor the repeatability and reproducibility of the

process to monitor if there is variation due to machine, time factor, operator

factor, environmental factor etc. Let’s take the case wire bonding operation, the

bond strength in gram-force and height of wire loop in mm can be plotted on

control charts at specified interval to the check the trends of the bond strength

and height of wire loop. If there is abnormal deviation from the targeted values

as well as their distribution variation over a period of the time, analysis can be

done. Since the data is taken real time in the manufacturing line, any deviation

from the pre-specified control limits would immediately alert the operator to

find the underlying causes and correct the problem before large amount non-

conformance or defective devices are produced. Comparison of SPC charts can


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also be done to check for variations between machines particularly this case the

wire bonding machines.

Any conformance manufacturing process, over a period of time process

data has mean 0 value and variance 2

0 value. Thus, one can say these data

values are in control since the process is a conformance process. It is important

and desires that the mean and variance 2 of the subsequent process

distribution throughout the entire duration of the process remains equal to 0

and 2

0 irrespective of time and duration. To continuous ensuring = 0

and 2

0

2 , it requires continuous monitoring by an easier mean of establishing

the statistical control chart SPC. Statistical speaking, it is the testing of

hypothesis that is the null hypothesis H0: = 0 and H0: 0 versus the

alternative hypothesis, which is H1: 0 and H1: 0 . If both null

hypotheses are true, one says that the process is in control. If either one or both

are not true then the process is out of control.

When setting up a hypothesis testing for the mean , one considers the null

hypothesis = 0 versus the alternative hypothesis 0, selecting an unbiased

statistic with minimum variance as possible, which means x , specify

probability of Type I error, which is = P[Rejecting H0, when it is true], and

using and distribution of x to set-up acceptance region for x that is accept the

null hypothesis H0 if n/Z 02/0 < x < n/Z 02/0 and reject the null

hypothesis H0 if x < n/Z 02/0 or x > n/Z 02/0 .

The statistical control chart has three lines, which are upper control limit

line UCL, center line CL, and lower control limit line LCL. These lines are

established based on the data collected over a period of time from a normal

conformance process and in the control acceptance region mentioned in the

above paragraphs. Thus, the upper control limit UCL line is defined as

UCL = n/Z 02/0 (4.1)

The lower control limit LCL line is

LCL = n/Z 02/0 (4.2)

The center line CL is


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CL = 0 (4.3)

where n is equal to number of sample. is probability of accepting the null

hypothesis when it is actually not true. The value of is taken as 0.0026, which

means that the 99.74% of the distribution is in the acceptable region. Z/2 is z-

score for the two-tailed standard normal distribution function, which has a value

3.00 for = 0.0026. Based on these statistical values, equation (4.1) and (4.2)

will become

UCL = n/3 00 (4.4)

The lower control limit LCL line is

LCL = n/3 00 (4.5)

The type II error will not be discussed here, where it defines equals to the

probability of the accepting the null hypothesis when actually it is not true.

Once the control chart is established and in used. If the trend of chart has

any of the following stated abnormality, collective action must be taken for the

specific process. The rules

Seven points in a row on one side of the center line.

Seven points in a row consistently going up or coming down.

Substantially more than 2/3 of the points close to the center line.

Substantially less than 2/3 of the points close to the center line.

4.4.1 Establishing Statistical Control Chart for Process Mean

Presented in this section are two ways to established the statistical control chart

SPC for process mean X using X , R /d2, and s /c4.

4.4.1.1 Estimating 0 by X and 0 by R /d2

Let’s use the data shown in Fig. 4.15 to illustrate how 0 and 0 can be

estimated by the mean X of the sample at defined interval and the range R of the

sample to estimate the value of 0.


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Batch # Sample 1

x1

Sample 2

x2

Sample

3

x3

Sample

Mean X

Range

R

Standard

Deviation or s

1 4.5 4.6 4.5 4.53 0.1 0.06

2 4.6 4.5 4.4 4.50 0.2 0.10

3 4.6 4.5 4.4 4.50 0.2 0.10

4 4.4 4.6 4.4 4.47 0.1 0.12

5 4.3 4.5 4.4 4.40 0.1 0.10

Average X = 4.48 R = 0.18 or s = 0.095

0 = 4.48 and 0 = 0.094

Figure 4.15: Data collected for the hermetic lid length at incoming store room

Let X be the grand average of the mean X for five batches of hermetic lid

length and R be the grand average of the range R for five batches of hermetic

lid length. The mean 0 can then be estimated by X and the standard deviation

(0) is estimated by R /d2, whereby the value of d2 can be obtained from the

constant table (refer to Appendix B) used for estimation and construction of

control chart. For the sample size of n = 3, d2 value is 1.6929. Thus, the

established lines of the control chart are: UCL = )nd/(R3X 2 =

)36929.1/(18.0x348.4 = 4.66, LCL = )nd/(R3X 2 = )36929.1/(18.0x348.4 =

4.29, and CL = 4.48.

The plot of the established statistical control chart is shown in Fig. 4.16.

Figure 4.16: Statistical control chart of the data shown in Fig. 10.1 using X and R as

estimate


- 113 -

4.4.1.2 Estimating 0 by X and 0 by s /c4

Let or s be the grand average of the standard deviation then the standard

deviation 0 is estimated by /c4, whereby the value of c4 can be obtained from

the constant table used for estimation and construction of control chart. For the

sample size of n = 3, c4 value is 0.9213. Thus, the established lines of the

control chart are: UCL = )nc/(3X 4 = )39213.0/(095.0x348.4 = 4.65, LCL =

)nc/(3X 4 = )39213.0/(095.0x348.4 = 4.30, and CL = 4.48.

The plot of the established statistical control chart is shown in Fig. 4.17.

Figure 4.17: Statistical control chart of the data shown in Fig. 10.1 using X and s as

estimate

4.4.2 Establishing Statistical Control Chart for Process Standard

Deviation

Presented in this section are two ways to established the statistical control chart

SPC for process standard deviation s using R /d2, and s /c4 statistics. The lengthy

discussion of how to establish the statistical control chart using these two

statistics will not be described.

4.4.2.1 Using R /d2 Statistics

The formulae for the lines of the control chart for process standard deviation

established using R /d2 statistics are


- 114 -

LCL = Rd/d31 23 = RD3 (4.6)

UCL = Rd/d31 23 = RD4 (4.7)

CL = R (4.8)

The values of d2, d3, D3, and D4 can be obtained from the constant table (refer to

appendices) used for estimation and construction of control chart. For the

sample size of n = 3, d2 = 1.6929, d3 = 0.8884, D3 = 0, and D4 = 2.5743. One

may ask; why D3 is equal 0 instead of -0.5743. The reason being the standard

deviation cannot be a smaller than 0. Using data shown in Fig. 2.19, the lines of

the control chart are: LCL = Rd/d31 23 = 0, UCL = Rd/d31 23 = 0.4639, and

CL = R = 0.18.

4.4.2.2 Using s /c4 Statistics

The formulae for the lines of the control chart for process standard device

established using s /c4 statistics are

LCL = sc

c131

4

4

= sB3 (4.9)

UCL = sc

c131

4

4

= sB4 (4.10)

CL = s (4.11)

The values of c4, B3, and B4 can be obtained from the constant table used for

estimation and construction of control chart. For the sample size of n = 3, c4 =

0.8862, B3 = 0, and B4 = 2.5684. One may ask why B3 is equal 0 instead of -

0.14198. The reason being the standard deviation cannot be a smaller than 0.

Using data shown in Fig. 10.1, the lines of the control chart are: LCL =

sc

c131

4

4

= sB3 = 0, UCL = s

c

c131

4

4

= sB4 = 0.244, and CL = s = 0.095.


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4.4.3 Establishing Statistical Control Chart for X and R Charts

X chart is meant for individual measurement and R chart is meant for moving

range. The sample taken at designated interval is one not like the earlier case

that has more than one. The acceptable control limits of the process mean X is

n/3 00 = nd/R3 20 taking is equal to 0.0026. Since for individual

measurement n = 1, then the for formulae for the lines of control chart are

2d/R3XLCL (4.12)

CL = X (4.13)

2d/R3XUCL (4.14)

Since moving range is calculated from two successive data, thus, d2 is equal to

1.128 taken from the constant table used for estimation and construction of

control chart. The formulae for the lines of control charts are:

2d/R3XLCL R66.2X , CL = X , and 2d/R3XUCL R66.2X .

The formulae for the statistical control chart for moving range R chart with

assumption that is equal to 0.0026 are

RDLCL 3 (4.15)

CL = R (4.16)

RDUCL 4 (4.17)

From the constant table used for estimation and construction of control chart, D3

= 0 and D4 = 3.2672. Thus, the formulae for the moving range R control charts

are; 0LCL , CL = R , and R267.3UCL .

4.4.4 Special Charts

There are situations where it may be difficult to take a sample of size greater

than one or when only one measurement is meaningful each time. Some

examples of these situation are the production rate is very slow or the batch size

is very small or a continuous process such as chemical process, measurement on

some quality characteristics, such as viscosity of paint or thickness of insulation

on a cable, varies only a little between successive observations. Based on these


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examples, it is difficult to establish SPC charts like those discussed earlier. Let’s

discuss a few methods to overcome these situations.

4.4.4.1 Pre-Control Chart

Individual measurement is plotted on this chart. This is suitable for situation

where the size of a batch is small. The control limits are established based on

the specification limits. As an example, let the specification limits for a quality

characteristic be 0.5±0.002, which means LSL = 0.498 and USL = 0.502. The

center line of the chart is located at the nominal size of 0.500. Horizontal lines

are drawn at the upper specification limit of 0.502) and the lower specification

limit of 0.498. In addition, horizontal lines are also drawn at nominal size ±1/4

× (USL – LSL).

In this example, these lines are at 0.5 – 1/4x(0.502 – 0.498) = 0.499 and 0.5

+ 1/4x(0.502 – 0.498) = 0.501. The regions above the USL and below the LSL

are called the red zone, the interval between nominal size – 1/4 x total tolerance

and nominal size + 1/4 x total tolerance is called the green zone, and the regions

between the red and green zones are called the yellow zone. The control chart is

shown in Fig. 4.18.

Figure 4.18: A pre-control chart

The following rules are used while setting up the process:

1. Collect the measurements and plot them on the chart until five

consecutive values fall in the green zone.


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2. If a measurement data falls in the yellow zone, restart the count to obtain

five consecutive pieces in the green zone. Do not adjust the process.

3. If two consecutive data fall in the yellow zone or one value falls in the

red zone then adjust the process.

4. When five consecutive measurement data fall in the green zone, approves

the setup as in-control process and starts regular manufacturing.

During regular manufacturing, sample two consecutive components every h

interval such as 10 minutes and follow these rules:

1. If the first data falls in the green zone, do not plot the second value and

continue the process.

2. If the first data falls in the red zone, stop the process and investigate.

3. If the first data falls in the yellow zone, then plot the second value. If it

falls in the green zone then continue the process, otherwise, stop the

process and investigate.

This chart is simple to maintain, which is very important. One main

disadvantage is that the information presented by the chart regarding the

variability of the process is incomplete.

4.4.4.2 D-NOM Charts

In these charts, the deviations of the characteristics from their respective

nominal values are used as the observations. The calculations of the control

limits are done in the same manner as in the regular X and R charts. Let’s use

the data shown in Fig. 4.19 to establish D-NOM charts. The nominal values of

two parts are 30.0 and 20.0 respectively were produced using an equipment.

Batch Part Obs 1 Obs 2 Obs 3

Dev. of

Obs 1

xi from

nominal

value

Dev. of

Obs 2

xi from

nominal

value

Dev. of

Obs 3

xi from

nominal

value

Test

Statistics

x

Test

Statistics

R

1 A 30 31 32 0 1 2 1.00 2

2 A 29 30 31 -1 0 1 0.00 2

3 A 28 29 32 -2 -1 2 -0.33 4

4 B 20 22 21 0 2 1 -0.67 2

5 B 20 22 19 0 2 -1 0.33 2

6 B 22 21 18 2 1 -2 0.33 4

7 B 20 19 18 0 -1 -2 -1.00 2

8 B 19 20 20 -1 0 0 -0.33 1

X = 0.084

R = 2.375

Figure 4.19: Data for D-NOM chart


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D-NOM charts are established based on the assumptions that the process

standard deviation is the same for all parts and sample size is constant. The

control limits of the established are X and R charts are as follows:

X chart

UCL = RAX 2 (4.18)

LCL = RAX 2 (4.19)

CL = X (4.20)

From Appendix B, A2 is equal to 1.0231 for sample size n = 3.

R chart

UCL = RD4 (4.21)

LCL = RD3 = 0 (4.22)

CL = R (4.23)

From Appendix B, D3 is equal to 0 and D4 is equal to 2.575 for n = 3.

4.4.4.3 Standardized X and R Charts

These charts are used if the assumption that the standard deviation is not the For

the part type j test statistic, let X0j be the target value for part type j and jR be

the average range of part type j then

X chart test statistics = j0jj R/Xx = (4.24)

where 0jj Xx is equal to n/Xxn

1

i

0jij and n is the sample size. The X chart

test statistics is also equal to jij R/x if X0j is equal to zero. The control limits of

standardized X shall be

LCL = -A2 (4.25)


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UCL = A2 (4.26)

CL = 0.0 (4.27)

The R chart test statistic is equal to jij R/RR and the control limits are

LCL = D3 (4.28)

UCL = D4 (4.29)

CL = 1.0 (4.30)

Let’s now use the data shown in Fig. 4.20 to establish standardized X and R

charts.

Batch Part

Dev. of

Obs 1

xi

Dev. of

Obs 2

xi

Dev. of

Obs 3

xi

jx

Rj

Test

Statistics

x

Test

Statistics

R

1 A 0 1 2 1.00 2 1/2.67 = 0.375 2/2.67 = 0.75

2 A -1 0 1 0.00 2 0.00 2/2.67 = 0.75

3 A -2 -1 2 -0.33 4 -0.33/2.67

= -0.124 4/2.67 = 1.50

67.2R

4 B 0 2 1 0.67 2 0.67/2.2 = 0.305 2/2.2 = 0.909

5 B 0 2 -1 0.33 2 0.33/2.2 = 0.15 2/2.2 = 0.909

6 B 2 1 -2 0.33 4 0.33/2.2 = 0.15 4/2.2 = 1.818

7 B 0 -1 -2 -1.00 2 1.00/2.2 = -0.455 2/2.2 = 0.909

8 B -1 0 0 -0.33 1 -0.33/2.2 = -0.15 1/2,2 = 0.455

2.2R

Figure 4.20: Data for standardized X and R charts

The control limits of standardized X and R charts are:

Standardized X ; LCL = -1.023 for n = 3, UCL = 1.023, and CL = 0.0.

R chart; LCL = 0, UCL = 2.575 for n = 3, and CL = 1.00.

The control charts are respectively shown in Fig. 4.21 and 4.22.


- 120 -

Standardized Mean Chart

-1.5

-1

-0.5

0

0.5

1

1.5

1 2 3 4 5 6 7 8

Observation

Mean

LCL

CL

UCL

Figure 4.21: Control chart of standardized mean X

Standardized R Chart

0

0.5

1

1.5

2

2.5

3

1 2 3 4 5 6 7 8

Observation

R

LCL

CL

UCL

Figure 4.22: Control chart of standardized range R


- 121 -

4.5 Process Capability Ratio and Process Capability Index

Process capability ratio CP or capability index Cpk allows process engineer and

quality control engineer to determine ability of the machine/equipment

performing certain process. Using the example for the case of wire bonding, if

the specification of bond strength is 50g±5g, which shall mean the lower

specification limit LSL is 45g and upper specification limit USL is 55g. If the

average measurement for the samples taken from a specific wire bonder is 53g,

we would like to say this wire bond has poor capability index Cpk. Likewise, the

average measurement for the second wire bonder is 50.3g, we say this wire

bonder has better process capability index Cpk then the previous wire bonder.

Let’s go through the process of establishing process capability ratio Cp, process

capability index Cpk, and Taguchi process capability index Cpm for the

machine/equipment.

4.5.1 Process Capability Ratio Cp

Process capability is simply the range that contains all possible values of a

specified quality characteristics generated by a process under a given set of

conditions. For a normal distribution with α = 0.0026, the range shall contain

99.74% of the values, which is equal to six standard deviation (). Thus, the

process capability is

Process capability = 6 (4.31)

The recent trend for the process capability is looking at eight standard

deviations, which is 99.9937% or 12 standard deviations, which is

99.9999998% of the values covering in the range.

Process capability ratio Cp compares the specification limits of the

characteristics of the device with the process capability. Thus, process

capability ratio Cp is defined as

Cp =

6

LSLUSL (4.32)

where LSL is the lower specification limit and USL is the upper specification

limit. For the VLSI device process, it normally demands the process capability

ratio of more than 2, which means Cp ≥ 2.


- 122 -

The portion of out of specification device produced is P[X < LSL] + P[X >

USL], which either equal to 2xP[X < LSL] or 2xP[X > USL]. If the mean of

the device produced is = (USL+LSL)/2, then the probability of defective

device is

LSLzP2 =

2/)LSLUSL(LSLzP2 or

USLzP2 =

2/)LSLUSL(USLzP2 , where z = (X-)/ that has standard normal

distribution with mean equals to 0 and standard deviation equals to 1. After

substituting from equation (4.32), the portion of defective device is equal to

pC3zP2 or pC3zP2 (4.33)

For the case whereby there only one specification limit, which is either LSL or

USL, the process capability ratio are respectively equal to

Cp =

3

)LSL( for the larger the better characteristic (4.34)

Cp =

3

)USL( for the smaller the better characteristic (4.35)

The portion of out of specification device produced is P[X < LSL] or P[X >

USL], which are also equal to

LSLzP or

USLzP . After

substituting equation (4.34) and (4.35), the out of specification device

portions are respectively equal to

pC3zP larger the better characteristic (4.36)

pC3zP smaller the better characteristic (4.37)

For the process case whereby the process mean is not equal to = (USL-

LSL)/2, which shall mean that can either closed to LSL or USL, the portion of

the defective device produced is equal to

LSLzP +

USLzP (4.38)

Let’s take an example to illustrate how equation (4.38) works. In test operation,

three testers are used to measure the leakage current for a batch of devices. The


- 123 -

specification of the leakage test is ±30.0nA. The means obtained from three

testers are 20nA, 10nA, -15nA, while the standard deviations obtained from

three testers are 5.0nA, 6.0nA and 4.0nA respectively. Find the portion of

defective devices produced by the three testers. With known z-score, use the

standard normal cumulate probability table to obtain the cumulative probability

of reject.

The LSL is -30nA, while the USL is 30nA. The portion of defective device

produced by tester 1 is

LSLzP +

USLzP =

5

2030zP +

5

2030zP = P[z < -10]

+ P[z > 2] = 1- 0.9772 = 0.0228.

The portion of defective device produced by tester 2 is

LSLzP +

USLzP =

6

1030zP +

6

1030zP

= P[z<-6.67]+P[z>3.33] = 1- 0.9995 = 0.0005.

The portion of defective device produced by tester 3 is

LSLzP +

USLzP =

4

1530zP +

4

1530zP

= P[z<-3.75]+P[z>11.25] = 1- 0.9999 = 0.00001.

Based on the example shown above, one can see that tester 3 is the most capable

tester. One can also see that the deviation of the mean from the nominal value

(in this case is 0nA) has greatly affect the portion of the defective device

produced by the testers. This effect is not capture by the process capability ratio

(Cp) because this ratio always assumes that the mean of the process is always

equal to (USL+LSL)/2. We shall discuss a different way that is to calculate the

process capability index Cpk to identify the effect.

4.5.2 Process Capability Index Cpk

Process capability index Cpk is introduced to resolve the limitation of process

capability ratio Cp. From the example shown above, the mean of tester 1 is

closer to the LSL, which means (USL - ) < ( - LSL). The mean of tester 2 is

closer to USL, which means (USL - ) < ( - LSL). The mean of tester 3 is

closer to LSL, which means ( - LSL) < (USL - ). Thus, there are two testers

have their means closed to LSL. The question is between the two testers, which

one has a better capability index?


- 124 -

Based on the above example, this shall mean that the process capability

ratio Cp shall be taken from the value closer to either the LSL or USL divided

by a divisor, which should be 3 instead of 6 because it does not cover the

entire range of the specifications. Thus, the process capability index Cpk is

defined in equation (4.39) the device characteristics that have both LSL and

USL limits.

3

USL,

3

LSLMinCpk (4.39)

The process capability index Cpk for VLSI device process demands the index

value of at least 1.5. i.e. Cpk ≥ 1.5.

For the device characteristic that has either LSL or USL, the process

capability index Cpk is defined as

Cpk =

3

)LSL( for the larger the better characteristic (4.40)

Cpk =

3

)USL( for the smaller the better characteristic (4.41)

Let’s use the earlier example to calculate the process capability indices of the

three tester s. The Cpk of tester 1 is

3

USL,

3

LSLMinCpk =

3

USL=

5x3

2030= 0.6666. The Cpk of tester 2 is

3

USL,

3

LSLMinCpk =

3

USL=

6x3

1030 = 1.1111. The Cpk of tester 3

is

3

USL,

3

LSLMinCpk =

3

LSL=

4x3

1030= 1.6666. Based on the

results, one can clearly see that tester 3 has a better process capability index

then two other two testers and tester 1 has the least process capability index.

These results concur with portion of defective device produced by the testers

using Cp method.

The portion of out of specification device produced is P[X < LSL] + P[X >

USL] =

USLzP

LSLzP . If the mean is closed to LSL then

USLzP

LSLzP and Cpk =

3

)LSL(, this shall mean that


- 125 -

portion of the defective device can be approximately as 2 times

LSLzP i.e.

LSLzP2 . Replacing the mean µ using equation

(10.41), the portion of the defective device is equal to

LSLzP2 = pkC3zP2 (4.42)

Similarly, if the mean is closed to USL, then

USLzP

LSLzP

and Cpk =

3

)USL(. This shall mean that portion of the defective device can be

approximately as 2 times

LSLzP i.e.

LSLzP2 . Replacing the

mean µ using equation (10.42), the portion of the defective device is equal to

USLzP2 = pkC3zP2 (4.43)

The main limitation of the Cpk index is due to the normality assumption of the

characteristics. Also, for the nominal-the-better type of characteristics, the Cpk

index yields only an upper bound for the total proportion of defectives.

4.5.3 Taguchi Process Capability Index Cpm

Taguchi process capability index Cpm takes into the consideration of loss due to

variation from the targeted value by replacing the standard deviation of the

process capability index Cp with the Taguchi’s loss function 20

2 X ,

where X0 is the targeted value. It is useful to identify processes that have same

Cpk. The Cpm index is calculated using equation (4.44).

Cpm =

20

2 X6

LSLUSL

(4.44)

Let’s use the example shown in Fig. 4.23 as the illustration. The targeted value

of the process is 1.00. The two processes have same Cpk values but different Cpm

indices theoretically saying that process B has a better process capability. In

practice, it may not be true since the variance of process B is higher means

expected more dissatisfaction from end user. The Cp values of process A and B

are respectively equal to 1.389 and 0.833, while the Cpk values are both equal to


- 126 -

0.833. Although process A has lower standard deviation, its mean is further

away from target value. This resulted same Cpk value like the process B

whereby it has wider spread with mean closes to target value.

Figure 4.23: Processes with same Cpk but different Cpm indices

The calculated Cpm for the processes are 0.712 for process A and 0.833 for

process B.

4.5.4 Ppk Index

Wrong estimation of mean and standard deviation was shown as one source of

error in measuring the process capability. Let’s take an example. 50

observations collected over a period of 60 minutes. These observations were

collected in 10 sample batches of size 5 each. The time interval between

successive batches was 10 minutes. The following estimates of the process

standard deviation were obtained.

1. Average value of standard deviations of the 10 sample batches is

0.000738.

2. Standard deviation of the entire 50 observations taken as one sample

batch is 0.001329.

It was pointed out that the estimate given by 0.000738 contains the variation

within each sample batch of size 10 (short-term variability) only, whereas the

estimate of 0.001329 contains the variation within the batches as well as the

long-term variation in the process over a period of 60 minutes. Assuming that

the process was not stopped and adjusted during the interval of 60 i.e. the


- 127 -

process control technique used to monitor the process allowed the observed

deviation in the mean. The true estimate of the total variability in the

characteristic is 0.001329. Usually the estimate of the variation within each

batch size of 10 is used in calculating of Cp and Cpk indices. As this estimate is

smaller than the estimate of the total variation including the long-term

variability, these indices over estimate the process capability and hence under

estimate the proportion of defectives. In order to address this problem, the Ppk

index was introduced.

The Ppk index is calculated using the same formulae for calculating the Cpk

index. For nominal-the-better type of formula is

3

USL,

3

LSLMinPpk (4.45)

For the device characteristic that has either LSL or USL, the process capability

index Cpk is defined as

Ppk =

3

)LSL( larger the better characteristic (4.46)

Ppk =

3

)USL( smaller the better characteristic (4.47)

The above formulae shown the standard deviation is estimated by long-term

standard deviation. The proportion of defectives is estimated in the same

manner like Cpk index, which is

LSLzP2 =

USLzP2

= pkP3zP2 = pkP3zP2 (4.48)

For nominal-the-best type of characteristics and

pkP3zP2 or pkP3zP2 (4.49)

For smaller the better and larger the better types characteristics. As in the case

of the Cpk index, the distribution of the characteristic must be normal in order

for equation (4.48) and (4.49) to be valid.


- 128 -

Let’s take an example to calculate the Ppk index for the data that has USL

0.995, USL 1.005, batch average standard deviation 0.000738, long-term

standard deviation 0.001329, batch average mean 1.001, long-term batch mean

1.0005, and estimate the proportion of defectives using the Ppk index.

The Ppk index is calculated using equation

3

USL,

3

LSLMinPpk

001329.0x3

0005.1005.1,

001329.0x3

995.00005.1Min

128.1 ,379.1Min = 1.128.

The Cpk index is calculated using equation

3

USL,

3

LSLMinCpk

000738.0x3

001.1005.1,

000738.0x3

995.0001.1Min .8061 ,71.2Min

= 1.806.

The portion of reject using Ppk is pkP3zP2 = 128.1x3zP2 = 2x[1-0.9996]

= 0.0008 = 800ppm.

The portion of reject using Cpk is pkC3zP2 = 86.1x3zP2 = 2x1.21x10-8

=

2.42x10-8

= 0.0008 = 0.0242ppm.

From the results, one can see that Ppk gives a more realistic result than Cpk.

The limitations of the Ppk index are the same as those of the Cpk index

discussed earlier. In short, these are the normality assumption required for the

expressions to be valid, the upper bound on the proportion of defectives, and the

masking of the deviation of the mean from the target value by the standard

deviation.

Exercises

4.1. What is the purpose of in-process quality control monitoring?

4.2. Name one rule to check if the SPC chart is normal.

4.3. The data in the table are obtained from an operation in fabrication. Derive

the values of SPC control lines for xi and R charts.


- 129 -

Observation Observation xi Moving Range

R

1 10.42 -

2 10.59 0.17

3 10.39 0.20

4 9.91 0.48

5 10.21 0.30

6 10.02 0.19

Mean x = 10.256 R = 0.268

4.4. Plot a SPC X chart and R chart of the control lines established in question

4.3.

4.5. The data in the table shown below are the current drain of eight integrated

circuits measured by a piece of equipment in test operation. The

specification limit of current drain is 10mA. Calculate the process

capability index of this equipment and defective part per million

produced by this equipment.

Observation Observation xi

1 9.0

2 9.2

3 9.9

4 9.0

5 9.5

6 9.8

7 8.9

8 9.8

Mean x = 9.39

Standard Deviation s = 0.41


- 130 -

Bibliography

1. S.M. Sze, “VLSI Technology”, McGraw Hill, 2002.

2. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic “Digital

Integrated Circuit – A Design Perspective”, 2nd

edition, Prentice Hall.

2003.

3. C.Y. Chang and S.M. Sze, “ULSI Technology”, McGraw Hill, 1996.

4. N. H. Weste and D. Harris, “CMOS VLSI Design: A Circuits and Systems

Perspective”, third edition, Pearson Addison Wesley, 2005.

5. M. Michael Vai, “VLSI Design”, CRC Press LLC, 2001.

process and statistical process controlsstaff.utar.edu.my/limsk/process integration and ic...

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