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Process Communication in VHDL Shantanu Dutt UIC

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Page 1: Process Communication in VHDL Shantanu Dutt UIC. Inter-Process Communication in VHDL signal x, z: std_logic; x

Process Communication in VHDL

Shantanu Dutt

UIC

Page 2: Process Communication in VHDL Shantanu Dutt UIC. Inter-Process Communication in VHDL signal x, z: std_logic; x

Inter-Process Communication in VHDL

signal x, z: std_logic;

x <= (a xor b) nand z after 4ns;

wait on z;

wait until x = ‘1y := (a1 xnor b1) xnor(c1 xnor d1);f <= y nand u after 2 ns;

port (start: in std_logic; f: out std_logic);entity xyz is

end entity xyz;

if (n <= m) then z <= ‘0’ after 6 ns;else z <= ‘1’ after 6 ns;end if;

wait until start = `1’ and last_value’start=‘0’;start (control)

z(control +data)

x (control only)

f

Processes

Architecture

Note: wait statements are event driven, i.e., are evaluated only when at least 1 event occurs on one of the signals in the wait statement (for “wait on” and “wait until” statements) OR when a time expiry event happens for the “wait for” statement.

Page 3: Process Communication in VHDL Shantanu Dutt UIC. Inter-Process Communication in VHDL signal x, z: std_logic; x

Microprocessor-Memory CommunicationFirst-cut behavioral description:entity cpu-mem isport(read, write: in std_logic; DR: in word; ARin: in integer; IR: out word);-- DR: data to write, ARin: its address, IR: instruction readend entity cpu-mem;

architecture behav_high of cpu-mem isbeginall_in_one: process (read, write) istype data_type is array (0 to 63) of word;variable store: data_type;variable addr, AR, PC: integer;variable data_reg, instr_reg, data_in, data_out : word;begin if read = ‘1’ then AR := PC; addr := AR; data_out := store(addr/2); instr_reg := data_out; IR <= instr_reg after 1 ns; PC := PC + 2; elsif write = ‘1’ then AR := ARin; addr := AR; data_reg := DR; data_in := data_reg; store(addr/2) := data_in; end if; end process cpu-mem;end architecture behav_high;

• Very high-level description• No description of module communication• Data/address/control-signal propagation delays are thus not obviously visible• Though some of these delays (not all) could be modeled by “wait for ..” statements• E.g., if 1-way commun. time w/ memory is 2 ns, and it takes 1 ns for the mem. controller to access the data store, as well as for the CPU-mem interface to write to a reg. then the delay of 2+1+2 = 5 ns to read an instruction from memory and store in the IR can be modeled as:• data_out := store(addr/2); (the 0 delay model) (a non-zero delay model) wait for 5 ns; data_out := store(addr/2);• A better behavioral description modeling various timing & comm. issues given next

Shantanu Dutt, UIC

Memory

data_in

data_out

data_read

data_write

mem_ready

addressAR

ir

CPU

rea

dw

rite

CPU-Mem

dr

CPU-MemInterface

IRDR

PC

ARinLegend: dr: data_reg ir: instr_regThe red arrows w/ #s show the seq. of operations (or of signals that need to be generated to cause the operations). Relate this seq. to the seq. of opers described in the VHDL code on the left.

1

2 3

4 5

6

1

2 3

4566

+2

6

Page 4: Process Communication in VHDL Shantanu Dutt UIC. Inter-Process Communication in VHDL signal x, z: std_logic; x

Microprocessor-Memory Communication (contd): A more detailed behavioral description

architecture behav_detailed of cpu-mem issignal address: integer; signal data_in, data_out : word;signal data_read, data_write, mem_ready: std_logic := `0’;beginCMI: process is -- CPU-Memory Interface modulevariable AR, PC : integer; variable data_reg, instr_reg: word;begin wait until read = ‘1’ or write = ‘1’; if read = ‘1’ then AR := PC; wait for 1 ns; -- 1 ns reg. acc. time address <= AR after 2 ns; -- 2 ns prop. delay data_read <= `1’ after 2 ns; -- 2ns prop. delay; note simult. w/ addr wait until mem_ready = ‘1’; instr_reg := data_out; wait for 1 ns; IR <= instr_reg after 1 ns; data_read <= `0’ after 2 ns; wait until mem_ready = `0’; PC := PC+2; wait for 1 ns; elsif write = ‘1’ then data_reg := DR; AR := ARin; wait for 1 ns; -- 1 ns reg acc (both happening in parallel) address <= AR after 2 ns; data_in <= data_reg after 2 ns; data_write <= ‘1’ after 2 ns; …………………… end if;end process CMI; Memory: process istype data_type is array (0 to 63) of word;variable store: data_type; variable temp_reg: word;variable addr: integer;beginwait until data_read = `1’ or data_write = `1’; if data_read = ‘1’ then – next:1ns reg. & ram accessaddr :=address; temp_reg := store(addr/2); wait for 2 ns; data_out <= temp_reg after 2 ns;-- RAM r/w time is 1ns; prop. time = 2ns mem_ready <= ‘1’ after 2 ns; wait until data_read = ‘0’; mem_ready <= ‘0’ after 2 ns; elsif data_write = ‘1’ then addr := address; store(addr/2) := data_in; wait for 2 ns; ……………… end if; end process Memory;end architecture behav_detailed;

• Multi-process description describing fully responsive handshaking between the CPU-Mem interface (CMI) and Memory modules• Most Data/address/control-signal propagation delays and storage access times are accounted for: delay parameters used: 1-way commun. time w/ memory = 2 ns, RAM/register r/w time = 1 ns.• Note: A safer form of wait until X = ‘1’ is if X /= ‘1’ then wait until X = ‘1’ when it is not known for sure that X will not be ‘1’ at the point we want to wait for X being ‘1’. Similarly for waiting for X to be ‘0’.

2ns prop. delay

2ns reg + RAM access

delay 2ns prop. delay

2ns prop. delay

1ns reg (PC) access delay

2ns prop. delay for read sig.

data_read

mem_ready

12334’

4

4

3’

5 6

6

6’7

7’8

Shantanu Dutt, UIC

Memory

data_in

data_out

data_read

data_write

mem_ready

addressAR

ir

CPU

rea

dw

rite

CPU-Mem

dr

CPU-MemInterface

IRDR

PC

ARin Legend: dr: data_reg ir: instr_regThe red arrows w/ #s show the seq. of operations (or of corresp. signals). For a # j, j’ denotes the delayed version of the corresp. signal Relate this seq. to the seq. of opers described in the VHDL code on the left.

1

2 3

4 5

6

+2

84 4’

6 6’

3 3’

7 7’

3’

4’

Page 5: Process Communication in VHDL Shantanu Dutt UIC. Inter-Process Communication in VHDL signal x, z: std_logic; x

data_out <= store(address/2);

store(address/2) <= data_in; mem_ready <= ‘1’;

data_out data_in

data_read <= ‘0’;

, data_read : std_logic;

data_out;

Original Code in the Notes for CPU-Mem Communication (w/ typos corrected)


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