processing and defect control in advanced ge technologies · processing and defect control in...

Processing and Defect Control in Advanced Ge Technologies

C. Claeys*

IMEC, Kapeldreef 75, 3001 Leuven, Belgium*Also E.E. Dept, KU Leuven, Kasteelpark Arenberg 10,

3001 Leuven, Belgium

IEEE ED Colloquium/Orlando/Feb. 21, 2008C. Claeys 2

Outline

– Introduction/Motivation

– Ge Fabrication Techniques

– Processing Aspects

Wet cleaning

Surface passivation

Shallow junction formationGermanidation

– Conclusions


Introduction

Interest in defects due to their impact on: physical processes (e.g. diffusion)electrical device performance yield

Interest since the early days of semiconductors, but now there is physical insight

No longer trial and error but ENGINEERING

Origin of defects can be

Grown-in (dislocations, vacancies, interstitials, swirls, COPs……)

Process-induced (dislocations, precipitates, metals, twinning,…)

Scaling is putting stringent requirements on the resolution of the analytical techniques


Introduction

• DownscalingChannel doping levels: UTSOI

High-κ dielectrics

FUSI/Metal gates

carrier mobility control


Scaling Aspects: Mobility Boosting

Use of high-κ dielectrics + metal gate + strained Si

S. Datta et al, IEDM 2003, p. 653

35% increase for strained Si/SiGe

n-MOS

SiON/Control Si


Why are we interested in Ge ?

• Ge has been shown to be a good material to make transistors….

Ge

Si

GaAs (electrons)

… and it has a high (low field) electron and hole mobility


Ge used in first transistor radios

• On October 18, 1954, the U.S. company I.D.E.A. announced Regency TR1.– Used 4 germanium transistors.

• Sony's first radio, TR-55, in 1955– Used 5 germanium transistors.

Regency TR1

Sony TR-55


Early results: pMOS and nMOS on 200mm GeOI

Partnership with

Ge Active area

Spacers0.15 μmGate

oxide

0

100

200

300

400

500

600

700

-2 -1 0 1

L=0.5μm L=0.25μm L=0.18μm

I sour

ce(μ

A/μ

m)

Vgate

[V]

W = 2μm

pMOS

0

20

40

60

80

100

0 1 2 3 4

I sour

ce(μ

A/μ

m)

Vgate

[V]

W = 2μm

0.5μm 0.15μm0.18μm

nMOS

pMOS• Good drive current>500mA/μm for

L=0.18μm

nMOS• Low drive current• Ge/high-k interface quality is

one of the main limiting factors


Experimental Results - Mobility

10

100

1000

0.1 1Effective Vertical Field (MV/cm)

Hol

e M

obili

ty (c

m2 /V

s)

Si/SiO2 universal hole mobility

Ge/Si/SiO2/HfO2/TaN/TiN

L = 10 µm, no VTA, no halo

Best peak mobilityachieved so far ~358 cm2/Vs

Mobility as a function of vertical field for L = 10 µm Ge pMOSFETs

following 350°C 20 min H2 PMA


Yoshiki Kamata Toshiba Corporation (2008)Materials Today, Jan/Feb 2008, vol. 11, no.1-2

Ge brought the microelectronics industry two Nobel prizes. The first transistor was based on Ge, as was the first integrated circuit. So why did we give it up?

Though semiconductor makers quickly switched to Si as the prime semiconducting material, Ge is now on the microelectronics research agenda again, and is being discussed as a possible replacement for Si.

It’s back to the future.


Motivation/Objective

Diffusion limited leakage current for Si diodes: 1 nA/cm2

Ge diodes: 10-4 – 10-7 A/cm2 theoretical limit at 298 K

ni 103 times higher: 103 (generation) or 106 (diffusion) higher current

Leakage current depends on the presence of defects

Impact defects on other parameters: lifetime, low frequency noise, reliability, …

Systematic study of the origin of grown-in and processing-induced defects in Ge

Defect Engineering


Czochralski Crystal Growth

Tilted 35° away [001] pulling axis

2 inch to 300 mm

Ge crystal

Higher Ge material cost ($600/kg) vs Si ($54/kg)


Defects in Ge

Vanhellemont et al., in Defects and Diffusion in Semiconductors – An Annual Retrospective VII, Trans. Tech. Publ. Inc., 230, 149 (2004)

Defect in as-grown Ge (row of dislocations)

* High-res. Ge, H-atm.crystal growth

* 30°, 60° and 90° disl.* Disl. sink for [V]

No V2-H complexesTilted 35° away [001] pulling axis


Crystal Growth Aspects

⇒ 30°, 60° and 90° dislocations: sinks for [V]

Reduction of V2-H complexes and COPs

⇒ Dopant and self-diffusion controlled by [I]

⇒ Reduced Oi content (IR: Ge-856 cm-1 Si- 1107 cm-1)Oxygen precipitation?

⇒ High quality Ge substrates for μE applications

GeOI, epitaxial Ge on Si, Ge condensation, …


Thick GeOI Process


Smart Cut Process for Ge


Defects in GeOI

K.K. Bourdelle, APL, 86 (2005) 181910

{311} defect


(Si)GeOI formation by Ge condensation

• Estimated defect density: < 1. 106 cm-2

Needs further improvement

Epitaxial deposition of SiGe on SOI

Si

BOXSi

SiGe

SOI

Ge

High T° oxidation (wet/dry)

Si

BOX

SiGe

SiO2

Ge is condensed between oxides

Si

BOX10<Ge<30 nm

SiO2

High temperature (>1000°C) oxidation of SiGe layers on SOI

50 nm

Si

SiO2(BOX)

SiGe

SiO2

Oxidation at 1150oC

Ge concentration ~ 40%

50 nm

2

1Scanning direction:

1 to 2

SiO2

SiGe

SiO2

Position (nm)

Cou

nts

100806040200

1500

1000

500

0

2 Ge

• Uniform Ge profile in SiGeCould allow to make ultra-thin (Si)GeOI substrates for fully depleted devices


Substrates – Epi Ge in Si STI

• Epi-Ge in Si STI – Utilizes Si STI module for device isolation.

– Enables monolithic integration of Ge and Si devices

Si substrate Si substrate

GeSiO2Start with Si STISelective etch of SiGrowth of epi GeAnneal & CMP

SiO2

Si substrate

Epi-Ge

SiO2STI

Si substrate

Epi-GeSiO2STI

Proof of Concept• 250 nm epi Ge• 4×108 TD / cm2

Note: TEM is without CMP.


Selective growth of Ge on Si

Selective growth of Geafter formation of STI

could reduce the active area leakage

Pure Ge on Si SiGe buffer layers

• Reduction in dislocations density needed

100 μm

Top view nomarski

• Nomarski indicates uniform deposition and smooth surface

10μm100nm thick 50nm thick

RMS:0.82nmRMS:0.97nm• AFM shows low RMS roughness for 50

and 100nm films


0.0E+00

5.0E+06

1.0E+07

1.5E+07

2.0E+07

2.5E+07

700 750 800 850 900 950Anneal Temperature (°C)

Dis

loca

tion

Den

sity

(cm-2

)

1 min3 min20 min

Substrates – Epi Ge on Si

• 200 mm of epi-Ge on Si used for most IMEC lots.– 2 μm thick, relaxed epi-Ge wafer from ASM

– As-grown: ~1×108 threading dislocations/cm2

– Dislocation density reduced by ~10x with >800°C anneal.


Crystal Growth Aspects

⇒ Same bulk minority lifetime as in Si

Less Auger recombination for high doping

⇒ More prone to metallic contamination

Fe, Ni, Co dominant, less impact Cun-type lower lifetime than p-type

Mid gap acceptors increase the leakage current

⇒ Gettering is difficult in Ge


Metals in Ge

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

1011 1012 1013 1014 1015 1016 1017

Germanium at 300 K

Leak

age

Cur

rent

Den

sity

per

μm

Dep

letio

n(A

./cm

2 )

Metal Concentration (cm-3)

Ni;Fe

CuMn

CoSolubility Ni at 700oC

Leakage current per μm depletion width at 300 K for differenttransition metals in function of their concentration


Ge Processing Issues

• Is Ge manufacturable in a Si processing line ?– Same toolset can be used, but processes have to be modified

• Ge surface and Ge/high-k interface quality– Passivation of interface states – EOT scaling– Cleaning is critical (severe etching during wet processing)

• Dopant activation and re-crystalization– Especially n-type activation– Leakage current of junctions

• Quality and availability of substrates– Defect density of Ge layer ?

• Main question: Ion(Ge transistor) > Ion(sSi transistor)?– Ion/Ioff ratio


Etching of Ge during wet processing

Etch rate calculated from weight loss, all treatments at Room Temperature

• HF does not etch Ge• all other solutions (incl. DI-water): measurable etch rate

Etch solution etch rate (nm/min)

H2O (dissolved oxygen) 0.005-0.00610% HF <0.001BOE <0.0011M HCl 0.010.5%HF/1M HCl 0.0061M NH4OH 0.03SC1(0.001/0.01/5) 17-27SC1(1/1/7) 200-280

Etch solution etch rate (nm/min)

H2O (dissolved oxygen) 0.005-0.00610% HF <0.001BOE <0.0011M HCl 0.010.5%HF/1M HCl 0.0061M NH4OH 0.03SC1(0.001/0.01/5) 17-27SC1(1/1/7) 200-280


Transistor Structure

Relaxed Ge on Si

Isolation

NiGe

TaN/TiN gate

HDD

Extension

n wellp+ p+

Relaxed Ge on Si

Isolation

NiGe

TaN/TiN gate

HDD

Extension

n wellp+ p+


Typical 200 mm Ge pMOS Process Flow

TiN

2 μm epi-Ge

NiGe

TaNExtensionSi/SiO2/HfO2

n well

p+ HDD

Metallization

Halo: P 25°

Dielectric: 4 nm HfO2

Sinter: 350°C 20 min H2

Metallization: TiN / Ti / Al / TiN

NiGe: 10 nm Ni, RTA, Etch, RTA

Anneal: 500°C 5 min

HDD: Ge PAI, B HDD

Spacer: 90 nm width

Extension: BF2

Gate: 10 nm TaN / 100 nm TiN

Passivation: ~6 ML epi-Si / SiO2

Isolation: ~200 nm SiO2, 45°

Wells: P 90, 180, & 570 keV

Start: 2 μm epi Ge on Si

SiO2

SiO2

SiO2

Halos

Si substrate


Ge surface preparation

• HF-dip → 0.3 nm GeOx

• HBr-dip → O-free

• HF-dip + NH3 anneal → 0.6 nm GeOxNy

• Out of the box → 1.68 nm GeOx

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Inte

nsity

(arb

. un.

)

40 38 36 34 32 30 28 26Binding Energy (eV)

Out-of-the-box

GeOxNy

GeOx

O-free

Ge

GeO2XPS:Ge3d region


Surface Passivation

Si

HfO 2

Ge

SiO x layer

S i

HfO 2

Ge

Si

HfO 2

Ge

SiO x layer

CeO2 good passivation : Nit 1x1012 (p) 6x1011(n) eV-1cm-2

S under investigation

Good results with Si


CV curve shows a passivatedsurface and a reduced Nit

Si passivation of Ge surface

• CV curve on Si passivated Ge surface has low NitH2 post treatment further improves C-V curves

- effect is similar to the passivation of silicon with H2

Si

HfO2

Ge

0

5 10-7

1 10-6

1.5 10-6

2 10-6

-2 -1 0 1 2 3

C (F

.cm

-2)

VGate

(V)

after H2 annealHf Hf HfO OO O O OHfO2 Hf Hf HfO OO O O OHfO2

Ge

Ge

Ge

Ge

Ge

Ge

Ge

Ge

Ge

Ge

Ge

GeGe

1 MLSiSi Si Si Si Si Si

Si Si Si Si Si Si1 MLSi

Si Si Si Si Si Si1 MLSi

Si Si Si Si Si Si

Si Si Si Si Si SiSi O Si Si SiSiO O O O

O

O O O O OOthinSiO2

SiO

Si O Si Si SiSiO O O O

O

O O O O OOthinSiO2

SiO

thickness control is essential

• Si layer too thickstress-induced interface defectsC-V curve shows high Dit

• Si layer too thinGe will oxidize and defective layer with poor interface is formed


Shallow Junction Formation

Ge: lower anneal temperatures for activation (400-600°C)

Higher I/I damage in Ge, but anneal at lower temperatures

Sheet resistivity: max solubility, dopant out-diffusionactivation degree

Thermal budget: balance between dopant activation, defect annealing and junction depth

Boron shallow junction can be obtained by Ge pre-amorphizationand RTA

More difficult to control n-type dopants like P, As an Sb

Co-implantation with non-doping impurities like N and C gives promising results for P – less dose loss and lower P in-diffusion


Boron Doping – Sheet Resistivity

Annealing temperature dependence at 60 s

0

20

40

60

80

100

120

300 400 500 600 700

Annealing T (oC)

Rs

(Ohm

/sq)

1e16 at/cm21e15 at/cm2

Sheet resistance versus RTA temperature (60 s), corresponding with a 4.5 keV B 1015 or 1016 at/cm2. A Ge pre-amorphization implantation was done at 120 keV & 1015 at/cm2. A junction depth at a carrier concentration of 1018 cm-3 of ~70 nm


As-implantedDepth of amorphous layer: 100 nm

Annealed at 400C, 60s, N2

• Fully re-grown• No visible residual defects at the EOR

Re-crystallization of pre-amorphized, B-doped Ge

2


Sb Doping – Void Formation

SEM image (x150 000) of a 10 nm SiO2/Ge sample implanted with 1015 at/cm2 Sbat 70 keV, showing voids extending up to 100 nm below the surface


P (as-)implanted and re-grown Ge: microstructure

After re-growth at 400C, 60 s, N2

• P-doped Ge fully re-grows at 400C (60 s) • No evidence of P clusters or residual damage after re-growth at low T• Inactive P may be in small P-V clusters or interstitials

60 nm

as-implanted P 25 keV 3e15 at/cm2


Control P doping in Ge - Precipitation

0100200300400500600700800

1E+13 1E+14 1E+15 1E+16Dose (at/cm2)

Rs

(Ohm

/sq)

P, 500C-60sP, 500C-1sP, 600C-1s

Above SS implant

15 keV P in Ge; no SiO2 cap

15 keV 5x1015 cm-2 P, 60 s at 500°C


Impact NiGe on ID

10-12

10-10

10-8

10-6

10-4

10-2

-1-0.8-0.6-0.4-0.20

Impact of NiGe

NiGe junction

No NiGe junction

Forw

ard

curr

ent (

A)

Forward voltage (V)


Impact NiGe on IR

10-10

10-9

10-8

10-7

10-6

10-5

10-4

00.20.40.60.81

Impact of NiGe

NiGe junction

No NiGe junction

Rev

erse

cur

rent

(A)

Reverse voltage (V)

10-12

10-11

10-10

10-9

10-8

10-7

10-6

00.20.40.60.81

Impact of NiGe

No NiGe junction

NiGe junction

Rev

erse

cur

rent

(A)

Reverse voltage (V)

10-10

10-9

10-8

10-7

10-6

10-5

10-4

00.20.40.60.81

Impact of NiGe

NiGe junction

No NiGe junction

Rev

erse

cur

rent

(A)

Reverse voltage (V)


Junction Diode: Theoretical Analysis

Geometrical componentsbulk – surface – corner

IR = AJA + PJP +NCJC + Ipar

3 diodes structures with different P/A ratios should be measured

Physical componentsdiffusion - generation

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

Dp

p

An

nidA NL

DNL

DqnJ 2

geff

AigA

WqnJτ

=

n+

pWA

+-

e

h


Junction Diode: Graphical Technique

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

I/A= JA+ P/A * JP

y = 0.17422 + 1.2777x R= 0.98903

I/A (

A/ m

2 )P/A (1/um)

For a Fixed VFor a Fixed VRR

PA JAPJ

AI

+=

Intercept!! Slope!!

PApar

CC

PAR J

APJ

AI

JA

NJAPJ

AI

+≈+++=

If there isn’t corner generation component


Impact NiGe and PMA

S. Sonde, E. Simoen, C. Claeys, A. Satta, B. De Jaeger, G. Nicholas and M. Meuris, in Avanced Gate Stack, Source/Drain and Channel Engineering for Si-Based CMOS 3: New Materials, Processes and Equipment, Electrochem. Soc. Trans., vol. 6, no. 1, 2007, pp. 31-39

10-3

10-2

350 400 450 500 550 600

Area component: Algebraic method

NiGe junction/ 0.5V

No NiGe junction/ 0.5V

Ja (A

/cm

2 )

PMA temperature (oC)

10-7

10-6

10-5

350 400 450 500 550 600

Perimeter component: Algebraic method

NiGe junction/ 0.5V

No NiGe junction/ 0.5V

Jp (A

/cm

)

PMA temperature (oC)


Experimental : Impact NiGe

void

Nickel

NiGe on Ge

SiO2 isolation

Small defects

270°C / Selective Etch / 330°C

1 μm

Germanide overgrowthon SiO2 isolation

NiGe on Ge

Massive voiding

330°C / Selective Etch

1 μm

D. Brunco et al.


Impact NiGe on LF noise in p+n Ge junctions

Low-frequency noise spectra for a germanided and a non-germanidedp+-n junction at a forward bias of 0.5 V. The area is 15000 mm2 and the perimeter P=10300 mm.

10-23

10-22

10-21

10-20

10-19

10-18

10-17

100 101 102 103 104 105

Noi

se S

pect

ral D

ensi

ty (A

2 /Hz)

Frequency (Hz)

no NiGe

NiGeV

F=0.5 V

A: 15000 μm2

P: 10300 μm

R.M. Todi, S. Sonde, E. Simoen, C. Claeys and K.B. Sundaram, Appl. Phys. Lett., vol. 90, no. 4, pp. 043501-1/3, 2007.


Germanidation: Impact on LF Noise

SI at 1 Hz and 100 mA for NiGe germanided and non-germanided p+-n junctions versus area.

10-18

10-17

103 104 105 106

Noi

se S

pect

ral D

ensi

ty (A

2 /Hz)

Junction Area (μm2)

~A0.39

NiGe

no NiGe

f=1 HzIF=100 μA

R.M. Todi, S. Sonde, E. Simoen, C. Claeys and K.B. Sundaram, Appl. Phys. Lett., vol. 90, no. 4, pp. 043501-1/3, 2007

SI is proportional with A0.39

Defect-assisted GR noise origin


Germanidation : Ni

DLT-spectra at tw=51.2 ms, tp=1 ms and a pulse from -4 to -1 V for a 4 mm diameter NiGe Schottky barrier on n-type Ge and corresponding with different RTA temperatures: 300, 350, 400 and 450oC

0 100

2 10-3

4 10-3

6 10-3

50 100 150 200 250

n-type Ge - Ni: 10 nm

DLT

S (p

F)

Temperature (K)

-4-->-1 Vtw=51.2 mstp=1 ms

300oC350oC

450oC

400oC

Low temperatures used

Phase = f(T)

300-350ºC: no deep electron traps

400-450ºC: double acceptor at Ec-03 eV – substitutional Ni

Low defect concentration


Germanidation : Pd and Pt

DLT-spectra corresponding with a Ni-, Pt- and Pd-germanided n-type Ge Schottky barrierfor an anneal temperature of 400oC. A bias pulse from -4 -1 V was applied for 1 ms, witha repetition time constant tw=51.2 ms. The Ge: Ni and Ge: Pd spectra are offset in they direction for reasons of clarity

30 nm metal deposited by Arsputtering

400ºC: V-related traps

Sputter damage

Low defect concentration

-1 10-2

-5 10-3

0 100

5 10-3

1 10-2

50 100 150 200 250 300

Tanneal

= 400oC

DLT

S (p

F)

Temperature (K)

Ge: Ni

Nis-/2-

Ge: Pt

Ge: PdSb-V ?

-4-->0 V


Germanidation : Pd and Pt

I-T curves for the Pt-germanided n-type Ge Schottky barriers and for the pure Pt Schottkybarrier indicated by as-deposited

300ºC –Pt2Ge400ºC: PtGe450ºC: PtGe2

200ºC: Sputter damage reduces

10-12

10-10

10-8

10-6

10-4

0 50 100 150 200 250 300

30 nm Pt on n-Ge

Rev

erse

Cur

rent

(A)

Temperature (K)

VR=-4 V

as-deposited

Tanneal

=300 oC400 oC

500 oC

E. Simoen, K. Opsomer, C. Claeys, K. Maex, C. Detavernier, R.L. Van Meirhaegheand P. Clauws, J. Electrochem. Soc. Vol. 154, no. 10, 2007, pp. H857-H861


Conclusions

Good performing p-channel transistors have been fabricated

mobility up to 350 cm2/Vs for L =0.12 μm

NiGe reduces the series resistance but increases the perimeter leakage current and lowers the LF noise

voids in the silicon substrate

PMA reduces the leakage current Optimum 450-500°C

Good understanding Ge processing


Ge pMOS vs. ITRS roadmap

• Ion and Ioff vs. gate length for (unstrained) Ge pMOSITRS specifications for Si pMOS are used

Ion: High Performance ITRS spec seems obtainable with Ge pMOS

Ioff: High Performance ITRS spec seems obtainable with GeOItechnology

On-state currents Off-state currents

10-710-610-510-410-310-210-1100101

0.01 0.1 1

Ge, ISOURCE

Ge, IDRAINO

ff-c

urre

nt (μ

A/μ

m)

Gate length (μm)

ITRS HP Spec

VDD

=1V

101

102

103

104

0.01 0.1 1

Ge, VDD

=1VGe, V

DD=0.6V

On-

curr

ent (μA

/μm

)

Gate length (μm)

ITRS HP Spec

Ge pMOS could fulfill ITRS specs, for GeOI substrates

G. Eneman et al.


What about Ge nMOS?

• Low mobility/drive current measured for n-type MOSFETs (also in literature) – Si IL cannot passivate Ge nMOS. Accurate Dit analysis only at 80K [1]

– Other potential problem: poor dopant activation for n-type dopants(activation limit for P ~ 6 × 1019 cm-3)

0

50

100

150

200

250

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Mob

ility

(cm

2 /Vs)

Vg (V)

pMOS

nMOS

[1] K. Martens et al., EDL 27(5), 405 (2006)

0

1 1013

2 1013

3 1013

4 1013

0 0.2 0.4 0.6 0.8In

terf

ace

stat

e de

nsity

(1/c

m2 /e

V)

Valence band offset (eV)

80Kn-type capacitor

Val

ence

ban

d ed

ge

Con

duct

. ban

d ed

ge

Ge nMOS and pMOS mobility Interface state density

Consider other options for nMOS. nFET with GaAs?


Ge and III/V transistors

CMOS: Work towards combination of Si, Ge and GaAs or other III/V materials on one substrate

Si CMOS

Si wafer

strained Ge pMOS

Strained Ge selectively grown on Si or GeOI substrate

GaAs or other III/V nMOS

GaAs or other III/V selectively grown on Ge


Acknowledgements

The author wish to acknowledge D. Brunco,P. Clauws, B. De Jaeger, G. Eneman, W. Guo, M. Meuris, G. Nicholas, K. Opsomer, R. Todi, A. Satta, E. Simoen, S. Sonde, J. Vanhellemont for useful discussions and the use of co-authored results.

Explore team at IMEC

IMEC Core Partners:


Conclusions

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