professional extended-10 video encoder with 54 mhz ...20-bit format and 3× 10-bit ycrcb progressive...

REV. A

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

aADV7194

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 World Wide Web Site: http://www.analog.comFax: 781/326-8703 © Analog Devices, Inc., 2001

Professional Extended-10 ™Video Encoder with 54 MHz Oversampling

SIMPLIFIED BLOCK DIAGRAM

I2C INTERFACE

CHROMALPF

10-BITDAC

10-BITDAC

10-BITDAC

10-BITDAC

10-BITDAC

10-BITDAC

2�OVERSAMPLING

4�OVERSAMPLING

OR

ADV7194

SSAFLPF

LUMALPF

COMPOSITE VIDEOY [S-VIDEO]C [S-VIDEO]RGBYUVYPrPb

TV SCREENORPROGRESSIVESCAN DISPLAY

COLOR CONTROLDNRGAMMACORRECTION

VBITELETEXTCLOSED CAPTIONCGMS/WSS

DEMUX

AND

YCrCb-TO-YUV

MATRIX

PLLAND

54MHz

VIDEOINPUTPROCESSING

VIDEOOUTPUTPROCESSING

VIDEOSIGNALPROCESSING

ANALOGOUTPUT

27MHzCLOCK

ITU–R.BT656/601

10-BIT YCrCbIN 4:2:2 FORMAT

DIGITALINPUT

Extended-10 is a trademark of Analog Devices, Inc. This technology combines 10-bit conversion, 10-bit digital video data processing, and 10-bit external interfacing.SSAF is a trademark of Analog Devices Inc.ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).I2C is a registered trademark of Philips Corporation.

FEATURES10-Bit Extended CCIR-656 Input Data PortSix High-Quality 10-Bit Video DACs10-Bit Internal Digital Video ProcessingMultistandard Video InputMultistandard Video Output4� Oversampling with Internal 54 MHz PLLProgrammable Video Control Includes:

Digital Noise ReductionGamma CorrectionBlack BurstLUMA DelayCHROMA DelayMultiple Luma and Chroma FiltersLuma SSAF™ (Super Sub-Alias Filter)Average Brightness DetectionField Counter

CGMS (Copy Generation Management System)WSS (Wide Screen Signaling)Closed Captioning SupportTeletext Insertion Port (PAL-WST)2-Wire Serial MPU Interface (I2C Compatible and

Fast I2C)Supply Voltage 5 V and 3.3 V Operation80-Lead LQFP Package

GENERAL DESCRIPTIONThe ADV7194 is part of the new generation of video encodersfrom Analog Devices. The device builds on the performance ofprevious video encoders and provides new features like inter-facing progressive scan devices, digital noise reduction, gammacorrection, 4× oversampling and 54 MHz operation, averagebrightness detection, black burst signal generation, chroma delay,an additional Chroma Filter, etc.

The ADV7194 supports NTSC-M, NTSC-N (Japan), PAL N,PAL-B/D/G/H/I and PAL-60 standards. Input standards sup-ported include ITU-R.BT656 4:2:2 YCrCb in 8-, 10-, 16- or20-bit format and 3× 10-bit YCrCb progressive scan format.The ADV7194 can output composite video (CVBS), S-Video(Y/C), Component YUV or RGB and analog progressive scan inYPrPb format. The analog component output is also compatiblewith Betacam, MII and SMPTE/EBU N10 levels, SMPTE 170MNTSC and ITU-R.BT 470 PAL.

For more information about the ADV7194’s features refer toDetailed Description of Features section.

APPLICATIONSProfessional DVD Playback SystemsPC Video/Multimedia Playback SystemsProgressive Scan Playback SystemsProfessional Studio Equipment

ADV7194

–2– REV. A

CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 1SPECIFICATIONS

5 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.3 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 V Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . . 53.3 V Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . 55 V Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63.3 V Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 13FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BLACK BURST OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . 17BRIGHTNESS DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . 17CHROMA/LUMA DELAY . . . . . . . . . . . . . . . . . . . . . . . . 17CLAMP OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17CSO, HSO, AND VSO OUTPUTS . . . . . . . . . . . . . . . . . . 17COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 17COLOR BURST SIGNAL CONTROL . . . . . . . . . . . . . . . 17COLOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17CHROMINANCE CONTROL . . . . . . . . . . . . . . . . . . . . . 17UNDERSHOOT LIMITER . . . . . . . . . . . . . . . . . . . . . . . . 18DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . . . . . 18DOUBLE BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 18GAMMA CORRECTION CONTROL . . . . . . . . . . . . . . . 18NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 18POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18PROGRESSIVE SCAN INPUT . . . . . . . . . . . . . . . . . . . . . 18REAL-TIME CONTROL, SUBCARRIER RESET, AND

TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19SCH PHASE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 19VERTICAL BLANKING DATA INSERTION

AND BLANK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 19YUV LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020-/16-BIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 204× OVERSAMPLING AND INTERNAL PLL . . . . . . . . . 20VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 20RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 28

REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 29MODE REGISTERS 0–9 . . . . . . . . . . . . . . . . . . . . . . . 30–35TIMING REGISTERS 0–1 . . . . . . . . . . . . . . . . . . . . . . . . 36SUBCARRIER FREQUENCY AND

PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 37CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 37NTSC PEDESTAL/PAL TELETEXT CONTROL

REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37TELETEXT REQUEST CONTROL REGISTER . . . . . . 38CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 38CONTRAST CONTROL REGISTERS . . . . . . . . . . . . . . . 39COLOR CONTROL REGISTERS . . . . . . . . . . . . . . . . . . 39HUE ADJUST CONTROL REGISTER (HCR) . . . . . . . . 40HCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40BRIGHTNESS CONTROL REGISTER (BCR) . . . . . . . . 40BCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40SHARPNESS RESPONSE REGISTER (PR) . . . . . . . . . . . 41PR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 41DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41DNR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 41GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 43BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 44OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 44OCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 44APPENDIX 1

Board Design and Layout Considerations . . . . . . . . . . . . 45APPENDIX 2

Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47APPENDIX 3

Copy Generation Management System (CGMS) . . . . . . . 48APPENDIX 4

Wide Screen Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 49APPENDIX 5

Teletext Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50APPENDIX 6

Optional Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 51APPENDIX 7

DAC Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52APPENDIX 8

Recommended Register Values . . . . . . . . . . . . . . . . . . . . 53Power-On Reset Register Values . . . . . . . . . . . . . . . . . . . 55

APPENDIX 9NTSC Waveforms (With Pedestal) . . . . . . . . . . . . . . . . . 56NTSC Waveforms (Without Pedestal) . . . . . . . . . . . . . . . 57PAL Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58UV Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Video Measurement Plots . . . . . . . . . . . . . . . . . . . . . . . . 64

APPENDIX 10Vector Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69

–3–REV. A

ADV7194

5 V SPECIFICATIONS1Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCEResolution (Each DAC) 10 BitsAccuracy (Each DAC)Integral Nonlinearity3 ±1.0 LSBDifferential Nonlinearity3 ±1.0 LSB Guaranteed Monotonic

DIGITAL INPUTSInput High Voltage, VINH 2 VInput Low Voltage, VINL 0.8 VInput Current, IIN 0 ±1 µA VIN = 0.4 V or 2.4 VInput Capacitance, CIN 6 10 pFInput Leakage Current4 1 µAInput Leakage Current5 200 µA

DIGITAL OUTPUTSOutput High Voltage, VOH 2.4 V ISOURCE = 400 µAOutput Low Voltage, VOL 0.8 0.4 V ISINK = 3.2 mAThree-State Leakage Current6 10 µAThree-State Leakage Current7 200 µAThree-State Output Capacitance 6 10 pF

ANALOG OUTPUTSOutput Current (Max) 4.125 4.33 4.625 mA RL = 300 ΩOutput Current (Min) 2.16 mA RL = 600 Ω, RSET1,2 = 2400 ΩDAC-to-DAC Matching3 0.4 2.5 %Output Compliance, VOC 0 1.4 VOutput Impedance, ROUT 100 kΩOutput Capacitance, COUT 6 pF IOUT = 0 mA

VOLTAGE REFERENCE8

Reference Range, VREF 1.112 1.235 1.359 V

POWER REQUIREMENTSVAA 4.75 5.0 5.25 VNormal Power Mode

IDAC9 29 35 mAICCT (2× Oversampling)10, 11 80 120 mAICCT (4× Oversampling)10, 11 120 170 mAIPLL 6 10 mA

Sleep ModeIDAC 0.01 µAICCT 85 µA

NOTES1All measurements are made in 4× Oversampling Mode unless otherwise specified.2Temperature range TMIN to TMAX: 0°C to 70°C.3Guaranteed by characterization.4For all inputs but PAL_NTSC and ALSB.5For PAL_NTSC and ALSB inputs.6For all outputs but VSO/TTX/CLAMP.7For VSO/TTX/CLAMP outputs.8Measurement made in 2× Oversampling Mode.9IDAC is the total current required to supply all DACs including the VREF circuitry.

10All six DACs on.11ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL.

Specifications subject to change without notice.

(VAA = 5 V, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All specifications TMIN to TMAX2 unlessotherwise noted.)

SPECIFICATIONS

–4– REV. A

ADV7194–SPECIFICATIONS3.3 V SPECIFICATIONS1Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCEResolution (Each DAC) 10 BitsAccuracy (Each DAC)Integral Nonlinearity ±1.0 LSBDifferential Nonlinearity ±1.0 LSB Guaranteed Monotonic

DIGITAL INPUTSInput High Voltage, VINH 2 VInput Low Voltage, VINL 0.8 VInput Current, IIN ±1 µA VIN = 0.4 V or 2.4 VInput Capacitance, CIN 6 10 pFInput Leakage Current3 1 µAInput Leakage Current4 200 µA

DIGITAL OUTPUTSOutput High Voltage, VOH 2.4 V ISOURCE = 400 µAOutput Low Voltage, VOL 0.4 V ISINK = 3.2 mAThree-State Leakage Current5 10 µAThree-State Leakage Current6 200 µAThree-State Output Capacitance 6 10 pF

ANALOG OUTPUTSOutput Current (Max) 4.125 4.33 4.625 mA RL = 300 ΩOutput Current (Min) 2.16 mA RL = 600 Ω, RSET1,2 = 2400 ΩDAC-to-DAC Matching 0.4 2.5 %Output Compliance, VOC 1.4 VOutput Impedance, ROUT 100 kΩOutput Capacitance, COUT 6 pF IOUT = 0 mA

VOLTAGE REFERENCEReference Range7 1.235 V

POWER REQUIREMENTSVAA 3.15 3.3 3.6 VNormal Power Mode

IDAC8 29 mAICCT (2× Oversampling)9, 10 42 54 mAICCT (4× Oversampling)9, 10 68 86 mAIPLL 6 mA

Sleep ModeIDAC 0.01 µAICCT 85 µA

NOTES1All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. For 2 × Oversampling Mode, the powerrequirements for the ADV7194 are typically 3.0 V.

2Temperature range TMIN to TMAX: 0°C to 70°C.3For all inputs but PAL_NTSC and ALSB.4For PAL_NTSC and ALSB inputs.5For all outputs but VSO/TTX/CLAMP.6For VSO/TTX/CLAMP outputs.7Measurement made in 2× Oversampling Mode.8IDAC is the total current required to supply all DACs including the VREF circuitry.9All six DACs on.

10ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL.


(VAA = 3.0 V, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All specifications TMIN to TMAX2

unless otherwise noted.)

–5–REV. A

ADV7194

5 V DYNAMIC SPECIFICATIONS1

Parameter Min Typ Max Unit Test Conditions

Hue Accuracy 0.5 DegreesColor Saturation Accuracy 0.7 %Chroma Nonlinear Gain 0.7 0.9 ±% Referenced to 40 IREChroma Nonlinear Phase 0.5 ±DegreesChroma/Luma Intermod 0.1 ±%Chroma/Luma Gain Ineq 1.7 ±%Chroma/Luma Delay Ineq 2.2 nsLuminance Nonlinearity 0.6 0.7 ±%Chroma AM Noise 82 dBChroma PM Noise 72 dBDifferential Gain3 0.1 (0.4) 0.3 (0.5) %Differential Phase3 0.4 (0.15) 0.5 (0.3) DegreesSNR (Pedestal)3 78.5 (78) dB rms RMS

78 (78) dB p-p Peak PeriodicSNR (Ramp)3 61.7 (61.7) dB rms RMS

62 (63) dB p-p Peak Periodic

NOTES1All measurements are made in 4× Oversampling Mode unless otherwise specified.2Temperature range TMIN to TMAX: 0°C to 70°C.3Values in parentheses apply to 2× Oversampling Mode.Specifications subject to change without notice.

3.3 V DYNAMIC SPECIFICATIONS1

Parameter Min Typ Max Unit Test Conditions

Hue Accuracy 0.5 DegreesColor Saturation Accuracy 0.8 %Luminance Nonlinearity 0.6 ±%Chroma AM Noise 83 dBChroma PM Noise 71 dBChroma Nonlinear Gain 0.7 ±% Referenced to 40 IREChroma Nonlinear Phase 0.5 ±DegreesChroma/Luma Intermod 0.1 ±%Differential Gain3 0.2 (0.5) %Differential Phase3 0.5 (0.2) DegreesSNR (Pedestal)3 78.5 (78) dB rms RMS

78 (78) dB p-p Peak PeriodicSNR (Ramp)3 62.3 (62) dB rms RMS

61 (62.5) dB p-p Peak Periodic

NOTES1All measurements are made in 4× Oversampling Mode unless otherwise specified.2Temperature range TMIN to TMAX: 0°C to 70°C.3Values in brackets apply to 2× Oversampling Mode.Specifications subject to change without notice.

(VAA = 5 V � 250 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. Allspecifications TMIN to TMAX2 unless otherwise noted.)

(VAA = 3.3 V � 150 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. Allspecifications TMIN to TMAX2 unless otherwise noted.)

ADV7194

–6– REV. A

5 V TIMING CHARACTERISTICSParameter Min Typ Max Unit Test Conditions

MPU PORT2

SCLOCK Frequency 0 400 kHzSCLOCK High Pulsewidth, t1 0.6 µsSCLOCK Low Pulsewidth, t2 1.3 µsHold Time (Start Condition), t3 0.6 µs After This Period the First Clock Is GeneratedSetup Time (Start Condition), t4 0.6 µs Relevant for Repeated Start ConditionData Setup Time, t5 100 nsSDATA, SCLOCK Rise Time, t6 300 nsSDATA, SCLOCK Fall Time, t7 300 nsSetup Time (Stop Condition), t8 0.6 µs

ANALOG OUTPUTS2

Analog Output Delay 8 nsDAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXELPORT3

fCLOCK 27 MHzClock High Time, t9 8 nsClock Low Time, t10 8 nsData Setup Time, t11 6 nsData Hold Time, t12 5 nsControl Setup Time, t11 6 nsControl Hold Time, t12 4 nsDigital Output Access Time, t13 13 24 nsDigital Output Hold Time, t14 12 nsPipeline Delay, t15 (2× Oversampling) 57 Clock CyclesPipeline Delay, t15 (4× Oversampling) 67 Clock Cycles

TELETEXT PORT4

Digital Output Access Time, t16 11 nsData Setup Time, t17 3 nsData Hold Time, t18 6 ns

RESET CONTROLReset Low Time 3 20 ns

PLL2

PLL Output Frequency 54 MHz

NOTES1Temperature range TMIN to TMAX: 0°C to 70°C.2Guaranteed by characterization.3Pixel Port consists of the following:Data: P0–P9, Y0/P10–Y9/P19,Control: HSYNC, VSYNC, BLANKClock: CLKIN Input.

4Teletext Port consists of:Digital Output: TTXRQ,Data: TTX.


(VAA = 5 V � 250 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. Allspecifications TMIN to TMAX1 unless otherwise noted.)

ADV7194

–7–REV. A

3.3 V TIMING CHARACTERISTICSParameter Min Typ Max Unit Test Conditions

MPU PORTSCLOCK Frequency 0 400 kHzSCLOCK High Pulsewidth, t1 0.6 µsSCLOCK Low Pulsewidth, t2 1.3 µsHold Time (Start Condition), t3 0.6 µs After This Period the First Clock Is GeneratedSetup Time (Start Condition), t4 0.6 µs Relevant for Repeated Start ConditionData Setup Time, t5 100 nsSDATA, SCLOCK Rise Time, t6 300 nsSDATA, SCLOCK Fall Time, t7 300 nsSetup Time (Stop Condition), t8 0.6 2 µs

ANALOG OUTPUTSAnalog Output Delay 8 nsDAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXELPORT3

fCLOCK 27 MHzClock High Time, t9 8 nsClock Low Time, t10 8 nsData Setup Time, t11 6 nsData Hold Time, t12 4 nsControl Setup Time, t11 2.5 nsControl Hold Time, t12 3 nsDigital Output Access Time, t13 13 nsDigital Output Hold Time, t14 12 nsPipeline Delay, t15, 2× Oversampling 37 Clock Cycles

TELETEXT PORT4

Digital Output Access Time, t16 11 nsData Setup Time, t17 3 nsData Hold Time, t18 6 ns

RESET CONTROLRESET Low Time 3 20 ns

PLLPLL Output Frequency 54 MHz

NOTES1Temperature range TMIN to TMAX: 0°C to 70°C.2Guaranteed by characterization.3Pixel Port consists of the following:Data: P0–P9, Y0/P10–Y9/P19,Control: HSYNC, VSYNC, BLANKClock: CLKIN Input.

4Teletext Port consists of:Digital Output: TTXRQ,Data: TTX.


(VAA = 3.3 V � 150 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. Allspecifications TMIN to TMAX1 unless otherwise noted.)2

ADV7194

–8– REV. A

t3

t2

t6 t1

t7

t5 t3

t4 t8

SDA

SCL

Figure 1. MPU Port Timing Diagram

t9

t11

CLOCK

PIXEL INPUTDATA

t10 t12HSYNC,VSYNC,BLANK

Cb Y Cr Y Cb Y

HSYNC,VSYNC,BLANK,

CSO_HSO,VSO, CLAMP

t13

t14

CONTROLI/PS

CONTROLO/PS

Figure 2. Pixel and Control Data Timing Diagram

t16

t17 t18

TTXREQ

CLOCK

TTX

4 CLOCKCYCLES

4 CLOCKCYCLES

4 CLOCKCYCLES

3 CLOCKCYCLES

4 CLOCKCYCLES

Figure 3. Teletext Timing Diagram

t9 t10t12

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cb1 Cb2 Cb3 Cb4 Cb5

Cr0 Cr1 Cr2 Cr3 Cr4 Cr5

t11

CLOCK

Y0 – Y9INCLUDING

SYNC INFORMATION

Cb0 – Cb9

Cr0 – Cr9

PROGRESSIVESCAN INPUT

Figure 4. Progressive Scan Input Timing

ADV7194

–9–REV. A

ABSOLUTE MAXIMUM RATINGS1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VVoltage on Any Digital Input Pin . . . . GND – 0.5 V to VAA + 0.5 VStorage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°CJunction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°CBody Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220°CAnalog Outputs to GND2 . . . . . . . . . . . . . . GND – 0.5 to VAANOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operational sectionsof this specification is not implied. Exposure to absolute maximum rating condi-tions for extended periods may affect device reliability.

2Analog Output Short Circuit to any Power Supply or Common can be of anindefinite duration.

PACKAGE THERMAL PERFORMANCEThe 80-lead package is used for this device. The junction-to-ambient (θJA) thermal resistance in still air on a four-layer PCBis 24.7°C.To reduce power consumption when using this part the usercan run the part on a 3.3 V supply, turn off any unused DACs.

The user must at all times stay below the maximum junctiontemperature of 110°C. The following equation shows how tocalculate this junction temperature:

Junction Temperature = (VAA × (IDAC + ICCT)) × θJA + 70°C (TAMB)IDAC = 10 mA + (sum of the average currents consumed by

each powered-on DAC)Average current consumed by each powered-on DAC =

(VREF × K )/RSETVREF = 1.235 V

K = 4.2146

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7194KST 0°C to 70°C 80-Lead Quad Flatpack ST-80

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe ADV7194 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATION

P2P3

P4

P5P6

P7

P8P9

P0

P1

Y[0]/P10

VREFCOMP 1

DAC ADAC BVAAAGND

DAC C

DAC D

AGNDVAADAC E

DAC FCOMP 2RSET2DGND

RESETPAL_NTSC

RSET1

ALSB

SCRESET/RTC/TR

DG

ND

HS

YN

C

VS

YN

CB

LA

NK

TT

XR

EQ

DG

ND

VD

D

AG

ND

VA

A

SC

LS

DA

CL

KIN

CL

KO

UT

VD

D

Cb

[4]

Cb

[5]

Cb

[6]

Cb

[7]

Cb

[8]

Cb

[9]

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1

2

3

4

5

6

7

8

9

10

11

13

14

15

16

12

17

18

20

19

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN 1IDENTIFIER

TOP VIEW(Not to Scale)

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

DG

ND

VD

DC

b[3

]

DG

ND

VS

O/T

TX

/CL

AM

P

CS

O_H

SO

Cb

[2]

Cb

[1]

Cb

[0]

Cr[

9]

Cr[

8]C

r[7]

Cr[

6]

Cr[

5]

VD

DC

r[4]

Cr[

3]

Cr[

2]

Cr[

1]

Cr[

0]

ADV7194LQFP

Y[1]/P11

Y[2]/P12

Y[3]/P13

Y[4]/P14

Y[5]/P15

Y[6]/P16

Y[7]/P17

Y[8]/P18

Y[9]/P19

ADV7194

–10– REV. A

PIN FUNCTION DESCRIPTIONS

Pin Input/No. Mnemonic Output Function

1–10 P0–P9 I 10-Bit or 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set upon Pin P0 (Pin Number 1) in 10-bit input mode.

11–20 Y0/P10–Y9/P19 I 20-Bit or 16-Bit Multiplexed YCrCb Pixel Port or 1× 10-bit progressive scan input for Y data.21, 34, 68, 79 VDD P Digital Power Supply (3.3 V to 5 V).

22, 33, 43, 69, DGND G Digital Ground.8023 HSYNC I/O HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output

(Master Mode) or an input (Slave Mode) and accept Sync Signals.

24 VSYNC I/O VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input(Slave Mode) and accept VSYNC as a Control Signal.

25 BLANK I/O Video Blanking Control Signal. This signal is optional. For further information see Verti-cal Blanking and Data Insertion Blanking Input section.

26–31, 75–78 Cb0–Cb9 I 1 × 10-Bit Progressive Scan Input Port for Cb Data.32 TTXREQ O Teletext Data Request Output Signal, used to control teletext data transfer.

35, 49, 52 AGND G Analog Ground.

36 CLKIN I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alterna-tively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

37 CLKOUT O Clock Output Pin.

38, 48, 53 VAA P Analog Power Supply (3.3 V to 5 V).

39 SCL I MPU Port Serial Interface Clock Input.

40 SDA I/O MPU Port Serial Data Input/Output.

41 SCRESET/RTC/TR I Multifunctional Input: Real-Time Control (RTC) input, Timing Reset input, SubcarrierReset input.

42 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.

44 RSET2 I A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudesof the Video Signals from the DAC D, E, F.

45 COMP 2 O Compensation Pin for DACs D, E, and F. Connect a 0.1 µF Capacitor from COMP 2 toVAA.

46 DAC F O S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.

47 DAC E O S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.

50 DAC D O Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.

51 DAC C O S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.

54 DAC B O S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.

55 DAC A O Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.

56 COMP 1 O Compensation Pin for DACs A, B, and C. Connect a 0.1 µF Capacitor from COMP 1 toVAA.

57 VREF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An externalVREF can not be used in 4× oversampling mode.

58 RSET1 I A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudesof the Video Signals from the DAC A, B, C.

59 PAL_NTSC I Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL.

60 RESET I The input resets the on-chip timing generator and sets the ADV7194 into default modeSee Appendix 8 for Default Register settings.

61 CSO_HSO O Dual function CSO or HSO output Sync Signal at TTL level.

62 VSO/TTX/CLAMP I/O Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin.CLAMP TTL Output Signals can be used to drive external circuitry to enable clampingof all Video Signals.

63–67, 70–74 Cr0–Cr9 I 1 × 10-Bit Progressive Scan Input Port for Cr Data.

ADV7194

–11–REV. A

DETAILED DESCRIPTION OF FEATURESClocking

Single 27 MHz Clock Required to Run the Device4� Oversampling with Internal 54 MHz PLLSquare Pixel Operation

Advanced Power ManagementProgrammable Video Control Features

Digital Noise ReductionBlack Burst Signal GenerationPedestal LevelHue, Brightness, Contrast and SaturationClamping Output signalVBI (Vertical Blanking Interval)Subcarrier Frequency and PhaseLUMA DelayCHROMA DelayGamma CorrectionLuma and Chroma FiltersLuma SSAF (Super Subalias Filter)

Average Brightness DetectionField CounterInterlaced/Noninterlaced OperationComplete On-Chip Video Timing GeneratorProgrammable Multimode Master/Slave OperationCGMS (Copy Generation Management System)WSS (Wide Screen Signaling)Closed Captioning SupportTeletext Insertion Port (PAL-WST)2-Wire Serial MPU Interface(I2C Compatible and Fast I2C)I2C Registers Synchronized to VSYNC

INTERPOLATOR

MODULATORAND

HUE CONTROL

BRIGHTNESSCONTROL

ANDADD SYNC

ANDINTERPOLATOR

SATURATIONCONTROL

ANDADD BURST

ANDINTERPOLATOR

PROGRAMMABLELUMA FILTER

ANDSHARPNESS

FILTER

PROGRAMMABLECHROMAFILTER

SIN/COSDDS

BLOCK

REAL-TIMECONTROLCIRCUIT

SCRESET/RTC/TR

INTERPOLATOR

MULTIPLEXER

YUV-TO-RGBMATRIX

ANDYUV LEVELCONTROL

BLOCK

Y0–Y9Cb0–Cb9Cr0–Cr9

10-BITDAC

10-BITDAC

10-BITDAC

DACCONTROL

BLOCK

10-BITDAC

10-BITDAC

10-BITDAC

DACCONTROL

BLOCK

DAC A

DAC B

DAC C

VREFRSET2COMP2

DAC D

DAC F

DAC E

RSET1COMP1

DNRAND

GAMMACORRECTION

10

10

10

V

U

YYCrCb-TO-YUV

MATRIX

10

10

10

V

U

Y

PLL

DEMUX

10 1010

TELETEXTINSERTION

BLOCK

VIDEO TIMINGGENERATOR

CGMS/WSSAND

CLOSED CAPTIONINGCONTROL

I2C MPU PORT

ALSBSDASCLPAL_NTSC VSO/CLAMP CSO_HSO

HSYNCVSYNCBLANK

RESET

TTX

TTXREQ

P0

P15

CLKIN

CLKOUT

ADV7194

Figure 5. Detailed Functional Block Diagram

GENERAL DESCRIPTIONThe ADV7194 is an integrated Digital Video Encoder that con-verts digital CCIR-601/656 4:2:2 10-bit (or 20-bit or 8-/16-bit)component video data into a standard analog baseband televisionsignal compatible with worldwide standards. Additionally thereis the possibility to input video data in 3× 10-bit YCrCb progres-sive scan format to facilitate interfacing devices such as progressivescan systems.

There are six DACs available on the ADV7194, each of whichis capable of providing 4.33 mA of current. In addition to thecomposite output signal there is the facility to output S-Video(Y/C Video), RGB Video, and YUV Video. All YUV formats(SMPTE/EBU N10, MII, or Betacam) are supported.

The on-board SSAF (Super Subalias Filter) with extendedluminance frequency response and sharp stopband attenuationenables studio quality video playback on modern TVs, givingoptimal horizontal line resolution. An additional sharpnesscontrol feature allows high-frequency enhancement on the lumi-nance signal.

SUBTRACT SIGNAL IN THRESHOLDRANGE FROM ORIGINAL SIGNAL

FILTER OUTPUT>THRESHOLD?

FILTER OUTPUT<THRESHOLD

INPUT FILTERBLOCK

MAIN SIGNAL PATH

NOISE SIGNAL PATH

Y DATAINPUT

DNR OUT

ADD SIGNAL ABOVE THRESHOLDRANGE TO ORIGINAL SIGNAL

DNR CONTROL

BLOCK SIZE CONTROLBORDER AREABLOCK OFFSET

GAIN

CORING GAIN DATACORING GAIN BORDER

DNR SHARPNESS MODE

FILTER OUTPUT

THRESHOLD

INPUT FILTERBLOCK

MAIN SIGNAL PATH

NOISE SIGNAL PATH

Y DATAINPUT

DNR OUT

DNR CONTROL

BLOCK SIZE CONTROLBORDER AREABLOCK OFFSET

GAIN

CORING GAIN DATACORING GAIN BORDER

DNR MODE

Figure 6. Block Diagram for DNR Mode and DNR Sharp-ness Mode

ADV7194

–12– REV. A

The output video frames are synchronized with the incomingdata timing reference codes. Optionally the encoder accepts(and can generate) HSYNC, VSYNC and FIELD timing sig-nals. These timing signals can be adjusted to change pulsewidthand position while the part is in master mode.

HSO/CSO and VSO TTL outputs are also available and aretimed to the analog output video.

A separate teletext port enables the user to directly input teletextdata during the vertical blanking interval.

The ADV7194 also incorporates WSS and CGMS-A data controlgeneration.

The ADV7194 modes are set up over a 2-wire serial bidirectionalport (I2C-compatible) with two slave addresses and the device isregister-compatible with the ADV7172/ADV7173.

The ADV7194 is packaged in an 80-lead LQFP package.

DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, N, and NTSC M, N modes, YCrCb4:2:2 Data is input via the CCIR-656/601-compatible Pixel Port ata 27 MHz Data Rate. The Pixel Data is demultiplexed to formthree data paths. Y typically has a range of 16 to 235, Cr and Cbtypically have a range of 128+/–112; however, it is possible to inputdata from 1 to 254 on both Y, Cb, and Cr. The ADV7194 sup-ports PAL (B, D, G, H, I, N) and NTSC M, N (with and withoutPedestal) and PAL60 standards.

Digital Noise Reduction can be applied to the Y signal. Pro-grammable gamma correction can also be applied to the Ysignal if required.

The Y data can be manipulated for contrast control and a setuplevel can be added for brightness control. The Cr, Cb data canbe scaled to achieve color saturation control. All settings becomeeffective at the start of the next field when double buffering isenabled.

The appropriate sync, blank and burst levels are added to theYCrCb data. Closed-Captioning and Teletext levels are alsoadded to Y and the resultant data is interpolated to 54 MHz(4× Oversampling Mode). The interpolated data is filtered andscaled by three digital FIR filters.

The U and V signals are modulated by the appropriate SubcarrierSine/Cosine waveforms and a phase offset may be added onto thecolor subcarrier during active video to allow hue adjustment. Theresulting U and V signals are added together to make up theChrominance Signal. The Luma (Y) signal can be delayed by upto six clock cycles (at 27 MHz) and the Chroma signal can bedelayed by up to eight clock cycles (at 27 MHz).

The Luma and Chroma signals are added together to make upthe Composite Video Signal. All timing signals are controlled.

The YCrCb data is also used to generate RGB data with appropri-ate sync and blank levels. The YUV levels are scaled to output thesuitable SMPTE/EBU N10, MII, or Betacam levels.

Each DAC can be individually powered off if not required. Acomplete description of DAC output configurations is given inthe Mode Register 2 section.

Video output levels are illustrated in Appendix 9.

Digital noise reduction allows improved picture quality inremoving low-amplitude, high-frequency noise. Figure 6 showsthe DNR functionality in the two modes available.

Programmable gamma correction is also available. The figurebelow shows the response of different gamma values to a rampinput signal.

250

200

150

100

50

0

300

SIGNAL OUTPUTS

SIGNA

L INP

UT

0.5

GAMMA CORRECTION BLOCK OUTPUTTO A RAMP INPUT FOR VARIOUS GAMMA VALUES

GA

MM

A-C

OR

RE

CT

ED

AM

PL

ITU

DE

0 50 100 150 200 250LOCATION

0.3

1.5

1.8

Figure 7. Signal Input (Ramp) and Selectable GammaOutput Curves

The device is driven by a 27 MHz clock. Data can be output at27 MHz or 54 MHz (on-board PLL) when 4× oversampling isenabled. Also, the filter requirements in 4× oversampling and 2×oversampling differ, as can be seen in the figure below.

–30dB

0dB

6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz

2� FILTERREQUIREMENTS


Figure 8. Output Filter Requirements in 2× and 4×Oversampling Mode

ENCODERCORE

2�

INTERPOLATION

6

DAC

OUTPUTS

54MHzOUTPUTRATE

ADV7194

PLL54MHz

MPEG2PIXEL BUS

27MHz

Figure 9. PLL and 4x Oversampling Block Diagram

The ADV7194 also supports both PAL and NTSC square pixeloperation. In this case, the encoder requires a 24.5454 MHzclock for NTSC or 29.5 MHz clock for PAL square pixel modeoperation. All internal timing is generated on-chip.

An advanced power management circuit enables optimal con-trol of power consumption in both normal operating modes orsleep modes.

ADV7194

–13–REV. A

Table I. Luminance Internal Filter Specifications (4� Oversampling)

Passband 3 dB Bandwidth2

Filter Type Filter Selection Ripple1 (dB) (MHz)

MR04 MR03 MR02Low-Pass (NTSC) 0 0 0 0.16 4.24Low-Pass (PAL) 0 0 1 0.1 4.81Notch (NTSC) 0 1 0 0.09 2.3/4.9/6.6Notch (PAL) 0 1 1 0.1 3.1/5.6/6.4Extended (SSAF) 1 0 0 0.04 6.45CIF 1 0 1 0.127 3.02QCIF 1 1 0 Monotonic 1.5

NOTES1Passband Ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). Thepassband is defined to have 0–fc frequency limits for a low-pass filter, 0–f1 and f2–infinity for a notch filter,where fc, f1, f2 are the –3 dB points.

23 dB bandwidth refers to the –3 dB cutoff frequency.

Table II. Chrominance Internal Filter Specifications (4� Oversampling)

Passband 3 dB Bandwidth2

Filter Type Filter Selection Ripple1 (dB) (MHz)

MR07 MR06 MR051.3 MHz Low-Pass 0 0 0 0.09 1.3950.65 MHz Low-Pass 0 0 1 Monotonic 0.651.0 MHz Low-Pass 0 1 0 Monotonic 1.02.0 MHz Low-Pass 0 1 1 0.048 2.23.0 MHz Low-Pass 1 1 1 Monotonic 3.2CIF 1 0 1 Monotonic 0.65QCIF 1 1 0 Monotonic 0.5

NOTES1Passband Ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). Thepassband is defined to have 0–fc frequency limits for a low-pass filter, 0–f1 and f2–infinity for a notch filter,where fc, f1, f2 are the –3 dB points.

23 dB bandwidth refers to the –3 dB cutoff frequency.

When used to interface progressive scan systems, the ADV7194allows input to YCrCb signals in Progressive Scan format (3 × 10bit) before these signals are routed to the interpolation filtersand the DACs.

INTERNAL FILTER RESPONSEThe Y Filter supports several different frequency responsesincluding two low-pass responses, two notch responses, anExtended (SSAF) response with or without gain boost/attenuation,a CIF response and a QCIF response. The UV Filter supportsseveral different frequency responses including five low-passresponses, a CIF response and a QCIF response, as can be seen inthe following figures.

In Extended Mode there is the option of 12 responses in therange from –4 dB to +4 dB. The desired response can be chosenby the user by programming the correct value via the I2C. Thevariation of frequency responses can be seen in the tables onthe following pages.

For a more detailed filter specification, refer to Analog Devices’application note AN-562.

ADV7194

–14– REV. A

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

FREQUENCY – MHz

MA

GN

ITU

DE

– d

B

Figure 10. NTSC Low-Pass Luma Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

FREQUENCY – MHz

MA

GN

ITU

DE

– d

B

Figure 11. PAL Low-Pass Luma Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 12. Extended Mode (SSAF) Luma Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 13. NTSC Notch Luma Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 14. PAL Notch Luma Filter

5

0

0

1

3

4

1 2 6 73 5–1

2

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz4

Figure 15. Extended SSAF and Programmable Gain,Showing Range 0 dB/4 dB

ADV7194

–15–REV. A

1

0

–4

–3

–1

0

1 2 6 73 5–5

–2

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz4

Figure 16. Extended SSAF and Programmable Attenua-tion, Showing Range 0 dB/–4 dB

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 17. Luma CIF Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 18. Chroma 0.65 MHz Low-Pass Filter

4

0

0

–8

–6

–2

2

1 2 6 73 5–12

–4

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

–10

4

Figure 19. Extended SSAF and Programmable Gain/Attenuation, Showing Range +4 dB/–12 dB

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 20. Luma QCIF Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 21. Chroma 1 MHz Low-Pass Filter

ADV7194

–16– REV. A

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 22. Chroma 1.3 MHz Low-Pass Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz


0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 24. Chroma QCIF Filter

0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz


0

–20

0

–50

–60

–30

–10

2 4 10 126 8–70

–40

MA

GN

ITU

DE

– d

B

FREQUENCY – MHz

Figure 26. Chroma CIF Filter

ADV7194

–17–REV. A

FEATURES—FUNCTIONAL DESCRIPTIONBLACK BURST OUTPUTIt is possible to output a black burst signal from two DACs. Thissignal output is very useful for professional video equipmentsince it enables two video sources to be locked together. (ModeRegister 9.)

BLACK BURST OUTPUTCVBS

CVBS

DIGITAL DATAGENERATOR ADV7194

DIGITAL DATAGENERATOR ADV7194

Figure 27. Possible Application for the Black Burst OutputSignal

BRIGHTNESS DETECTThis feature is used to monitor the average brightness of theincoming Y video signal on a field by field basis. The informa-tion is read from the I2C and based on this information the colorsaturation, contrast and brightness controls can be adjusted(for example to compensate for very dark pictures). (Bright-ness Detect Register.)

CHROMA/LUMA DELAYThe luminance data can be delayed by maximum of six clockcycles. Additionally the Chroma can be delayed by a maximumof eight clock cycles (one clock cycle at 27 MHz). (Timing Reg-ister 0 and Mode Register 9.)

CHROMA DELAY LUMA DELAY

Figure 28. Chroma Delay Figure 29. Luma Delay

CLAMP OUTPUTThe ADV7194 has a programmable clamp TTL output signal.This clamp signal is programmable to the front and back porch.The clamp signal can be varied by one to three clock cycles ina positive and negative direction from the default position. (ModeRegister 5, Mode Register 7.)

CVBSOUTPUT PIN

CLAMPOUTPUT PIN

MR57 = 1

MR57 = 0

CLAMP O/P SIGNALS

Figure 30. Clamp Output Timing

CSO, HSO, AND VSO OUTPUTSThe ADV7194 supports three output timing signals, CSO (com-posite sync signal), HSO (Horizontal Sync Signal) and VSO(Vertical Sync Signal). These output TTL signals are alignedwith the analog video outputs. See Figure 31 for an exampleof these waveforms. (Mode Register 7.)

OUTPUTVIDEO

525 1 2 3 4 5 6 7 8 9 10 11–19

EXAMPLE:- NTSC

CSO

HSO

VSO

Figure 31. CSO, HSO, VSO Timing Diagram

COLOR BAR GENERATIONThe ADV7194 can be configured to generate 100/7.5/75/7.5color bars for NTSC or 100/0/75/0 color bars for PAL. (ModeRegister 4.)

COLOR BURST SIGNAL CONTROLThe burst information can be switched on and off the compositeand chroma video output. (Mode Register 4.)

COLOR CONTROLSThe ADV7194 allows the user to control the brightness, contrast,hue and saturation of the color. The control registers may bedouble-buffered, meaning that any modification to the registerswill be done outside the active video region and, therefore, changesmade will not be visible during active video.

Contrast ControlContrast adjustment is achieved by scaling the Y input data by afactor programmed by the user. This factor allows the data to bescaled between 0% and 150%. (Contrast Control Register.)

Brightness ControlThe brightness is controlled by adding a programmable setup levelonto the scaled Y data. This brightness level may be added ontothe Y data. For NTSC with pedestal, the setup can vary from0 IRE to 22.5 IRE. For NTSC without pedestal and PAL, thesetup can vary from –7.5 IRE to +15 IRE. (Brightness ControlRegister.)

Color SaturationColor adjustment is achieved by scaling the Cr and Cb inputdata by a factor programmed by the user. This factor allows thedata to be scaled between 0% and 200%. (U Scale Register andV Scale Register.)

Hue Adjust ControlThe hue adjustment is achieved on the composite and chromaoutputs by adding a phase offset onto the color subcarrier in theactive video but leaving the color burst unmodified, i.e., onlythe phase between the video and the colorburst is modified andhence the hue is shifted. The ADV7194 provides a range of± 22° in increments of 0.17578125°. (Hue Adjust Register.)

CHROMINANCE CONTROLThe color information can be switched on and off the com-posite, chroma and color component video outputs. (ModeRegister 4.)

ADV7194

–18– REV. A

UNDERSHOOT LIMITERA limiter is placed after the digital filters. This prevents anysynchronization problems for TVs. The level of undershoot isprogrammable between –1.5 IRE, –6 IRE, –11 IRE when oper-ating in 4× Oversampling Mode. In 2× Oversampling Mode thelimits are –7.5 IRE and 0 IRE. (Mode Register 9 and TimingRegister 0.)

DIGITAL NOISE REDUCTIONDNR is applied to the Y data only. A filter block selects thehigh frequency, low-amplitude components of the incomingsignal (DNR Input Select). The absolute value of the filter outputis compared to a programmable threshold value (DNR Thresh-old Control). There are two DNR modes available: DNR Modeand DNR Sharpness Mode.

In DNR Mode, if the absolute value of the filter output is smallerthan the threshold, it is assumed to be noise. A programmableamount (Coring Gain Control) of this noise signal will be sub-tracted from the original signal.

In DNR Sharpness Mode, if the absolute value of the filter outputis less than the programmed threshold, it is assumed to be noise,as before. Otherwise, if the level exceeds the threshold, nowbeing identified as a valid signal, a fraction of the signal (CoringGain Control) will be added to the original signal in order to boosthigh frequency components and to sharpen the video image.

In MPEG systems it is common to process the video informa-tion in blocks of 8 × 8 pixels for MPEG2 systems, or 16 × 16pixels for MPEG1 systems (Block Size Control). DNR can beapplied to the resulting block transition areas that are known tocontain noise. Generally the block transition area contains twopixels. It is possible to define this area to contain four pixels(Border Area Control).

It is also possible to compensate for variable block positioning ordifferences in YCrCb pixel timing with the use of the Block OffsetControl. (Mode Register 8, DNR Registers 0–2.)

DOUBLE BUFFERINGDouble buffering can be enabled or disabled on the followingregisters: Closed Captioning Registers, Brightness ControlRegister, V-Scale Register, U-Scale Register, Contrast ControlRegister, Hue Adjust Register, and the Gamma Curve Selectbit. These registers are updated once per field on the fallingedge of the VSYNC signal. Double Buffering improves the over-all performance of the ADV7194, since modifications to registersettings will not be made during active video, but take effect onthe start of the active video. (Mode Register 8.)

GAMMA CORRECTION CONTROLGamma correction may be performed on the luma data. Theuser has the choice to use either of two different gamma curves,A or B. At any one time one of these curves is operational ifgamma correction is enabled. Gamma correction allows themapping of the luma data to a user-defined function. (ModeRegister 8, Gamma Correction Registers 0–13.)

NTSC PEDESTAL CONTROLIn NTSC mode it is possible to have the pedestal signal gener-ated on the output video signal. (Mode Register 2.)

POWER-ON RESETAfter power-up, it is necessary to execute a RESET operation.A reset occurs on the falling edge of a high-to-low transition onthe RESET pin. This initializes the pixel port such that the dataon the pixel inputs pins is ignored. See Appendix 8 for the regis-ter settings after RESET is applied.

PROGRESSIVE SCAN INPUTIt is possible to input data to the ADV7194 in progressive scanformat. For this purpose the input pins Y0/P10–Y9/P19, Cr0–Cr9,Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data and 10-bit Crdata. The data is clocked into the part at 27 MHz. The datais then filtered and sinc corrected in an 2× Interpolation filterand then output to three video DACs at 54 MHz (to interface toa progressive scan monitor).

FREQUENCY – MHz

0

0 305

AM

PL

ITU

DE

– d

B

10 15 20 25

–10

–20

–30

–50

–60

–40

–70

Figure 32. Plot of the Interpolation Filter for the Y Data

FREQUENCY – MHz

0

0 305

AM

PL

ITU

DE

– d

B

10 15 20 25

–10

–20

–30

–50

–60

–40

–70

Figure 33. Plot of the Interpolation Filter for the CrCb Data

It is assumed that there is no color space conversion or any othersuch operation to be performed on the incoming data. Thus ifthese DAC outputs are to drive a TV, all relevant timing andsynchronization data should be contained in the incoming digitalY data. An FPGA can be used to achieve this.

The block diagram below shows a possible configuration forprogressive scan mode using the ADV7194.

ADV7194

–19–REV. A

27MHz

54MHz

6

DAC

OUTPUTS

ADV7194

MPEG2

PLL

ENCODERCOREPIXEL BUS

INTERPOLATION

2�

PROGRESSIVESCAN

DECODER30-BIT INTERFACE

Figure 34. Block Diagram Using the ADV7194 in Progres-sive Scan Mode

The progressive scan decoder deinterlaces the data from theMPEG2 decoder. This now means that there are 525 video linesper field in NTSC mode and 625 video lines per field in PALmode. The duration of the video line is now 32 µs.It is important to note that the data from the MPEG2 decoder isin 4:2:2 format. The data output from the progressive scan decoderis in 4:4:4 format. Thus it is assumed that some form of interpola-tion on the color component data is performed in the progressivescan decoder IC. (Mode Register 8.)

REAL-TIME CONTROL, SUBCARRIER RESET ANDTIMING RESETTogether with the SCRESET/RTC/TR pin and of ModeRegister 4 (Genlock Control), the ADV7194 can be used in(a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or(c) RTC Mode.

(a) A TIMING RESET is achieved in holding this pin high. Inthis state the horizontal and vertical counters will remainreset. On releasing this pin (set to low), the internal counterswill commence counting again. The minimum time the pinhas to be held high is 37 ns (1 clock cycle at 27 MHz),otherwise the reset signal might not be recognized.

(b) The SUBCARRIER PHASE will reset to that of Field 0 atthe start of the following field when a low to high transitionoccurs on this input pin.

(c) In RTC MODE, the ADV7194 can be used to lock to anexternal video source.

The real-time control mode allows the ADV7194 to auto-matically alter the subcarrier frequency to compensate forline length variations. When the part is connected to a devicethat outputs a digital datastream in the RTC format (suchas an ADV7185 video decoder, see Figure 37), the part willautomatically change to the compensated subcarrier fre-quency on a line-by-line basis. This digital datastream is67 bits wide and the subcarrier is contained in Bits 0 to 21.Each bit is two clock cycles long. 00Hex should be writteninto all four Subcarrier Frequency registers when using thismode. It is recommended to use the ADV7185 in this mode(Mode Register 4.)

SCH PHASE MODEThe SCH phase is configured in default mode to reset everyfour (NTSC) or eight (PAL) fields to avoid an accumulation ofSCH phase error over time. In an ideal system, zero SCH phaseerror would be maintained forever, but, in reality, this is impossibleto achieve due to clock frequency variations. This effect is reducedby the use of a 32-bit DDS, which generates this SCH.

Resetting the SCH phase every four or eight fields avoids theaccumulation of SCH phase error, and results in very minorSCH phase jumps at the start of the four or eight field sequence.

Resetting the SCH phase should not be done if the video sourcedoes not have stable timing or the ADV7194 is configured in RTCmode. Under these conditions (unstable video) the SubcarrierPhase Reset should be enabled but no reset applied. In thisconfiguration the SCH Phase will never be reset; this meansthat the output video will now track the unstable input video. TheSubcarrier Phase Reset when applied will reset the SCH phaseto Field 0 at the start of the next field (e.g., Subcarrier PhaseReset applied in Field 5 (PAL) on the start of the next field SCHphase will be reset to Field 0). (Mode Register 4.)

SLEEP MODEIf, after RESET, the SCRESET/RTC/TR and NTSC_PAL pinsare both set high, the ADV7194 will power-up in Sleep Mode tofacilitate low-power consumption before all registers have beeninitialized.

If Power-up in Sleep Mode is disabled, Sleep Mode controlpasses to the Sleep Mode control in Mode Register 2 (i.e., con-trol via I2C). (Mode Register 2 and Mode Register 6.)

SQUARE PIXEL MODEThe ADV7194 can be used to operate in square pixel mode. ForNTSC operation an input clock of 24.5454 MHz is required.Alternatively, for PAL operation, an input clock of 29.5 MHzis required. The internal timing logic adjusts accordingly forsquare pixel mode operation. Square pixel mode is not availablein 4× Oversampling mode. (Mode Register 2.)

VERTICAL BLANKING DATA INSERTION AND BLANKINPUTIt is possible to allow encoding of incoming YCbCr data onthose lines of VBI that do not have line sync or pre-/post-equal-ization pulses. This mode of operation is called Partial Blanking. Itallows the insertion of any VBI data (Opened VBI) into theencoded output waveform, this data is present in digitizedincoming YCbCr data stream (e.g., WSS data, CGMS, VPSetc.). Alternatively the entire VBI may be blanked (no VBI datainserted) on these lines. VBI is available in all timing modes.

It is possible to allow control over the BLANK signal usingTiming Register 0. When the BLANK input is enabled (TR03 =0 and input pin tied low), the BLANK input can be used toinput externally generated blank signals in Slave Mode 1, 2, or3. When the BLANK input is disabled (TR03 = 1 and input pintied low or tied high) the BLANK input is not used and theADV7194 automatically blanks all normally blank lines as perCCIR-624. (Timing Register 0.)

ADV7194

–20– REV. A

YUV LEVELSThis functionality allows the ADV7194 to output SMPTE levelsor Betacam levels on the Y output when configured in PAL orNTSC mode.

Sync VideoBetacam 286 mV 714 mVSMPTE 300 mV 700 mVMII 300 mV 700 mV

As the data path is branched at the output of the filters the lumasignal relating to the CVBS or S-Video Y/C output is unaltered.It is only the Y output of the YCrCb outputs that is scaled.This control allows color component levels to have a peak-peakamplitude of 700 mV, 1000 mV or the default values of 934 mVin NTSC and 700 mV in PAL. (Mode Register 5.)

20-/16-BIT INTERFACEIt is possible to input data in 20-bit or 16-bit format. In thiscase, the interface only operates if the data is accompanied byseparate HSYNC/VSYNC/BLANK signals. Twenty-bit or 16-bit mode is not available in Slave Mode 0 since EAV/SAV timingcodes are used. (Mode Register 8.)

4� OVERSAMPLING AND INTERNAL PLLIt is possible to operate all six DACs at 27 MHz (2× Oversam-pling) or 54 MHz (4× Oversampling).The ADV7194 is supplied with a 27 MHz clock synced with theincoming data. Two options are available: to run the devicethroughout at 27 MHz or to enable the PLL. In the latter case,even if the incoming data runs at 27 MHz, 4× Oversamplingand the internal PLL will output the data at 54 MHz.

NOTEIn 4× Oversampling Mode the requirements for the optionaloutput filters are different than from those in 2× Oversampling.(Mode Register 1, Mode Register 6.)

27MHz 54MHzOUTPUT

PLL

INTERPOLATION

2�

54MHz

6

DAC

OUTPUTS

ADV7194

PIXEL BUS ENCODERCORE

MPEG2

Figure 35a. PLL and 4× Oversampling Block Diagram

–30dB

0dB

6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz



Figure 35b. Output Filter Requirements in 4× Oversam-pling Mode

VIDEO TIMING DESCRIPTIONThe ADV7194 is intended to interface to off-the-shelf MPEG1and MPEG2 Decoders. As a consequence, the ADV7194 accepts4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and hasseveral Video Timing Modes of operation that allow it to beconfigured as either System Master Video Timing Generator ora Slave to the System Video Timing Generator. The ADV7194generates all of the required horizontal and vertical timing periodsand levels for the analog video outputs.

The ADV7194 calculates the width and placement of analog syncpulses, blanking levels, and color burst envelopes. Color burstsare disabled on appropriate lines and serration and equalizationpulses are inserted where required.

In addition, the ADV7194 supports a PAL or NTSC square pixeloperation. The part requires an input pixel clock of 24.5454 MHzfor NTSC square pixel operation and an input pixel clock of29.5 MHz for PAL square pixel operation. The internal hori-zontal line counters place the various video waveform sections inthe correct location for the new clock frequencies.

The ADV7194 has four distinct Master and four distinct Slavetiming configurations. Timing Control is established with thebidirectional HSYNC, BLANK and VSYNC pins. Timing Regis-ter 1 can also be used to vary the timing pulsewidths and wherethey occur in relation to each other. (Mode Register 2, TimingRegister 0, 1.)

RESET SEQUENCEWhen RESET becomes active the ADV7194 reverts to thedefault output configuration (see Appendix for register settings).The ADV7194 internal timing is under the control of the logiclevel on the NTSC_PAL pin.

When RESET is released Y, Cr, Cb values corresponding to ablack screen are input to the ADV7194. Output timing signalsare still suppressed at this stage. DACs A, B, C are switched offand DACs D, E, F are switched on.

When the user requires valid data, Pixel Data Valid Control isenabled (MR26 = 1) to allow the valid pixel data to pass throughthe encoder. Digital output timing signals become active andthe encoder timing is now under the control of the Timing Regis-ters. If at this stage, the user wishes to select a different videostandard to that on the NTSC_PAL pin, Standard I2C Con-trol should be enabled (MR25 = 1) and the video standardrequired is selected by programming Mode Register 0 (Out-put Video Standard Selection). Figure 36 illustrates the RESETsequence timing.

ADV7194

–21–REV. A

XXXXXXX XXXXXXX

XXXXXXX XXXXXXX

XXXXXXX

XXXXXXX

XXXXXXX

OFF

0

DIGITAL TIMING SIGNALS SUPPRESSED TIMING ACTIVE

1

VALID VIDEO

VALID VIDEO

VALID VIDEO

BLACK VALUE

BLACK VALUE WITH SYNC

RESET

DAC D,DAC E

DAC F

DAC A,DAC B,DAC C

MR26PIXEL_DATA_VALID

DIGITAL TIMING

Figure 36. RESET Sequence Timing Diagram

COMPOSITEVIDEO

e.g., VCROR CABLE

CLOCK

GREEN/COMPOSITE/Y

BLUE/LUMA/U

ADV7194

P9–P0

SCRESET/RTC/TRVIDEODECODERADV7185

GLLLCC1

P19–P10RED/CHROMA/V

GREEN/COMPOSITE/Y

BLUE/LUMA/U

RED/CHROMA/V

H/L TRANSITIONCOUNT START

LOW128

RTC

TIME SLOT: 01 14 67 68NOT USED IN

ADV7194

19

VALIDSAMPLE

INVALIDSAMPLE

FSCPLL INCREMENT1

8/LINELOCKED CLOCK

5 BITSRESERVED

SEQUENCEBIT2

RESETBIT3

RESERVED

4 BITSRESERVED

21013

14 BITSRESERVED

0

FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7194 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCYREGISTERS OF THE ADV7194.SEQUENCE BITPAL: 0 = LINE NORMAL, 1 = LINE INVERTEDNTSC: 0 = NO CHANGERESET BITRESET ADV7194’s DDS

NOTES:1

2

3

Figure 37. RTC Timing and Connections

ADV7194

–22– REV. A

Mode 0 (CCIR–656): Slave Option(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7194 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timinginformation is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and aftereach line during active picture and retrace. Mode 0 is illustrated in Figure 38. The HSYNC, VSYNC and BLANK (if not used) pinsshould be tied high during this mode. Blank output is available.

YCr Y

FF

00

00

XY

80

10

80

10

FF

00

FF

AB

AB

AB

80

10

80

10

FF

00

00

XY

Cb Y

Cr

CbY

CbY

Cr

EAV CODE SAV CODE

ANCILLARY DATA(HANC)4 CLOCK 4 CLOCK

268 CLOCK 1440 CLOCK

4 CLOCK 4 CLOCK 280 CLOCK 1440 CLOCK

END OF ACTIVEVIDEO LINE

START OF ACTIVEVIDEO LINE

ANALOGVIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM(525 LlNES/60Hz)

PAL SYSTEM(625 LINES/50Hz)

Y

Figure 38. Timing Mode 0, Slave Mode

Mode 0 (CCIR–656): Master Option(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7194 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes inthe CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output onthe VSYNC pin. Mode 0 is illustrated in Figure 39 (NTSC) and Figure 40 (PAL). The H, V, and F transitions relative to the videowaveform are illustrated in Figure 41.

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22

DISPLAY DISPLAY VERTICAL BLANK

ODD FIELDEVEN FIELD

H

V

F

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285

ODD FIELD EVEN FIELD


H

V

F

Figure 39. Timing Mode 0, NTSC Master Mode

ADV7194

–23–REV. A

622 623 624 625 1 2 3 4 5 6 7 21 22 23


H

V

F ODD FIELDEVEN FIELD

309 310 311 312 314 315 316 317 318 319 320 334 335 336313


H

V

F ODD FIELD EVEN FIELD

Figure 40. Timing Mode 0, PAL Master Mode

ANALOGVIDEO

H

F

V

Figure 41. Timing Mode 0 Data Transitions, Master Mode

ADV7194

–24– REV. A

Mode 1: Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7194 accepts Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC islow indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7194automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 42 (NTSC) and Figure 43 (PAL).

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285



HSYNC

BLANK

FIELD

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22


ODD FIELDEVEN FIELD

HSYNC

BLANK

FIELD

Figure 42. Timing Mode 1, NTSC

622 623 624 625 1 2 3 4 5 6 7 21 22 23

DISPLAY VERTICAL BLANK

ODD FIELDEVEN FIELD

HSYNC

BLANK

FIELD

DISPLAY

309 310 311 312 313 314 315 316 317 318 319 334 335 336320



HSYNC

BLANK

FIELD

DISPLAY

Figure 43. Timing Mode 1, PAL

ADV7194

–25–REV. A

Mode 1: Master Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7194 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input whenHSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled theADV7194 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge follow-ing the timing signal transitions. Mode 1 is illustrated in Figure 42 (NTSC) and Figure 43 (PAL). Figure 44 illustrates the HSYNC,BLANK and FIELD for an odd-or-even field transition relative to the pixel data.

FIELD

PIXELDATA

PAL = 12 � CLOCK/2NTSC = 16 � CLOCK/2

Cb Y Cr Y

HSYNC

BLANK


Figure 44. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode the ADV7194 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNCinputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. TheBLANK signal is optional. When the BLANK input is disabled, the ADV7194 automatically blanks all normally blank lines as perCCIR-624. Mode 2 is illustrated in Figure 45 (NTSC) and Figure 46 (PAL).

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22


ODD FIELDEVEN FIELD

HSYNC

BLANK

VSYNC

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285



HSYNC

BLANK

VSYNC


ADV7194

–26– REV. A

622 623 624 625 1 2 3 4 5 6 7 21 22 23


ODD FIELDEVEN FIELD

HSYNC

BLANK

VSYNC

DISPLAY

309 310 311 312 313 314 315 316 317 318 319 334 335 336320



HSYNC

BLANK

DISPLAY

VSYNC


Mode 2: Master Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode the ADV7194 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC andVSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an EvenField. The BLANK signal is optional. When the BLANK input is disabled, the ADV7194 automatically blanks all normally blank lines asper CCIR-624. Mode 2 is illustrated in Figure 45 (NTSC) and Figure 46 (PAL). Figure 47 illustrates the HSYNC, BLANK andVSYNC for an even-to-odd field transition relative to the pixel data. Figure 48 illustrates the HSYNC, BLANK and VSYNC foran odd-to-even field transition relative to the pixel data.


HSYNC

VSYNC

BLANK

PIXELDATA

PAL = 132 � CLOCK/2 NTSC = 122 � CLOCK/2

Cb Y Cr Y

Figure 47. Timing Mode 2, Even-to-Odd Field Transition Master/Slave

PAL = 864 � CLOCK/2 NTSC = 858 � CLOCK/2


HSYNC

VSYNC

BLANK

PIXELDATA


Cb Y Cr Y Cb

Figure 48. Timing Mode 2, Odd-to-Even Field Transition Master/Slave

ADV7194

–27–REV. A

Mode 3: Master/Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)In this mode the ADV7194 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD inputwhen HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is dis-abled the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 49 (NTSC) andFigure 50 (PAL).

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285



HSYNC

BLANK

FIELD

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22


ODD FIELDEVEN FIELD

HSYNC

BLANK

FIELD


622 623 624 625 1 2 3 4 5 6 7 21 22 23


ODD FIELDEVEN FIELD

HSYNC

BLANK

FIELD

DISPLAY

309 310 311 312 313 314 315 316 317 318 319 334 335 336320


ODD FIELDEVEN FIELD

HSYNC

BLANK

FIELD

DISPLAY


ADV7194

–28– REV. A

MPU PORT DESCRIPTIONThe ADV7194 supports a 2-wire serial (I2C-compatible) micro-processor bus driving multiple peripherals. Two inputs SerialData (SDA) and Serial Clock (SCL) carry information betweenany device connected to the bus. Each slave device is recog-nized by a unique address. The ADV7194 has four possible slaveaddresses for both read and write operations. These are uniqueaddresses for each device and are illustrated in Figure 51 andFigure 53. The LSB sets either a read or write operation. LogicLevel 1 corresponds to a read operation while Logic Level 0corresponds to a write operation. A1 is set by setting the ALSBpin of the ADV7194 to Logic Level 0 or Logic Level 1. WhenALSB is set to 0, there is greater input bandwidth on the I2Clines, which allows high speed data transfers on this bus. WhenALSB is set to 1, there is reduced input bandwidth on the I2Clines, which means that pulses of less than 50 ns will not passinto the I2C internal controller. This mode is recommended fornoisy systems.

0 X1 0 1 0 1 A1

ADDRESSCONTROL

SETUP BYALSB

READ/WRITECONTROL

0 WRITE1 READ

Figure 51. Slave Address

To control the various devices on the bus the following protocolmust be followed. First the master initiates a data transfer byestablishing a start condition, defined by a high to low transition onSDA while SCL remains high. This indicates that an address/datastream will follow. All peripherals respond to the start conditionand shift the next eight bits (7-bit address + R/W bit). The bits aretransferred from MSB down to LSB. The peripheral that recog-nizes the transmitted address responds by pulling the data linelow during the ninth clock pulse. This is known as an acknowledgebit. All other devices withdraw from the bus at this point andmaintain an idle condition. The idle condition is where the devicemonitors the SDA and SCL lines waiting for the start condi-tion and the correct transmitted address. The R/W bit determinesthe direction of the data.

A Logic 0 on the LSB of the first byte means that the masterwill write information to the peripheral. A Logic 1 on the LSBof the first byte means that the master will read informationfrom the peripheral.

DATA A(S)S SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 0 LSB = 1

DATA A(S) P

S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) A(M)DATA P

WRITESEQUENCE

READSEQUENCE

A(S) = NO ACKNOWLEDGE BY SLAVEA(M) = NO ACKNOWLEDGE BY MASTER

A(S) = ACKNOWLEDGE BY SLAVEA(M) = ACKNOWLEDGE BY MASTER

S = START BITP = STOP BIT

Figure 53. Write and Read Sequences

The ADV7194 acts as a standard slave device on the bus. The dataon the SDA pin is 8 bits long supporting the 7-bit addresses plusthe R/W bit. It interprets the first byte as the device address andthe second byte as the starting subaddress. The subaddressesautoincrement allowing data to be written to or read from thestarting subaddress. A data transfer is always terminated by astop condition. The user can also access any unique subaddressregister on a one by one basis without having to update all theregisters. There is one exception. The Subcarrier FrequencyRegisters should be updated in sequence, starting with Sub-carrier Frequency Register 0. The autoincrement function shouldbe then used to increment and access Subcarrier FrequencyRegisters 1, 2, and 3. The Subcarrier Frequency Registersshould not be accessed independently.

Stop and start conditions can be detected at any stage duringthe data transfer. If these conditions are asserted out of sequencewith normal read and write operations, then these cause animmediate jump to the idle condition. During a given SCL highperiod the user should only issue one start condition, one stopcondition or a single stop condition followed by a single startcondition. If an invalid subaddress is issued by the user, theADV7194 will not issue an acknowledge and will return to theidle condition. If in autoincrement mode, the user exceeds thehighest subaddress then the following action will be taken:

1. In Read Mode, the highest subaddress register contentswill continue to be output until the master device issuesa no-acknowledge. This indicates the end of a read. Ano-acknowledge condition is where the SDA line is notpulled low on the ninth pulse.

2. In Write Mode, the data for the invalid byte will be not beloaded into any subaddress register, a no-acknowledge willbe issued by the ADV7194 and the part will return to theidle condition.

8 9 1 7 8 9 1 7 8 9 PS

START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP

SDATA

SCLOCK 1 7

Figure 52. Bus Data Transfer

Figure 52 illustrates an example of data transfer for a readsequence and the start and stop conditions.

Figure 53 shows bus write and read sequences.

ADV7194

–29–REV. A

REGISTER ACCESSESThe MPU can write to or read from all of the registers of theADV7194 except the Subaddress Registers which are write onlyregisters. The Subaddress Register determines which register thenext read or write operation accesses. All communications withthe part through the bus start with an access to the SubaddressRegister. Then a read/write operation is performed from/to thetarget address which then increments to the next address untila stop command on the bus is performed.

REGISTER PROGRAMMINGThe following section describes each register. All registers canbe read from as well as written to.

ADDRESS SR6 SR5 SR4 SR3 SR2 SR1 SR000H 0 0 0 0 0 0 0 MODE REGISTER 001H 0 0 0 0 0 0 1 MODE REGISTER 102H 0 0 0 0 0 1 0 MODE REGISTER 203H 0 0 0 0 0 1 1 MODE REGISTER 304H 0 0 0 0 1 0 0 MODE REGISTER 405H 0 0 0 0 1 0 1 MODE REGISTER 506H 0 0 0 0 1 1 0 MODE REGISTER 607H 0 0 0 0 1 1 1 MODE REGISTER 708H 0 0 0 1 0 0 0 MODE REGISTER 809H 0 0 0 1 0 0 1 MODE REGISTER 90AH 0 0 0 1 0 1 0 TIMING REGISTER 00BH 0 0 0 1 0 1 1 TIMING REGISTER 10CH 0 0 0 1 1 0 0 SUBCARRIER FREQUENCY REGISTER 00DH 0 0 0 1 1 0 1 SUBCARRIER FREQUENCY REGISTER 10EH 0 0 0 1 1 1 0 SUBCARRIER FREQUENCY REGISTER 20FH 0 0 0 1 1 1 1 SUBCARRIER FREQUENCY REGISTER 310H 0 0 1 0 0 0 0 SUBCARRIER PHASE REGISTER11H 0 0 1 0 0 0 1 CLOSED CAPTIONING EXTENDED DATA BYTE 012H 0 0 1 0 0 1 0 CLOSED CAPTIONING EXTENDED DATA BYTE 113H 0 0 1 0 0 1 1 CLOSED CAPTIONING DATA BYTE 014H 0 0 1 0 1 0 0 CLOSED CAPTIONING DATA BYTE 115H 0 0 1 0 1 0 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 016H 0 0 1 0 1 1 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 117H 0 0 1 0 1 1 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 218H 0 0 1 1 0 0 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 319H 0 0 1 1 0 0 1 CGMS/WSS 01AH 0 0 1 1 0 1 0 CGMS/WSS 11BH 0 0 1 1 0 1 1 CGMS/WSS 21CH 0 0 1 1 1 0 0 TELETEXT REQUEST CONTROL REGISTER1DH 0 0 1 1 1 0 1 CONTRAST CONTROL REGISTER1EH 0 0 1 1 1 1 0 U SCALE REGISTER1FH 0 0 1 1 1 1 1 V SCALE REGISTER20H 0 1 0 0 0 0 0 HUE ADJUST REGISTER21H 0 1 0 0 0 0 1 BRIGHTNESS CONTROL REGISTER22H 0 1 0 0 0 1 0 SHARPNESS CONTROL REGISTER23H 0 1 0 0 0 1 1 DNR REGISTER 024H 0 1 0 0 1 0 0 DNR REGISTER 125H 0 1 0 0 1 0 1 DNR REGISTER 226H 0 1 0 0 1 1 0 GAMMA CORRECTION REGISTER 027H 0 1 0 0 1 1 1 GAMMA CORRECTION REGISTER 128H 0 1 0 1 0 0 0 GAMMA CORRECTION REGISTER 229H 0 1 0 1 0 0 1 GAMMA CORRECTION REGISTER 32AH 0 1 0 1 0 1 0 GAMMA CORRECTION REGISTER 42BH 0 1 0 1 0 1 1 GAMMA CORRECTION REGISTER 52CH 0 1 0 1 1 0 0 GAMMA CORRECTION REGISTER 62DH 0 1 0 1 1 0 1 GAMMA CORRECTION REGISTER 72EH 0 1 0 1 1 1 0 GAMMA CORRECTION REGISTER 82FH 0 1 0 1 1 1 1 GAMMA CORRECTION REGISTER 930H 0 1 1 0 0 0 0 GAMMA CORRECTION REGISTER 1031H 0 1 1 0 0 0 1 GAMMA CORRECTION REGISTER 1132H 0 1 1 0 0 1 0 GAMMA CORRECTION REGISTER 1233H 0 1 1 0 0 1 1 GAMMA CORRECTION REGISTER 1334H 0 1 1 0 1 0 0 BRIGHTNESS DETECT REGISTER35H 0 1 1 0 1 0 1 OUTPUT CLOCK REGISTER36H 0 1 1 0 1 1 0 RESERVED37H 0 1 1 0 1 1 1 RESERVED38H 0 1 1 1 0 0 0 RESERVED39H 0 1 1 1 0 0 1 RESERVED3AH 0 1 1 1 0 1 0 RESERVED3BH 0 1 1 1 0 1 1 RESERVED3CH 0 1 1 1 1 0 0 RESERVED3DH 0 1 1 1 1 0 1 RESERVED3EH 0 1 1 1 1 1 0 RESERVED3FH 1 1 1 1 1 1 1 RESERVED40H 1 0 0 0 0 0 0 RESERVED41H 1 0 0 0 0 0 1 RESERVED42H 1 0 0 0 0 1 0 RESERVED43H 1 0 0 0 0 1 1 RESERVED44H 1 0 0 0 1 0 0 RESERVED45H 1 0 0 0 1 0 1 RESERVED46H 1 0 0 0 1 1 0 RESERVED47H 1 0 0 1 1 1 1 RESERVED48H 1 0 0 1 0 1 0 RESERVED49H 1 0 0 1 0 0 1 RESERVED4AH 1 0 0 1 0 0 0 RESERVED4BH 1 0 0 1 0 1 1 RESERVED

ADV7194 SUBADDRESS REGISTER

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR7ZERO SHOULDBE WRITTEN

HERE

Figure 54. Subaddress Register for the ADV7194

Subaddress Register (SR7–SR0)The Communications Register is an 8-bit write-only register. Afterthe part has been accessed over the bus and a read/write operationis selected, the subaddress is set up. The Subaddress Registerdetermines to/from which register the operation takes place.

Figure 54 shows the various operations under the control of theSubaddress Register 0 should always be written to SR7.

Register Select (SR6–SR0)These bits are set up to point to the required starting address.

ADV7194

–30– REV. A

MODE REGISTER 0MR0 (MR07–MR00)(Address (SR4–SR0) = 00H)Figure 55 shows the various operations under the control ofMode Register 0.

MR0 BIT DESCRIPTIONOutput Video Standard Selection (MR00–MR01)These bits are used to setup the encoder mode. The ADV7194can be set up to output NTSC, PAL (B, D, G, H, I), or PAL Nstandard video.

Luminance Filter Select (MR02–MR04)These bits specify which luma filter is to be selected. The filterselection is made independent of whether PAL or NTSC isselected.

Chrominance Filter Select (MR05–MR07)These bits select the chrominance filter. A low-pass filter can beselected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF orQCIF filters.

MODE REGISTER 1MR1 (MR17–MR10)(Address (SR4–SR0) = 01H)Figure 56 shows the various operations under the control ofMode Register 1.

MR1 BIT DESCRIPTIONDAC Control (MR10–MR15)Bits MR15–MR10 can be used to power down the DACs. This areused to reduce the power consumption of the ADV7194 or if anyof the DACs are not required in the application.

4� Oversampling Control (MR16)To enable 4× Oversampling this bit has to be set to 1. Whenenabled, the data is output at a frequency of 54 MHz.

Note that PLL Enable Control has to be enabled (MR61 = 0) in4× Oversampling mode.Reserved (MR17)A Logical 0 must be written to this bit.

MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00

CHROMA FILTER SELECT

0 0 0 1.3 MHz LOW-PASS FILTER0 0 1 0.65 MHz LOW-PASS FILTER0 1 0 1.0 MHz LOW-PASS FILTER0 1 1 2.0 MHz LOW-PASS FILTER1 0 0 RESERVED1 0 1 CIF1 1 0 QCIF1 1 1 3.0 MHz LOW-PASS FILTER

MR07 MR06 MR05

MR04 MR03 MR02

LUMA FILTER SELECT

0 0 0 LOW-PASS FILTER (NTSC)0 0 1 LOW-PASS FILTER (PAL)0 1 0 NOTCH FILTER (NTSC)0 1 1 NOTCH FILTER (PAL)1 0 0 EXTENDED MODE1 0 1 CIF1 1 0 QCIF1 1 1 RESERVED

MR01 MR00

0 0 NTSC0 1 PAL (B, D, G, H, I)1 0 RESERVED1 1 PAL (N)

OUTPUT VIDEOSTANDARD SELECTION

Figure 55. Mode Register 0, MR0


DAC ADAC CONTROL

0 POWER-DOWN1 NORMAL

MR15

DAC CDAC CONTROL


MR13

DAC EDAC CONTROL


MR11

4� OVERSAMPLINGCONTROL

0 2� OVERSAMPLING1 4� OVERSAMPLING

MR16

DAC BDAC CONTROL


MR14

DAC DDAC CONTROL


MR12

DAC FDAC CONTROL


MR10

MR17ZERO MUSTBE WRITTENTO THIS BIT


ADV7194

–31–REV. A

MODE REGISTER 2MR2 (MR27–MR20)(Address (SR4–SR0) = 02H)Mode Register 2 is an 8-bit-wide register.

Figure 57 shows the various operations under the control of ModeRegister 2.

MR2 BIT DESCRIPTIONRGB/YUV Control (MR20)This bit enables the output from the DACs to be set to YUV orRGB output video standard.

DAC Output Control (MR21)This bit controls the output from DACs A, B, and C. When thisbit is set to 1, Composite, Luma and Chroma Signals are outputfrom DACs A, B and C (respectively). When this bit is set to 0,RGB or YUV may be output from these DACs.

SCART Enable Control (MR22)This bit is used to switch the DAC outputs from SCART to aEUROSCART configuration. A complete table of all DAC out-put configurations is shown below.

Pedestal Control (MR23)This bit specifies whether a pedestal is to be generated on theNTSC composite video signal. This bit is invalid when the deviceis configured in PAL mode.

Square Pixel Control (MR24)This bit is used to setup square pixel mode. This is available inSlave Mode only. For NTSC, a 24.54 MHz clock must be sup-plied. For PAL, a 29.5 MHz clock must be supplied. Squarepixel operation is not available in 4× Oversampling mode.

Standard I2C Control (MR25)This bit controls the video standard used by the ADV7194.When this bit is set to 1 the video standard is as programmed inMode Register 0 (Output Video Standard Selection). When it isset to 0, the ADV7194 is forced into the standard selected bythe NTSC_PAL pin. When NTSC_PAL is low the standard isNTSC, when the NTSC_PAL pin is high, the standard is PAL.

Pixel Data Valid Control (MR26)After resetting the device this bit has the value 0 and the pixeldata input to the encoder is blanked such that a black screen isoutput from the DACs. The ADV7194 will be set to MasterMode timing. When this bit is set to 1 by the user (via the I2C),pixel data passes to the pins and the encoder reverts to the tim-ing mode defined by Timing Mode Register 0.

Sleep Mode Control (MR27)When this bit is set (1), Sleep Mode is enabled. With this modeenabled the ADV7194 current consumption is reduced to typicallyless than 0.1 mA. The I2C registers can be written to and readfrom when the ADV7194 is in Sleep Mode.

When the device is in Sleep Mode and 0 is written to MR27, theADV7194 will come out of Sleep Mode and resume normaloperation. Also, if a RESET is applied during Sleep Mode theADV7194 will come out of Sleep Mode and resume normaloperation.

For this to operate, Power up in Sleep Mode control has to beenabled (MR60 is set to a Logic 1), otherwise Sleep Mode iscontrolled by the PAL_NTSC and SCRESET/RTC/TR pins.


RGB/YUVCONTROL

0 RGB OUTPUT1 YUV OUTPUT

MR20

SCART ENABLECONTROL

0 DISABLE1 ENABLE

MR22

SQUARE PIXELCONTROL

0 DISABLE1 ENABLE

MR24

PIXEL DATAVALID CONTROL

0 DISABLE1 ENABLE

MR26

DAC OUTPUTCONTROL

0 RGB/YUV/COMP1 COMP/LUMA/CHROMA

MR21

PEDESTALCONTROL

0 PEDESTAL OFF1 PEDESTAL ON

MR23

STANDARD I2CCONTROL

0 DISABLE1 ENABLE

MR25

SLEEP MODECONTROL

0 DISABLE1 ENABLE

MR27


Table V. DAC Output Configuration

MR22 MR21 MR20 DAC A DAC B DAC C DAC D DAC E DAC F

0 0 0 G (Y) B (Pb) R (Pr) CVBS LUMA CHROMA0 0 1 Y (Y) U (Pb) V (Pr) CVBS LUMA CHROMA0 1 0 CVBS LUMA CHROMA G (Y) B (Pb) R (Pr)0 1 1 CVBS LUMA CHROMA Y (Y) U (Pb) V (Pr)1 0 0 CVBS B (Pb) R (Pr) G (Y) LUMA CHROMA1 0 1 CVBS U (Pb) V (Pr) Y (Y) LUMA CHROMA1 1 0 CVBS LUMA CHROMA G (Y) B (Pb) R (Pr)1 1 1 CVBS LUMA CHROMA Y (Y) U (Pb) V (Pr)

NOTEIn Progressive Scan Mode (MR80, 1) the DAC output configuration is stated in the brackets.

ADV7194

–32– REV. A

MODE REGISTER 3MR3 (MR37–MR30)(Address (SR4–SR0) = 03H)Mode Register 3 is an 8-bit-wide register. Figure 58 showsthe various operations under the control of Mode Register 3.

MR3 BIT DESCRIPTIONRevision Code (MR30–MR31)This bit is read only and indicates the revision of the device.

VBI_Open (MR32)This bit determines whether or not data in the Vertical BlankingInterval (VBI) is output to the analog outputs or blanked. Notethat this condition is also valid in Timing Slave Mode 0. Forfurther information see Vertical Blanking section.

Teletext Enable (MR33)This bit must be set to 1 to enable teletext data insertion onthe TTX pin. Note: TTX functionality is shared with VSO andCLAMP on Pin 62. CLAMP/VSO Select (MR77) and TTXInput/CLAMP/VSO Output (MR76) have to be set accordingly.

Teletext Bit Request Mode Control (MR34)This bit enables switching of the teletext request signal from acontinuous high signal (MR34 = 0) to a bitwise request signal(MR34 = 1).

Closed Captioning Field

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