programmable peripheral - icbase

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Abstract

Programmable PeripheralApplication Note 029Interfacing PSD4XX/5XX To MicrocontrollersBy Ravi Kumar

This application note is intended to give the reader a general guideline on howto interface PSD4XX/5XX FieldProgrammable Microcontroller Peripheralsto specific microcontrollers. RelevantPSDabel files, bus simulation results andthe PSD bus configurations of the interfaceexamples are included in this applicationnote.

The PSD4XX/5XX series provides the user with an innovative architecture forembedded applications. A PSD5XX devicehas the following features:

❏ Programmable bus interface, "no glue" logic interface to microcontrollers.

❏ Three ZPLDs (Zero Power PLDs) with atotal of 61 inputs, 140 product terms outputs, 30 macrocells and 24 I/O pins.

❏ Forty individually programmable I/O pins that are divided into 5 ports.

❏ Four 16-bit Counter/Timers that performpulse, waveform, time capture, event counting and watchdog functions.

❏ Eight input priority encoded Interrupt Controller. Four Interrupts are generated internally by Counter/Timers and the other four can be user defined through the ZPLD.

❏ 4-bit Page Register.

❏ Up to 1 Mbit Reprogrammable EPROM,consists of four 256 Kbit blocks.

❏ 16 Kbit of SRAM with battery backup mode.

❏ Power management unit with automatic power down and sleep modes.

❏ Security mode for code protection.

Figure 1 is a top level diagram ofPSD4XX/5XX.

PSD4XX/5XXArchitecture

At the core of the PSD4XX/5XX are 3 dedicated ZPLDs:

❏ DPLD: The Decoding ZPLD.Its main function is to perform address decoding for the internal I/O ports, EPROM, SRAM and periheral mode of Port A.

❏ GPLD: The General Purpose ZPLD.The user can implement state machinesand other logic functions in the GPLD. It can also generare chip selects for external memories and peripheral devices.

❏ PPLD: The Peripheral ZPLD.It provides additional control for the operation of the Counter/Timer Units and the Interrupt Controller. The PPLD is available only in the PSD5XX series.

The microcontrollers covered in this application note are:

❏ 80C31 ❏ Z8/Z80

❏ 68HC11 ❏ 80C166

❏ 80C196 ❏ ST9026

❏ 68302 ❏ NEURON® 3150™

❏ 68332

Return to Main Menu

PSD4XX/5XX – Application Note 029

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The Bus InterfaceOf The PSD4XX/5XX

The PSD4XX/5XX have a user configurable bus interface. This interface can be configuredto allow the PSD4XX/5XX to interface directly to most microcontrollers with "no glue" logic.

There are only five bus control pins on the PSD4XX/5XX. Each pin has multiple functionsas shown in Table 1. For example, the "RD" pin can act as a "RD", or "E", or DS, or LDS,depending on the microcontroller bus interface. Please note the "RD" and "WR" pins arededicated bus pins, but PE0 and PE1 are two general purpose I/O pins on port E. If the businterface does not require these two pins, they can be configured to perform any of theother Port E functions.

The selection of these pin functions is implemented in the PSDconfiguration menu insidethe PSDsoft.

Pin Pin Pin Pin Pin Pin

Name Function Function Function Function Function1 2 3 4 5

RD RD E DS LDS

WR WR R/W WRL

PE0 BHE PSEN WRH UDS SIZ0

PE1 ALE

AD0 A0 BLE

Table 1. Alternate Pin Functions

Multiplexed Data Bus Bus Control Signals MicrocontrollersWidthMux 8 WR, RD, PSEN 80C31 Family

Mux8/16 R/W, E, BHE 68HC11 Family

Non-Mux

Mux8/16 WR, RD, BHE

80196/80186 Family80C166 Family

Mux 16 WRL, RD, WRH 80196SP

Mux 8 R/W, DS ST9 Family

Non-Mux 16 R/W, LDS, UDS 68302

Non-Mux 8/16 R/W, DS, SIZ0 683XX Family

Non-Mux 8/16 R/W, DS, BHE, BLE 68330

Table 2. Typical Microcontroller Bus Types

The multiple functions of the PSD bus pins allow the PSD4XX/5XX to support a largenumber of microcontrollers. Table 2 shows some of these microcontroller families, the bustype and control signals associated with the microcontrollers.


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PSD4XX/5XX Interface To a Multiplexed BusFigure 2 shows a typical connection to a microcontroller with a multiplexed bus. The ADIO port of the PSD4XX/5XX is connected directly to the microcontroller address/data bus. Foran 8-bit bus, the low byte of the ADIO port is connected to AD0 – AD7 and the high byte toA8 – A15 of the microcontroller. For 16-bit bus, the ADIO port connects to AD0-AD15. The address lines are latched internally by the ALE signal. In a read bus cycle, data isdriven out through the ADIO Port transceivers after the specified access time. The ADIOPort is in tristate mode if none of the internal PSD resources are selected.

PSD4XX/5XXInterface To aMultiplexed Bus

Optional FeaturesThe PSD4XX/5XX provides two optional features to add flexibility to the Bus Interface:

1. Address In Port A can be configured as high order address (A16-A23) inputs to the ZPLD for DPLD or other decoding. Any other signals which also are included in the DPLD chip select equations must come from Port A.

Port C & D can be configured as address input ports for the ZPLD. These inputs should not be used for EPROM decoding.

2. Address OutFor multiplexed bus only. Latched address lines A0-A15 are available on Port A, B, C or D. The latched address can be used as address to external memory or I/O devices.

PSD4XX/5XX Interface To a Non-Multiplexed BusFigure 3 shows a PSD4XX/5XX interfacing to a microcontroller with a non-multiplexed address/data bus. The address bus is connected to the ADIO Port, and the data bus isconnected to Port C and/or Port D, depending on the bus width. If the microcontroller hasan address strobe signal, the user has an option to latch or not to latch the address by theALE/AS signal internally in the PSD.


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Figure 2. Bus Interface – Multiplexed BusBus InterfaceOf The PSD4XX/5XX(Cont.)


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Bus TimingConsideration

Access Time CalculationAccess time of PSD4XX/5XX (EPROM or SRAM ) is the time measured when the address is valid on the Microcontroller address bus to the time the data is available on the data bus.This access time (tAVQA, see Figure 4) includes any delay on internal address latches andDPLD decoding.

EPROM CMiser Option The PSD4XX/5XX devices have a power management unit which enables the user to configure the power consumption level. The EPROM power is controlled by theEPROM_CMiser bit (bit 3) in the PMMR0 Register. If this bit is set to “1”, the EPROMpower consumption is lower but the access time is increased by 10 nanoseconds.

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Figure 4. Read Timing


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T1 T2

Figure 5. Reset Timing Requirement

Reset timingFigure 5 shows the reset signal timing requirement of the PSD4XX/5XX devices. The active low (T1) has a minimum of 300 ns. After the rising edge of RESET, the PSD4XX/5XXremains inactive during T2 (minimum of 300 ns).

RST_OUT Signal (Optional)The reset circuit of the PSD4XX/5XX has a Schmitt trigger that senses the RESET line logic level. The PSD4XX/5XX is able to output a RESET signal (referred to as RST_OUT inthis application note) through the GPLD to the microcontroller based on its own reset input.The RST_OUT signal is not recommended in 68HC11 based design.

Bus TimingConsideration(Cont.)

The PSD4XX/5XX is able to support, but is not limited to, the following list of microcontrollers:

❏ 16-Bit Multiplexed Mode ❏ 8-Bit Non-multiplexed ModeIntel 8096, 80C196, 80C186 families. Zilog Z80 familyNational HPC16000 family. Motorola 68008/6809 family.Siemens 80C166 families. Echelon 3150TM.

❏ 8-Bit Multiplexed Mode ❏ 16-Bit Non-multiplexed ModeIntel/Philips 80C51/52, 80C31/32, Motorola 68302, 68331, 68302, 68HC16

80C451 families. families.Motorola/Toshiba 68HC11 families.Intel 80C188 and 80C198 families.SGS-Thomson ST9 families.

Microcontrollers Supported


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Select The BusInterface InPSDconfiguration

The main screen of the PSDconfiguration is shown in Figure 6. Click on the Configurationmenu to get to the next screen in Figure 7 where you specify the data bus width andwhether the bus is a multiplexed or non-multiplexed bus.

In the next window, as shown in Figure 8, specify the bus control signals of your microcontroller. The polarity of ALE is defined as high if the falling edge of the signal isused to latch the address. In Figure 8, the signals specified are for the 80C31 family ofmicrocontrollers. Please note the question “Use the read signal to access the EPROM” isapplicable only to 80C31 type controllers.

This completes the specification of the bus interface. The PSDcompiler will generate the necessary fuse map for the specified bus interface in the .obj file which is to beprogrammed into the PSD4XX/5XX.

Figure 6.

How To ConfigureThe PSD BusInterface

The design, configuration and programming of the PSD4XX/5XX is created in the PSDsoftDevelopment Software Tools. The PSDsoft consists of five submodules:

❏ PSDabelTo generate a PLD-ABEL description file which defines the functions of the DPLD (decoder), GPLD and the PPLD (PSD5XX).

❏ PSDconfigurationTo configure the bus interface and other I/O functions.

❏ PSDcompilerTo fit the functions defined in the ABEL file to the PSD and map program codes to the PSD EPROM

❏ PSDsimulatorChip level simulation based on the ABEL, configuration and stimulus files.

❏ PSDprogrammerTo program the chip with the .obj file generated in the PSDcompiler.

There are two places in the PSDsoft where you specify and define the bus interface for yourapplication:

1. In PSDabelDefine the DPLD equations (chip select equations) for EPROM, SRAM and I/O.

2. In PSDconfiguration:Select the bus type/interface for the PSD such as data bus width, control signals, etc.


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Figure 8.

Select The BusInterface InPSDconfiguration(Cont.)

Figure 7.


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Definition Of The DPLDEquations In TheABEL FIle

The DPLD is the address decoder for the PSD. It generates the chip select signal for all theinternal PSD devices. These signals include:

❏ ES0 – ES3 EPROM chip selects (4 blocks)

❏ RS0SRAM chip select

❏ CSIOPPort select, Counter/Timer, Interrupt Controller

❏ PSEL0-1Port A Peripheral Mode selects

The chip select equations normally consist of address inputs and Page Register outputs.You define only the chip selects which you need in the ABEL file. For example, you don’thave to define ES3 if the fourth EPROM block is not used. The following is an ABELexample file in which the address lines a0 to a18 of the microcontroller, and pgr0-3 of thePage Register outputs are used as inputs to the DPLD. The memory map of the exampleis shown in Table 3.

Device Memory Space Memory Page

EPROM, Block 0 0000 – 7FFF Page 0


EPROM, Block 2 4800 – 4FFF Any page

SRAM 8000 - 87FF Any page

I/O Devices C000 - CFFF Any page

Table 3. System Memory Map


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The example ABEL file shows only the DPLD portion of the equations (GPLD equations are not included here). A typical ABEL file consists of a module name and/or title; a declarations area where the input/output signals are defined ; and an equations area where the logic equations, and the state machines are defined. An optional test_vectorsarea is used for the logic simulation.

module dpld title ‘DPLD chip select equations source file’;

declarations

“Input signals

“Address lines, using reserved names.

a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

a18,a17,a16 pin ; “high order address“input for fitting

pgr3,pgr2,pgr1,pgr0 pin; “page register embedded inputs

“Output signals

csiop,rs0,es0,es1,es2 node; “DPLD output chip selects

“DEFINITIONS

page = [pgr3,pgr2,pgr1,pgr0];X = .x. ; “ Don’t careAddress =[a18,a17,a16,a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,a0];

equations

“DPLD EQUATIONScsiop = (Address >= ^h0C000) & (Address <= ^h0C0FF) ; “Chip Select 256 byte blockrs0 = (Address <= ^h087FF) & (Address >= ^h08000); “SRAM 2k blockes0 = (Address <= ^h07FFF) & (page == 0); “EPROM 32k block only at page 0es1 = (Address <= ^h07FFF) & (page == 1); “EPROM 32k block only at page 1es2 = (Address <= ^h4FFFF) & (Address >= ^h48000); ”EPROM 32k block, always visible

END dpld

Definition Of The DPLDEquations In TheABEL FIle (Cont.)


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Bus Interface Examples

This section demonstrates the interface between the PSD4XX/5XX and some microcontrollers. The following documents are included in each of the microcontroller interface examples:

❏ The Bus Configuration (PSDconfiguration) screens captured from the PSDsoft design tool.

❏ The ABEL file which shows only the declaration and DPLD equations of the targeted microcontroller.

❏ The logic interface schematic showing the connection between the PSD4XX/5XX and the microcontroller.

❏ The bus interface simulation screen captured from the SILOSIII Simulator. The Simulator provides a full function, chip level simulation of the PSD4XX/5XX for design verification. The stimulus input file to the Simulator is written in Verilog . The results of the simulation is shown in the SDA ( Silos Data Analyzer) window where user defined signals or PSD internal nodes can be traced/displayed.

In the following examples, only the bus interface function of the PSD4XX/5XX is simulated.This includes read bus cycles to the PSD EPROM and SRAM, and write cycles to theSRAM. The EPROM blocks have pre-filled data per Table 4 as the default configuration.The data should give you an indication if the PSD is enabling the right block and byte of theEPROM.

Although the SDA can display many PSD signals, only bus related signals are shown in theexamples in this Application Note. Please note the signal names displayed in SDA do notindicate the signal’s polarity. As a rule, internal PSD signals all have active high polarity.The bus control signals have the same polarity as defined by the individual microcontroller. The displayed signals include:

❏ Control SignalsSuch as RD, WR, DS, ALE, PSEN, etc.

❏ Address/Data BusADIOH and ADIOL (high and low byte of microcontroller address/data bus)

❏ Data BusDATAH and DATAL (high and low byte of data bus, for non-mux bus only)

❏ Chip SelectsChip select signals to EPROM (es0 – es3) and SRAM (rs0).

EPROM Block Odd Byte Even Byte

Block0 (ES0) 01h 23h

Block1 (ES1) 45h 67h

Block2 (ES2) 89h abh

Block3 (ES3) cdh efh

Table 4.


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Interfacing To The 80C31Family OfMicrocontrollers

The 80C31 Bus80C31 is an 8-bit microcontroller with multiplexed address/data bus. It has the following bussignals:

❏ Address/Data Bus: AD7 – AD0

❏ Address Bus: A15 – A8

❏ Address Strobe: ALE

❏ Control Signals: RD, WR, PSEN

The PSEN signal is used to fetch code and RD is used to read data. This allows the 80C31to address up to 64KB of data memory and 64KB of program memory.

Two Modes of Memory AccessThe PSD4XX/5XX provides two modes of memory access: the Separated Space Mode and the Combined Space Mode (see Tables 5 and 5a). In Separated Mode, the PSENsignal can access the EPROM only and the RD signal can access the SRAM only. InCombined Space Mode, the EPROM can be accessed both by the PSEN and RD signal.The Combined Mode is for application where blocks of data or look up tables are requiredto reside in the EPROM.

The PSD4XX/5XX also provide an option for program code to be stored and executed fromthe SRAM. This option is enabled if the SRCODE bit in the VM Register is set to “1” duringrun time.

EPROM Access SRAM AccessRD Signal No Yes

PSEN Signal Yes Yes only if SRCODE = 1

Table 5. Separated Space Mode

EPROM Access SRAM AccessRD Signal Yes Yes

PSEN Signal Yes Yes only if SRCODE = 1

Table 5a. Combined Space Mode


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The 80C31 and PSD4XX/5XX Interface SchematicFigure 9 shows the 80C31 and PSD4XX/5XX interface schematic. The address/data bus and the bus control signals such as ALE, RD, WR, PSEN etc., are directly connected to thecorresponding pins of PSD4XX/5XX without any additional glue logic. Reset for the 80C31is generated from the RESET input to the PSD4XX/5XX and outputs on pin PE2 in thisexample. If clock input is not required, the CLKIN pin should always be grounded.

Reset Circuit RecommendationsThe following three reset circuits are recommended for use with 80C31 and PSD4XX/5XX based designs:

1. Input RESET signal into the PS4XX/5XX RESET pin. Based on the polarity of the RESET INPUT signal of the microcontroller interfaced to the PSD, generate RST_OUTthrough the GPLD and connect it to the microcontroller’s RESET INPUT pin (as illustrated in this application note.)

2. Use a Reset Chip such as Dallas Semiconductor’s DS1232, or Maxim’s Max 699. In case of Maxim’s Max 699, the Small Outline (SO) package should be used where the RESET output without inversion is also available. The inverted RESET signal goes to the PSD RESET input pin and the non-inverted RESET signal is connectd to the RESET input of 80C31.

3. Use two separate RC reset circuits: one which generates a high reset pulse to the 80C31 and the other one generates a low reset pulse to the PSD4XX/5XX. The RC constant of the PSD4XX/5XX reset circuit should be less than that of the 80C31 such that the PSD4XX/5XX reset signal has a shorter pulse and eliminates any race condition.

Interfacing To The 80C31Family OfMicrocontrollers(Cont.)


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Figure 9. 80C31 and PSD4XX/5XX Interface

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Specify The 80C31 Bus Interface In PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the 80C31 bus interface can be specified by selecting:

❏ Data Bus Width: X8

❏ Address/Data Mode: MX

❏ Polarity of ALE: High

❏ RD/WR Setting: WR, RD, PSEN

The PSDconfiguration also asks the question “Use the read signal to access the EPROM”.A click on “Yes” means you are selecting the Combined Space Mode and that both thePSEN or RD signal can access the EPROM. A “no” will select the Separated Space Modeand EPROM can be accessed by PSEN only.



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Define The DPLD/Decoding Function In The ABEL file The following is an example of defining the decoding function for the 80C31 based application. Please note the reset input to the 80C31, rst_out, is also included in the file.This file is applicable to both the Separated or Combined Space mode. The memory map isshown in Table 6.

module psen title ‘Design example of 80C31 DPLD source file’;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

“Output signals

csiop, rs0, es0, es1, es2 node; “DPLD output chip selects reset pin; “reset is declared here, used in rst_out generationrst_out pin 36;

“DEFINITIONS

X = .x. ; “ Don’t careAddress = [a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,a0];

equations

“DPLD EQUATIONS

csiop = (Address >= ^hC000) & (Address <= ^hC0FF); “CSIOP 256bytes blockrs0 = (Address <= ^h0000) & (Address >= ^h03FF); “SRAM 2KB block

es0 = (Address >= ^h0000) & (Address <= ^h3FFF); “1st EPROM block cs es1 = (Address >= ^h4000) & (Address <= ^h7FFF); “2nd EPROM block cs es2 = (Address >= ^h8000) & (Address <= ^hBFFF); “3rd EPROM block cs es3 = (Address >= ^hC000) & (Address <= ^hFFFF); “4th EPROM block cs

“GPLD EQUATIONS

rst_out = !reset; ”generate a high active reset to 80C31

END


Device Memory Space Memory PageEPROM, Block 0 0000 – 3FFF

EPROM, Block 1 4000 – 7FFF

EPROM, Block 2 8000 – BFFF

SRAM 0000 – 03FF

I/O Devices C000 – CFFF



4-91

Overlapping EPROM Space In Combined ModeIf your application requires the data and program to be resided in the EPROM (Combined Space Mode)and share the same address space, you need to modify the chip select equations . For example, if EPROM blocks 0-1 are used as code area and blocks 2-3 areused as data area, and that code and data space share the same address. In this case, theRD signal is used to separate the program and data space. The program space is enabledby an active PSEN, while the data space is enabled by an active RD. The RD signal now isconsidered as an address input and thus the access time of the EPROM starts from whenRD is valid, instead of when address is valid. The following is the chip select equations ofthe EPROM blocks.

es0 = (Address >= ^h0000) & (Address <= ^h3FFF) & RD ; “ program area es1 = (Address >= ^h4000) & (Address <= ^h7FFF) & RD ; “ program area

es2 = (Address >= ^h0000) & (Address <= ^h3FFF) & !RD; “data areaes3 = (Address >= ^h4000) & (Address <= ^h7FFF) & !RD; “data area

Simulation of 80C31 Bus Cycles With The PSD4XX/5XX Figure 10 shows the simulation of three 80C31 bus cycles. The first cycle is a code fetch from EPROM block 0 where code “23” is driven on to the ADIOL bus by the PSD. The next two cycles are SRAM write (data = 55h) and read cycles to location 0300h.

WSI Silos Data Analyzer

* 0 IZoom

Signal State 1189 1479 1769

D1

R0

D0

D0

FF

FF

D1

D1

D1

D1

D1

T1 = 1402 Level High Strength Driving

T2 = 1969 Level Low Strength Driving tDelta(T1,T2) = 567

00

00 23 FF 00 00 0055 55

FF 03 03

reset

rst_out

clkin

ale

adioh

adiol

es0

rs0

psen

wr

rd

Fi le Edi t Mode HelpSelect

80C31 With PSD4XX/5XX and External Memory In applications where large amount of SRAM is required, the PSD4XX/5XX is able to support an additional external SRAM. Figure 11 illustrates how an external SRAM (6164)can be interfaced to the PSD4XX/5XX and the 80C31 without additional hardware. Port C(or any other port) is configured to provide latched output addresses A0 – A7, and theSRAM chip select is generated from the GPLD.

Figure 10.



4-92

Figure 11. 80C31, PSD4XX/5XX and External SRAM Interface

EA

/VP

RE

SE

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0IN

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2.1

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9 31 9 12 13 14 15 1 2 3 4 5 6 7 8

18 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

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9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

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31

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E

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31 E

XT

ER

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M IN

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UT


4-93

Interfacing To The 68HC11Family OfMicrocontrollers

The 68HC11 family of microcontrollers have two types of bus interfaces. The standard HC11 has a multiplexed bus, while the 68HC11K4 has a non multiplexed bus. Theexample here covers both bus configurations.

The 68HC11 BusThe standard 68HC11 has a multiplexed bus where the lower address lines multiplex with an 8-bits data bus. It has the following bus signals:



❏ Address Strobe: AS

❏ Control Signals: E, R/W

68HC11 Interface to PSD4XX/5XXThe 68HC11 can interface directly to the PSD4XX/5XX without any additional glue logic. As shown in Figure 12, the E clock is connected to the “RD” pin, which is configured to actas the E clock input. The R/W signal is connected to the “WR” pin, which is configured toact as the R/W input.

The PSD4XX/5XX generates internal “write” and “read” signals based on the E clock andthe R/W inputs. If E clock is high and R/W is hgih, then PSD4XX/5XX sees it as a read buscycle and drives data on to the data bus through the ADIO Port if any of its internal devicesare selected.

XT

EX

RE

SE

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QX

IRQ

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0 29 39 41 40 8 7 6 17 18 19 20 22 21

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60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

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C11

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XX

CL

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F

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V CC

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V CC

17 16 15 14 13 12 11 10

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QIR

Q

CL

KIN

RE

SE

T

E R/W

RE

SE

T

HC

11 IN

TE

RF

AC

E


4-94

Figure 12. 68HC11 and PSD4XX/5XX Interface


4-95

Interfacing To The 68HC11Family OfMicrocontrollers(Cont.)

Specify the 68HC11 Multiplexed Bus Interface in PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the 68HC11 bus interface can be specified by selecting:




❏ RD/WR Setting: R/W, E


4-96

Define The DPLD/Decoding Function In The ABEL File The following is a an example of defining the decoding function for the 68HC11 based application. Table 7 shows the memory map implemented by the DPLD.




EPROM, Block 3 C000 – FFFF

SRAM 1000 – 13FF

I/O Devices 0000 – 00FF


module hc11 title ‘DPLD chip select equations source file ‘;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

“Output signalsas,rd_wr,e pin 37,29,41; “Motorola related ale and read/write signalscsiop, rs0, es1, es2, es3 node ; “DPLD output chip selects

“DEFINITIONS

X = .x. ; “ Don’t careAddress =[a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,a0];

equations

“DPLD EQUATIONS

csiop = (Address >= ^h0000) & (Address <= ^h00FF); “CSIOP 256bytes blockrs0 = (Address <= ^h1000) & (Address >= ^h13FF); “SRAM 2KB block

es1 = (Address >= ^h4000) & (Address <= ^h7FFF); “2nd EPROM block cs es2 = (Address >= ^h8000) & (Address <= ^hBFFF); “3rd EPROM block cs es3 = (Address >= ^hC000) & (Address <= ^hFFFF); “4th EPROM block cs

“The first EPROM block is not used and it is not required to define es0

END



4-97


Simulation of 68HC11 Bus Cycles With the PSD4XX/5XX Figure 13 shows the output of the 68HC11 bus cycle simulation. Data byte 55h is written to location 1000h of the SRAM in a write bus cycle with the R/W signal low. In the next cycle, the R/W signal is high and the same data byte is being read back as shown in theADIOL bus.


* 0 IZoom

Signal State682 992 1302


T2 = 1267 Level High Strength Driving tDelta(T1,T2) = 503

reset

clkin

adioh

adiol

as

csiop

e

es1

rs0

rd_wr


10 FF 10

55 55 500 FF 00

Figure 13.

68HC11 With PSD4XX/5XX and External Memory In applications where a large amount of SRAM is required, the PSD4XX/5XX is able to support an additional external SRAM. Figure 14 illustrates how an external SRAM (6164)can be interfaced to the PSD4XX/5XX and the 68HC11 with multiplexed address/data buswithout additional hardware. Port C is configured to provide the latched output addressesA0 – A7 (A8 – A15 come directly from the 68HC11). The SRAM chip select and theread/write signals are generated from the GPLD.


4-98

Figure 14. 68HC11 and PSD4XX/5XX and External SRAM Interface

XT

EX

RE

SE

TIR

QX

IRQ

PA

0P

A1

PA

2

PE

0P

E1

PE

2P

E3

VR

HV

RL

AD

0/A

0A

D1/

A1

AD

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2A

D3

/A3

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4A

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/A5

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/A13

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SE

T

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I

CL

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AL

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3

0 29 39 41 40 8 7 6 17 18 19 20 22 21

5 4 3 2 1 16 15 14 13 12 11 10 9 31 32 33 34 35 36 37 38 42 43 44 45 46 47 25 24 27 26 28

60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

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9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

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C11

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XX

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AM

CE


4-99





SRAM (PSD) 1000 – 13FF

SRAM (External) 2000 – 3FFF



Define The DPLD/Decoding Function In The ABEL File For External SRAMThe following is a an example of defining the decoding function for the 68HC11 based application with external SRAM. The latched address A0 – A7 are assigned to Port C. The“/wr” and “/rd” signals, which can be used for other devices besides the SRAM, are alsogenerated. Table 8 shows the memory map.



4-100

Define The DPLD/Decoding Function In The ABEL File For External SRAM (Cont.)

module hc11 title ‘Design example of 68hc11 DPLD source file to interface with external SRAM’;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

“Output signalsas,rd_wr,e pin 37,29,41; “Motorola related ale and read/write signalscsiop, rs0, es0, es1, es2 node ; “DPLD output chip selects

“assign pins (port c) for latched address outaddr0, addr1,addr2,addr3,addr4,addr6, addr7 pin 17,16,15,14,13,12,11,10;

“External SRAM chip select and read/write signal generationswr, srd, sram_ce pin;

“DEFINITIONS

X = .x. ; “ Don’t careAddress = [a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,a0];

equations

“DPLD EQUATIONS

csiop = (Address >= ^h0000) & (Address <= ^h00FF); “CSIOP 256bytes blockrs0 = (Address <= ^h1000) & (Address >= ^h13FF); “SRAM 2KB block

es1 = (Address >= ^h4000) & (Address <= ^h7FFF); “2nd EPROM block cs es2 = (Address >= ^h8000) & (Address <= ^hBFFF); “3rd EPROM block cs es3 = (Address >= ^hC000) & (Address <= ^hFFFF); “4th EPROM block cs

“The first EPROM block is not used and it is not required to define es0

“Equations to select/read/write the 61128, external SRAM through PSD

swr = !(e & !rd_wr); “write signalsrd = !(e & rd_wr); “read signalsram_ce = (Address >= ^h2000) & (Address <= ^h3FFF); “8K SRAM chip select

END



4-101


The 68HC11K4 BusMotorola’s 68HC11K4 has a non-multiplexed 16-bit address and an 8-bit data bus. The control signals used for accessing I/O devices or memory are the E clock and the R/W signal.

The 68HC11K4 Interface to PSD4XX/5XX:The 68HC11K4 can interface directly to the PSD4XX/5XX without any additional glue logic. As shown in Figure 15 , the E clock is connected to the “RD” pin, which is configured to act as the E clock input. The R/W signal is connected to the “WR” pin, which is configured to act as the R/W input.

The PSD4XX/5XX generates internal “write” and “read” signals based on the E clock and the R/W inputs. If E clock is high and R/W is high, then PSD4XX/5XX sees it as a read bus cycle and drive data onto the data bus through the Port C if any of its internal devices is selected.


4-102

Figure 15. 68HC11K4 and PSD4XX/5XX Interface

XT

EX

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4 73 61 30 76 11 10 9 49 48 47 46 45 44 43 42 51 50

60 59 58 57 56 55 54 53 20 19 18 17 16 15 14 13 62 63 64 65 66 67 68 69 33 72

60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

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9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

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C11

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F

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17 16 15 14 13 12 11 10

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CL

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75

R/W

RE

SE

T

RE

SE

T


4-103


Specify The 68HC11K4 Non-Multiplexed Bus Interface In PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the 68HC11 bus interface can be specified by selecting:


❏ Address/Data Mode: NM

❏ RD/WR Setting: R/W, E


4-104


Define The DPLD/Decoding Function In The ABEL File The following is a an example of defining the decoding function for the 68HC11K4 based application. Table 9 shows the memory map implemented by the DPLD.





SRAM 1000 – 13FF



module hc11k4 title ‘Design example of 68hC11K4 DPLD source file’;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

“Output signalsrd_wr,e pin 29,41; “Motorola related ale and read/write signalscsiop, rs0, es0, es1, es2, es3 node ; “DPLD output chip selects

“DEFINITIONS


equations

“DPLD EQUATIONS

csiop = (Address >= ^h0000) & (Address <= ^h00FF); “CSIOP 256bytes blockrs0 = (Address >= ^h1000) & (Address <= ^h13FF); “SRAM 2k block

es1 = (Address >= ^h4000) & (Address <= ^h7FFF); “2nd EPROM block cs es2 = (Address >= ^h8000) & (Address <= ^hBFFF); “3rd EPROM block cses3 = (Address >= ^hC000) & (Address <= ^hFFFF); “4th EPROM block cs

END


4-105

Simulation Of 68HC11K4 Bus Cycles With The PSD4XX/5XX Figure 16 shows the output of the 68HC11K4 bus cycle simulation. Data byte 55h is written to loaction 1000h of the SRAM in a write bus cycle with the R/W signal low. In the nextcycle, the R/W signal is high and the same data byte is being read back as shown in theDATAL bus.



* 0 IZoom




reset

e

rd_wr

adioh

adiol

csi

csiop

datal

rs0


00

55 55 55

0000 FF

FFXX XX

10 0000 FF

Figure 16.

The 80C196 BusThe 80C196 family of microcontrollers has a 16-bit multiplexed address/data bus. The processor has a dynamic data bus width. In a typical application, the EPROM has an 8-bit data bus while the SRAM has a 16-bit data bus. The PSD4XX/5XX is able to provide a16-bit data bus interface to both the SRAM and EPROM, thus increase system performance and throughput.

The 80C196 bus control signals include the ALE, the RD, the WR and the BHE. It also has a special mode, the Write Strobe Mode. In this mode, the WR and BHE signalsare replaced by WRL and WRH. The PSD4XX/5XX supports both interfaces.

The 80C196 and PSD4XX/5XX Interface SchematicFigure 17 shows the 80C196 and PSD4XX/5XX interface schematic. The address/data bus and the bus control signals such as ALE, RD, ER, BHE etc., are directly connected tothe corresponding pins of PSD4XX/5XX without any additional glue logic.

Interfacing To The 80C196Family OfMicrocontrollers


4-106

Figure 17. 80C196 and PSD4XX/5XX Interface

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

RD

WR

RE

SE

T

CS

I

CL

KIN

PE

0/B

HE

PE

1/A

LE

PE

2P

E3

PE

4P

E5

PE

6P

E7

VS

TD

BY

X2

P3.

0 / A

D0

P3.

1 / A

D1

P3.

2 / A

D2

P3.

3 / A

D3

P3.

4 / A

D4

P3.

5 / A

D5

P3.

6 / A

D6

P3.

7 / A

D7

P4.

0 / A

D8

P4.

1 / A

D9

P4.

2 / A

D10

P4.

3 / A

D11

P4.

4 / A

D12

P4.

5 / A

D13

P4.

6 / A

D14

P4.

7 / A

D15 RD

WR

BH

EA

LE

INS

TC

LK

OU

T

P1.

0P

1.1

P1.

2P

1.3

P1.

4P

1.5

P1.

6P

1.7

HS

O.0

HS

O.1

HS

O.2

HS

O.3

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

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PD

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PD

6P

D7

PA

0P

A1

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2P

A3

PA

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PA

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PB

6P

B7

1

1 3 43 14 64 16 6 5 7 4 11 10 8 9 18 17 15 44 42 39 33 38 24 25 26 27 13 12 2

12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 61 40 41 62 63 65 59 58 57 56 55 48 47 46 50 49 44 43

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

A8

A9

A10

A11

A12

A13

A14

A15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

80C

196

NM

I

PS

D4X

X/5

XX

CL

KIN

RD

WR

BH

EA

LE

Y1

C1

C2

U1

U2

C3

R1

RE

SE

T

V CC

V CC

V CC

NM

IR

EA

DY

CD

EB

US

WID

TH

RE

SE

T

AC

H0

/ P0

. 0A

CH

1 / P

0 . 1

AC

H2

/ P0

. 2A

CH

3 / P

0 . 3

AC

H4

/ P0

. 4A

CH

5 / P

0 . 5

PC

S6

/ P0

. 6P

CS

7 / P

0 . 7

P2

. 0 /

TX

DP

2 . 1

/ R

XD

P2

. 2 /

EX

INT

P2

. 3 /

T2C

LK

P2

. 4 /

T2R

ST

P2

. 5 /

PW

MP

2 . 6

/ T

2UP

– D

NP

2 . 7

/ T

2CA

P

HS

I . 0

HS

I . 1

HS

I . 2

/ H

SO

. 4

HS

I . 3

/ H

SO

. 5

VR

EF

AN

GN

DE

A

RS

T_

OU

T

X1


4-107


Specify The 80C196 Bus Interface In PSDconfiguration As shown in the following windows captured from PSDconfiguration, specify the 80C196 interface bus by selecting:




❏ RD/WR Setting: WR, RD, BHE (WRL, RD, WRH for Write Strobe Mode)


4-108


Define The DPLD/Decoding Function In The ABEL FileThe following is an example of defining the decoding function for the 80C196 based application. The codes are stored in three 32KB EPROM blocks and occupy the sameaddress space from 0000h to 7FFFh. This requires the EPROM blocks to be assigned to 3different pages. Table 10 illustrates the address map.

Depending on your application, you could also use the GPLD to generate the controlsignals for the 80C196 “Ready” and the “Buswidth” input.





SRAM 8000 – 87FF All Pages

I/O Devices C000 – C0FF All Pages


module 80C196 title ‘Design example of 80C196 DPLD source file’;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin; pgr3, pgr2, pgr1, pgr0 node; “Page Register outputsreset pin ;rst_out pin 34;

“Output signals

csiop, rs0, es0, es1, es2 node ; “DPLD output chip selects

“DEFINITIONS

page = [pgr3,pgr2,pgr1,pgr0];X = .x. ; “ Don’t careAddress =[a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,a0];

equations

“DPLD EQUATIONS

csiop= (Address >= ^hC000) & (Address <= ^hC0FF) ; “Chip Select 256 blockrs0 = (Address >= ^h8000) & (Address <= ^h87FF) ; “ SRAM, 2KB es0 = (Address >= ^h0000) & (Address <= ^h7FFF) & (page == 0); “EPROM 32KB, page 0es1 = (Address >= ^h0000) & (Address <= ^h7FFF) & (page == 1); “EPROM 32KB, page 1es2 = (Address >= ^h0000) & (Address <= ^h7FFF) & (page == 2); “EPROM 32KB, page 2

“GPLD EQUATIONS

rst_out = reset;

END


4-109


Simulation Of 80C196 Bus Cycle With The PSD4XX/5XX Figure 18 shows the simulation output of the SILOS3 Simulator. The 80C196 is writing a word 6677h to SRAM location 8000h and reading back the same location in the next buscycle.


* 0 IZoom

Scale = 15/div Tstart = 0 Tstop = 800




c196.sim

D1

D1

R1

80

00

D1

D0

D0

D1

D1

D1

clkin

reset

rst_out

adioh

adiol

ale

bhe

es0

rd

rs0

wr

78

80 FF 66 80 FF 66 6680 FF 66 80 FF 66 66

80 FF 77 00 FF 77 7780 FF FF


Figure 18.


4-110

The 68302 BusThe Motorola 68302 has a non-multiplexed bus with a 16-bit data bus. It has the following bus signals:

❏ Address Bus: A23-A1

❏ Data Bus D15-D0


❏ Control Signals: R/W, UDS, LDS

The 68302 has no A0 in the address bus; therefore the A0 (ADIO0) pin on the PSD4XX/5XXis grounded. The signals UDS and LDS (Upper and Lower Data Strobe) are used to selectwhether the low byte, high byte or both bytes for the current bus cycle. See Table 11 for thebyte enable assignment.

Interfacing The PSD4XX/5XXTo The 68302

UDS LDS D8 – D15 D0 – D7Low Low Enabled Enabled

Low High Enabled Disabled

High Low Disabled Enabled

High High Disabled Disabled

Table 11. Byte Enable Assignment

The 68302 and PSD4XX/5XX Interface SchematicFigure 19 is the 68302 and PSD4XX/5XX interface schematic. The address bus, data bus and bus control signals such as LDS, UDS, R/W, AS etc., are directly connected to thecorresponding pins of PSD4XX/5XX without any additional glue logic. Please note A0 pinon the PSD4XX/5XX is grounded.

For Motorola 16-bit microcontrollers, the data byte D0 – D7 is considered as an odd byteand D8 – D15 as an even byte. This is just the reverse of Intel and other similar processors.If you select a Motorola 16-bit bus interface, the PSDcompiler automatically swaps thesebytes such that D0-D7 is programmed to even byte locations and D8 – 15 is programmed toodd byte locations in the PSD EPROM. This swapping is transparent to the user. In theinterface schematic, connect D0 – D7 from the 68302 to Port D (Data Port D0 – D7) and D8 – D15 from the 68302 to Port D (Data Port D8 – D15).

The CS0 signal from the 68302 can be connected to the CSI pin on the PSD4XX/5XX forpower management. If the 68302 is not fetching code from the PSD, CS0 is high and thusputs the PSD into power saving Standby Mode.


4-111

Figure 19. 68302 and PSD4XX/5XX Interface

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

LD

S

R/W

RE

SE

T

CS

I

CL

KIN

PE

0/U

DS

PE

1/A

SP

E2

PE

3P

E4

PE

5P

E6

PE

7

VS

TD

BY

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

100

101 98 52 80 82 81 50 51 79 76 92 91 94 74 73 48 47 46 45 43 42 41 40 38 37 36 35 33 32 31 30 69 70 71 108

109

110

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113

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115

117

118

119

EX

TA

LX

TA

LC

LK

O

RX

D1_

L1R

XD

TX

D1_

L1T

XD

RC

LK

1_L

1CL

KT

CL

K1_

SD

S1

CD

1_L

ISY

1C

TS

1_L

IGR

RT

S1_

L1R

QB

RG

1

RE

SE

TH

AL

TB

ER

RB

US

WD

ISC

PU

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

DR

EQ

_PA

13D

AC

K_P

A14

DO

NE

_PA

15

IAC

K7_

PB

0IA

CK

6_P

B1

IAC

K1_

PB

2T

IN1_

PB

3T

OU

T1_

PB

4T

IN2

_P

B5

TO

UT

2_

PB

6W

DO

G_

PB

7P

B8

PB

9

1 2 3 5 6 7 8 9 10 11 12 14 15 16 17 19 20 21 22 24 25 26 27 104

103

106

105

85 123

122

86 90 87 88 97 96 95 132

130

129

93 128

129

125

124

72

A1

A2

A2

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23 AS

R_W

UD

S_

A0

LD

S_D

SD

AT

AK

RM

CIA

CB

CL

R

BR

BG

BG

AC

K

IRQ

1IR

Q6

IRQ

7F

C0

FC

1F

C2

AV

EC

CS

0C

S1

CS

2C

S3

FR

Z

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

PS

D4X

X/5

XX

6830

2

X1

C1

C2

U1

U1

V CC

LD

S

R/W

UD

S

AS

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

V CC 10

K

V CC 10

K

V CC 10

K

RE

SE

T

CL

KIN

D0

– D

15

RE

SE

T

CL

KIN

RS

T_

OU

T


4-112

Specify The 68302 Bus Interface In PSDConfigurationAs shown in the following windows captured from PSDconfiguration, specify the 68302 bus interface by selecting:



❏ ALE/AS signal: Yes (No if you prefer not to use AS to latch address)

❏ Polarity of ALE: High (if Yes on ALE/AS)

❏ RD/WR Setting: R/W, LDS, UDS

Interfacing The PSD4XX/5XXTo The 68302(Cont.)


4-113

Define the DPLD/Decoding function in the ABEL fileThe following is an example of defining the decoding function for the 68302 based application. The codes are stored in three 32KB EPROM blocks and occupy the sameaddress space from 0000h to 7FFFh. This requires the EPROM blocks to be assigned to 3different pages. Table 12 illustrates the address map.

Interfacing ThePSD4XX/5XXTo The 68302(Cont.)

module 68302 title ‘example of 68302 DPLD source file ‘;

“Input signals

“Address lines, using reserved names.a15,a14,a13,a12,a11,a10,a9,a8,a1 pin;

“Use the reserved names to declare the following special functionsreset pin; rst_out pin 34;

“ Output signals

“ Internal PSD5XX PLD output signals.

“DPLD outputs using reserved names.csiop, rs0, es0, es1, es2, es3 node ;

“ Definitions

“ Don’t careX = .x. ;

“Note in the Address definition that a7 - a2 are denoted by don’t-caresAddress = [a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,X];

equations

“DPLD EQUATIONS

csiop = (Address >= ^hC000) & (Address <= ^hC0FF) ; “Chip Select 256 blockrs0 = (Address >= ^h8000) & (Address <= ^h87FF) ; “SRAM, 2KB es0 = (Address >= ^h0000) & (Address <= ^h3FFF) & (page == X);

“EPROM 16KB, any pagees1 = (Address >= ^h4000) & (Address <= ^h7FFF) & (page == 1); “EPROM 16KB, page 1es2 = (Address >= ^h4000) & (Address <= ^h7FFF) & (page == 2); “EPROM 16KB, page 2

“GPLD EQUATIONS

rst_out = reset;

END

Device Memory Space Memory PageEPROM, Block 0 0000 – 3FFF All Pages







4-114

Interfacing ThePSD4XX/5XXTo The 68302(Cont.)

Simulation Of 68302 Bus Cycle With The PSD4XX/5XX Figure 20 shows the simulation of 3 bus cycles of the 68302. The 68302 is writing a byte to SRAM location 8477h and location 8476h. The third bus cycle is a word read to thesame locations.


* 0 IZoom


T1 = 330 Level Low Strength Driving


D1

R1

D1

00

00

D1

XX

XX

D1

D0

D1

D1

D0

D1

00 84 84 84 839FF FF

00 76 77 76 0FEFF FF

XX FF 27 27 01 0127

XX FF A5 A5 23 23A5

reset

rst_out

clkin

adioh

adiol

as

datah

datal

es0

es1

lds

rdorwr

rs0

uds


Figure 20.


4-115

Interfacing The PSD4XX/5XX To68HC16/68330/331/332/340

The 683XX BusThis group of Motorola 16-bits microcontrollers have similar bus structure and the bus interface to the PSD4XX/5XX are identical. The 68332 microcontroller is used here as anexample. The bus is a non-multiplexed data and address bus and has the following signals:


❏ Data Bus: D15-D0


❏ Control Signals: DS, R/W, SIZ0, SIZ1

The higher address pins A23-A19 can be configured either as address lines or as chipselect outputs (CS6 – CS10) at reset time. Two of the signals, SIZ0 and A0 are used todetermine whether the current cycle is a byte or a word operation. If SIZ0 is low, it is alwaysa word operation. If SIZ0 is high , it is a byte operation and A0 determines which byte isenabled.

The PSD4XX/5XX generates internal write or read pulses based on the status of the R/Wand DS signal inputs.

The 68332 And PSD4XX/5XX Interface SchematicFigure 21 is the 68332 and PSD4XX/5XX interface schematic. The address bus, data bus and the bus control signals such as DS, R/W, SIZ0, AS etc., are directly connected to thecorresponding pins of PSD4XX/5XX without any additional glue logic.

For Motorola 16-bit microcontrollers the data byte D0 – D7 is considered as odd byte and D8 – D15 as even byte, which is the reverse of Intel and other similar processors. If youselect a Motorola 16-bit bus interface, the PSDcompiler automatically swaps these bytessuch that D0 – D7 is programmed to even byte locations and D8 – 15 is programmed to oddbyte locations in the PSD EPROM. This swapping is transparent to the user. In the interfaceschematic, connect D0 – D7 from the 68332 to Port C (Data Port D0 – D7) and D8 – D15 to Port D (Data Port D8 – D15).

The CSBOOT signal from the 68332 can be connected to the CSI pin on the PSD4XX/5XXto control the device power consumption. If the 68332 is not fetching code from the PSD,the CSBOOT is high and puts PSD4XX/5XX into power saving Standby Mode. Aftersystem reset, the CSBOOT has a default value of 1M byte memory space starting fromaddress 000000h. This value can be re-programmed after system initialization to includethe PSD EPROM, SRAM and I/O space.


4-116

Figure 21. 68332 and PSD4XX/5XX Interface

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

LD

S

R/W

RE

SE

T

CS

I

CL

KIN

PE

0/S

IZ0

PE

1/A

LE

P

E2

PE

3P

E4

PE

5P

E6

PE

7

VS

TD

BY

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

111

110

109

108

105

104

103

102

100 99 98 97 94 93 92 91 68 89 88 77 76 75 74 73 72 71

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

RE

SE

T

DS

AC

K0

DS

AC

K1

IRQ

1IR

Q2

IRQ

3IR

Q4

IRQ

5IR

Q6

IRQ

7

90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 121

122

123

124

125

82 79 85 81 80 66 112

113

114

115

118

119

120

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

_C

S6

A20

_C

S7

A21

_C

S8

A22

_C

S9

A23

_C

S10 AS

R/W DS

SIZ

0S

IZ1

CL

KO

UT

CS

BO

OT

BR

_C

S0

BG

_C

S1

BG

AC

K_

CS

2F

C0

_C

S3

FC

1_

CS

4F

C2

_C

S5

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

PS

D4X

X/5

XX

MC

6833

2U

2U

1

DS

SIZ

0A

S

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

RE

SE

T

CL

KIN

R/W

D0

– D

15

RE

SE

T

CL

KIN

RS

T–

OU

T


4-117

Interfacing The PSD4XX/5XX To68HC16/68330/331/332/340(Cont.)

Specify the 68332 Bus Interface in PSDConfigurationAs shown in the following windows which are captured from PSDconfiguration, the 68332 bus interface can be specified by selecting:



❏ ALE/AS signal: Yes (No if you prefer not to use AS to latch address)

❏ Polarity of ALE: High (if Yes on ALE/AS)

❏ RD/WR Setting: R/W, DS, SIZ0


4-118


Define the DPLD/Decoding function in the ABEL fileThe following is an example of defining the decoding function for the 68332 based application. The codes are stored in three 32KB EPROM blocks and occupy the sameaddress space from 0000h to 7FFFh. This requires the EPROM blocks to be assigned to 3different pages. Table 13 illustrates the address map.

Device Memory Space Memory PageEPROM, Block 0 0000 – 3FFF All Pages






module 68332 title ‘example of 68332 DPLD source file ‘;

“Input signals

“Address lines, using reserved names.a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

“Use the reserved names to declare the following special functionsreset pin; rst_out pin 34;

“ Output signals

“ Internal PLD output signals.

“DPLD outputs using reserved names.csiop, rs0, es0, es1, es2 node ;

“ Definitions


“Note in the Address definition that a7 - a2 are denoted by don’t-caresAddress = [a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,a0];

equations

“DPLD EQUATIONS

csiop =(Address >= ^hC000) & (Address <= ^hC0FF) ; “Chip Select 256 blockrs0 =(Address >= ^h8000) & (Address <= ^h87FF) ; “SRAM, 2KB es0 =(Address >= ^h0000) & (Address <= ^h3FFF) & (page == X);

“ EPROM 16KB , any pagees1 =(Address >= ^h4000) & (Address <= ^h7FFF) & (page == 1); “EPROM 16KB, page 1es2 =(Address >= ^h4000) & (Address <= ^h7FFF) & (page == 2); “EPROM 16KB, page 2

“GPLD EQUATIONS

rst_out = reset;

END


4-119


Simulation Of 68332 Bus Cycle With The PSD4XX/5XX Figure 22 shows the simulation of five 68332 bus cycles. The first two are byte write cyclesto SRAM locations 8476 and 8477. The next cycle is a word read to the same location. The next cycle is reading an EPROM block.


* 0 IZoom

Scale = 26/div Tstart = 0 Tstop = 1600

Signal State286 546 806 1068



siz0.sim

D0

D1

R1

84

76

XX

XX

D1

D0

D0

D0

D1

D1

as

reset

rst_out

adioh

adiol

datah

datal

rs 0

es0

es1

rdorwr

siz0

ds

84 84 39 78

76 77 76 FE 26

27 27XX FF FF 01 01 452727

XX A5 A5A5 A5 23 23 67


Figure 22.


4-120

Interfacing The PSD4XX/5XX To Z8

The Z8 BusThe Z8 has an 8-bit multiplexed external memory bus. Port 1 of the Z8 is used as the multiplexed bus port which provides the multiplexed lower address byte and data. Port 0can be used as the output port for the non-multiplexed address lines A15-A8. The bus hasthe following signals:




❏ Control Signals: DS, R/W, DM

The Z8 has 64KB of program memory space. It can also address another 64KB of data memory if the signal DM (data memory) is enabled. The signal DM can be programmed toappear on pin 4 of Port 3. If your application does not require separate data space, there isno need to connect the DM as input to the PSD4X/5XX.

The Z8 And PSD4XX/5XX Interface SchematicFigure 23 is the Z8 and PSD4XX/5XX interface schematic. The address bus, data bus and the bus control signals such as DS, R/W, AS etc., are directly connected to the corresponding pins of PSD4XX/5XX without any additional glue logic.

In this example, DM is used to separate the program space from the data space by including it in the DPLD chip select equations. Due to the PSD4XX/5XX architecturerequirement that any input signals which are included in the EPROM chip select equationsmust come from Port A, the DM signal is connected to pin PA0 in the schematic.


4-121

Figure 23. Z8 and PSD4XX/5XX Interface

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

DS

R/W

RE

SE

T

CS

I

CL

KIN

PE

0P

E1

/AS

PE

2P

E3

PE

4P

E5

PE

6P

E7

VS

TD

BY

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

2 3 6 7 8 9

XT

AL

1X

TA

L2

RE

SE

T

R/W

DS

AS

21 22 23 24 25 26 27 28 13 14 15 16 17 18 19 20

P1

– 0

P1

– 1

P1

– 2

P1

– 3

P1

– 4

P1

– 5

P1

– 6

P1

– 7

P0

– 0

P0

– 1

P0

– 2

P0

– 3

P0

– 4

P0

– 5

P0

– 6

P0

– 7

P3

– 4

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

A8

A9

A10

A11

A12

A13

A14

A15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

PS

D4X

X/5

XX

Z8

U2

U1

C3

R1

V CC

AS

RE

SE

T

DS

DM

R/W

29

X1

C1

C2

RS

T–

OU

T


4-122

Interfacing The PSD4XX/5XX To Z8(Cont.)

Specify The Z8 Bus Interface In PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the Z8 bus interface can be specified by selecting:



❏ Polarity of ALE/AS: Low

❏ RD/WR Setting: R/W, DS


4-123


Define The DPLD/Decoding Function In The ABEL FileThe following is an example of defining the decoding function for the Z8 based application. 64KB of code is stored in EPROM blocks 0 and 1. The SRAM, I/O space and EPROMblock 2 are assigned as data memory. Table 14 illustrates the address map.

Device Memory SpaceEPROM, Block 0 0000 – 7FFF Code Area

EPROM, Block 1 8000 – FFFF Code Area

EPROM, Block 2 0000 – 7FFF Data Area

SRAM 8000 – 87FF Data Area

I/O Devices C000 – C0FF Data Area


module Z8 title ‘example of Z8 DPLD source file ‘;

“Input signals


“Use the reserved names to declare the following special functionsreset pin; dm pin 27 “assign pin PA0 as input pin for DMrst_out pin 34;

“ Output signals

“ Internal PLD output signals.

“DPLD outputs using reserved names.csiop, rs0, es0, es1, es2, es3 node ;

“ Definitions


“Note in the Address definition that a7 - a2 are denoted by don’t-caresAddress = [a15,a14,a13,a12,a11,a10,a9,a8,X,X,X,X,X,X,a1,a0];

equations

“DPLD EQUATIONS

csiop = (Address >= ^hC000) & (Address <= ^hC0FF) & !DM ; “Chip Select 256 blockrs0 = (Address >= ^h8000) & (Address <= ^h87FF) & !DM; “ SRAM, 2KB es0 = (Address >= ^h0000) & (Address <= ^h7FFF) & DM; “ EPROM 32KB code es1 = (Address >= ^h8000) & (Address <= ^hFFFF) & DM; “ EPROM 32KB code es2 = (Address >= ^h0000) & (Address <= ^h7FFF) & !DM; “ EPROM 32KB data

“GPLD EQUATIONS

rst_out = reset;

END


4-124


Simulation Of Z8 Bus Cycle With The PSD4XX/5XX Figure 24 shows the simulation of two Z8 bus cycles. The first is a code fetch at location 0000h from EPROM block 0, with /DM input high. The second cycle is a data read at location 0000h from EPROM block 1.The /DM signal is low since this is a datamemory bus cycle.


* 0 IZoom


T1 = 1315 Level Low Strength Driving


00

67

D1

D1

D0

D0

D1

D0

D1

D0

R1

D1

adioh

adiol

ale

dm

ds

es0

es1

es2

reset

rs0

rst_out

rw

00 67 FF

00 FF 00

00 23


Figure 24.


4-125

Interfacing The PSD4XX/5XX To Z80

The Z80 BusThe Z80 has an 8-bit non-multiplexed bus. The following signals are used to interface to memory or I/O devices:


❏ Data Bus: D7 – D0

❏ Address Strobe: None

❏ Control Signals: M1, MREQ, IORQ, RD, WR

The Z80 has 64KB of program memory space and 256 bytes of I/O space. In a memorycycle both M1 and MREQ are low. In an I/O bus cycle, M1 is high and IORQ is low . OnlyA7-A0 are active and thus limit the I/O space to 256 bytes. If M1 is low and IORQ is low, it isan interrupt acknowledge bus cycle. M1 can be ignored if interrupt is not used.

The Z80 And PSD4XX/5XX Interface SchematicFigure 25 is the Z80 and PSD4XX/5XX interface schematic. The address lines A15 – A0 are connected to the ADIO Port and the data lines D7 – D0 are connected to PortC. Control signals RD and WR are directly connected to the corresponding pins of thePSD4XX/5XX without any additional glue logic.

The PSD4XX/5XX does not have specific pins assigned to MREQ, IORQ and M1. Sincethese signals are used in the EPROM chip select equations, you should assign them toPort A pins in the ABEL file.


4-126

Figure 25. Z80 and PSD4XX/5XX Interface

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

RD

WR

RE

SE

T

CS

I

CL

KIN

PE

0P

E1

PE

2P

E3

PE

4P

E5

PE

6P

E7

VS

TD

BY

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

27 19 20 22 21 28 18 24 16 17 26 25 23 6

M1

MR

EQ

IOR

QW

RR

D

RE

FS

H

HA

LT

WA

IT

INT

NM

I

RE

SE

T

BU

SR

QB

US

AK

CL

K

30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 14 15 12 8 7 9 10 13

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15 D0

D1

D2

D3

D4

D5

D6

D7

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

PS

D4X

X/5

XX

Z80

U2

U1

C1

R2

V CC

R1

4.7K

V CC

RE

SE

T

RS

T–

OU

T

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

– D

7

INT

RF

SH

HA

LT

NM

I

WA

IT

BU

SR

Q

CL

KIN

CL

KIN

RD

WR

IOR

Q

MR

EQ

M1


4-127


Specify The Z80 Bus Interface In PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the Z80 bus interface can be specified by selecting:



❏ ALE/AS signal: No

❏ RD/WR Setting: RD, WR


4-128


Define The DPLD/Decoding Function In The ABEL FileThe following is an example of defining the decoding function for the Z80 based application. Please note the 256 bytes of I/O space are all taken by the PSD4XX/5XX internal I/Odevices, and that the CSIOP signal becomes active whenever /IORQ is active.

You could define a 256 byte block of memory space to the CSIOP chip select. In this case,you have to use memory reference instructions to access the PSD4XX/5XX I/O devices.Table 15 illustrates the address map. The CSIOP completely takes up 256 bytes of I/Ospace and is enabled whenever IORQ is active.

Device Memory SpaceEPROM, Block 0 0000 – 3FFF Code

EPROM, Block 1 4000 – 7FFF Code

EPROM, Block 2 8000 – BFFF Data

SRAM C000 – C7FF Data


module z80 title ‘ example of z80 DPLD source file’;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

reset pin;rst_out pin 34;

mreq pin 27; “ assign mreq input to Port A pin PA0 iorq pin 26; “ assign ioreq input to Port A pin PA1 m1 pin 25; “ assign m1 input to Port A pin PA2

“Output signals


“DEFINITIONS


equations

“DPLD EQUATIONS

csiop = !iorq & m1; “I/O Chip Select 256 bytesrs0 = (Address >= ^hC000) & (Address <= ^hC7FF) & !mreq “SRAM, 2KB es0 = (Address >= ^h0000) & (Address <= ^h3FFF) & !mreq; “EPROM 16KB code es1 = (Address >= ^h4000) & (Address <= ^h7FFF) & !mreq; “EPROM 16KB code es2 = (Address >= ^h8000) & (Address <= ^hBFFF) & !mreq; “EPROM 16KB data

rst_out = reset;

END


4-129


Simulation Of Z80 Bus Cycle With The PSD4XX/5XX Figure 26 shows the simulation of three Z80 bus cycles. The first is a code fetch at location 0000h from EPROM block 0. The second cycle is a data write to SRAM at location8000h, and a read to the same location in the next cycle.


* 0 IZoom

Scale = 42/div Tstart = 0 Tstop = 176 0

Signal State378 798 1218 1638



z80.sim

D1

R1

00

00

23

D1

D0

D0

D1

D0

D1

reset

rst_out

adioh

adiol

datal

ioreq

mreq

rd

es0

rs0

wr

FF 80 FF00 FF 80

FF 00 FF00 FF 00

00 23 55 FF23 55


Figure 26.


4-130

Interfacing The PSD4XX/5XX To ST90R26

The ST90R26 BusThe ST90R26 is the ROMless member of the ST9 family of microcontrollers from SGS-Thomson. The ST9 has an 8-bit multiplexed bus and the following are the bus signalsused to interface to memory or I/O devices.

❏ Address/Data Bus: AD7-AD0



❏ Control Signals: DS, R/W, P/D

The higher address lines A15-A8 are not multiplexed and are driven from Port P1. The ST9has two memory spaces: the program and data memory. Each space has 64KB and isselected by the P/D signals. A high on the P/D signal indicates program space.

The PSD4XX/5XX generates internal write or read pulses based on the status of the R/Wand DS signal inputs.

The ST90R26 And PSD4XX/5XX Interface SchematicFigure 27 is the ST90R26 and PSD4XX/5XX interface schematic. The address bus, data bus and the bus control signals such as /DS, R/W, /AS etc., are directly connected to thecorresponding pins of PSD4XX/5XX without any additional glue logic. The P/D signal isconnected to one of the pins in Port A as input to the DPLD.


4-131

Figure 27. ST90R26 and PSD4XX/5XX Interface

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

DS

R/W

RE

SE

T

CS

I

CL

KIN

PE

0P

E1

/AS

PE

2P

E3

PE

4P

E5

PE

6P

E7

VS

TD

BY

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

OS

CIN

RE

SE

TA

8/P

1– 0

A9

/P1–

1A

10/P

1– 2

A11

/P1–

3A

12/P

1– 4

A13

/P1–

5A

14/P

1– 6

A15

/P1–

7A

0/D

0A

1/D

1/P

0 –

1A

2/D

2/P

0 –

2A

3/D

3/P

0 –

3A

4/D

4/P

0 –

4A

5/D

5/P

0 –

5A

6/D

6/P

0 –

6A

7/D

7

P/D

/NM

I/P

2 –

0

AS

OS

CO

UT

R/W DS

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

A8

A9

A10

A11

A12

A13

A14

A15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

PS

D4X

X/5

XX

ST

90R

26U

2U

1

DS

R/W

48

A8

A9

A10

A11

A12

A13

A14

A15

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

RE

SE

T

CL

K

RS

T_O

UT

26 25

20 24

P/DAS

AD

0 –

AD

7 A8

– A

15

RE

SE

T


4-132

Interfacing The PSD4XX/5XX To ST90R26(Cont.)

Specify The ST90R26 Bus Interface In PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the ST90R26 bus interface can be specified by selecting:



❏ ALE/AS signal: Yes

❏ Polarity of ALE: Low

❏ RD/WR Setting: R/W, DS


4-133


Define The DPLD/Decoding Function In the ABEL FileThe following is an example of defining the decoding function for the ST9 based application. The codes are stored in three 16KB EPROM blocks and occupy address spacefrom 0000h to BFFFh. The SRAM space is from 8000h to 87FFh. The P/D input is used toseparate the EPROM (program) space to SRAM and I/O (data) space.



EPROM, Block 2 8000 – BFFF Code

SRAM 8000 – 87FF Data

I/O Devices A000 – A0FF Data


module st9 title ‘example of st9 DPLD source file’;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin;

reset pin; “using the right pin #spd pin 27; “port A pin-0 for P/D input

“Output signals

csiop, rs0, es0, es1, es2 node ; “DPLD output chip selects rst_out pin 34;

“DEFINITIONS


equations

“DPLD EQUATIONS

csiop = (Address >= ^hA000) & (Address <= ^hA0FF) & !pd ; “Chip Select 256 blockrs0 = (Address >= ^h8000) & (Address <= ^h87FF) & !pd; “SRAM, 2KB es0 = (Address >= ^h0000) & (Address <= ^h3FFF) & pd; “EPROM 16KB es1 = (Address >= ^h4000) & (Address <= ^h7FFF) & pd; “EPROM 16KB es2 = (Address >= ^h8000) & (Address <= ^hBFFF) & pd; “EPROM 16KB

“GPLD EQUATIONS

rst_out = reset;

END


4-134


Simulation Of The ST90R26 Bus Cycle With The PSD4XX/5XX Figure 28 shows the simulation of three ST90R26 bus cycles. The first two cycles are byte write (55h) and read to SRAM location 8000h, and the third is a code fetch cycle toEPROM location 0000h. Please note that the P/D separates the data and program space.


* 0 IZoom

Signal State

T1 = 40

T2 = 562 tDelta(T1, T2) = 612

D0

R0

00

00

D1

D1

UNSET

D1

D0

D1

0 260 520

00 FF 80 80 00

00 FF 55 23 55 0000 23

reset

rst_out

adioh

adiol

as

ds

es0

pd

rs0

rw


Figure 28.


4-135

Interfacing The PSD4XX/5XX To 80C166

The 80C166 BusThe Siemens’ 80C166 is a very flexible microcontroller which can be operated in multiplexed or non-multiplexed bus mode. The bus configuration and data bus width (8 or 16) are determined at reset by sampling the EBC0-1 input pins. The multiplexed 16-bit data/16 bit address bus mode is selected here for PSD4XX/5XX implementationsince it provides the best performance with the least pin count.

The 16-bit multiplexed bus consists of the following signals:

❏ Address/Data: AD15-AD0

❏ Address Latch: ALE

❏ Control Signals: RD, WR, BHE

The 80C166 also provides higher address lines A16-17 (segment address) if required.

The 80C166 And PSD4XX/5XX Interface SchematicFigure 29 shows the 80C166 and PSD4XX/5XX interface schematic. The address bus, data bus and bus control signals such as /RD, /WR, /BHE etc., are directly connected to thecorresponding pins of PSD4XX/5XX without any additional glue logic. Note that EBC0 isconnected to ground and EBC1 is connected to VCC to select the 16-bit address and 16-bitdata multiplexed bus mode.


4-136

Figure 29. Siemens' 80C166 and PSD4XX/5XX Interface

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

RD

WR

RE

SE

T

CS

I

CL

KIN

PE

0/B

HE

PE

1/A

LE

PE

2P

E3

PE

4P

E5

PE

6P

E7

VS

TD

BY

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

83 84 85 86 87 88 89 90 93 94 95 96 97 98 99 100

11 80 77 10 14 8 9

P0

. 0P

0 . 1

P0

. 2P

0 . 3

P0

. 4P

0 . 5

P0

. 6P

0 . 7

P0

. 8P

0 . 9

P0

. 10

P0

. 11

P0

. 12

P0

. 13

P0

. 14

P0

. 15

RD

#

P3

. 13

/ WR

#

P3

. 12

/BH

E#

AL

ER

ST

IN#

EB

C1

EB

C0

17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

AD

8A

D9

AD

10A

D11

AD

12A

D13

AD

14A

D15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

PS

D4X

X/5

XX

80C

166

U2

U1

CL

KIN

CL

KIN

RE

SE

T

RE

SE

T

RS

T_

OU

T

BH

E

RD

WR

V CC

AL

E


4-137

Interfacing The PSD4XX/5XX To 80C166(Cont.)

Specify The 80C166 Bus Interface In PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the 80C166 bus interface can be specified by selecting:



❏ ALE/AS signal: Yes


❏ RD/WR Setting: RD, WR, BHE


4-138


Define The DPLD/Decoding Function In The ABEL fileThe following is an example of defining the decoding function for the 80C166 application.The code is stored in two 16KB EPROM blocks and occupies address space 0000h to7FFFh. The SRAM space is from 8000h to 87FFh. Table 17 illustrates the address map.



SRAM 8000 – 87FF Data

I/O Devices C000 – C0FF Data


module 80c166 title ‘example of 80c166 DPLD source file’;

“Input signals


a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin; reset pin ;rst_out pin 34;

“Output signals

csiop, rs0, es0, es1 node ; “DPLD output chip selects

“DEFINITIONS


equations

“DPLD EQUATIONS

csiop = (Address >= ^hC000) & (Address <= ^hC0FF) ; “Chip Select 256 blockrs0 = (Address >= ^h8000) & (Address <= ^h87FF) ; “ SRAM, 2KB es0 = (Address >= ^h0000) & (Address <= ^h3FFF) ; “ EPROM 16KB es1 = (Address >= ^h4000) & (Address <= ^h7FFF) ; “ EPROM 16KB

“GPLD EQUATIONS

rst_out = reset;

END


4-139


Simulation Of 80C166 Bus Cycle With The PSD4XX/5XX Figure 30 shows the simulation of three 80C166 bus cycles. The first two cycles are byte write (55h) and read to SRAM location 8000h, the second is a code fetch cycle to EPROMlocation 0000h.


* 0 I


Zoom


D1

R1

80

00

D1

D1

D0

D0

D1

D1

D1



reset

rst_out

adioh

adiol

ale

bhe

es0

es1

rd

rs0

wr

8000 80 0100

00 55

00 00

005555 2300 00

Figure 30.

Figure 30 depicts a WORD read at location 0000hex when bhe=0 and A0=0.

Interfacing The PSD4XX/5XX To EchelonNEURON®

3150™ Chip

The 3150 BusThe 3150 has an 8-bit non-multiplexed bus. The following signals are used to interface to memory or I/O devices:

❏ Address/Data: A15-A0

❏ Data bus: D7–D0

❏ Address Strobe: None

❏ Control Signals: R/W, E (Enable Clock)

The 3150 has 64KB of program memory space. The E signal frequency is half that of the input clock. It is low during the second half of the bus cycle when read or write operation is taking place. A low R/W signal indicates it is a write bus cycle.

The 3150 and PSD4XX/5XX Interface SchematicFigure 31 shows the 3150 and PSD4XX/5XX interface schematic. The address lines A15–A0 are connected to the ADIO Port and the data lines D7–D0 are connected to Port C.Control signals R/W and E are directly connected to the corresponding pins of thePSD4XX/5XX without any additional glue logic.


4-140

Figure 31. NEURON® 3150™ Chip and PSD4XX/5XX Interface

CP

0C

P1

CP

2C

P3

CP

4

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

IO8

IO9

IO10

SE

RV

I

CL

K1

CL

K2

AD

0/A

0A

D1/

A1

AD

2/A

2A

D3

/A3

AD

4/A

4A

D5

/A5

AD

6/A

6A

D7/

A7

AD

8/A

8A

D9

/A9

AD

10/A

10A

D11

/A11

AD

12/A

12A

D13

/A13

AD

14/A

14A

D15

/A15

DS

R/W

RE

SE

T

CS

I

CL

KIN

PE

0 /S

IZ0

PE

1 / A

LE

PE

2P

E3

PE

4P

E5

PE

6P

E7

VS

TD

BY

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15 D

0D

1D

2D

3D

4D

5D

6D

7 ER

/W

PC

0P

C1

PC

2P

C3

PC

4P

C5

PC

6P

C7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

2

8 29 30 31 32 2 3 4 5 10 11 12 13 14 15 16 17 24 23 44 6

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 47 43 42 38 37 36 35 34 33 46 45

60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28

N31

50P

SD

4XX

/5X

X

RE

SE

T

V CC

D [

7 :

0]

A [

15 :

0]

D0

D1

D2

D3

D4

D5

D6

D7

A8

A9

A10

A11

A12

A13

A14

A15

A0

A1

A2

A3

A4

A5

A6

A7

17 16 15 14 13 12 11 10

D0

D1

D2

D3

D4

D5

D6

D7

R/W

RE

SE

T

RE

SE

T

E

XD


4-141

Specify The 3150 Bus Interface In PSDconfigurationAs shown in the following windows which are captured from PSDconfiguration, the 3150bus interface can be specified by selecting:



❏ ALE/AS signal: No

❏ RD/WR Setting: RD, DS, (E acts as an active low data strobe signal)


3150™ Chip(Cont.)


4-142

Define The DPLD/Decoding Function In The ABEL fileThe following is an example of defining the decoding function for the 3150 based application. The code is stored in three 16KB EPROM blocks and occupies address space0000h to BFFFh. The SRAM space is from F000h to F7FFh. Table 18 illustrates theaddress map.

Device Memory Space Memory PageEPROM, Block 0 0000 – 3FFF



SRAM C000 – C7FF

I/O Devices C800 – C8FF


module 3150 title ‘example of 3150 DPLD source file’;

“Input signals


e pin 41; “ds in the configuration file has been aliased to e

“Output signals


“DEFINITIONS


equations

“DPLD EQUATIONS

csiop = (Address >= ^hC800) & (Address <= ^hC8FF) ; “ I/O Chip Select 256 bytesrs0 = (Address >= ^hC000) & (Address <= ^hC7FF) ; “ SRAM, 2KB es0 = (Address >= ^h0000) & (Address <= ^h3FFF) ; “ EPROM 16KB codees1 = (Address >= ^h4000) & (Address <= ^h7FFF) ; “ EPROM 16KB codees2 = (Address >= ^h8000) & (Address <= ^hBFFF) ; “ EPROM 16KB data

END


3150™ Chip(Cont.)


4-143

Conclusion Using the PSD4XX/5XX with microcontrollers in embedded applications provides the follow-ing benefits over designs implemented with discrete components:

❏ Two chip solution (MCU & PSD) – smaller board size with fewer layers.

❏ ZPLD allows quick logic fixes and updates.

❏ Short development cycle

❏ Increase in system performance

❏ Reprogrammability.

❏ Lower power consumption

❏ Lower manufacturing cost

❏ Lower system cost.

❏ Security of design (security bit)

❏ Increase in system reliability.

❏ Reduced inventory cost.

Simulation Of The Echelon NEURON 3150 Bus Cycle With The PSD4XX/5XX Figure 32 shows the simulation of three 3150 bus cycles. The first cycle is a code fetch cycle to EPROM location 0000h and the following two cycles are write (55h) and read toSRAM location F000h.


3150™ Chip(Cont.) WSI Silos Data Analyzer

* 0 IZoom


T1 = 557 8'h XX Unset Strength

T2 = 1229 8'h FF Driving Strength tDelta(T1,T2) = 672

reset

rst_out

e

r–w

adioh

adiol

datal

es0

rs0

rs0


00

FF 55 55

00FF 00

FF FFXX 23

00 C0FF C0

Figure 32.

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