programmer’s register reference guide...

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Programmer’s Register Reference Guide

BCM56500

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Programmer’s Register Reference Guide

10/18/2005 11797

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56500-PR100-R

16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 10/11/05

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REVISION HISTORY

Revision Date Description

56500-PR100-R 10/11/05 Initial release.

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Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks ofBroadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any othertrademarks or trade names mentioned are the property of their respective owners.

Broadcom CorporationP.O. Box 57013

16215 Alton ParkwayIrvine, CA 92619-7013

© 2005 by Broadcom CorporationAll rights reserved

Printed in the U.S.A.

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TABLE OF CONTENTS

Section 1: Introduction........................................................................................................1

Overview ....................................................................................................................................................... 1

Audience ....................................................................................................................................................... 1

Related Documentation ............................................................................................................................... 1

Notations and Conventions..................................................................................................................... 1

Address Conventions.............................................................................................................................. 2

Section 2: PCI Configuration Registers.............................................................................3

PCI Configuration Space ............................................................................................................................. 3

VENDOR ID ............................................................................................................................................ 4

COMMAND/STATUS.............................................................................................................................. 5

CLASS CODE, REVISION ID ................................................................................................................. 7

HEADER TYPE, LATENCY TIMER, CACHELINE SIZE ........................................................................ 7

BASE ADDRESS LOW........................................................................................................................... 8

BASE ADDRESS HIGH .......................................................................................................................... 9

SUBSYSTEM, SUBSYSTEM VENDOR ID............................................................................................. 9

INTERRUPT, MAX LATENCY, MIN GRANT........................................................................................ 10

RETRY, TRDY TIMEOUT..................................................................................................................... 10

Section 3: CMIC Registers ................................................................................................11

CMIC_SCHAN_MESSAGE (CMIC_SCHAN_MESSAGE_EXT)........................................................... 11

CMIC_SCHAN_CTRL........................................................................................................................... 12

CMIC_SCHAN_ERR............................................................................................................................. 13

CMIC_DMA_CTRL ............................................................................................................................... 14

CMIC_DMA_STAT................................................................................................................................ 16

CMIC_CONFIG..................................................................................................................................... 18

CMIC_DMA_DESC............................................................................................................................... 20

CMIC_I2C_SLAVE_ADDR ................................................................................................................... 20

CMIC_I2C_DATA.................................................................................................................................. 21

CMIC_I2C_CTRL.................................................................................................................................. 22

CMIC_I2C_CCR ................................................................................................................................... 23

CMIC_I2C_STAT .................................................................................................................................. 24

CMIC_I2C_SLAVE_XADDR ................................................................................................................. 25

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CMIC_I2C_RESET................................................................................................................................25

CMIC_LINK_STAT ................................................................................................................................26

CMIC_IRQ_STAT..................................................................................................................................27

CMIC_IRQ_MASK.................................................................................................................................29

CMIC_MIIM_PARAM.............................................................................................................................30

CMIC_MIIM_READ_DATA....................................................................................................................32

CMIC_SCAN_PORTS...........................................................................................................................32

CMIC_STAT_DMA_SETUP ..................................................................................................................33

CMIC_STAT_DMA_ADDR....................................................................................................................33

CMIC_STAT_DMA_PORTS..................................................................................................................34

CMIC_STAT_DMA_CURRENT.............................................................................................................34

CMIC_ENDIANESS_SEL......................................................................................................................35

CMIC_DEV_REV_ID.............................................................................................................................35

CMIC_COS_CTRL_RX .........................................................................................................................36

CMIC_TAP_CONTROL.........................................................................................................................37

CMIC_RATE_ADJUST..........................................................................................................................38

CMIC_SBUS_RING_MAP.....................................................................................................................39

CMIC_TABLE_DMA_PCIMEM_START_ADDR....................................................................................40

CMIC_TABLE_DMA_SBUS_START_ADDR ........................................................................................40

CMIC_TABLE_DMA_ENTRY_COUNT.................................................................................................41

CMIC_TABLE_DMA_CFG ....................................................................................................................41

CMIC_TABLE_DMA_CUR_ENTRY_SBUS_ADDR..............................................................................42

CMIC_SLAM_DMA_PCIMEM_START_ADDR .....................................................................................42

CMIC_SLAM_DMA_SBUS_START_ADDR..........................................................................................43

CMIC_SLAM_DMA_ENTRY_COUNT...................................................................................................43

CMIC_SLAM_DMA_CFG......................................................................................................................44

CMIC_SLAM_DMA_CUR_ENTRY_SBUS_ADDR................................................................................45

CMIC_STAT_DMA_ING_STATS_CFG.................................................................................................45

CMIC_STATS_DMA_EGR_STATS_CFG.............................................................................................46

CMIC_STAT_DMA_MAC_STATS_CFG...............................................................................................47

CMIC_STAT_DMA_PORT_TYPE_MAP...............................................................................................47

CMIC_STAT_DMA_BLKNUM_MAP_7_0 .............................................................................................48

CMIC_STAT_DMA_BLKNUM_MAP_15_8 ...........................................................................................48

CMIC_STAT_DMA_BLKNUM_MAP_23_16 .........................................................................................49

CMIC_STAT_DMA_BLKNUM_MAP_31_24 .........................................................................................49

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CMIC_STAT_DMA_PORTNUM_MAP_7_0.......................................................................................... 50

CMIC_STAT_DMA_PORTNUM_MAP_15_8........................................................................................ 50

CMIC_STAT_DMA_PORTNUM_MAP_23_16...................................................................................... 51

CMIC_STAT_DMA_PORTNUM_MAP_31_24...................................................................................... 51

CMIC_MIIM_ADDRESS ....................................................................................................................... 52

CMIC_MIIM_PROTOCOL_MAP........................................................................................................... 52

CMIC_MIIM_PORT_TYPE_MAP.......................................................................................................... 53

CMIC_MIIM_INT_SEL_MAP ................................................................................................................ 53

CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0........................................................................................... 54

CMIC_MIIM_EXT_PHY_ADDR_MAP_7_4........................................................................................... 54

CMIC_MIIM_EXT_PHY_ADDR_MAP_11_8......................................................................................... 55

CMIC_MIIM_EXT_PHY_ADDR_MAP_15_12....................................................................................... 55





CMIC_XGXS_MDIO_CONFIG.............................................................................................................. 58

CMIC_SOFT_RESET_REG ................................................................................................................. 59

CMIC_XGXS_PLL_CONTROL_1......................................................................................................... 60

CMIC_XGXS_PLL_CONTROL_2......................................................................................................... 60

CMIC_LEDUP_CTRL ........................................................................................................................... 61

CMIC_LEDUP_STATUS....................................................................................................................... 61

CMIC_LEDUP_PROGRAM_RAM ........................................................................................................ 62

CMIC_LEDUP_DATA_RAM ................................................................................................................. 62

Section 4: S-Channel Messaging .....................................................................................63

Messaging Mechanism .............................................................................................................................. 63

Messaging Registers ............................................................................................................................ 63

S-Channel Messaging Mechanism ........................................................................................................... 66

Section 5: GbE Port Registers..........................................................................................70

GMACC0............................................................................................................................................... 70

GMACC1............................................................................................................................................... 71

GMACC2............................................................................................................................................... 72

GPCSC ................................................................................................................................................. 72

GSA0 .................................................................................................................................................... 73

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GSA1.....................................................................................................................................................73

MAXFR..................................................................................................................................................74

REVCD..................................................................................................................................................74

GTH_FE_MAC1 ....................................................................................................................................75

GTH_FE_MAC2 ....................................................................................................................................76

GTH_FE_IPGT......................................................................................................................................77

GTHG_FE_IPGR...................................................................................................................................78

GTH_FE_CLRT.....................................................................................................................................79

GTH_FE_MAXF ....................................................................................................................................79

GTH_FE_SUPP.....................................................................................................................................80

GTH_FE_EXCESSIVE_DEFER_LIMIT.................................................................................................81

ESA0 .....................................................................................................................................................81

ESA1 .....................................................................................................................................................82

ESA2 .....................................................................................................................................................82

GE_PORT_CONFIG .............................................................................................................................83

GE_EGR_PKT_DROP_CTRL...............................................................................................................84

PAUSE_CONTROL...............................................................................................................................84

MAC_TX_STATUS................................................................................................................................85

GPORT_CONFIG..................................................................................................................................85

GPORT_RSV_MASK ............................................................................................................................86

GPORT_STAT_UPDATE_MASK..........................................................................................................86

GPORT_CNTMAXSIZE.........................................................................................................................87

GPORT_TPID........................................................................................................................................87

Section 6: XG Port Registers ........................................................................................... 88

MAC_CTRL ...........................................................................................................................................88

MAC_XGXS_CTRL ...............................................................................................................................89

MAC_XGXS_STAT ...............................................................................................................................90

MAC_CNTMAXSZ.................................................................................................................................91

MAC_TXCTRL.......................................................................................................................................92

MAC_TXMACSA ...................................................................................................................................93

MAC_TXMAXSZ....................................................................................................................................93

MAC_TXPSETHR .................................................................................................................................94

MAC_RXCTRL ......................................................................................................................................95

MAC_RXMACSA...................................................................................................................................96

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MAC_RXMAXSZ................................................................................................................................... 96

MAC_RXLSSCTRL............................................................................................................................... 97

MAC_RXLSSSTAT ............................................................................................................................... 98

XPORT_CONFIG.................................................................................................................................. 99

XPAUSE_TX_PKT_XOFF_VAL ......................................................................................................... 100

XPAUSE_WATCHDOG_INIT_VAL..................................................................................................... 100

XPAUSE_WATCHDOG_THRESH ..................................................................................................... 101

XPAUSE_MH0.................................................................................................................................... 102

XPAUSE_MH1.................................................................................................................................... 103

XPAUSE_MH2.................................................................................................................................... 104

XPAUSE_D0....................................................................................................................................... 104

XPAUSE_D1....................................................................................................................................... 105

XPAUSE_D2....................................................................................................................................... 105

XPAUSE_D3....................................................................................................................................... 106

XHOL_MH0......................................................................................................................................... 107

XHOL_MH1......................................................................................................................................... 108

XHOL_MH2......................................................................................................................................... 109

XHOL_D0............................................................................................................................................ 109

XHOL_D1............................................................................................................................................ 110

XHOL_D2............................................................................................................................................ 110

XHOL_D3............................................................................................................................................ 111

XIBP_MH0 .......................................................................................................................................... 112

XIBP_MH1 .......................................................................................................................................... 113

XIBP_MH2 .......................................................................................................................................... 114

XIBP_D0 ............................................................................................................................................. 114

XIBP_D1 ............................................................................................................................................. 115

XIBP_D2 ............................................................................................................................................. 115

XIBP_D3 ............................................................................................................................................. 116

XPAUSE_RX_DA_MS ........................................................................................................................ 116

XPAUSE_RX_DA_LS ......................................................................................................................... 117

XPAUSE_RX_LENGTH_TYPE .......................................................................................................... 117

XPAUSE_RX_OPCODE..................................................................................................................... 118

XP_EGR_PKT_DROP_CTL ............................................................................................................... 118

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Section 7: Ingress Pipeline Registers ........................................................................... 119

AUX_ARB_CONTROL ........................................................................................................................119

ING_HW_RESET_CONTROL_1.........................................................................................................120

ING_HW_RESET_CONTROL_2.........................................................................................................120

L2_AGE_TIMER..................................................................................................................................121

PER_PORT_AGE_CONTROL............................................................................................................122

ING_CONFIG ......................................................................................................................................123

DOS_CONTROL .................................................................................................................................124

DOS_CONTROL_2 .............................................................................................................................125

VLAN_CTRL........................................................................................................................................125

HASH_CONTROL...............................................................................................................................126

UDF_ETHERTYPE_MATCH...............................................................................................................128

UDF_IPPROTO_MATCH ....................................................................................................................128

PER_PORT_REPL_CONTROL ..........................................................................................................129

L2_MOD_FIFO_CNT...........................................................................................................................129

L2_ENTRY_PARITY_CONTROL........................................................................................................130

L2_ENTRY_PARITY_STATUS ...........................................................................................................130

L3_DEFIP_CAM_ENABLE..................................................................................................................131

L3_ENTRY_PARITY_CONTROL........................................................................................................132

L3_ENTRY_PARITY_STATUS ...........................................................................................................132

L3_DEFIP_PARITY_CONTROL .........................................................................................................133

L3_DEFIP_PARITY_STATUS.............................................................................................................133

CNG_MAP...........................................................................................................................................134

BCAST_STORM_CONTROL..............................................................................................................135

MCAST_STORM_CONTROL .............................................................................................................136

DLF_STORM_CONTROL ...................................................................................................................137

PROTOCOL_PKT_CONTROL............................................................................................................138

CPU_CONTROL_1 .............................................................................................................................140

ING_IPMC_PTR_CTRL.......................................................................................................................142

FP_SLICE_ENABLE ...........................................................................................................................143

FP_CAM_CONTROL_UPPER............................................................................................................146

FP_CAM_CONTROL_LOWER ...........................................................................................................147

FP_SLICE_CONFIG............................................................................................................................148

FP_F4_SELECT..................................................................................................................................150

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FP_METER_CONTROL ..................................................................................................................... 152

UNKNOWN_UCAST_BLOCK_MASK................................................................................................. 152

UNKNOWN_MCAST_BLOCK_MASK ................................................................................................ 153

BCAST_BLOCK_MASK...................................................................................................................... 153

MIRROR_CONTROL.......................................................................................................................... 154

EMIRROR_CONTROL ....................................................................................................................... 155

SFLOW_ING_THRESHOLD............................................................................................................... 155

SFLOW_EGR_THRESHOLD ............................................................................................................. 156

COS_SEL ........................................................................................................................................... 156

EGR_MTU_SIZE ................................................................................................................................ 157

HIGIG_TRUNK_GROUP .................................................................................................................... 158

HIGIG_TRUNK_CONTROL................................................................................................................ 159

EPC_LINK_BMAP .............................................................................................................................. 160

BKP_DISC_BMAP .............................................................................................................................. 160

HOL_STAT_BMAP ............................................................................................................................. 161

CPU_CONTROL_2............................................................................................................................. 162

SFLOW_ING_RAND_SEED............................................................................................................... 163

SFLOW_EGR_RAND_SEED ............................................................................................................. 163

HOLD_COS_PORT_SELECT ............................................................................................................ 164

HOLD_COS[0:7] ................................................................................................................................. 164

CPU_PRIORITY_SEL......................................................................................................................... 165

CPU_COS_SEL.................................................................................................................................. 166

RDBGC[0:8]_SELECT ........................................................................................................................ 167

IPMC_MTU_CONFIG ......................................................................................................................... 169

IPMC_L3_MTU_[0:7] .......................................................................................................................... 169

IPMC_L2_MTU_[0:7] .......................................................................................................................... 170

ING_MISC_CONFIG........................................................................................................................... 170

USER_TRUNK_HASH_SELECT........................................................................................................ 171

Section 8: Ingress (Hi) Pipeline Registers.....................................................................172

IE2E_CONTROL................................................................................................................................. 172

HG_LOOKUP...................................................................................................................................... 173

E2E_HOL_RX_DA_MS ...................................................................................................................... 174

E2E_HOL_RX_DA_LS ....................................................................................................................... 174

E2E_HOL_RX_LENGTH_TYPE......................................................................................................... 175

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E2E_HOL_RX_OPCODE....................................................................................................................175

E2E_IBP_RX_DA_MS.........................................................................................................................176

E2E_IBP_RX_DA_LS..........................................................................................................................176

E2E_IBP_RX_LENGTH_TYPE...........................................................................................................177

E2E_IBP_RX_OPCODE .....................................................................................................................177

ICONTROL_OPCODE_BITMAP.........................................................................................................178

IUNKNOWN_UCAST_BLOCK_MASK................................................................................................178

IUNKNOWN_MCAST_BLOCK_MASK................................................................................................179

IBCAST_BLOCK_MASK .....................................................................................................................179

IMIRROR_CONTROL .........................................................................................................................180

IEMIRROR_CONTROL.......................................................................................................................180

ICOS_SEL...........................................................................................................................................181

IMIRROR_BITMAP..............................................................................................................................181

Section 9: Egress Pipeline Registers ............................................................................ 182

EGR_HW_RESET_CONTROL_0 .......................................................................................................182

EGR_HW_RESET_CONTROL_1 .......................................................................................................183

EGR_PORT.........................................................................................................................................184

EGR_VLAN_CONTROL_1..................................................................................................................185

EGR_CONFIG.....................................................................................................................................186

EGR_CONFIG_1.................................................................................................................................187

EGR_IPMC_CFG2 ..............................................................................................................................188

EGR_PORT_L3UC_MODS.................................................................................................................189

EGR_TUNNEL_CONTROL.................................................................................................................190

EGR_TUNNEL_ID_MASK...................................................................................................................190

EGR_TUNNEL_PIMDR1_CFG0 .........................................................................................................191




EGR_RSPAN_VLAN_TAG..................................................................................................................193

EGR_ENABLE.....................................................................................................................................194

EGR_SHAPING_CONTROL...............................................................................................................194

TDBGC[0:11]_SELECT.......................................................................................................................195

Section 10: Egress (Hi) Pipeline Registers ................................................................... 197

IEGR_PORT........................................................................................................................................197

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IEGR_PORT_L3UC_MODS ............................................................................................................... 198

Section 11: BroadSAFE Registers .................................................................................199

BSAFE_GLB_TIMER.......................................................................................................................... 199

BSAFE_GLB_PRESCALE.................................................................................................................. 200

BSAFE_GLB_UHSM_CFG................................................................................................................. 201

BSAFE_GLB_PROD_CFG ................................................................................................................. 202

BSAFE_GLB_DEV_STATUS ............................................................................................................. 203

BSAFE_GLB_CMD_CTRL ................................................................................................................. 204

BSAFE_GLB_CMD_DATA_IN............................................................................................................ 205

BSAFE_GLB_CMD_DATA_OUT........................................................................................................ 205

BSAFE_GLB_INT_CTRL.................................................................................................................... 206

Section 12: Memory Management Unit (MMU) Registers.............................................207

IBPPKTSETLIMIT ............................................................................................................................... 207

IBPPKTCOUNT .................................................................................................................................. 208

IBPCELLSETLIMIT ............................................................................................................................. 208

IBPDISCARDSETLIMIT...................................................................................................................... 209

IBPCELLCOUNT ................................................................................................................................ 209

E2EIBPPKTSETLIMIT ........................................................................................................................ 210

E2EIBPPKTCOUNT............................................................................................................................ 210

E2EIBPCELLSETLIMIT ...................................................................................................................... 211

E2EIBPDISCARDSETLIMIT ............................................................................................................... 211

E2EIBPCELLCOUNT.......................................................................................................................... 212

BKPMETERINGCONFIG.................................................................................................................... 213

BKPMETERINGBUCKET ................................................................................................................... 214

HOLCOSPKTSETLIMIT...................................................................................................................... 215

CNGCOSPKTLIMIT0 .......................................................................................................................... 216

CNGCOSPKTLIMIT1 .......................................................................................................................... 217

COSPKTCOUNT ................................................................................................................................ 218

LWMCOSCELLSETLIMIT................................................................................................................... 219

COSLCCOUNT................................................................................................................................... 220

DYNCELLLIMIT .................................................................................................................................. 221

DYNCELLCOUNT............................................................................................................................... 222

XQEMPTY .......................................................................................................................................... 223

EGRESSCELLREQUESTCOUNT...................................................................................................... 224

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XQCOSARBSEL .................................................................................................................................224

WRRWEIGHTS ...................................................................................................................................225

EGRDROPPKTCOUNT.......................................................................................................................226

CNGDROPCOUNT0 ...........................................................................................................................226

CNGDROPCOUNT1 ...........................................................................................................................227

IPMCREPLICATIONCOUNT...............................................................................................................228

ASFPORTSPEED ...............................................................................................................................229

MINBUCKETCONFIG .........................................................................................................................230

MINBUCKET .......................................................................................................................................231

MAXBUCKETCONFIG ........................................................................................................................232

MAXBUCKET ......................................................................................................................................233

EGRMETERINGCONFIG....................................................................................................................234

EGRMETERINGBUCKET ...................................................................................................................235

XQPARITYERRORPTR ......................................................................................................................235

IBPBKPSTATUS .................................................................................................................................236

E2EIBPBKPSTATUS...........................................................................................................................236

BKPMETERINGSTATUS ....................................................................................................................237

IBPDISCSTATUS................................................................................................................................237

E2EIBPDISCSTATUS .........................................................................................................................238

BKPMETERINGDISCSTATUS............................................................................................................238

RXE2EIBPBKPSTATUS......................................................................................................................239

HOLCOSSTATUS ...............................................................................................................................239

CFAPCONFIG.....................................................................................................................................240

CFAPREADPOINTER.........................................................................................................................240

CFAPFULLTHRESHOLD....................................................................................................................241

PKTAGINGTIMER...............................................................................................................................241

PKTAGINGLIMIT.................................................................................................................................242

MISCCONFIG......................................................................................................................................243

E2ECONFIG........................................................................................................................................245

ASFCONFIG........................................................................................................................................247

IPV4IPMCIDXINCONFIG ....................................................................................................................249

TOTALDYNCELLLIMIT .......................................................................................................................250

TOTALDYNCELLUSED ......................................................................................................................250

CMICMINTIMER..................................................................................................................................251

CMICTXCOSMASK.............................................................................................................................251

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MMUPORTENABLE ........................................................................................................................... 252

EGRTXPKTCTRCONFIG[7:0] ............................................................................................................ 253

EGRTXPKTCTR[7:0] .......................................................................................................................... 254

MEMFAILINTMASK ............................................................................................................................ 255

MEMFAILINTSTATUS ........................................................................................................................ 256

CBPCELLCRCERRPTR ..................................................................................................................... 257

CBPCELLHDRPARITYERRPTR ........................................................................................................ 257

CBPPKTHDRPARITYERRPTR .......................................................................................................... 258

SOFTRESETPBM............................................................................................................................... 258

IPMCREPOVERLMTPBM .................................................................................................................. 259

XQPARITYERRORPBM ..................................................................................................................... 259

CFAPPARITYERRORPTR ................................................................................................................. 260

CCPPARITYERRORPTR ................................................................................................................... 260

Section 13: GbE Port Internal PHY Registers ...............................................................261

Register Map............................................................................................................................................. 262

MII CONTROL .................................................................................................................................... 263

MIISTATUS......................................................................................................................................... 264

AUTONEGADV................................................................................................................................... 265

AUTONEGLINKPARTNERABILITY.................................................................................................... 266

AUTONEGEXPANSION ..................................................................................................................... 267

EXTENDEDSTATUS .......................................................................................................................... 267

1000XCONTROL1 .............................................................................................................................. 268

1000XCONTROL2 .............................................................................................................................. 270

1000XCONTROL3 .............................................................................................................................. 271

1000XCONTROL4 .............................................................................................................................. 273

1000XSTATUS1 ................................................................................................................................. 274

1000XSTATUS2 ................................................................................................................................. 275

1000XSTATUS3 ................................................................................................................................. 276

ANALOG_TX ...................................................................................................................................... 277

ANALOG_RX_1 .................................................................................................................................. 278

BLOCKADDRESS .............................................................................................................................. 279

Section 14: XG Port Internal PHY Registers..................................................................280

IEEE_CONTROL1 .............................................................................................................................. 281

IEEE_STATUS1.................................................................................................................................. 282

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IEEE_SPEED_ABILITY.......................................................................................................................282

IEEE_CONTROL 2..............................................................................................................................283

IEEE_STATUS2 ..................................................................................................................................284

TX_ACONTROL..................................................................................................................................285

RX_STATUS .......................................................................................................................................286

BLOCKADDRESS...............................................................................................................................287

Section 15: Gigabit Port Statistics (Counters) ............................................................. 288

Overview....................................................................................................................................................288

GbE Receive Counters Table...................................................................................................................288

GbE Transmit Counters Table .................................................................................................................291

Section 16: XG Port Statistics (Counters)..................................................................... 294

HiGig+™ Port Statistics Counters ..........................................................................................................294

HiGig+ Transmit Counters Table.........................................................................................................294

HiGig+ Receive Counters Table..........................................................................................................296

Section 17: Miscellaneous Counters............................................................................. 299

L3 Packet Counters ..................................................................................................................................299

General Packet Counters .........................................................................................................................301

MMU Packet Counters..............................................................................................................................303

Section 18: Switching Memories ................................................................................... 307

Memory Map..............................................................................................................................................307

Memory Tables..........................................................................................................................................309

L2_ENTRY Table–L2X........................................................................................................................309

L2_ENTRY_ONLY Table.....................................................................................................................311

L2_HITDA_ONLY Table ......................................................................................................................313

L2_HITSA_ONLY Table ......................................................................................................................313

L2_USER_ENTRY Table ....................................................................................................................314

L2_USER_ENTRY_ONLY Table.........................................................................................................315

L2_USER_ENTRY_DATA_ONLY Table .............................................................................................316

L2_MOD_FIFO Table ..........................................................................................................................317

L2MC Table .........................................................................................................................................317

PORT Table–PORT_TAB....................................................................................................................318

IPORT_TABLE Table ..........................................................................................................................320

NONUCAST_TRUNK_BLOCK_MASK Table......................................................................................322

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PORT_TRUNK_EGRESS Table–TRUNK_EGR_MASK .................................................................... 322

EGRESS_MASK Table–EGR_MASK................................................................................................. 323

SRC_MODID_BLOCK ........................................................................................................................ 323

ALTERNATE_EMIRROR_BITMAP..................................................................................................... 324

PORT_MAC_BLOCK Table–MAC_BLOCK........................................................................................ 324

VLAN_PROTOCOL Table .................................................................................................................. 325

VLAN_PROTOCOL_DATA Table....................................................................................................... 326

VLAN_SUBNET Table ........................................................................................................................ 326

VLAN_SUBNET_ONLY Table ............................................................................................................ 327

VLAN_SUBNET_DATA_ONLY Table................................................................................................. 327

VLAN_MAC Table............................................................................................................................... 328

VLAN_XLATE Table ........................................................................................................................... 329

VLAN_XLATE_ONLY Table ............................................................................................................... 329

VLAN_XLATE_DATA_ONLY Table.................................................................................................... 330

VLAN Table–VLAN_TAB .................................................................................................................... 330

VLAN_STG Table–STG_TAB............................................................................................................. 331

EGR_VLAN Table............................................................................................................................... 332

EGR_VLAN_STG Table ..................................................................................................................... 333

EGR_VLAN_XLATE Table ................................................................................................................. 335

EGR_VLAN_XLATE_ONLY Table...................................................................................................... 336

EGR_VLAN_XLATE_DATA_ONLY Table .......................................................................................... 336

TRUNK_GROUP Table ...................................................................................................................... 337

TRUNK_BITMAP Table ...................................................................................................................... 338

MODPORT_MAP Table...................................................................................................................... 338

DSCP_TABLE Table........................................................................................................................... 339

EGR_DSCP_TABLE Table................................................................................................................. 339

EGR_DSCP_ECN_MAP..................................................................................................................... 339

EGR_IP_TUNNEL Table .................................................................................................................... 340

L3_TUNNEL Table.............................................................................................................................. 341

L3_ENTRY_ONLY Table .................................................................................................................... 342

L3_ENTRY_IPV4_UNICAST Table .................................................................................................... 343

L3_ENTRY_IPV4_MULTICAST Table................................................................................................ 344

L3_ENTRY_IPV6_UNICAST Table .................................................................................................... 345

L3_ENTRY_IPV6_MULTICAST Table................................................................................................ 346

L3_ENTRY_VALID_ONLY Table........................................................................................................ 348

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L3_IPMC Table....................................................................................................................................348

L3_DEFIP Table ..................................................................................................................................349

L3_DEFIP_ONLY Table ......................................................................................................................350

L3_DEFIP_DATA_ONLY Table...........................................................................................................351

L3_ENTRY_HIT_ONLY Table.............................................................................................................352

L3_DEFIP_HIT_ONLY Table ..............................................................................................................352

L3_ECMP Table ..................................................................................................................................352

EGR_L3_NEXT_HOP Table ...............................................................................................................353

EGR_L3_INTF Table...........................................................................................................................353

ING_L3_NEXT_HOP Table.................................................................................................................354

IPV6_PROXY_ENABLE......................................................................................................................354

LPORT.................................................................................................................................................355

IPMC_GROUP0 Table–MMU_IPMC_GROUP_TBL0 .........................................................................356








IPMC_VLAN Table–MMU_IPMC_VLAN_TBL.....................................................................................360

IM_MTP_INDEX Table ........................................................................................................................360

EM_MTP_INDEX Table.......................................................................................................................361

EGR_IM_MTP_INDEX Table ..............................................................................................................361

EGR_EM_MTP_INDEX Table.............................................................................................................361

SOURCE_TRUNK_MAP Table–SOURCE_TRUNK_MAP_TABLE ....................................................362

E2E_HOL_STATUS Table ..................................................................................................................362

BSAFE_CMD_DATA_IN Table ...........................................................................................................362

BSAFE_CMD_DATA_OUT Table .......................................................................................................363

UDF_OFFSET Table–FP_UDF_OFFSET...........................................................................................363

FP_PORT_FIELD_SEL Table .............................................................................................................364

IFP_PORT_FIELD_SEL Table ............................................................................................................367

FP_RANGE_CHECK Table.................................................................................................................369

FP_TCAM Table..................................................................................................................................370

FP_TCAM_PLUS_POLICY Table .......................................................................................................371

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FP_POLICY_TABLE Table................................................................................................................. 375

FP_METER_TABLE Table ................................................................................................................. 378

FP_COUNTER_TABLE Table ............................................................................................................ 378

Section 19: DMA, Interrupts, and Endianess ................................................................379

PCI Interrupts ........................................................................................................................................... 379

Packet Data Transfer ............................................................................................................................... 382

DMA Operations ................................................................................................................................. 382

CoS Based DMA Receive (RX)—DMA Memory Write ................................................................ 382

DMA Registers.................................................................................................................................... 383

CMIC_DMA_CTRL—DMA Control Register................................................................................ 383

CMIC_DMA_STAT—Status and Control Register ...................................................................... 383

DMA Descriptors................................................................................................................................. 383

DMA Alignment Requirements............................................................................................................ 387

DMA Programming ............................................................................................................................. 388

DMA Transmit (Transmit)............................................................................................................. 388

DMA Receive (RX) ...................................................................................................................... 389

Cancelling an Active DMA Operation.................................................................................................. 393

Interrupt Driven DMA Programming.................................................................................................... 394

Counter Data Transfer ............................................................................................................................. 395

Counter DMA Registers ...................................................................................................................... 396

DMA Buffer Organization .................................................................................................................... 397

Port Selection...................................................................................................................................... 397

Address Configuration ........................................................................................................................ 397

Timer Modes ....................................................................................................................................... 398

Interrupts............................................................................................................................................. 399

Table Data Transfer (Table DMA)....................................................................................................... 399

Hardware Endian Modes .................................................................................................................... 399

Data Transfer Types 400

Swapping Requirements.............................................................................................................. 400

Swap Modes ................................................................................................................................ 400

Endian Select Register ................................................................................................................ 401

Section 20: CMIC 2-Wire Serial Interface (I2C Compatible)..........................................402

I2C Slave Only Mode ................................................................................................................................ 402

I2C Write Protocol ............................................................................................................................... 402

I2C Read Protocol ............................................................................................................................... 402

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Random Read .....................................................................................................................................402

Read at Current Address.....................................................................................................................402

Continuous Burst Read .......................................................................................................................403

CPU Controlled Master / Slave Mode ......................................................................................................403

CMIC_I2C_SLAVE_ADDR (PCI_MBAR + 0x120) ..............................................................................403

For 7-bit Addressing .....................................................................................................................403

For 10-bit Addressing ...................................................................................................................404

CMIC_I2C_XADDR (PCI_MBAR + 0x130) .........................................................................................404

CMIC_I2C_DATA = PCI_MBAR + 0x124............................................................................................404

CMIC_I2C_CTRL = PCI_MBAR + 0x128 ............................................................................................405

IEN ...............................................................................................................................................405

ENAB............................................................................................................................................405

STA ..............................................................................................................................................405

STP ..............................................................................................................................................405

IFLG .............................................................................................................................................405

AAK ..............................................................................................................................................406

CMIC_I2C_STAT (PCI_MBAR + 0x12C) ............................................................................................406

CCR Register (PCI_MBAR + 0x12C) ..................................................................................................407

Bus Clock Speed..........................................................................................................................408

Clock Synchronization..................................................................................................................408

Bus Arbitration..............................................................................................................................408

Operating Modes ......................................................................................................................................408

Master Transmit...................................................................................................................................408

Master Receive....................................................................................................................................410

Slave Transmit.....................................................................................................................................412

Slave Receive......................................................................................................................................412

Section 21: LED Interface ............................................................................................... 414

Purpose of LED Interface.........................................................................................................................414

LED Serial Port..........................................................................................................................................414

LED Processor ..........................................................................................................................................417

Host Interface ......................................................................................................................................417

Processor Architecture ........................................................................................................................418

Program Space....................................................................................................................................418

Data Space..........................................................................................................................................419

Register Set.........................................................................................................................................420

Address Modes....................................................................................................................................420

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Subroutines......................................................................................................................................... 421

Instruction Set ..................................................................................................................................... 421

PORT and PUSHST Instructions................................................................................................. 422

PUSH Instruction ......................................................................................................................... 422

POP Instruction............................................................................................................................ 422

TAND, TOR, TXOR, TINV Instructions........................................................................................ 422

PACK Instruction ......................................................................................................................... 423

SEND Instruction ......................................................................................................................... 423

JT and JNT Instructions............................................................................................................... 424

Opcode Maps...................................................................................................................................... 424

LED Processor Tools ............................................................................................................................... 427

Assembler ........................................................................................................................................... 427

Disassembler ...................................................................................................................................... 427

Simulator............................................................................................................................................. 427

Example Programs................................................................................................................................... 427

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LIST OF FIGURES

1: Messaging Registers ....................................................................................................................................64

2: Packet Data DMA Mechanism ....................................................................................................................391

3: Packet Data DMA Transmit Mechanism .....................................................................................................392

4: Packet Data DMA Receive Mechanism ......................................................................................................393

5: S-Channel DMA Access .............................................................................................................................395

6: Counter Blocks............................................................................................................................................398

7: LED_CLK/LED_DATA Phase Relationship ................................................................................................414

8: LED_CLK/LED_DATA Refresh Interval ......................................................................................................415

9: LED_CLK/LED_DATA Refresh Interval ......................................................................................................415

10: LED_DATA Sync Bit Decode....................................................................................................................416

11: LED Processor Host Interface ..................................................................................................................418

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LIST OF TABLES

Table 1: VENDOR ID.......................................................................................................................................... 4

Table 2: COMMAND/STATUS ........................................................................................................................... 5

Table 3: CLASS CODE, REVISION ID............................................................................................................... 7

Table 4: HEADER TYPE, LATENCY TIMER, CACHELINE SIZE...................................................................... 7

Table 5: BASE ADDRESS LOW ........................................................................................................................ 8

Table 6: BASE ADDRESS HIGH........................................................................................................................ 9

Table 7: SUBSYSTEM, SUBSYSTEM VENDOR ID .......................................................................................... 9

Table 8: INTERRUPT, MAX LATENCY, MIN GRANT ..................................................................................... 10

Table 9: RETRY, TRDY TIMEOUT .................................................................................................................. 10

Table 10: CMIC_SCHAN_MESSAGE (CMIC_SCHAN_MESSAGE_EXT) ...................................................... 11

Table 11: CMIC_SCHAN_CTRL ...................................................................................................................... 12

Table 12: CMIC_SCHAN_ERR ........................................................................................................................ 13

Table 13: CMIC_SCHAN_ERR ........................................................................................................................ 14

Table 14: CMIC_DMA_STAT ........................................................................................................................... 16

Table 15: CMIC_CONFIG ................................................................................................................................ 18

Table 16: CMIC_DMA_DESC .......................................................................................................................... 20

Table 17: CMIC_I2C_SLAVE_ADDR ............................................................................................................... 20

Table 18: CMIC_I2C_DATA ............................................................................................................................. 21

Table 19: CMIC_I2C_CTRL ............................................................................................................................. 22

Table 20: CMIC_I2C_CCR ............................................................................................................................... 23

Table 21: CMIC_I2C_STAT.............................................................................................................................. 24

Table 22: CMIC_I2C_SLAVE_XADDR............................................................................................................. 25

Table 23: CMIC_I2C_RESET........................................................................................................................... 25

Table 24: CMIC_LINK_STAT ........................................................................................................................... 26

Table 25: CMIC_IRQ_STAT............................................................................................................................. 27

Table 26: CMIC_IRQ_MASK............................................................................................................................ 29

Table 27: CMIC_MIIM_PARAM........................................................................................................................ 30

Table 28: CMIC_MIIM_READ_DATA............................................................................................................... 32

Table 29: CMIC_SCAN_PORTS ...................................................................................................................... 32

Table 30: CMIC_STAT_DMA_SETUP ............................................................................................................. 33

Table 31: CMIC_STAT_DMA_ADDR ............................................................................................................... 33

Table 32: CMIC_STAT_DMA_PORTS............................................................................................................. 34

Table 33: CMIC_STAT_DMA_CURRENT........................................................................................................ 34

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Table 34: CMIC_ENDIANESS_SEL .................................................................................................................35

Table 35: CMIC_DEV_REV_ID ........................................................................................................................35

Table 36: CMIC_COS_CTRL_RX.....................................................................................................................36

Table 37: CMIC_TAP_CONTROL ....................................................................................................................37

Table 38: CMIC_RATE_ADJUST .....................................................................................................................38

Table 39: CMIC_SBUS_RING_MAP ................................................................................................................39

Table 40: CMIC_TABLE_DMA_PCIMEM_START_ADDR ...............................................................................40

Table 41: CMIC_TABLE_DMA_SBUS_START_ADDR....................................................................................40

Table 42: CMIC_TABLE_DMA_ENTRY_COUNT.............................................................................................41

Table 43: CMIC_TABLE_DMA_CFG................................................................................................................41

Table 44: CMIC_TABLE_DMA_CUR_ENTRY_SBUS_ADDR..........................................................................42

Table 45: CMIC_SLAM_DMA_PCIMEM_START_ADDR.................................................................................42

Table 46: CMIC_SLAM_DMA_SBUS_START_ADDR .....................................................................................43

Table 47: CMIC_SLAM_DMA_ENTRY_COUNT ..............................................................................................43

Table 48: CMIC_SLAM_DMA_CFG .................................................................................................................44

Table 49: CMIC_SLAM_DMA_CUR_ENTRY_SBUS_ADDR ...........................................................................45

Table 50: CMIC_STAT_DMA_ING_STATS_CFG ............................................................................................45

Table 51: CMIC_STATS_DMA_EGR_STATS_CFG ........................................................................................46

Table 52: CMIC_STAT_DMA_MAC_STATS_CFG...........................................................................................47

Table 53: CMIC_STAT_DMA_PORT_TYPE_MAP...........................................................................................47

Table 54: CMIC_STAT_DMA_BLKNUM_MAP_7_0.........................................................................................48

Table 55: CMIC_STAT_DMA_BLKNUM_MAP_15_8.......................................................................................48

Table 56: CMIC_STAT_DMA_BLKNUM_MAP_23_16.....................................................................................49

Table 57: CMIC_STAT_DMA_BLKNUM_MAP_31_24.....................................................................................49

Table 58: CMIC_STAT_DMA_PORTNUM_MAP_7_0......................................................................................50

Table 59: CMIC_STAT_DMA_PORTNUM_MAP_15_8....................................................................................50

Table 60: CMIC_STAT_DMA_PORTNUM_MAP_23_16..................................................................................51

Table 61: CMIC_STAT_DMA_PORTNUM_MAP_31_24..................................................................................51

Table 62: CMIC_MIIM_ADDRESS ...................................................................................................................52

Table 63: CMIC_MIIM_PROTOCOL_MAP.......................................................................................................52

Table 64: CMIC_MIIM_PORT_TYPE_MAP......................................................................................................53

Table 65: CMIC_MIIM_INT_SEL_MAP ............................................................................................................53

Table 66: CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0.......................................................................................54

Table 67: CMIC_MIIM_EXT_PHY_ADDR_MAP_7_4.......................................................................................54

Table 68: CMIC_MIIM_EXT_PHY_ADDR_MAP_11_8.....................................................................................55

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Table 69: CMIC_MIIM_EXT_PHY_ADDR_MAP_15_12 .................................................................................. 55





Table 74: CMIC_XGXS_MDIO_CONFIG ......................................................................................................... 58

Table 75: CMIC_SOFT_RESET_REG ............................................................................................................. 59

Table 76: CMIC_XGXS_PLL_CONTROL_1 .................................................................................................... 60

Table 77: CMIC_XGXS_PLL_CONTROL_2 .................................................................................................... 60

Table 78: CMIC_LEDUP_CTRL ....................................................................................................................... 61

Table 79: CMIC_LEDUP_STATUS .................................................................................................................. 61

Table 80: CMIC_LEDUP_PROGRAM_RAM.................................................................................................... 62

Table 81: CMIC_LEDUP_DATA_RAM............................................................................................................. 62

Table 82: S-Channel Message Bit Format Description .................................................................................... 66

Table 83: S-Channel Message Source and Destination Blocks ....................................................................... 67

Table 84: GMACC0 .......................................................................................................................................... 70

Table 85: GMACC1 .......................................................................................................................................... 71

Table 86: GMACC2 .......................................................................................................................................... 72

Table 87: GPCSC............................................................................................................................................. 72

Table 88: GSA0 ................................................................................................................................................ 73

Table 89: GSA1 ................................................................................................................................................ 73

Table 90: MAXFR............................................................................................................................................. 74

Table 91: REVCD............................................................................................................................................. 74

Table 92: GTH_FE_MAC1 ............................................................................................................................... 75

Table 93: GTH_FE_MAC2 ............................................................................................................................... 76

Table 94: GTH_FE_IPGT................................................................................................................................. 77

Table 95: GTHG_FE_IPGR.............................................................................................................................. 78

Table 96: GTH_FE_CLRT................................................................................................................................ 79

Table 97: GTH_FE_MAXF ............................................................................................................................... 79

Table 98: GTH_FE_SUPP................................................................................................................................ 80

Table 99: GTH_FE_EXCESSIVE_DEFER_LIMIT............................................................................................ 81

Table 100: ESA0 .............................................................................................................................................. 81

Table 101: ESA1 .............................................................................................................................................. 82

Table 102: ESA2 .............................................................................................................................................. 82

Table 103: GE_PORT_CONFIG ...................................................................................................................... 83

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Table 104: GE_EGR_PKT_DROP_CTRL ........................................................................................................84

Table 105: PAUSE_CONTROL ........................................................................................................................84

Table 106: MAC_TX_STATUS .........................................................................................................................85

Table 107: GPORT_CONFIG ...........................................................................................................................85

Table 108: GPORT_RSV_MASK......................................................................................................................86

Table 109: GPORT_STAT_UPDATE_MASK ...................................................................................................86

Table 110: GPORT_CNTMAXSIZE ..................................................................................................................87

Table 111: GPORT_TPID .................................................................................................................................87

Table 112: MAC_CTRL.....................................................................................................................................88

Table 113: MAC_XGXS_CTRL.........................................................................................................................89

Table 114: MAC_XGXS_STAT.........................................................................................................................90

Table 115: MAC_CNTMAXSZ ..........................................................................................................................91

Table 116: MAC_TXCTRL ................................................................................................................................92

Table 117: MAC_TXMACSA.............................................................................................................................93

Table 118: MAC_TXMAXSZ .............................................................................................................................93

Table 119: MAC_TXPSETHR...........................................................................................................................94

Table 120: MAC_RXCTRL................................................................................................................................95

Table 121: MAC_RXMACSA ............................................................................................................................96

Table 122: MAC_RXMAXSZ.............................................................................................................................96

Table 123: MAC_RXLSSCTRL.........................................................................................................................97

Table 124: MAC_RXLSSSTAT .........................................................................................................................98

Table 125: XPORT_CONFIG............................................................................................................................99

Table 126: XPAUSE_TX_PKT_XOFF_VAL ...................................................................................................100

Table 127: XPAUSE_WATCHDOG_INIT_VAL ..............................................................................................100

Table 128: XPAUSE_WATCHDOG_THRESH ...............................................................................................101

Table 129: XPAUSE_MH0..............................................................................................................................102

Table 130: XPAUSE_MH1..............................................................................................................................103

Table 131: XPAUSE_MH2..............................................................................................................................104

Table 132: XPAUSE_D0.................................................................................................................................104

Table 133: XPAUSE_D1.................................................................................................................................105

Table 134: XPAUSE_D2.................................................................................................................................105

Table 135: XPAUSE_D3.................................................................................................................................106

Table 136: XHOL_MH0...................................................................................................................................107

Table 137: XHOL_MH1...................................................................................................................................108

Table 138: XHOL_MH2...................................................................................................................................109

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Table 139: XHOL_D0 ..................................................................................................................................... 109

Table 140: XHOL_D1 ..................................................................................................................................... 110

Table 141: XHOL_D2 ..................................................................................................................................... 110

Table 142: XHOL_D3 ..................................................................................................................................... 111

Table 143: XIBP_MH0.................................................................................................................................... 112

Table 144: XIBP_MH1.................................................................................................................................... 113

Table 145: XIBP_MH2.................................................................................................................................... 114

Table 146: XIBP_D0....................................................................................................................................... 114

Table 147: XIBP_D1....................................................................................................................................... 115

Table 148: XIBP_D2....................................................................................................................................... 115

Table 149: XIBP_D3....................................................................................................................................... 116

Table 150: XPAUSE_RX_DA_MS.................................................................................................................. 116

Table 151: XPAUSE_RX_DA_LS................................................................................................................... 117

Table 152: XPAUSE_RX_LENGTH_TYPE.................................................................................................... 117

Table 153: XPAUSE_RX_OPCODE .............................................................................................................. 118

Table 154: XP_EGR_PKT_DROP_CTL......................................................................................................... 118

Table 155: AUX_ARB_CONTROL ................................................................................................................. 119

Table 156: ING_HW_RESET_CONTROL_1.................................................................................................. 120

Table 157: ING_HW_RESET_CONTROL_2.................................................................................................. 120

Table 158: L2_AGE_TIMER........................................................................................................................... 121

Table 159: PER_PORT_AGE_CONTROL..................................................................................................... 122

Table 160: ING_CONFIG ............................................................................................................................... 123

Table 161: DOS_CONTROL .......................................................................................................................... 124

Table 162: DOS_CONTROL_2 ...................................................................................................................... 125

Table 163: VLAN_CTRL................................................................................................................................. 125

Table 164: HASH_CONTROL........................................................................................................................ 126

Table 165: UDF_ETHERTYPE_MATCH........................................................................................................ 128

Table 166: UDF_ETHERTYPE_MATCH........................................................................................................ 128

Table 167: PER_PORT_REPL_CONTROL ................................................................................................... 129

Table 168: L2_MOD_FIFO_CNT.................................................................................................................... 129

Table 169: L2_ENTRY_PARITY_CONTROL................................................................................................. 130

Table 170: L2_ENTRY_PARITY_STATUS .................................................................................................... 130

Table 171: L3_DEFIP_CAM_ENABLE........................................................................................................... 131

Table 172: L3_ENTRY_PARITY_CONTROL................................................................................................. 132

Table 173: L3_ENTRY_PARITY_STATUS .................................................................................................... 132

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Table 174: L3_DEFIP_PARITY_CONTROL...................................................................................................133

Table 175: L3_DEFIP_PARITY_STATUS ......................................................................................................133

Table 176: CNG_MAP ....................................................................................................................................134

Table 177: BCAST_STORM_CONTROL .......................................................................................................135

Table 178: MCAST_STORM_CONTROL.......................................................................................................136

Table 179: DLF_STORM_CONTROL.............................................................................................................137

Table 180: PROTOCOL_PKT_CONTROL .....................................................................................................138

Table 181: CPU_CONTROL_1.......................................................................................................................140

Table 182: ING_IPMC_PTR_CTRL ................................................................................................................142

Table 183: FP_SLICE_ENABLE.....................................................................................................................143

Table 184: FP_CAM_CONTROL_UPPER .....................................................................................................146

Table 185: FP_CAM_CONTROL_LOWER.....................................................................................................147

Table 186: FP_SLICE_CONFIG .....................................................................................................................148

Table 187: FP_F4_SELECT ...........................................................................................................................150

Table 188: FP_METER_CONTROL ...............................................................................................................152

Table 189: UNKNOWN_UCAST_BLOCK_MASK...........................................................................................152

Table 190: UNKNOWN_MCAST_BLOCK_MASK ..........................................................................................153

Table 191: BCAST_BLOCK_MASK................................................................................................................153

Table 192: MIRROR_CONTROL....................................................................................................................154

Table 193: EMIRROR_CONTROL .................................................................................................................155

Table 194: SFLOW_ING_THRESHOLD.........................................................................................................155

Table 195: SFLOW_EGR_THRESHOLD .......................................................................................................156

Table 196: COS_SEL .....................................................................................................................................156

Table 197: EGR_MTU_SIZE ..........................................................................................................................157

Table 198: HIGIG_TRUNK_GROUP ..............................................................................................................158

Table 199: HIGIG_TRUNK_CONTROL..........................................................................................................159

Table 200: EPC_LINK_BMAP ........................................................................................................................160

Table 201: BKP_DISC_BMAP ........................................................................................................................160

Table 202: HOL_STAT_BMAP .......................................................................................................................161

Table 203: CPU_CONTROL_2.......................................................................................................................162

Table 204: SFLOW_ING_RAND_SEED.........................................................................................................163

Table 205: SFLOW_EGR_RAND_SEED .......................................................................................................163

Table 206: HOLD_COS_PORT_SELECT ......................................................................................................164

Table 207: CPU_PRIORITY_SEL...................................................................................................................165

Table 208: CPU_COS_SEL............................................................................................................................166

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Table 209: RDBGC[0:8]_SELECT.................................................................................................................. 167

Table 210: IPMC_MTU_CONFIG................................................................................................................... 169

Table 211: IPMC_L3_MTU_[0:7].................................................................................................................... 169

Table 212: IPMC_L2_MTU_[0:7].................................................................................................................... 170

Table 213: ING_MISC_CONFIG .................................................................................................................... 170

Table 214: USER_TRUNK_HASH_SELECT ................................................................................................. 171

Table 215: IE2E_CONTROL .......................................................................................................................... 172

Table 216: HG_LOOKUP ............................................................................................................................... 173

Table 217: E2E_HOL_RX_DA_MS ................................................................................................................ 174

Table 218: E2E_HOL_RX_DA_LS................................................................................................................. 174

Table 220: E2E_IBP_RX_DA_MS.................................................................................................................. 176

Table 221: E2E_IBP_RX_DA_LS................................................................................................................... 176

Table 222: E2E_IBP_RX_LENGTH_TYPE.................................................................................................... 177

Table 223: E2E_IBP_RX_OPCODE .............................................................................................................. 177

Table 224: ICONTROL_OPCODE_BITMAP .................................................................................................. 178

Table 225: IUNKNOWN_UCAST_BLOCK_MASK ......................................................................................... 178

Table 226: IUNKNOWN_MCAST_BLOCK_MASK......................................................................................... 179

Table 227: IBCAST_BLOCK_MASK .............................................................................................................. 179

Table 228: IMIRROR_CONTROL .................................................................................................................. 180

Table 229: IEMIRROR_CONTROL ................................................................................................................ 180

Table 230: ICOS_SEL.................................................................................................................................... 181

Table 231: IMIRROR_BITMAP....................................................................................................................... 181

Table 232: EGR_HW_RESET_CONTROL_0 ................................................................................................ 182

Table 233: EGR_HW_RESET_CONTROL_1 ................................................................................................ 183

Table 234: EGR_PORT.................................................................................................................................. 184

Table 235: EGR_VLAN_CONTROL_1........................................................................................................... 185

Table 236: EGR_CONFIG.............................................................................................................................. 186

Table 237: EGR_CONFIG_1.......................................................................................................................... 187

Table 238: EGR_IPMC_CFG2 ....................................................................................................................... 188

Table 239: EGR_PORT_L3UC_MODS.......................................................................................................... 189

Table 240: EGR_TUNNEL_CONTROL.......................................................................................................... 190

Table 241: EGR_TUNNEL_ID_MASK............................................................................................................ 190

Table 242: EGR_TUNNEL_PIMDR1_CFG0 .................................................................................................. 191



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Table 245: EGR_TUNNEL_PIMDR2_CFG1...................................................................................................192

Table 246: EGR_RSPAN_VLAN_TAG ...........................................................................................................193

Table 247: EGR_ENABLE ..............................................................................................................................194

Table 248: EGR_SHAPING_CONTROL ........................................................................................................194

Table 249: TDBGC[0:11]_SELECT ................................................................................................................195

Table 250: IEGR_PORT .................................................................................................................................197

Table 251: IEGR_PORT_L3UC_MODS .........................................................................................................198

Table 252: BSAFE_GLB_TIMER....................................................................................................................199

Table 253: BSAFE_GLB_PRESCALE............................................................................................................200

Table 254: BSAFE_GLB_UHSM_CFG...........................................................................................................201

Table 255: BSAFE_GLB_PROD_CFG ...........................................................................................................202

Table 256: BSAFE_GLB_DEV_STATUS .......................................................................................................203

Table 257: BSAFE_GLB_CMD_CTRL ...........................................................................................................204

Table 258: BSAFE_GLB_CMD_DATA_IN......................................................................................................205

Table 259: BSAFE_GLB_CMD_DATA_OUT..................................................................................................205

Table 260: BSAFE_GLB_INT_CTRL..............................................................................................................206

Table 261: IBPPKTSETLIMIT .........................................................................................................................207

Table 262: IBPPKTCOUNT ............................................................................................................................208

Table 263: IBPCELLSETLIMIT .......................................................................................................................208

Table 264: IBPDISCARDSETLIMIT................................................................................................................209

Table 265: IBPCELLCOUNT ..........................................................................................................................209

Table 266: E2EIBPPKTSETLIMIT ..................................................................................................................210

Table 267: E2EIBPPKTCOUNT......................................................................................................................210

Table 268: E2EIBPCELLSETLIMIT ................................................................................................................211

Table 269: E2EIBPDISCARDSETLIMIT .........................................................................................................211

Table 270: E2EIBPCELLCOUNT....................................................................................................................212

Table 271: BKPMETERINGCONFIG..............................................................................................................213

Table 272: BKPMETERINGBUCKET .............................................................................................................214

Table 273: HOLCOSPKTSETLIMIT................................................................................................................215

Table 274: CNGCOSPKTLIMIT0 ....................................................................................................................216

Table 275: CNGCOSPKTLIMIT1 ....................................................................................................................217

Table 276: COSPKTCOUNT ..........................................................................................................................218

Table 277: LWMCOSCELLSETLIMIT.............................................................................................................219

Table 278: COSLCCOUNT.............................................................................................................................220

Table 279: DYNCELLLIMIT ............................................................................................................................221

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Table 280: DYNCELLCOUNT ........................................................................................................................ 222

Table 281: XQEMPTY.................................................................................................................................... 223

Table 282: EGRESSCELLREQUESTCOUNT ............................................................................................... 224

Table 283: XQCOSARBSEL .......................................................................................................................... 224

Table 284: WRRWEIGHTS ............................................................................................................................ 225

Table 285: EGRDROPPKTCOUNT................................................................................................................ 226

Table 286: CNGDROPCOUNT0 .................................................................................................................... 226

Table 287: CNGDROPCOUNT1 .................................................................................................................... 227

Table 288: IPMCREPLICATIONCOUNT........................................................................................................ 228

Table 289: ASFPORTSPEED ........................................................................................................................ 229

Table 290: MINBUCKETCONFIG .................................................................................................................. 230

Table 291: MINBUCKET ................................................................................................................................ 231

Table 292: MAXBUCKETCONFIG ................................................................................................................. 232

Table 293: MAXBUCKET ............................................................................................................................... 233

Table 294: EGRMETERINGCONFIG............................................................................................................. 234

Table 295: EGRMETERINGBUCKET ............................................................................................................ 235

Table 296: XQPARITYERRORPTR ............................................................................................................... 235

Table 297: IBPBKPSTATUS .......................................................................................................................... 236

Table 298: E2EIBPBKPSTATUS.................................................................................................................... 236

Table 299: BKPMETERINGSTATUS ............................................................................................................. 237

Table 300: IBPDISCSTATUS......................................................................................................................... 237

Table 301: E2EIBPDISCSTATUS .................................................................................................................. 238

Table 302: BKPMETERINGDISCSTATUS..................................................................................................... 238

Table 303: RXE2EIBPBKPSTATUS............................................................................................................... 239

Table 304: HOLCOSSTATUS ........................................................................................................................ 239

Table 305: CFAPCONFIG.............................................................................................................................. 240

Table 306: CFAPREADPOINTER.................................................................................................................. 240

Table 307: CFAPFULLTHRESHOLD............................................................................................................. 241

Table 308: PKTAGINGTIMER........................................................................................................................ 241

Table 309: PKTAGINGLIMIT.......................................................................................................................... 242

Table 310: MISCCONFIG............................................................................................................................... 243

Table 311: E2ECONFIG................................................................................................................................. 245

Table 312: ASFCONFIG................................................................................................................................. 247

Table 313: IPV6IPMCIDXINCONFIG ............................................................................................................. 247

Table 314: IPV4IPMCIDXINCONFIG ............................................................................................................. 249

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Table 315: TOTALDYNCELLLIMIT.................................................................................................................250

Table 316: TOTALDYNCELLUSED................................................................................................................250

Table 317: CMICMINTIMER ...........................................................................................................................251

Table 318: CMICTXCOSMASK ......................................................................................................................251

Table 319: MMUPORTENABLE .....................................................................................................................252

Table 320: EGRTXPKTCTRCONFIG[7:0] ......................................................................................................253

Table 321: EGRTXPKTCTR[7:0] ....................................................................................................................254

Table 322: MEMFAILINTMASK ......................................................................................................................255

Table 323: MEMFAILINTSTATUS ..................................................................................................................256

Table 324: CBPCELLCRCERRPTR ...............................................................................................................257

Table 325: CBPCELLHDRPARITYERRPTR ..................................................................................................257

Table 326: CBPPKTHDRPARITYERRPTR ....................................................................................................258

Table 327: SOFTRESETPBM.........................................................................................................................258

Table 328: IPMCREPOVERLMTPBM ............................................................................................................259

Table 329: XQPARITYERRORPBM ...............................................................................................................259

Table 330: CFAPPARITYERRORPTR ...........................................................................................................260

Table 331: CCPPARITYERRORPTR .............................................................................................................260

Table 332: GbE Port Internal PHY Register Map ...........................................................................................262

Table 333: CONTROL ....................................................................................................................................263

Table 334: MIISTATUS...................................................................................................................................264

Table 335: AUTONEGADV.............................................................................................................................265

Table 336: AUTONEGLINKPARTNERABILITY..............................................................................................266

Table 337: AUTONEGEXPANSION ...............................................................................................................267

Table 338: EXTENDEDSTATUS ....................................................................................................................267

Table 339: 1000XCONTROL1 ........................................................................................................................268

Table 340: 1000XCONTROL2 ........................................................................................................................270

Table 341: 1000XCONTROL3 ........................................................................................................................271

Table 342: 1000XCONTROL4 ........................................................................................................................273

Table 343: 1000XSTATUS1 ...........................................................................................................................274

Table 344: 1000XSTATUS2 ...........................................................................................................................275

Table 345: 1000XSTATUS3 ...........................................................................................................................276

Table 346: ANALOG_TX ................................................................................................................................277

Table 347: ANALOG_RX_1 ............................................................................................................................278

Table 348: BLOCKADDRESS ........................................................................................................................279

Table 349: Internal PHY Register Addresses .................................................................................................280

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Table 350: Register Map ................................................................................................................................ 280

Table 351: IEEE_CONTROL1........................................................................................................................ 281

Table 352: IEEE_STATUS1 ........................................................................................................................... 282

Table 353: IEEE_SPEED_ABILITY................................................................................................................ 282

Table 354: IEEE_CONTROL 2....................................................................................................................... 283

Table 355: IEEE_STATUS2 ........................................................................................................................... 284

Table 356: TX_ACONTROL........................................................................................................................... 285

Table 357: RX_STATUS ................................................................................................................................ 286

Table 358: BLOCKADDRESS........................................................................................................................ 287

Table 359: GbE Receive Counters Table....................................................................................................... 288

Table 360: GbE Transmit Counters Table...................................................................................................... 291

Table 361: HiGig+ Transmit Counters Table.................................................................................................. 294

Table 362: HiGig+ Receive Counters Table................................................................................................... 296

Table 363: L3 Packet Counters ...................................................................................................................... 299

Table 364: General Packet Counters ............................................................................................................. 301

Table 365: MMU Packet Counters ................................................................................................................. 303

Table 366: Memory Map................................................................................................................................. 307

Table 367: L2_ENTRY Table–L2X................................................................................................................. 310

Table 368: L2_ENTRY_ONLY........................................................................................................................ 311

Table 369: L2_HITDA_ONLY......................................................................................................................... 313

Table 370: L2_HITSA_ONLY ......................................................................................................................... 313

Table 371: L2_USER_ENTRY ....................................................................................................................... 314

Table 372: L2_USER_ENTRY_ONLY............................................................................................................ 315

Table 373: L2_USER_ENTRY_DATA_ONLY ................................................................................................ 316

Table 374: L2_MOD_FIFO............................................................................................................................. 317

Table 375: L2MC............................................................................................................................................ 317

Table 376: PORT Table–PORT_TAB............................................................................................................. 318

Table 377: IPORT_TABLE ............................................................................................................................. 320

Table 378: NONUCAST_TRUNK_BLOCK_MASK......................................................................................... 322

Table 379: PORT_TRUNK_EGRESS Table–TRUNK_EGR_MASK.............................................................. 322

Table 380: EGRESS_MASK Table–EGR_MASK .......................................................................................... 323

Table 381: SRC_MODID_BLOCK.................................................................................................................. 323

Table 382: ALTERNATE_EMIRROR_BITMAP.............................................................................................. 324

Table 383: PORT_MAC_BLOCK Table–MAC_BLOCK ................................................................................. 324

Table 384: VLAN_PROTOCOL ...................................................................................................................... 325

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Table 385: VLAN_PROTOCOL_DATA...........................................................................................................326

Table 386: VLAN_SUBNET ............................................................................................................................326

Table 387: VLAN_SUBNET_ONLY ................................................................................................................327

Table 388: VLAN_SUBNET_DATA_ONLY.....................................................................................................327

Table 389: VLAN_MAC...................................................................................................................................328

Table 390: VLAN_XLATE ...............................................................................................................................329

Table 391: VLAN_XLATE_ONLY ...................................................................................................................329

Table 392: VLAN_XLATE_DATA_ONLY........................................................................................................330

Table 393: VLAN Table–VLAN_TAB ..............................................................................................................330

Table 394: VLAN_STG Table–STG_TAB.......................................................................................................331

Table 395: EGR_VLAN...................................................................................................................................332

Table 396: EGR_VLAN_STG .........................................................................................................................333

Table 397: EGR_VLAN_XLATE .....................................................................................................................335

Table 398: EGR_VLAN_XLATE_ONLY..........................................................................................................336

Table 399: EGR_VLAN_XLATE_DATA_ONLY ..............................................................................................336

Table 400: TRUNK_GROUP ..........................................................................................................................337

Table 401: TRUNK_BITMAP ..........................................................................................................................338

Table 402: MODPORT_MAP..........................................................................................................................338

Table 403: DSCP_TABLE...............................................................................................................................339

Table 404: EGR_DSCP_TABLE.....................................................................................................................339

Table 405: EGR_DSCP_ECN_MAP...............................................................................................................339

Table 406: EGR_IP_TUNNEL ........................................................................................................................340

Table 407: L3_TUNNEL..................................................................................................................................341

Table 408: L3_ENTRY_ONLY ........................................................................................................................342

Table 409: L3_ENTRY_IPV4_UNICAST ........................................................................................................343

Table 410: L3_ENTRY_IPV4_MULTICAST....................................................................................................344

Table 411: L3_ENTRY_IPV6_UNICAST ........................................................................................................345

Table 412: L3_ENTRY_IPV6_MULTICAST....................................................................................................346

Table 413: L3_ENTRY_VALID_ONLY............................................................................................................348

Table 414: L3_IPMC .......................................................................................................................................348

Table 415: L3_DEFIP .....................................................................................................................................349

Table 416: L3_DEFIP_ONLY..........................................................................................................................350

Table 417: L3_DEFIP_DATA_ONLY ..............................................................................................................351

Table 418: L3_ENTRY_HIT_ONLY ................................................................................................................352

Table 419: L3_DEFIP_HIT_ONLY..................................................................................................................352

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Table 420: L3_ECMP ..................................................................................................................................... 352

Table 421: EGR_L3_NEXT_HOP .................................................................................................................. 353

Table 422: EGR_L3_INTF.............................................................................................................................. 353

Table 423: ING_L3_NEXT_HOP.................................................................................................................... 354

Table 424: IPV6_PROXY_ENABLE ............................................................................................................... 354

Table 425: LPORT.......................................................................................................................................... 355

Table 426: IPMC_GROUP0 Table–MMU_IPMC_GROUP_TBL0 .................................................................. 356








Table 434: IPMC_VLAN Table–MMU_IPMC_VLAN_TBL.............................................................................. 360

Table 435: IM_MTP_INDEX ........................................................................................................................... 360

Table 436: EM_MTP_INDEX.......................................................................................................................... 361

Table 437: EGR_IM_MTP_INDEX ................................................................................................................. 361

Table 438: EGR_EM_MTP_INDEX................................................................................................................ 361

Table 439: SOURCE_TRUNK_MAP Table–SOURCE_TRUNK_MAP_TABLE ............................................. 362

Table 440: E2E_HOL_STATUS ..................................................................................................................... 362

Table 441: BSAFE_CMD_DATA_IN .............................................................................................................. 362

Table 442: BSAFE_CMD_DATA_OUT .......................................................................................................... 363

Table 443: UDF_OFFSET Table–FP_UDF_OFFSET.................................................................................... 363

Table 444: FP_PORT_FIELD_SEL ................................................................................................................ 364

Table 445: Intelligent Protocol-Aware Selector Encoding .............................................................................. 365

Table 446: IFP_PORT_FIELD_SEL............................................................................................................... 367

Table 447: Intelligent Protocol-Aware Selector Encoding .............................................................................. 368

Table 448: FP_RANGE_CHECK.................................................................................................................... 369

Table 449: FP_TCAM..................................................................................................................................... 370

Table 450: FP_TCAM_PLUS_POLICY .......................................................................................................... 371

Table 451: FP_POLICY_TABLE .................................................................................................................... 375

Table 452: FP_METER_TABLE ..................................................................................................................... 378

Table 453: FP_COUNTER_TABLE................................................................................................................ 378

Table 454: PCI Interrupts ............................................................................................................................... 379

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Table 455: DMA Control Block Format ...........................................................................................................384

Table 456: DMA Control Block Fields .............................................................................................................385

Table 457: Transmit DCB Special Functions ..................................................................................................388

Table 458: Receive DCB Special Functions ...................................................................................................389

Table 459: Counter DMA Resources ..............................................................................................................396

Table 460: Counter DMA Buffer Organization ................................................................................................397

Table 461: Data Transfer Types .....................................................................................................................400

Table 462: CMIC I2C Control Registers .........................................................................................................403

Table 463: CMIC I2C Slave Addresses...........................................................................................................404

Table 464: CMIC I2C Extended Slave Addresses ..........................................................................................404

Table 465: CMIC I2C Interrupt Control Bits.....................................................................................................405

Table 466: CMIC I2C Status Codes ................................................................................................................406

Table 467: CCR Register Bits.........................................................................................................................407

Table 468: STAT Register Status Codes and Meanings ................................................................................409

Table 469: STAT Register Status Return Codes ............................................................................................409

Table 470: STAT Register IFLG Return Codes ..............................................................................................410

Table 471: STAT Register Status Codes and Meanings (Master Receive)....................................................410

Table 472: STAT Register Status Return Codes (Master Receive)................................................................411

Table 473: STAT Register IFLG Return Codes (Master Receive) ..................................................................411

Table 474: LED_CLK/LED_DATA Timing Specifications................................................................................416

Table 475: Designated DMA RAM Locations .................................................................................................419

Table 476: Per-Port Status Bits ......................................................................................................................419

Table 477: Address Modes .............................................................................................................................420

Table 478: Address Mode Examples ..............................................................................................................420

Table 479: Opcodes 0x00 to 0x7F..................................................................................................................424

Table 480: Opcodes 0x80 to 0xFF..................................................................................................................425

Table 481: Instruction Opcode Encoding........................................................................................................425

Table 482: Instruction Field Encoding.............................................................................................................426

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Section 1: Introduction

OVERVIEW

This document describes the register and bit description information of the StrataXGS® BCM56500 Gigabit Ethernet (GbE)Multilayer Switch device. This document is applicable to the following devices (B0 and later revisions only): BCM56500,BCM56501, BCM56502, BCM56503, BCM56504, BCM56505, BCM56506, BCM56507, BCM56508, and BCM56509.

Multiple StrataXGS devices may be used to build large switches, such as chassis-based and stackable switches. Thescalable, module StrataXGS architecture allows these systems to seamlessly share a single consistent feature set.

AUDIENCE

This document is intended primarily for system architects and programmers, as it describes the bit descriptions for each ofthe BCM56500 registers.

RELATED DOCUMENTATION

The Theory of Operations document includes a full description of all functionality. It also includes a feature list, architecturalinformation, packet flow and programming details, as well as system configurations. Each StrataXGS device has a datasheet that describes the hardware aspects (system interfaces, signal definitions, and device characteristics) of that device.In addition, there are numerous Application Notes and other documents that describe various aspects of the BCM56500device.

All official documentation is available on Broadcom’s secure online document system, DocSAFE (http://support.broadcom.com/). Contact your sales representative for information regarding docSAFE access.

NOTATIONS AND CONVENTIONS

The following notational conventions are used in this document:

• Signal names are shown in UPPERCASE letters. For example: DATA.

• A bar over a signal name indicates that it is active low. For example: CE.

• In register descriptions, [n:m] indicates a range from bit n to bit m. For example: [7:0] indicates bits 7 through 0,inclusive.

• Use of leading 0x indicates a hexadecimal number. For example: 0x03F.

• Use of leading 0b indicates a binary number. For example: 0b00100111.

• The use of R, RSVD, or RESERVED indicates that a bit or field is reserved by Broadcom for future use. Typically, R orRSVD is used for individual bits, and RESERVED is used for fields.

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ADDRESS CONVENTIONS

The following address conventions are used in this document:

• For register addresses, a p within a hexidecimal address uniquely identifies a port in the entire chip as follows:

- 0x0–0x0a indicates a GPIC number 11, identifying one of the twelve 10/100/1000-Mbit Ports 1–24, twelve in ablock. For example, register address 0x0pp80018 represents register addresses 0x00080018 (GPIC0) to0x00a80018 (GPIC11).

- 0x18–0x1B indicates the IPIC number (0 to 3) identifying one of the four 10-Gbit Ports 1–4.

- 0x1C indicates the Host CPU Port.

• For register addresses, a g within a hexidecimal address indicates a block number (0 or 1). For example, registeraddress 0x00g0p100 represents register addresses 0x0000p100 (block 0) to 0x 0x0010p100 (block 1).

• For register addresses, a q within a hexidecimal address indicates a CoS number (0 to 7). For example, registeraddress 0x00D0000q represents register addresses 0x00D00000 (CoS0) to 0x00D00007 (CoS7).

Several registers and tables include one or more port bitmaps. These bitmaps are 12, 14, or 32 bits wide. In all cases, onlythe bits listed below are used. Unused bits in status registers should be ignored on a read and should be written as a 0.

[28] CMIC (CPU port)

[24, 25, 26, 27] IPIC (XG ports, bit 24 = XG Port 1)

[23:0] 1000-Mbit ports 1–24 (bit 0 = Port 1)

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Section 2: PCI Configuration Registers

PCI CONFIGURATION SPACE

The BCM56500 supports a subset of the configuration registers described in the PCI specifications. These registers allowdevice relocation, device independent system address map construction, and automatic configuration.

The configuration register space occupies 256 bytes. During the configuration cycles, the value on the address bus (AD[7:0])specifies a register. Reading of unimplemented registers returns a value of 0’s.

The StrataXGS device is detected by probing for all devices with VENDOR ID = 0x14E4 and DEVICE ID = B50X. For otherStrataXGS devices, refer to “PCI Configuration Space” on page 3 for the StrataXGS device and for the DEVICE ID for thatStrataXGS device.

Offset [31:24] [23:16] [15:8] [7:0]

0x0 DEVICE ID = VENDOR ID = 0x14E4

0x4 COMMAND/STATUS

0x8 CLASS CODE = 0x2800 REVISION ID

0xC BUILT-IN SELF TEST HEADER TYPE LATENCY TIMER CACHE LINE SIZE

0x10 BASE ADDRESS LOW

0x14 BASE ADDRESS HIGH

0x18–28 RESERVED

0x2C SUBSYSTEM ID = 0x0000 SUBSYSTEM VENDOR ID = 0x0000

0x30–38 RESERVED

0x3C MAX LATENCY = 0x0 MIN GRANT = 0x0 INTERRUPT PIN = 1 INTERRUPT LINE

0x40 RESERVED TRDY TIMEOUT RETRY COUNT

Note: In x86 or Pentium® systems that have a PCI BIOS, the memory base address may be assigned to thedevice automatically. System software should check that the mapping assigned by the BIOS is usable, and if not,provide checks to avoid resource conflicts in the event that mapping needs to be preconfigured.

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VENDOR ID

Register description: Vendor ID

Register offset: 0x00

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DEVICE_ID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VENDOR_ID

Table 1: VENDOR ID

Bit Name R/W Description Default

31:16 DEVICE_ID RO Hardwired to identify the BCM56500 device 0xB50X

15:0 VENDOR_ID RO Hardwired to 0x14E4 to identify Broadcom as the vendor 0x14E4

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COMMAND/STATUS

Register description: PCI command and status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

See bit description below

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

See bit description below

Table 2: COMMAND/STATUS


31 PARITY_ERR_DETECTED

R/Wa A parity error is detected.0 = Parity Error has not occurred.1 = Parity Error has occurred.

0

30 SYSTEM_ERR R/Wa A system error is detected and signalled on PCI_SERR.

0 = System error not signalled on PCI_SERR.1 = System error is signalled on PCI_SERR.

0

29 MASTER_ABORT_RECEIVED

R/Wa A transaction on the PCI bus terminated with a Master Abort.0 = Cycle terminated normally.1 = Cycle terminated with a Master Abort.

0

28 TARGET_ABORT_RECEIVED

R/Wa A transaction initiated by the device as a Master was terminated with a Target Abort.0 = Master Cycle terminated normally.1 = Master Cycle terminated with a Target Abort.

0

27 TARGET_ABORT_GENERATED

R/Wa The BCM56500 terminated the transaction on the PCI bus with a Target Abort.0 = Target Cycle terminated normally.1 = Target Cycle terminated with a Target Abort.

0

26:25 PCI_DEVSEL_TIMING RO Hardwired to 0b01 to indicate medium PCI_DVSEL timing. 0b01

24 DATA_PARITY_ERR_DETECT

R/Wa A parity error has been detected and signaled on PCI_PERR.0 = Parity Error has not occurred.1 = Parity Error has occurred.

0

23 FAST_B2B_ENA R/W Hardwired to 1 to indicate that the BCM56500 as a target can accept back-to-back transactions.

1

22 RESERVED RO Reserved 0

21 66MHZ_ENA R/W Hardwired to 1 to indicate that the BCM56500 is capable of supporting 66-MHz PCI bus timing.0 = Disabled1 = Enabled

1

20:10 RESERVED RO Reserved 0

9 FAST_B2B_MASTR_ENA

R/W Allows the device to perform fast back-to-back transactions.0 = Disabled1 = Enabled

8 SYS_ERROR_ENA R/W Allows the device to signal system errors on PCI_SERR output.0 = Disabled1 = Enabled

0


6 PARITY_ERROR_ENA R/W Allows the device to signal parity errors on PCI_PERR output.0 = Disabled1 = Enabled

0


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4 MEM_WRITE_INVALIDATE

R/W Allows the device to generate Memory Write and Invalidate commands.0 = Disabled1 = Enabled

0

3 RESERVED RO Reserved –

2 BUS_MASTER_ENA R/W Allows the device to be a bus master. 0

1 MEM_ACCESS_ENA R/W Memory access enable. Allows the device to respond to PCI memory access cycles as a target.

0


a. Writing a 1 to the bit position clears the bit.

Table 2: COMMAND/STATUS


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CLASS CODE, REVISION ID

HEADER TYPE, LATENCY TIMER, CACHELINE SIZE

Register description: Class code and revision ID


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BASE_CLASS SUB_CLASS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PROG_INTF REVISION_ID

Table 3: CLASS CODE, REVISION ID


31:24 BASE_CLASS RO Hardwired to 0x02 to identify a network controller class. 0x02

23:16 SUB_CLASS RO Hardwired to 0x80 to identify other network controllers. 0x80

15:8 PROG_INTF RO Hardwired to 0x00 (PCI does not specify for BASE_CLASS = 02). 0x00

7:0 REVISION_ID RO Device revision A0: 0x01A1: 0x02B0: 0x11B1: 0x12

Register description: Header type, latency timer, and cacheline size

Register offset: 0x0C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BIST HEADER_TYPE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATENCY_TIMER CACHELINE_SZ

Table 4: HEADER TYPE, LATENCY TIMER, CACHELINE SIZE


31:24 BIST RO Not supported 0x00

23:16 HEADER_TYPE RO Hardwired to 0x00 to indicate a single-function device. 0x00

15:8 LATENCY_TIMER R/W Controls the amount of time the device, as a bus master, can perform burst transfers when another master requests the bus. Bits [9:8] are hardwired to 2’b00, yielding interval increments of four PCI bus clocks.

0x00

7:0 CACHLINE_SZ R/W Cacheline size in units of 32-bit words. Set during initialization. 0x00

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BASE ADDRESS LOW

The device supports 64-bit PCI addressing. This is done via support for the PCI Dual Address Cycle, allowing a 64-bitaddress to be communicated on a 32-bit bus. However, only bits [39:0] of the 64-bit address are decoded. This registerdefines bits [31:0] and the register “BASE ADDRESS HIGH” defines bits [39:32].

Register description: PCI base address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BASE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PREF TYPE MSI

Table 5: BASE ADDRESS LOW


31:16 BASE R/W Address programmed by the host to map the device to a base address in the system memory space.

0x0000

15:4 RESERVED RO Reserved 0x000

3 PREF RO Hardwired to 0, indicating that prefetching is not supported. 0

2:1 TYPE RO Hardwired to 0b10, indicating that the mapped memory can be located anywhere in the 64-bit address space.

0b10

0 MSI RO Memory Space Indicator that is hardwired to 0, indicating that the requested space is reserved for memory transactions.

0

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BASE ADDRESS HIGH

The device supports 64-bit PCI addressing. This is done via support for the PCI Dual Address Cycle, allowing a 64-bitaddress to be communicated on a 32-bit bus. However, only bits [39:0] of the 64-bit address are decoded. This registerdefines bits [39:32], and the register BASE ADDRESS LOW defines bits [31:0].

SUBSYSTEM, SUBSYSTEM VENDOR ID

Register description: PCI base address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BASE_ADDR

Table 6: BASE ADDRESS HIGH


31:8 RESERVED RO This field always returns a value of 0, indicating that address bits [63:40] are not decoded.

0x000

7:0 BASE_ADDR R/W This field defines bits [39:32] of the address to which the device should respond. This is programmed by the host to configure the memory mapped address of the device.

0x0000

Note: For 32-bit PCI access, this register must be programmed to 0.

Register description: Subsystem and subsystem vendor ID


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SUBSYSTEM_ID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SUBSYSTEM_VENDOR_ID

Table 7: SUBSYSTEM, SUBSYSTEM VENDOR ID


31:16 SUBSYSTEM_ID RO Hardwired to 0x0000 0x0000

15:0 SUBSYSTEM_VENDOR_ID RO Hardwired to 0x0000 0x0000

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INTERRUPT, MAX LATENCY, MIN GRANT

RETRY, TRDY TIMEOUT

Register description: Interrupt, maximum latency, minimum grant


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MAX_LATENCY MIN_GRANT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTERRUPT_PIN INTERRUPT_LINE

Table 8: INTERRUPT, MAX LATENCY, MIN GRANT


31:24 MAX_LATENCY RO Hardwired to 0x00. This is the maximum latency of a PCI access, in units of 250 ns. 0x00

23:16 MIN_GRANT RO Length of burst period required, in units of 250 ns. 0x00

15:8 INTERRUPT_PIN RO Hardwired to 0x01, indicating that PCI_INTA is used for interrupt signaling. 0x01

7:0 INTERRUPT_LINE R/W Maps the device’s interrupt pin to the specified interrupt line on the system interrupt controller.

0x00

Register description: Retry, Target Ready timeout


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RETRY TRDY_TIMEOUT

Table 9: RETRY, TRDY TIMEOUT



15:8 RETRY R/W Hardwired to 0x80, indicating that the device, as a PCI bus master, performs 128 retry operations before terminating the cycle.

0x80

7:0 TRDY_TIMEOUT R/W Hardwired to 0x80, indicating that the device, as a PCI bus master, waits 128 PCI clocks after initiating a cycle for TRDY input.

0x80

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Section 3: CMIC RegistersThe BCM56500 contains a set of registers mapped directly to the host system’s memory address space. These registersare at a fixed offset from the base address programmed into the PCI Configuration register. These registers indicate variousstatus conditions, such as DMA, ARL buffer, error conditions, and so on. They also configure/control DMA operations (table,stats) and S-channel messages, which are used to program Indirect Mapped registers and tables.

CMIC_SCHAN_MESSAGE (CMIC_SCHAN_MESSAGE_EXT)

There are twenty CMIC_SCHAN_MESSAGE registers mapped from 0x0000 to 0x004C, and there are twenty-twoCMIC_SCHAN_MESSAGE_EXT registers mapped to 0x0800 to 0x0854. The CMIC_SCHAN_MESSAGE_EXT registersare aliased to CMIC_SCHAN_MESSAGE registers; both point to the same internal locations. Some internal tables/memories require twenty-two CMIC_SCHAN_MESSAGE registers for access.

The CMIC_SCHAN_MESSAGE_EXT registers are recommended for all usage. However, CMIC_SCHAN_MESSAGEregisters remain valid, but they cannot be used to access tables that require twenty-two 32-bit buffers.

Register description: CMIC S-channel message

Register offset: 0x0000–0x004C or 0x0800–0x084C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Table 10: CMIC_SCHAN_MESSAGE (CMIC_SCHAN_MESSAGE_EXT)


31:0 DATA R/W S-channel data word. The CPU can conditionally read or write these registers. Undefined

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CMIC_SCHAN_CTRL

The CMIC_SCHAN_CTRL register reports the status of various operations and conditions inside the device. Some bits mustbe explicitly cleared by the CPU. To set or reset these bits, write a value to the lowest significant byte (bits 7–0) of thisregister. The bit position, specified by [4:0], indicates which bit to modify. The new bit value is specified by bit [7].

Register description: S-channel control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED TIME_OUT

NACK RESERVED MIIM_OP_

DONE

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV MIIM_SCAN_BUSY

RESERVED PCI_PARITYERROR

PCI_FATAL_

ERR

LINK_STAT_CHG

RESERVED MSG_DONE

MSG_START

Table 11: CMIC_SCHAN_CTRL


31:23 RESERVED Reserved 0x00

22 TIMEOUT RO 0 = No S-bus timeout1 = The last S-bus operation resulted in a TIMEOUT (that is, no ACK was received by CMIC within the TIMEOUT interval specified in CMIC_SBUS_TIMEOUT register).This bit is cleared when bit 1 (MSG_DONE) is set or a new S-channel message is started.

0

21 NACK RO 0 = For L2/L3 insert/delete commands, the S-channel message was completed1 = For L2/L3 insert/delete commands, the S-channel message was not completedThis bit is cleared when bit 1 (MSG_DONE) is set or a new S-channel message is started.

0


18 MIIM_OP_DONE RO 0 = In progress1 = MIIM operation completed

0


14 MIIM_SCAN_BUSY RO 0 = Not busy1 = MIIM scan in progress

0


10 PCI_PARITY_ERR RO 0 = No error detected1 = PCI parity error detected

0

9 PCI_FATAL_ERR RO 0 = No error1 = PCI fatal error detected

0

8 LINK_STAT_CHG RO 0 = No link status change1 = Link status change

0


1 MSG_DONE RO 0 = In progress1 = Message done

0

0 MSG_START RO Message start 0

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CMIC_SCHAN_ERR

Register description: S-channel error


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OPCODE DST_PORT SRC_PORT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SRC_PORT DATA_LEN ERRBIT RESERVED NACK

Table 12: CMIC_SCHAN_ERR


31:26 OPCODE R/W Opcode in the S-channel error ACK message0x07 = MEM_RD—Memory read, S1 = Address

0x08 = MEM_RD_ACK—Memory read ACK, S1... = Data0x09 = MEM_WR—Memory write, S1 = Address, S2... = Data0x0A = MEM_WR_ACK—Memory write ACK

0x0B = REG_RD—Register read, S1 = Address0x0C = REG_RD_ACK—egister read ACK, S1 = Data0x0D = REG_WR—Register write, S1 = Address, S2 = Data

0x0E = REG_WR_ACK—Register write ACK0x0F = L2_INS—L2 insert, S1... = Entry0x10 = L2_INS_ACK—L2 insert ACK

0x11 = L2_DEL—L2 delete, S1... = Entry0x12 = L2_DEL_ACK—L2 delete ACK0x1A = L3_INS—L3 insert, S1... = Entry

0x1B = L3_INS_ACK—L3 insert ACK0x1C = L3_DEL—L3 delete, S1... = Entry0x1D = L3_DEL_ACK—L3 delete ACK

0x20 = FB_L2_LKUP—Firebolt L2 lookup, S1... = Key0x21 = FB_L2_LKUP_ACK—Firebolt L2 lookup ACK, S1... = Key0x22 = FB_L3_LKUP—Firebolt L3 lookup, S1... = Key

0x23 = FB_L3_LKUP_ACK—Firebolt L3 lookup ACK, S1... = Key

0x0

25:20 DST_PORT R/W Destination port in the S-channel error ACK message 0x0

19:14 SRC_PORT R/W Source port in the S-channel error ACK message (not guaranteed for all blocks) 0x0

13:7 DATA_LEN R/W Data length of the S-channel error ACK message 0x0

6 ERRBIT R/W Error Bit0 = An error did not occur in the last S-channel command.1 = The last S-channel command resulted in an error (that is, an illegal command or invalid address).

0


0 NACK R/W No acknowledge

0 = ACK received.1 = Last S-channel message resulted in a NACK.

0

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CMIC_DMA_CTRL

Register description: DMA control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CH3_DROP_

RX

RESERVED CH3_SEL_INTR

CH3_ABORT_DMA

RESV CH3_DIR

CH2_DROP_

RX


CH2_ABORT_DMA

RESV CH2_DIR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CH1_DROP_

RX


CH1_ABORT_DMA

RESV CH0_DIR

CH0_DROP_

RX


CH0_ABORT_DMA

RESV CH0_DIR

Table 13: CMIC_SCHAN_ERR


31 CH3_DROP_RX_

PKT_ON_CHAIN_END

R/W DMA channel setting for packets received after hitting the end of a chain (that is, no descriptors available).0 = Block, waiting for descriptor to be available1 = Drop the packet

0


27 CH3_SEL_INTR R/W DMA channel interrupt select0 = After packet1 = After descriptor

0

26 CH3_ABORT_DMA R/W DMA channel abort0 = Normal operation1 = Abort DMA

0


24 CH3_DIR R/W DMA channel direction0 = SoC to Memory1 = Memory to SoC

0

23 CH2_DROP_RX_PKT_ON_CHAIN_END


0


19 CH2_SEL_INTR R/W DMA channel interrupt select

0 = After packet1 = After descriptor

0


0


16 CH2_DIR R/W DMA channel direction

0 = SoC to memory1 = Memory to SoC

0


R/W DMA channel setting for packets received after hitting the end of a chain (that is, no descriptors available).

0 = Block, waiting for descriptor to be available1 = Drop the packet

0



0

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0


8 CH1_DIR R/W DMA channel direction0 = SoC to memory1 = Memory to SoC

0



0



0


0


0 CH0_DIR R/W DMA channel direction0 = SoC to memory1 = Memory to SoC

0

Table 13: CMIC_SCHAN_ERR (Cont.)


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CMIC_DMA_STAT

Register description: DMA status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCI_FATAL_ERR PCI_PARITY_ERR CH3_DMA_

ACTIVE

CH2_DMA_

ACTIVE

CH1_DMA_

ACTIVE

CH0_DMA_

ACTIVE

STATS_DMA_

ACTIVE

STATS_DMA_ERR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TX_DMA_

ABORT

STATS_DMA_ITER_DONE

STATS_DMA_OPN_

CMPLT

DMA_RESET

CH3_DESC_DONE

CH2_DESC_DONE

CH1_DESC_DONE

CH0_DESC_DONE

CH3_CHAIN_DONE

CH2_CHAIN_DONE

CH1_CHAIN_DONE

CH0_CHAIN_DONE

CH3_DMA_

EN

CH2_DMA_

EN

CH1_DMA_

EN

CH0_DMA_

EN

– BIT_VAL

– BIT_POS

Table 14: CMIC_DMA_STAT


31:27 PCI_FATAL_ERR RO DMA resulting in a PCI fatal error 0x0

26:22 PCI_PARITY_ERR RO DMA resulting in a PCI parity error 0x0

21 CH3_DMA_ACTIVE

RO Channel 3 DMA Active0 = Not active1 = Channel DMA active

0

20 CH2_DMA_ACTIVE


0

19 CH1_DMA_

ACTIVE

RO Channel 1 DMA Active

0 = Not active1 = Channel DMA active

0

18 CH0_DMA_ACTIVE


0

17 STATS_DMA_ACTIVE

RO Stats DMA active0 = Not active1 = Stats DMA active

0

16 STATS_DMA_ERR RO Stats DMA Error

0 = No error1 = Error detected

0

15 TX_DMA_ABORT_NEEDS_CLEANUP

RO Previous TX DMA was aborted in the middle of a packet0 = No error1 = Error detected

0

14 STATS_DMA_ITER_DONE

RO Stats DMA iteration done0 = Not done1 = DMA stats operation completed

0

13 STATS_DMA_

OPN_CMPLT

RO Stats DMA operation complete

0 = Not complete1 = DMA stats operation completed

0

12 DMA_RESET R/W Reset DMA0 = Normal operation1 = Reset the DMA

0

11 CH3_DESC_DONE RO Channel 3 Descriptor done0 = Not done1 = Current DMA descriptor done

0

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10 CH2_DESC_DONE RO Channel 2 Descriptor done0 = Not done1 = Current DMA descriptor done

0

9 CH1_DESC_DONE RO Channel 1 Descriptor done

0 = Not done1 = Current DMA descriptor done

0

8 CH0_DESC_DONE RO Channel 0 descriptor done0 = Not done1 = Current DMA descriptor done

0

7 CH3_CHAIN_DONE RO Channel 3 chain done0 = Not done1 = DMA complete

0


0


0

4 CH0_CHAIN_DONE RO Channel 0 chain done

0 = Not done1 = DMA complete

0

3 CH3_DMA_EN R Set by CPU to start a DMA on CH3 0




7 BIT_VAL WO 0 = Bit specified in BIT_POS is set to 01 = Bit specified in BIT_POS is set to 1

Undefined

4:0 BIT_POS WO Bit position within this register to write Undefined

Table 14: CMIC_DMA_STAT (Cont.)


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CMIC_CONFIG

Register description: CMIC configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED MIIM_ADDR_MAP_

EN

OVER_RIDE_EXT_

MSTR_CTRL

RESV COS_RX_EN

RESV ABORT_STAT_

DMA

STOP_LS_ON_

CHG

RLD_STS_UPD_DIS

SG_RLD_

EN

SG_EN RESV RESET_PCI_EN

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMA_GRBG_COL_

EN

RESV IGNOR_ADDR_ALIGN_

EN

RESV I2C_EN LE_DMA_

EN

UNTAG_EN

UNTAG_ALL_RCV_

EN

SCHAN_ABRT

ACT_LOW_

INT

RESET_CPS

RESV MSTR_Q_

MAX_EN

BE_CHK_

EN

WR_BURST

_EN

RD_BURST

_EN

Table 15: CMIC_CONFIG


31:28 RESERVED R/W Reserved 0

27 MIIM_ADDR_MAP_EN R/W MIIM address map table enable0 = Use PHY_ID as is1 = Use the MDIO address map table to get the PHY_ID from the port number. Used for both read/write and link scan

0

26 OVER_RIDE_EXT_MSTR_CTRL

R/W External MDIO master override0 = Allow an external MDIO master1 = Normal operation

0

25 RESERVED R/W Reserved 0

24 COS_RX_EN R/W Cos Receive

0 = Packet DMA is not based on received CoS1 = Packet DMA is based on received CoS. Multiple write channels can be active.

0


22 ABORT_STAT_DMA R/W Abort Stats DMA0 = Normal operation1 = Abort current stats DMA operation

0

21 STOP_LS_ON_CHG R/W Stop MIIM scan on link status change

0 = Do not stop link scanning on a link status change1 = Stop link scanning upon detection of link status change

0

20 RLD_STS_UPD_DIS R/W Reload status operation0 = Update status fields on reload operations1 = Do not update status fields on reload operations

0

19 SG_RELOAD_EN R/W Scatter/gather reload enable0 = Do not allow scatter/gather reload operation1 = Enable scatter/gather reload operation

0

18 SG_EN R/W Scatter/gather enable

0 = Do not allow scatter/gather operation1 = Allow scatter/gather operation

0


16 RESET_PCI_EN R/W PCI reset enable0 = Do not reset1 = Reset the PCI interface1 = A CPS reset also resets the internal CMIC PCI interface

0

15 DMA_GARBAGE_COLLECT_EN

R/W DMA garbage collection enable0 = CMIC will not collect packets with the purge bit set1 = CMIC collects packets with the purge bit set

0

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13 IGNORE_ADDR_

ALIGN_EN

R/W Ignore address alignment

0 = CMIC DMA (PCI to SoC) must be aligned on an address boundary1 = CMIC DMA (PCI to SoC) is allowed on any address boundary

0


11 I2C_EN R/W I2C enable0 = CMIC PCI access to I2C interface is disabled1 = CMIC PCI access to I2C interface is enabled

0

10 LE_DMA_EN R/W Little-endian enable0 = DMA operations are in big-endian format1 = DMA operations are in little-endian format

0

9 UNTAG_EN R/W Untag enable

0 = CMIC will not remove the tag field1 = CMIC can remove the tag field

0

8 UNTAG_ALL_RCV_EN R/W Untag all0 = Do not remove tags1 = CMIC removes the tag field from all received packets

0

7 SCHAN_ABORT R/W S-channel abort0 = Normal operation1 = CMIC aborts any pending S-channel operation

0

6 ACT_LOW_INT R/W Active low interrupt

0 = Active high interrupts1 = Active low interrupts (default)

1

5 RESET_CPS R/W CPS bus channel reset0 = Normal operation1 = CMIC drives CPS channel reset

0


3 MSTR_Q_MAX_EN R/W PCI master queue enable

0 = CMIC can queue one PCI master request1 = CMIC can queue up to four PCI master requests

0

2 BE_CHK_EN R/W BE check enable0 = CMIC does not support BE checks on PCI writes1 = CMIC supports BE checks on PCI writes

0

1 WR_BRST_EN R/W Write burst enable0 = CMIC does not support PIO write bursts1 = CMIC supports PIO write bursts

0

0 RD_BRST_EN R/W Read burst enable

0 = CMIC does not support PIO read bursts1 = CMIC supports PIO read bursts

1

Table 15: CMIC_CONFIG (Cont.)


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CMIC_DMA_DESC

CMIC_I2C_SLAVE_ADDR

Register description: DMA channel descriptor addresses

Register offset: 0x0110 DMA00x0114 DMA10x0118 DMA20x011C DMA3

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDRESS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESS

Table 16: CMIC_DMA_DESC


31:0 ADDR R/W DMA channel n descriptor address. Undefined

Register description: I2C slave address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ADDRESS GEN_CALL_

EN

Table 17: CMIC_I2C_SLAVE_ADDR



7:1 ADDR R/W The address to which the I2C interface responds as a slave. If the address received is 0xF7–0xF0, then the two LSBs are recognized as SLAX9 and SLAX8 for the extended addressing mode. The value programmed overrides the default value of 0b1000100.

0x44

0 GEN_CALL_EN R/W General call address recognition enable0 = Disable general address call recognition1 = Enable general address call recognition

0

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CMIC_I2C_DATA

Register description: I2C data


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED DATA

Table 18: CMIC_I2C_DATA



7:0 DATA R/W Data that is read from or written to the I2C interface 0x00

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CMIC_I2C_CTRL

Register description: I2C control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED INT_EN

BUS_EN

MM_STRT

MM_STP

INT_FLAG

AAAK RESERVED

Table 19: CMIC_I2C_CTRL



7 INT_EN R/W Controls the interrupt capability due to I2C operations.

0 = Disable interrupts1 = Enable interrupts

0

6 BUS_EN R/W Controls the active state of I2C bus.

0 = Disable I2C bus1 = Enable I2C bus and respond to calls to the slave address and the General Call Address ability.

0

5 MM_STRT R/W Control entering Master mode and sending a START condition on the bus when it is free. This bit is automatically cleared after sending the START condition.0 = Do not enter Master mode1 = Enter Master mode and send a START condition

0

4 MM_STP R/W Controls entering the Master mode and send a STOP condition on the bus when it is free. This bit is automatically cleared after the STOP condition has been sent.0 = Do not enter Master mode1 = Enter Master mode and send a STOP condition

0

3 INT_FLAG R/W Status bit indicating that an interrupt has occurred due to any one of the status conditions, except for the condition code 0xF8. (See “I2C Condition Status Register” for details of condition codes).

0 = No interrupt occurred1 = Interrupt occurred

This bit should be written as a 0 to clear the I2C interrupt.

0

2 AAAK R/W Controls sending an Acknowledge clock pulse, (a low level) on SDA line. If a 7-bit slave address was received, the second byte of a 10-bit address was received, a general call address was received, or a data byte was received or transmitted on the bus.

0 = Do not send the ACK pulse1 = Send the ACK pulse

0


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CMIC_I2C_CCR

Register description: I2C Clock Control. The read-only register, CMIC_I2C_STAT is also accessed. This register is write-only. The seven LSBs control the divider. (The input to the clock divider is FCLK.)

The frequency of the I2C interface is given by:

where:

• F is the clock frequency of the I2C interface.

• M is the value stored in CCR bits 3–6.

• N is the value stored in CCR bits 0–2.

• DIVIDEND is set in CMIC_RATE_ADJUST (see “CMIC_RATE_ADJUST” on page 38).

• DIVISOR is set in CMIC_RATE_ADJUST (see “CMIC_RATE_ADJUST” on page 38).

For the default values of CMIC_RATE_ADJUST, a 100-kHz I2C clock will require that M = 10 andN = 0.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED M N

Table 20: CMIC_I2C_CCR


31:7 RESERVED R/W Reserved 0x000

6:3 M WO M 0x0a

2:0 N WO N 0x0

F 133MHz DIVIDEND×10 DIVISOR M 1+( ) 2 N 1+( )××--------------------------------------------------------------------------------------=

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CMIC_I2C_STAT

Register description: I2C status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CONDITION_CODES RESERVED

Table 21: CMIC_I2C_STAT



7:3 COND RO Condition codes

0x00 = Bus error0x08 = START condition transmitted0x10 = Repeated START condition transmitted0x18 = Address + write bit transmitted, ACK received0x20 = Address + write bit transmitted, ACK not received0x28 = Data byte transmitted in master mode, ACK received0x30 = Data byte transmitted in master mode, ACK not received0x38 = Arbitration lost in address or data byte0x40 = Address + read bit transmitted, ACK received0x48 = Address + read bit transmitted, ACK not received0x50 = Data byte received in master mode, ACK transmitted0x58 = Data byte received in master mode, ACK not transmitted0x60 = Slave address + write bit received, ACK transmitted0x68 = Arbitration lost in address as master, slave address + write bit received, ACK transmitted0x70 = General Call Address received, ACK transmitted0x78 = Arbitration lost in address as master, General Call received, ACK transmitted0x80 = DB_SL_ACK—Data byte received after slave address received, ACK transmitted0x88 = DB_SL_NAK —Data byte received after slave address received, ACK not transmitted0x90 = DB_GC_ACK—Data byte received after General Call received, ACK transmitted0x98 = DB_GC_NAK—Data byte received after General Call received, ACK not transmitted0xA0 = STOP_SL—STOP or repeated START condition received in slave mode0xA8 = SL_RX_ACK—Slave address + read bit received, ACK transmitted0xB0 = SL_RX_NAK—Arbitration lost in address as master, slave address + read bit received, ACK transmitted0xB8 = SL_DB_NAK—Data byte transmitted in slave mode, ACK not received0xC0 = SL_DB_ACK— Data byte transmitted in slave mode, ACK received0xC8 = SL_LB_ACK—Last byte transmitted in slave mode, ACK received0xD0 = SEC_TX_ACK—Second Address byte + write bit transmitted, ACK received0xD8 = SEC_TX_NAK—Second Address byte + write bit transmitted, ACK not received0xE0 = SEC_RX_ACK—Second Address byte + read bit transmitted, ACK received0xE8 = SEC_RX_NAK—Second Address byte + read bit transmitted, ACK not received0xF8 = NO_STAT—No relevant status information, IFLAG = 0.

0x00


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CMIC_I2C_SLAVE_XADDR

CMIC_I2C_RESET

Register description: I2C extended slave address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ADDRESS

Table 22: CMIC_I2C_SLAVE_XADDR



7:0 ADDR R/W Slave address 7–0 for the extended Slave Address mode. When the address received starts with 0xF7–0xF0, the two LSBs are recognized as slave address 9–8 and the content of this register is used as address 0x7–0x0 to form the 10-bit address used in extended addressing mode.

0x00

Register description: I2C soft reset. Access to this register is valid only when CMIC_CONFIG.I2C_EN = 1.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RESET

Table 23: CMIC_I2C_RESET



7:0 RESET WO A write operation to this register with any data performs a soft reset to the I2C interface.

The bus is set to the idle state and the MM_STOP, MM_STRT, and INT_FLAG in the I2C Status and Control register are set to 0.

0x00

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CMIC_LINK_STAT

Register description: Link status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PORT_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 24: CMIC_LINK_STAT


31:0 PORT_BITMAP RO Link status indication0 = Link-down1 = Link-up

0xFFFFFFFF

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CMIC_IRQ_STAT

Register description: CMIC interrupt status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BSAFE_OP_DONE

SLAM_DMA_

CMPLT

TABLE_DMA_

CMPLT

MEM_FAIL

HSE_CMD_MEM_FAIL

CSE_CMD_MEM_FAIL

BSE_CMD_MEM_FAIL

RESERVED STAT_DMA_DONE

MIIM_OP_

DONE

I2C_INTR

SCHAN_ERR

PCI_FATAL_

ERR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCI_PARITY_ERR

CH3_CHAIN_DONE

CH3_DESC_DONE

CH2_CHAIN_DONE

CH2_DESC_DONE

CH1_CHAIN_DONE

CH1_DESC_DONE

CH0_CHAIN_DONE

CH0_DESC_DONE

RESV L2_MOD_FIFO_NOT_

EMPTY

LINK_STAT_MOD

RESERVED SCH_MSG_DONE

Table 25: CMIC_IRQ_STAT


31 BSAFE_OP_DONE RO BroadSAFE™ operation complete

0 = Not complete1 = Complete

0

30 SLAM_DMA_CMPLT RO Slam DMA complete0 = Not complete1 = Complete

0

29 TABLE_DMA_CMPLT RO Table DMA complete0 = Not complete1 = Complete

0

28 MEM_FAIL RO MMU memory failed

0 = Normal operation1 = MMU memory failed

0

27 HSE_CMDMEM_DONE RO HSE command memory complete0 = Not complete1 = Complete

0

26 CSE_CMDMEM_DONE RO CSE command memory complete0 = Not complete1 = Complete

00

25 BSE_CMDMEM_DONE RO BSE command memory complete


0


20 STAT_DMA_DONE RO Stats DMA operation completed0 = Not complete1 = Operation complete.

0

19 MIIM_OP_DONE RO MIIM operation completed

0 = Not complete1 = Operation complete

0

18 I2C_INTR RO I2C interrupt

0 = Normal operation1 = Interrupt

0

17 SCHAN_ERR RO S-channel error detected0 = Normal operation1 = S-channel error detected

0

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16 PCI_FATAL_ERR RO PCI fatal error detected0 = Normal operation1 = Fatal error detected.

0

15 PCI_PARITY_ERR RO PCI parity error detected

0 = Normal operation1 = Parity error detected

0

14 CH3_CHAIN_DONE RO DMA channel 3 end of chain0 = Not the end of chain1 = End of chain

0

13 CH3_DESC_DONE RO DMA channel 3 next descriptor execution complete0 = Not complete1 = Complete

0


0


0

10 CH1_CHAIN_DONE RO DMA channel 1 end of chain

0 = Not the end of chain1 = End of chain

0


0


0

7 CH0_DESC_DONE RO DMA channel 0 next descriptor execution complete


0


5 L2_MOD_FIFO_NOT_EMPTY

RO L2 MOD FIFO0 = Empty1 = Full

0

4 LINK_STAT_MOD RO Link status change

0 = No link status change1 = Link status change

0


0 SCH_MSG_DONE RO SCH Message Operation Complete0 = Operation not complete1 = Operation complete

0

Table 25: CMIC_IRQ_STAT (Cont.)


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CMIC_IRQ_MASK

Register description: CMIC interrupt mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BSAFE_OP_DONE

SLAM_DMA_

CMPLT

TABLE_DMA_

CMPLT

MEM_FAIL

HSE_CMD_MEM_FAIL

CSE_CMD_MEM_FAIL

BSE_CMD_MEM_FAIL

RESERVED STAT_DMA_DONE

MIIM_OP_

DONE

I2C_INTR

SCHAN_ERR

PCI_FATAL_

ERR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCI_PARITY_ERR

CH3_CHAIN_DONE

CH3_DESC_DONE

CH2_CHAIN_DONE

CH2_DESC_DONE

CH1_CHAIN_DONE

CH1_DESC_DONE

CH0_CHAIN_DONE

CH0_DESC_DONE

RESV L2_MOD_FIFO_NOT_

EMPTY

LINK_STAT_MOD

RESERVED SCH_MSG_DONE

Table 26: CMIC_IRQ_MASK


31 BSAFE_OP_DONE R/W BroadSAFE operation complete mask 0

30 SLAM_DMA_CMPLT R/W Slam DMA complete mask 0

29 TABLE_DMA_CMPLT R/W Table DMA complete mask 0

28 MEM_FAIL R/W MMU memory failed mask 0

27 HSE_CMDMEM_DONE R/W HSE command memory complete mask 0

26 CSE_CMDMEM_DONE R/W CSE command memory complete mask 00

25 BSE_CMDMEM_DONE R/W BSE command memory complete mask 0


20 STAT_DMA_DONE R/W Stats DMA operation completed mask 0

19 MIIM_OP_DONE R/W MIIM operation completed mask 0

18 I2C_INTR R/W I2C interrupt mask 0

17 SCHAN_ERR R/W S-channel error detected mask 0

16 PCI_FATAL_ERR R/W PCI fatal error detected mask 0

15 PCI_PARITY_ERR R/W PCI parity error detected mask 0

14 CH3_CHAIN_DONE R/W DMA channel 3 end of chain mask 0

13 CH3_DESC_DONE R/W DMA channel 3 next descriptor execution complete mask 0



10 CH1_CHAIN_DONE RW DMA channel 1 end of chain mask 0





5 L2_MOD_FIFO_NOT_EMPTY

R/W L2 MOD FIFO mask 0

4 LINK_STAT_MOD R/W Link status change mask 0


0 SCH_MSG_DONE R/W SCH Message Operation Complete mask 0

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CMIC_MIIM_PARAM

Register description: MIIM parameter


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MIIM_CYCLE RESERVED INT_SEL

HG_SEL

C45_SEL

PHY_ID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PHY_DATA

Table 27: CMIC_MIIM_PARAM


31:29 MIIM_CYCLE R/W MIIM cycle

This field is used to select which type of MIIM cycle to run. Normally it should just be set to 000.

000: Automatically runs the proper read or write cycle based on the port’s protocol preference, and whether a read or write cycle was requested. If the port is Clause 45 enabled, then the read or write is proceeded by an address cycle.001: Requests a Clause 22 write cycle; use MIIM_WR_REG_EN control010: Requests a Clause 22 read cycle; use MIIM_RD_REG_EN control100: Requests a Clause 45 address cycle; use MIIM_WR_REG_EN control101: Requests a Clause 45 write cycle; use MIIM_WR_REG_EN control110: Requests a Clause 45 read cycle w/addr increment; use MIIM_RD_REG_EN control111: Requests a Clause 45 read cycle; use MIIM_RD_REG_EN control

Undefined

28:24 RESERVED RO Reserved Undefined

23 INT_SEL R/W Internal selection0 = External MDIO bus1 = Internal MDIO bus

Undefined

22 HG_SEL R/W MIIM transaction selection0 = Send transaction on Gigabit Ethernet (GbE) MDIO1 = Send transaction on HiGig+™ MDIO

Undefined

21 C45_SEL R/W Clause 45 select

0 = Clause 221 = Clause 45

Undefined

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20:16 PHY_ID R/W Physical ID to be accessed. Only five bits (LSB 5 bits) are actual PHY-ID bits.0b000000 = (Gig port 0)0b000001 = (Gig port 1)0b000010 = (Gig port 2)0b000011 = (Gig port 3)0b000010 = (Gig port 4)0b000101 = (Gig port 5)0b000110 = (Gig port 6)0b000111 = (Gig port 7)0b001000 = (Gig port 8)0b001001 = (Gig port 9)0b001010 = (Gig port 10)0b001011 = (Gig port 11)0b001100 = (Gig port 12)0b001101 = (Gig port 13)0b001110 = (Gig port 14)0b001111 = (Gig port 15)0b010000 = (Gig port 16)0b010001 = (Gig port 17)0b010010 = (Gig port 18)0b010011 = (Gig port 19)0b010100 = (Gig port 20)0b010101 = (Gig port 21)0b010110 = (Gig port 22)0b010111 = (Gig port 23)0b011000 = (HiGig+/10G port 0)0b011001 = (HiGig+/10G port 1)0b011000 = (HiGig+/10G port 2)0b011011 = (HiGig+/10G port 3)

Undefined

15:0 PHY_DATA R/W Data to be written Undefined

Table 27: CMIC_MIIM_PARAM (Cont.)


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CMIC_MIIM_READ_DATA

CMIC_SCAN_PORTS

Register description: MIIM read data


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Table 28: CMIC_MIIM_READ_DATA



15:0 DATA R/W Contains the data returned as a result of a register read. DATA is valid only if MIIM read operation is done (MIIM_OP_DONE set).

Undefined

Register description: Linkscan port select


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PORT_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 29: CMIC_SCAN_PORTS


31:0 PORT_BITMAP R/W Port bitmap indicating which ports need to be scanned for Link status (link up/dn). Bit 0 indicates GE0, bit 23 indicates GE23, bit 24 indicates HG/XE0, bit 27 indicates HG/XE3, bit 28 indicates the CPU port.

0x00000000

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CMIC_STAT_DMA_SETUP

This register gives the length of duration to wait after all the registers have been read before starting the next counter.

CMIC_STAT_DMA_ADDR

Register description: Statistics DMA set-up


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EN E_T TIME_VAL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

Table 30: CMIC_STAT_DMA_SETUP


31 EN R/W Enable DMA0 = Disable1 = Enable

0

30 E_T R/W Enable timer

0 = Disable1 = Enable

0

29:16 TIME_VAL R/W Timer Value. This timer value is based on a 512-microsecond (µs) interval. The minimum timer value of 0x1 gives 512 µs—0.512 milliseconds (ms)— and the maximum time duration is 8.38 seconds (s).

0x0000


Register description: Statistics DMA address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Table 31: CMIC_STAT_DMA_ADDR


31:0 ADDR R/W Gives the PCI memory address where the counters for each of the ports are DMAed. This starting address gives the pointer for the first port counters. The fixed size in memory for each port counters is 1024 bytes (one-hundred and twenty-eight 64-bit registers). Each port has a fixed offset of 128 × port number from this starting memory address (ADDR). The same addresses are repeatedly written.

Undefined

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CMIC_STAT_DMA_PORTS

CMIC_STAT_DMA_CURRENT

Register description: Statistics DMA port selected


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PORT_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 32: CMIC_STAT_DMA_PORTS


31:0 PORT_BITMAP R/W Port bitmap to enable/disable each port’s counter collection0 = CMIC skips this port1 = CMIC reads the counters for this port

0x00000000

Register description: Statistics DMA current value


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Table 33: CMIC_STAT_DMA_CURRENT


31:0 DATA R/W Address of stats counter currently being processed 0x00000000

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CMIC_ENDIANESS_SEL

CMIC_DEV_REV_ID

Register description: Endian select


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BYTELANE3 BYTELANE2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BYTELANE1 BYTELANE0

Table 34: CMIC_ENDIANESS_SEL


31:24 BYTELANE3 R/W See definition for BYTELANE0. 0x00



7:0 BYTELANE0 R/W Byte Lane n.Each byte lane must carry the same data value, especially the MSB byte and the LSB byte. The various bits in the byte are interpreted as:Bit 2: EN_BIG_ENDIAN_BUS_4_NRM_DMA 0 = Little 1 = Big.Bit 1: EN_BIG_ENDIAN_BUS_4_PKT_DMA 0 = Little 1 = Big for packet DMA operations.

Bit 0: EN_BIG_ENDIAN_BUS_4_PIO 0 = Little 1 = Big for PIO (CPU read/write) operations.

0x00

Register description: CMIC device ID


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED REV_ID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DEV_ID

Table 35: CMIC_DEV_REV_ID



23:16 REV_ID RO Revision ID A0: 0x01A1: 0x02B0: 0x11B1: 0x12

15:0 DEV_ID RO Device ID 0xB50X

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CMIC_COS_CTRL_RX

This register is valid if bit 24 (COS_RX_EN) of the CMIC_CONFIG register is set (1).

For each DMA Receive (RX) channel programmed to be in receive mode (DMA Memory Write = 1), there are eight bits; oneper CoS to select the CoS for which the DMA receive is effective. Software must guarantee that a given CoS is enabled onlyin one DMA channel programmed as a receive channel. This allows multiple receive DMA channels to receive specific CoS-based packets. When COS_RX_EN = 1, this register indicates which CoS types are admitted by the channel.

Register description: CMIC receive CoS control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CH3_COS_BMP CH2_COS_BMP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CH1_COS_BMP CH0_COS_BMP

Table 36: CMIC_COS_CTRL_RX


31:24 CH3_COS_BMP R/W Channel 3 CoS bitmap 0x00




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CMIC_TAP_CONTROL

Register description: CMIC TAP control. Must follow TAP protocol to initiate BIST and read BIST results.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED TDO TRST TCK TMS TDI

Table 37: CMIC_TAP_CONTROL



4 TDO RO TAP data out 0

3 TRST R/W TAP reset 0

2 TCK R/W TAP clock 0

1 TMS R/W Test mode select 0

0 TDI R/W Control data input 0

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CMIC_RATE_ADJUST

Various parts of the device involved in rate control require a constant, known frequency. This reference frequency is basedon the core clock. The core clock frequency is multiplied by the rational quantity (DIVIDEND/DIVISOR) and is further dividedby 2 to produce the actual MDIO operation frequency. To avoid skew, it is recommended that the DIVIDEND value is usuallyset to 1.

The default values are for 133-MHz operation:

• DIVIDEND = 1, DIVISOR = 6,

• MDIO operation frequency = 133 MHz/(6*2) = ~ 11 MHz for 157-MHz core clock chips,

• Set: DIVIDEND = 1, DIVISOR = 6, MDIO operation frequency = 133 MHz/(6*2) = ~ 11 MHz

Register description: CMIC clock rate adjust

Register offset: 0x01B0

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DIVIDEND

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIVISOR

Table 38: CMIC_RATE_ADJUST


31:16 DIVIDENE R/W Numerator of clock scale factor 0x0001

15:0 DIVISOR R/W Denominator of clock scale factor 0x0006

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CMIC_SBUS_RING_MAP

Register description: S-Bus ring map


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RING_NUM_SBUS_ID_15

RING_NUM_SBUS_ID_14

RING_NUM_SBUS_ID_13

RING_NUM_SBUS_ID_12

RING_NUM_SBUS_ID_11

RING_NUM_SBUS_ID_10

RING_NUM_SBUS_ID_9

RING_NUM_SBUS_ID_8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RING_NUM_SBUS_ID_7

RING_NUM_SBUS_ID_6

RING_NUM_SBUS_ID_5

RING_NUM_SBUS_ID_4

RING_NUM_SBUS_ID_3

RING_NUM_SBUS_ID_2

RING_NUM_SBUS_ID_1

RING_NUM_SBUS_ID_0

Table 39: CMIC_SBUS_RING_MAP


31:30 RING_NUM_SBUS_ID_15 R/W S-bus ring number for agent with S-bus ID 15 0x0
















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CMIC_TABLE_DMA_PCIMEM_START_ADDR

CMIC_TABLE_DMA_SBUS_START_ADDR

Register description: Table DMA start address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Table 40: CMIC_TABLE_DMA_PCIMEM_START_ADDR


31:0 ADDR R/W The CPU memory address where the table DMA data are written. Must be aligned on a 4-byte boundary.

Undefined

Register description: Table DMA S-bus start address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Table 41: CMIC_TABLE_DMA_SBUS_START_ADDR


31:0 ADDR R/W Written by the CPU indicating table DMA logical memory start Address. This address has the following fields: table (6b), block (4b) and region+index (20b)

Undefined

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CMIC_TABLE_DMA_ENTRY_COUNT

CMIC_TABLE_DMA_CFG

Register description: Table DMA count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESV COUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

COUNT

Table 42: CMIC_TABLE_DMA_ENTRY_COUNT



23:0 COUNT R/W Specifies the number of table entries to DMA 0x000000

Register description: Table DMA configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BEATS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ERR DONE ABORT EN

Table 43: CMIC_TABLE_DMA_CFG



20:16 BEATS R/W Indicates the number of data beats. For table DMA purposes, each table entry is 32-bit aligned. The widest S-bus table write/read supported is 640 bits. The valid values for this field are 1–20 (beats).

0x00


3 ERR R/W Table DMA transfer was aborted due to an error (most probably due to a NACK). Can be cleared (but not set) by the CPU.

0

2 DONE R/W Table DMA complete. Can be cleared (but not set) by the CPU.


0

1 ABORT R/W Abort Table DMA0 = Normal operation1 = Abort Table DMA

0

0 EN R/W Enable Table DMA0 = Disable1 = Enable

0

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CMIC_TABLE_DMA_CUR_ENTRY_SBUS_ADDR

CMIC_SLAM_DMA_PCIMEM_START_ADDR

Register description: Table DMA address of current entry


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Table 44: CMIC_TABLE_DMA_CUR_ENTRY_SBUS_ADDR


31:0 ADDR R/W Indicates the address of the table entry currently being processed 0x00000000

Register description: SLAM DMA physical start address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Table 45: CMIC_SLAM_DMA_PCIMEM_START_ADDR


31:0 ADDR R/W Written by the CPU indicating SLAM DMA physical (PCI) memory start address 0x00000000

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CMIC_SLAM_DMA_SBUS_START_ADDR

CMIC_SLAM_DMA_ENTRY_COUNT

Register description: SLAM DMA logical (s-bus) start address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Table 46: CMIC_SLAM_DMA_SBUS_START_ADDR


31:0 ADDR R/W Written by the CPU indicating SLAM DMA logical (s-bus) memory start address 0x00000000

Register description: SLAM DMA entry count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESV COUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

COUNT

Table 47: CMIC_SLAM_DMA_ENTRY_COUNT


31:24 RESERVED RO Reserved –

23:0 COUNT R/W Specifies the number of SLAM entries to SLAM DMA 0x000000

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CMIC_SLAM_DMA_CFG

Register description: SLAM DMA configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED REV_MOD_CNT ORDER BEATS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ERR DONE ABORT EN

Table 48: CMIC_SLAM_DMA_CFG



27:22 REV_MOD_CNT R/W Specifies the entry count for the first iteration of a Reverse Slam DMA operation. The formula for this value is:(CMIC_SLAM_DMA_ENTRY_COUNT[23:0] % (64 / BEATS[4:0]))

0x00

21 ORDER R/W Specifies Slam DMA order0 = Forward (used for DELETE operations)1 = Backward (used for INSERT operations)

0

20:16 BEATS R/W Indicates the number of data beats. For SLAM DMA purposes, each SLAM entry is 32-bit aligned. The widest s-bus table write/read supported is 640 bits. The valid values for this field are 1–20 (beats).

0x00


3 ERR R/W SLAM DMA transfer was aborted due to an error (most probably due to a NACK). Can be cleared (but not set) by CPU.

0

2 DONE R/W Table SLAM complete. Can be cleared (but not set) by the CPU.0 = Not complete1 = Complete

0

1 ABORT R/W Abort table SLAM

0 = Normal operation1 = Abort Table DMA

0

0 EN R/W Enable SLAM DMA0 = Disable1 = Enable

0

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CMIC_SLAM_DMA_CUR_ENTRY_SBUS_ADDR

CMIC_STAT_DMA_ING_STATS_CFG

Register description: SLAM DMA address of current entry


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Table 49: CMIC_SLAM_DMA_CUR_ENTRY_SBUS_ADDR


31:0 ADDR R/W Indicates the address of the SLAM Entry currently being processed 0x00000000

Register description: Ingress stats DMA configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ING_STATS_STAGE_NUM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ING_STATS_COUNTER_NUM RESERVED ING_ETH_BLK_NUM

Table 50: CMIC_STAT_DMA_ING_STATS_CFG



21:16 ING_STATS_STAGE_NUM

R/W Ingress pipeline stats counter stage number (if any) 0x00


13:8 ING_STATS_COUNTER_NUM

R/W Indicates the number of ingress stats counters per port 0x00


3:0 ING_ETH_BLK_NUM R/W Ingress block number for stats counters 0x0

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CMIC_STATS_DMA_EGR_STATS_CFG

Register description: Egress stats DMA configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED EGR_STATS_STAGE_NUM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EGR_STATS_COUNTER_NUM RESERVED EGR_ETH_BLK_NUM

Table 51: CMIC_STATS_DMA_EGR_STATS_CFG



21:16 EGR_STATS_STAGE_NUM

R/W Egress pipeline stats counter stage number (if any) 0x00


13:8 EGR_STATS_COUNTER_NUM

R/W Indicates the number of egress stats counters per port 0x00


3:0 EGR_ETH_BLK_NUM R/W Egress block number for stats counters 0x0

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CMIC_STAT_DMA_MAC_STATS_CFG

CMIC_STAT_DMA_PORT_TYPE_MAP

Register description: MAC stats DMA configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED CPU_STATS_PORT_NUM RESERVED MAC_STATS_STAGE_NUM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV MAC_X_STAT_COUNTER_NUM RESERVED MAC_G_STAT_COUNT_NUM

Table 52: CMIC_STAT_DMA_MAC_STATS_CFG



28:24 CPU_STATS_PORT_NUM

R/W Identifies the CPU port number 0x00


21:16 MAC_STATS_STAGE_NUM

R/W MAC stats counter stage number (if any) 0x00


14:8 MAC_X_STAT_COUNTER_NUM

R/W The number of MAC stats counters per XG port 0x00


5:0 MAC_G_STAT_COUNTER_NUM

R/W The number of MAC stats counters per GbE port 0x00

Register description: Port type for stats DMA


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 53: CMIC_STAT_DMA_PORT_TYPE_MAP


31:0 BITMAP R/W Specifies the port type0 = Gig ports, get MAC_G_STAT_COUNTERS_NUM counters1 = HiGig+ ports, get MAC_X_STAT_COUNTERS_NUM counters

0x00000000

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CMIC_STAT_DMA_BLKNUM_MAP_7_0


Register description: Stats DMA port to block_number map for port [7:0]


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SBUS_BLKNUM_7 SBUS_BLKNUM_6 SBUS_BLKNUM_5 SBUS_BLKNUM_4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 54: CMIC_STAT_DMA_BLKNUM_MAP_7_0


31:28 SBUS_BLOCKNUM_7 R/W S-bus block number for port 7 0x0










Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0














Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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CMIC_STAT_DMA_PORTNUM_MAP_7_0


Register description: Stats DMA port to port_number map for port [7:0]


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SBUS_PORTNUM_7 SBUS_PORTNUM_6 SBUS_PORTNUM_5 SBUS_PORTNUM_4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 58: CMIC_STAT_DMA_PORTNUM_MAP_7_0


31:28 SBUS_PORTNUM_7 R/W S-bus port number for port 7 0x0










Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0














Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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CMIC_MIIM_ADDRESS

For Clause 22 devices, bits [4:0] supply the REGAD. For Clause 45 devices, bits [20:16] supply the DTYPE and bits [15:0]supply the reg address.

CMIC_MIIM_PROTOCOL_MAP

Register description: Supplies the register address of MIIM reads and writes.

Register offset: 0x04A0

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED CLAUSE_45_DTYPE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLAUSE_45_REGADR

CLAUSE_22_REGADR

Table 62: CMIC_MIIM_ADDRESS



20:16 CLAUSE_45_DTYPE R/W Clause 45 DTYPE 0x00

15:0 CLAUSE_45_REGADR R/W Clause 45 register address 0x0000

4:0 CLAUSE_22_REGADR R/W Clause 22 register address 0x00

Register description: Port bitmap of MIIM protocol: 0 = Clause 22, 1 = Clause 45


Note: The bitmap is indexed by port number.

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 63: CMIC_MIIM_PROTOCOL_MAP


31:0 PORT_BITMAP R/W Port bitmap specifies Clause 22/450 = Ports that use Clause 221 = Ports that use Clause 45This register is shared by external and internal PHYs, so it should be programmed appropriately before launching MIIM wr/rd or link scan commands.

0x00000000

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CMIC_MIIM_PORT_TYPE_MAP

CMIC_MIIM_INT_SEL_MAP

Register description: Port type bitmap: 0 = Gig port, 1 = HiGig+ port.


Note: The port type bitmap is indexed by port number.

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 64: CMIC_MIIM_PORT_TYPE_MAP


31:0 PORT_BITMAP R/W Port bitmap specifies GbE/XG ports0 = Gig ports—access Gig MIIM interface1 = XG ports—access HiGig+ MIIM interface

0x00000000

Register description: Internal/external PHY select

Register offset: 0x04AC

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 65: CMIC_MIIM_INT_SEL_MAP


31:0 PORT_BITMAP R/W Port bitmap select internal/external PHY0 = Obtain link status via external PHY1 = Obtain link status via internal PHY

0x00000000

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CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0


Register description: External PHY ID mapping

Register offset: 0x04C0

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED PHY_ID_3 RESERVED PHY_ID_2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 66: CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0



28:24 PHY_ID_3 R/W PHY ID of external PHY attached to port 3 0x0









Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0













Register offset: 0x04CC

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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Register offset: 0x04D0

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0














Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0













Register offset: 0x04DC

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0












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CMIC_XGXS_MDIO_CONFIG

Register description: XGXS MDIO configuration

Register offset: CMIC_XGXS_MDIO_CONFIG_0 – 0x0500CMIC_XGXS_MDIO_CONFIG_1 – 0x0504CMIC_XGXS_MDIO_CONFIG_2 – 0x0508CMIC_XGXS_MDIO_CONFIG_3 – 0x050C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED MD_ST MD_DEVAD IEEE_DEV_IN_PKG

Table 74: CMIC_XGXS_MDIO_CONFIG



13 MD_ST R/W Internal PHY Clause 45 select

0 = Clause 221 = Clause 45

0

12:8 MD_DEVAD R/W MDIO device address 0x00

7:0 IEEE_DEV_IN_PKG R/W IEEE devices in XGXS package 0x00

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CMIC_SOFT_RESET_REG

Register description: CMIC software reset


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED CMIC_XG_PLL_RSTL

RESV

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CMIC_BSAFE_

CLK_GEN_RSTL

CMIC_BSAFE_

RSTL

RESV CMIC_EP_

RSTL

RESV CMIC_IP_

RSTL

CMIC_MMU_RSTL

CMIC_XGXS_RSTL

CMIC_XP_

RSTL

RESERVED CMIC_GX4_RSTL

CMIC_GP_RSTL

Table 75: CMIC_SOFT_RESET_REG



17 CMIC_XG_PLL_RSTL R/W PLL reset0 = Reset1 = Normal operation

0


12 CMIC_BSAFE_

CLKGEN_RSTL

R/W BroadSAFE clock generator reset

0 = Reset1 = Normal operation

0

11 CMIC_BSAFE_RSTL R/W BroadSAFE reset0 = Reset1 = Normal operation

0


9 CMIC_EP_RSTL R/W EP reset


0


7 CMIC_IP_RSTL R/W IP reset0 = Reset1 = Normal operation

0

6 CMIC_MMU_RSTL R/W MMU reset


0

5 CMIC_XGXS_RSTL R/W XGXS reset0 = Reset1 = Normal operation

0

4 CMIC_XP_RSTL R/W XPort reset0 = Reset1 = Normal operation

0


1 CMIC_GX4_RSTL R/W GX4 reset0 = Reset1 = Normal operation

0

0 CMIC_GP_RSTL R/W GPort reset0 = Reset1 = Normal operation

0

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CMIC_XGXS_PLL_CONTROL_1

CMIC_XGXS_PLL_CONTROL_2

Register description: XAUI PLL control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL_CONTROL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_CONTROL

Table 76: CMIC_XGXS_PLL_CONTROL_1


31:14 PLL_CONTROL_31_14 R/W XAUI PLL control register bits [31:14] 0x00000

13 PLL_CONTROL_13 R/W When set to 1, PLL runs at 12 Gbps—select between 10 Gbps and 12 Gbps for HG/XE port 0

0

12 PLL_CONTROL_12 R/W When set to 1, PLL runs at 12 Gbps—select between 10 Gbps and 12 Gbp for HG/XE port 1

0

11 PLL_CONTROL_11 R/W When set to 1, PLL runs at 12 Gbps—select between 10 Gbps and 12 Gbp for HG/XE port 2

0

10 PLL_CONTROL_10 R/W XAUI PLL control register bit 10—select between 10 Gbps and 12 Gbp for HG/XE port 3

0

9:0 PLL_CONTROL_9_0 R/W XAUI PLL control register bits [9:0] 0x000

Register description: XAUI PLL control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CMIC_XG_PLL_LOCK

PLL_STATUS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL_STATUS XGPLL_CTRL_PWDN_INDEX

PLL CONTROL

Table 77: CMIC_XGXS_PLL_CONTROL_2


31 CMIC_XG_PLL_LOCK RO XG PLL lock 0

30:13 PLL_STATUS RO XAUI PLL status [17:0] 0x00000

12 XGPLL_CTRL_PWDN_INDEX

R/W XG PLL control power-dn index 0

11:0 PLL_CONTROL[43:32] R/W XAUI PLL control [43:32] 0x000

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CMIC_LEDUP_CTRL

CMIC_LEDUP_STATUS

Register description: LED processor control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED LEDUP_SKIP_SCAN_IN

LEDUP_SKIP_PROCES

SOR

LEDUP_SKIP_SCAN_O

UT

LED_UPEN

Table 78: CMIC_LEDUP_CTRL



0 LED_EN R/W LED processor enable. This bit enables the LED processor to run. It is cleared to 0 on reset and should be set to 1 after initializing the program RAM.0 = Disable1 = Enable

0

Register description: LED processor status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED LED_INIT

LED_RUN

LED_PC

Table 79: CMIC_LEDUP_STATUS



9 LED_INIT RO Initialization in progress. This status bit is 1 during initialization of the LED processor immediately after a reset.

0

8 LED_RUN RO LED processor status

0 = Stopped1 = Running

0

7:0 LED_PC RO Current program counter (PC) value 0x00

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CMIC_LEDUP_PROGRAM_RAM

The LED processor contains 256 bytes of program RAM. These 256 registers are used to read or write the program RAM.The LED processor should be stopped when the program RAM is written. The program RAM should be initialized before theLED processor is started.

CMIC_LEDUP_DATA_RAM

Register description: LED processor program RAM

Register offset: 0x1800 to 0x1BFC

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED DATA

Table 80: CMIC_LEDUP_PROGRAM_RAM



7:0 DATA R/W LED program RAM data Undefined

Register description: LED processor data RAM

Register offset: 0x1C00 to 0x1FFC

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED DATA

Table 81: CMIC_LEDUP_DATA_RAM



7:0 DATA R/W LED data RAM Undefined

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Section 4: S-Channel Messaging

MESSAGING MECHANISM

The Sideband-channel (S-channel) messaging mechanism is used to access all Indirect Mapped registers, table memory,and packet memory. This allows system software to communicate directly with on-chip (internal) functional units (registers,memories, and so forth) that are not directly accessible on the PCI bus. In order to use the S-channel messaging scheme,and, therefore, communicate with the StrataXGS, the CPU maps a block of PCI memory-mapped registers and obeys theS-channel messaging protocol.

Under this scheme, a message is sent to the chip with a command to perform a read or a write operation, along with theaddress/data associated with the operation. A message must be sent for every operation. For each message sent, the PCIcontroller transfers the data from PCI memory space into the StrataXGS device. After the operation is done, the PCIcontroller tracks messages sent and receives status information for that request. Each message sent by the CPU has acorresponding response from the StrataXGS PCI controller, the CMIC.

Each word of the S-channel message must be read/written sequentially from the start to the end of the S-channel messagebuffer region. This involves copying a maximum of twenty-two 32-bit words of PCI memory sequentially to/from theStrataXGS device into the PCI host (CPU) memory. If a message is only four words in length, only four words need to becopied into the messaging buffer. All StrataXGS internal registers, tables, and memories are accessed through thismechanism.

MESSAGING REGISTERS

When the CPU needs to generate an S-channel message, it creates an S-channel message (Opcode, length, address, databytes, and so forth) using a memory structure in the proper format for the transaction. The CPU then copies the messageinto the S-channel data registers and enables the internal transmission of the message by setting the MSG_START bit inCMIC_SCHAN_CTRL.

After the CPU notifies the CMIC to start the S-channel operation, the CMIC responds by starting the operation on the internalStrataXGS S-channel, setting the MSG_DONE bit in CMIC_SCHAN_CTRL when the operation is complete and theresponse data is available in the message buffers.

Note: 32-bit PCI memory accesses require endian-conversion (byte-swapping) routines if your host CPU is bigendian. Registers in the StrataXGS device are little endian.

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Registers and tables accessed via S-channel messaging are:

• Ingress Pipeline registers

• Ingress (Hi) Pipeline registers

• Egress Pipeline registers

• Egress (Hi) Pipeline registers

• BroadSAFE registers

• GPIC registers

• IPIC registers

• MMU registers

• Gig MAC registers

• HiGig+/XG MAC registers

• Statistic counters

• Switching memories

Figure 1: Messaging Registers

For optimal performance, the StrataXGS2 device can be programmed to generate the MSG_DONE interrupt uponcompletion of an S-channel messaging operation. Interrupt-driven I/O is performed by initiating a transaction as describedabove, and then when the interrupt is received and cleared, the MSG_DONE bit is cleared as well.

Every S-channel message sent should be correlated with the MSG_DONE bit set in CMIC_SCHAN_CTRL, indicating thatthere is a valid response waiting in the message buffer. Every S-channel message sent by the CPU results in a response.

S-channel message data is written into the StrataXGS device when the CPU initiates a transaction by setting theMSG_START bit in CMIC_SCHAN_CTRL. For Programmed I/O (PIO), the driver should wait for the operation to completeby polling the MSG_DONE bit some number of times.

STATUS AND CONTROL REGISTER - CMIC_SCHAN_CTRL

XX

31

SCHANNEL MESSAGE REGISTER SET031

CMIC_SCHAN_D0

0 = OPERATION IN PROGRESS (R)1 = OPERATION COMPLETE (R)

0 = NO MESSAGE PENDING (R)1 = MESSAGE PENDING (R)1 = START MESSAGE PROCESSING (W)

MESSAGE REGISTER 0MESSAGE REGISTER 1MESSAGE REGISTER 2

MESSAGE REGISTER 21

01

CMIC_SCHAN_D2CMIC_SCHAN_D1

CMIC_SCHAN_D21

S-CHANNEL MESSAGE

S-CHANNEL HEADER

Host System Memory PCI Memory

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In the event that the MSG_DONE bit is not set after some number of iterations (polling mode) or a timeout period (interruptmode), the driver should assume that the operation has failed and reset the internal S-channel bus by togglingSCHAN_ABORT (bit 7) in CMIC_CONFIG.

For interrupt-driven I/O, the S-channel bus driver must enable the SCH_MSG_DONE bit in CMIC_IRQ_MASK to enable theinterrupt on completion.

If the interrupt-driven driver:

• initiates the start of the S-channel transaction by writing the message buffer out to the PCI memory window;

• toggles the bit MSG_START in CMIC_SCHAN_CTRL; or,

• blocks waiting for an interrupt;

then the software should initialize an empty semaphore, and after starting the transmission of the message (as in PIO mode,by setting MSG_START in CMIC_SCHAN_CTRL), it should wait on the semaphore.

The interrupt service routine for the S-channel bus driver must check for the interrupt on completion of the S-channelmessage by:

• verifying that SCH_MSG_DONE is set in CMIC_IRQ_STAT;

• clearing the interrupt via the MSG_DONE bit in CMIC_SCHAN_CTRL;

• awakening the caller by giving back the semaphore.

After the operation is complete, the caller should read up to 22 words from the message buffer and process the responseaccordingly. To simplify the messaging mechanism, the development of the driver should proceed as follows:

1 Develop structures for all of S-channel message types, paying special attention to the C example declarations providedin the sample driver header files.

2 Write a simple routine that uses PIO to send a message and return a response.

3 Write routines to read/write registers.

4 Write routines to read/write memory.

5 Develop all table- and memory-based manipulation routines on top of step 4.

6 Switch to interrupt driven I/O for optimal performance.

Refer to “CMIC Registers” on page 11 for more details on the bit definitions for each of the registers inCMIC_SCHAN_CTRL, CMIC_IRQ_STAT, CMIC_IRQ_MASK, and CMIC_CONFIG, as well as the data message buffers.

Note: While an S-channel operation is in progress, the CPU must not attempt to read S-channel data registersuntil the operation is complete, as indicated by setting of the CMIC_SCHAN_CTRL.MSG_DONE bit.

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S-CHANNEL MESSAGING MECHANISM

The S-channel Messaging Mechanism is used to access Indirect Mapped registers and memories in the device.

A set of messaging registers is used by the CPU to set up S-channel messages. These messages are sent on the internalmessaging bus by the CMIC.

Typically the CPU sets up a message in the messaging registers and instructs the CMIC to send the message on the internalmessaging bus. The CMIC sends the message on the bus and notifies the CPU when the operation is complete. Most of themessages sent on this bus have a direct response.

Bit Number

31:25 25:20 19:14 13:7 6 5:4 3:1 0

OPCODE DPORT RESV DLEN ERR ECODE RESV NACK

S-channel message 1 (S1)



...


Table 82: S-Channel Message Bit Format Description

S-Channel Msg # Bit Name Description

S0 31:26 OPCODE Identifies the S-bus message type:0x07 = MEM_RD—Memory read, S1 = Address0x08 = MEM_RD_ACK—Memory read ACK, S1... = Data0x09 = MEM_WR—Memory write, S1 = Address, S2... = Data0x0A = MEM_WR_ACK— Memory write ACK0x0B = REG_RD—Register read, S1 = Address0x0C = REG_RD_ACK— Register read ACK, S1 = Data0x0D = REG_WR—Register write, S1 = Address, S2 = Data0x0E = REG_WR_ACK—Register write ACK0x0F = L2_INS— L2 insert, S1... = Entry0x10 = L2_INS_ACK—L2 insert ACK0x11 = L2_DEL— L2 delete, S1... = Entry0x12 = L2_DEL_ACK—L2 delete ACK0x1A = L3_INS— L3 insert, S1... = Entry0x1B = L3_INS_ACK—L3 insert ACK0x1C = L3_DEL—L3 delete, S1... = Entry0x1D = L3_DEL_ACK— L3 delete ACK0x20 = FB_L2_LKUP— Firebolt L2 lookup, S1... = Key0x21 = FB_L2_LKUP_ACK— Firebolt L2 lookup ACK, S1... = Key0x22 = FB_L3_LKUP— Firebolt L3 lookup, S1... = Key0x23 = FB_L3_LKUP_ACK—Firebolt L3 lookup ACK, S1... = Key

25:20 DPORT Identifies the S-bus destination block ID. See the previous section for details. All ACK messages have DPORT = CMIC.

19:14 RESV Reserved

13:7 DLEN Data length (in bytes) of the S-bus message. Since the S-bus is 32-bits (4B) wide, the data length is always a multiple of four. The data length is not valid for all ACKs and is not valid for some commands (see below).

6 ERR Error. Set due to an illegal/invalid access. Valid only for S-bus ACKs, not for S-bus commands.

5:4 ECODE Error code (cause for ERR bit getting set). Valid only for S-bus ACKs, not for S-bus commands.

3:1 RESV Reserved

0 NACK NACK (Negative ACK) bit. Set when a legal S-bus command cannot be serviced due to hardware resource limitations. Valid only for S-bus ACKs, not for S-bus commands.

S1 31:0 S-channel message 1

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Table 83 lists the block IDs for the various internal sections of the BCM56500.

Fields not mentioned for a particular opcode are not applicable/don’t-care for that opcode.

MEM_RD (memory read)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x7, DPORT

CMIC_SCHAN_MESSAGE 1: ADDRESS

MEM_RD_ACK (memory read acknowledgement)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x8, DPORT = CMIC, ERR, ECODE

CMIC_SCHAN_MESSAGE 1: DATA

...

CMIC_SCHAN_MESSAGE n: DATA

MEM_WR (memory write)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x9, DPORT, DLEN



...

CMIC_SCHAN_MESSAGE n: DATA

S2 31:0 S-channel Message 2

: : :

S21 31:0 – S-channel Message 21

Table 83: S-Channel Message Source and Destination Blocks

Block ID Port(s)

0x0 Gigabit ports 0–1

0x1 Gigabit ports 12–23

0x2 IPIC/XPIC port 0




0x6 MMU

0x7 Ingress pipeline

0x8 Ingress pipeline high

0x9 Egress pipeline

0xA Egress pipeline high

0xB BroadSAFE

0xF CMIC

Table 82: S-Channel Message Bit Format Description

S-Channel Msg # Bit Name Description

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MEM_WR_ACK (memory write acknowledgement)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0xa, DPORT = CMIC, ERR, ECODE

REG_RD (register read)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0xb, DPORT


REG_RD_ACK (register read acknowledgement)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0xc, DPORT = CMIC, ERR, ECODE


REG_WR (register write)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0xd, DPORT, DLEN = 4



REG_WR_ACK (register write acknowledgement)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0xe, DPORT = CMIC, ERR, ECODE

L2_INSERT (L2 insert)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0xf, DPORT = IPIPE/IPIPE_HI, DLEN = 12

CMIC_SCHAN_MESSAGE 1: L2_ENTRY[31:0]



L2_INSERT_ACK (L2 insert acknowledgement)


L2_DELETE (L2 delete)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x11, DPORT = IPIPE/IPIPE_HI, DLEN = 12




L2_DELETE_ACK (L2 delete acknowledgement)


L3_INSERT (L3 insert)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x1a, DPORT = IPIPE/IPIPE_HI, DLEN = 12




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L3_INSERT_ACK (L3 insert acknowledgement)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x1b, DPORT = CMIC, ERR, ECODE

L3_DELETE (L3 delete)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x1c, DPORT = IPIPE/IPIPE_HI, DLEN = 12




L3_DELETE_ACK (L3 delete acknowledgement)

CMIC_SCHAN_MESSAGE 0: OPCODE = 0x1d, DPORT = CMIC, ERR, ECODE

FB_L2_LKUP (Firebolt L2 lookup)




FB_L2_LKUP_ACK (Firebolt L2 lookup acknowledgement)





FB_L3_LKUP (Firebolt L3 lookup)





FB_L3_LKUP_ACK (Firebolt L3 lookup acknowledgement)





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Section 5: GbE Por t RegistersThe registers in this section control the GbE port MACs. There are two sets of registers for each MAC: one for 1000megabits-per-second (Mbps) and one for 10/100 Mbps. Selection is based on the CONFIG speed select bit.

• 1000 Mbps MAC registers: GMACC0, GMACC1, GMACC2, GPCSC, GSA0, GSA1, and MAXFR.

• 10/100 Mbps MAC registers: GTH_FE_MAC1, GTH_FE_MAC2, GTH_FE_IPGT, GTH_FE_IPGR, GTH_FE_CLRT,GTH_FE_MAXF, ESA0, ESA1, and ESA2.

GMACC0

Register description: GigMAC control 0

Register offset: 0x00g0p100 (g = block number [0, 1], p = port number [0–0xB])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRST RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED L10B L32B TMDS

Table 84: GMACC0


31 SRST R/W Soft reset0 = Normal operation1 = Reset

0


9 L10B R/W Loopback 10B symbols0 = Normal operation1 = Loopback enable

0

8 L32B R/W Loopback 32B data0 = Normal operation1 = Loopback enable

0

7:0 TMDS R/W Test mode select

0x00 = Reserved0x01 = Normal operation. Software should program TMDS = 0x01 for normal operation.0x02–0xFF = Reserved

0x00

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GMACC1



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESV TXEN0 RESV RXEN0 RESERVED RESERVED GLVR RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED LONGP RESV FCRX FCTX PUREP RESERVED FLCHK RESERVED

Table 85: GMACC1



30 TXEN0 R/W Transmitter function enable

0 = Disable1 = Enable (normal operation)

0


28 RXEN0 R/W Receiver function enable0 = Disable1 = Enable (normal operation)

0




19 GLVR R/W Must be written to 1 for normal operation 1



12 LONGP R/W MAC control to accept long preamble

0 = Do not accept preamble over 11 bytes1 = Accept preambles over 11 bytes (recommended per IEEE specification)

1


10 FCRX R/W Flow control receive enable0 = Disable1 = Enable

0

9 FCTX R/W Flow control transmit enable


0

8 PUREP R/W Pure preamble enforcement0 = No preamble checking is performed1 = The MAC verifies the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an error preamble is discarded.

0


5 FLCHK R/W Frame length check0 = Disable1 = Enable

0



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GMACC2

GPCSC



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED IPGT

Table 86: GMACC2



5:0 IPGT R/W This field is the back-to-back Transmit Inter Packet Gap represented in bytes. The minimum IPGT value is 0x08. The recommended value is 0xC (96 bits), which is the minimum allowed by the standard.

0x0C

Register description: Gig PCS configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RCSEL EWRAP RESV

Table 87: GPCSC



2 RCSEL R/W Must be written to 1 for normal operation 0

1 EWRAP R/W Loopback for SerDes0 = Normal operation1 = Enable loopback

0


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GSA0

GSA1

Register description: Station ID address byte register 0


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STAD1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STAD1

Table 88: GSA0


31:0 STAD1 R/W Bits 47–16 of the programmable Station ID address for the port. This is used as the source address whenever the port sends a PAUSE frame.PAUSE frames directed to this address or to the reserved address 01:80:C2:00:00:01 are detected (and are acted upon if the MAC is configured to honor PAUSE frames).

Undefined

Register description: Station ID address byte register 1


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STAD2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

Table 89: GSA1


31:16 STAD2 R/W Bits 15–0 of the programmable Station ID address for the port. Used as the source address whenever the port sends a PAUSE frame.PAUSE frames directed to this address or to the reserved address 01:80:C2:00:00:01 are detected (and are acted upon if the MAC is configured to honor PAUSE frames).

Undefined


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MAXFR

REVCD

Register description: Maximum receive frame length


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAXFR

Table 90: MAXFR



15:0 MAXFR R/W This default is 0x05EE, which represents a maximum receive frame of 1518 octets. This allows an untagged maximum size Ethernet frame of 1518 octets or a tagged frame of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field.

0x05EE

Register description: Revision information

Register offset: 0x00g0p10B (g = block number [0, 1], p = port number [0–0xB])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YEAR MONTH DAY

Table 91: REVCD



15:8 YEAR RO Year 0x05

7:4 MONTH RO Month 0x0

3:0 DAY RO Day 0x1

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GTH_FE_MAC1

Register description: 10/100 MAC control 1


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED HRRFN RESV HRTFN RESERVED LBACK TX_PAU

RX_PAU

RESV RXEN

Table 92: GTH_FE_MAC1



15:11 RESERVED R/W Reserved 0

10 HRRFN R/W Reset receive block0 = Normal operation1 = Reset

0


8 HRTFN R/W Reset transmit block0 = Normal operation1 = Reset

0


4 LBACK R/W Loopback Control

0 = Normal operation1 = Enable MAC Transmit interface to loop back on the MAC Receive interface

0

3 TX_PAU R/W Transmit flow control0 = Flow control frames are not transmitted1 = PAUSE flow control frames are allowed to be transmitted

0

2 RX_PAU R/W Receive flow control0 = Received PAUSE flow control frames are ignored1 = Respond to PAUSE flow control frames

0


0 RXEN R/W Receive Enable0 = Disable1 = Receiver enabled

0

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GTH_FE_MAC2

Register description: 10/100 MAC control 2


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV EXC_DEF

BP__NO_

BOFF

NO_BOFF

RESV LONG_PRE

PURE_PAD

RESERVED LG_CHK

FULL_DP

Table 93: GTH_FE_MAC2



14 EXC_DEF R/W Excess defer0 = MAC aborts when the excessive deferral limit is reached and provides feedback to the host system.1 = MAC defers to the carrier, indefinitely, as per the standard.

0

13 BP_NO_BOFF R/W Controls the retransmission of a packet by the MAC immediately after a collision, thereby reducing the chance of further collisions and ensuring transmit packets get sent.

0 = Do not retransmit immediately. Instead, use the Binary Exponential Backoff algorithm for backoff.1 = Retransmit immediately without backoff.

0

12 NO_BOFF R/W Control the backoff mechanism upon collision.

0 = Use the Binary Backoff Algorithm, as specified in the standard, before retransmit.1 = MAC immediately retransmits following a collision rather than using the Binary Exponential Backoff algorithm as specified in the standard.

0


9 LONGPRE R/W Long Preamble Enforcement

0 = MAC allows any length preamble (as per the standard).1 = MAC allows only packets with preamble length <= 12 bytes.

0

8 PUREPAD R/W Pure Preamble Enforcement0 = No preamble checking is performed.1 = The MAC verifies the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an error preamble is discarded.

0


1 LG_CHK R/W Frame Length Checking0 = Disable1 = Enable

0

0 FULL_DP R/W Full-Duplex Operation

0 = Enable half-duplex operation1 = Enable full-duplex operation

0

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GTH_FE_IPGT

Register description: 10/100 IPGT


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED IPGT

Table 94: GTH_FE_IPGT



6:0 IPGT R/W IPGT

This field specifies the minimum inter-packet gap for back-to-back transmitted packets.

In 10 and 100 Mbps full-duplex mode, the minimum inter-packet gap (in bits) is (IPGT+3)*4. A value of 0x15 (recommended) sets the minimum IPG at 96 bit-times, per the standard. The minimum allowed setting is 0x13 (88 bit-times).In 100 Mbps half-duplex mode, the minimum inter-packet gap (in bits) is (IPGT+13)*4. A value of 0xB (recommended) sets the minimum IPG at 96 bit-times, per the standard. The minimum allowed setting is 0xB.In 10 Mbps half-duplex mode, the minimum inter-packet gap (in bits) is (IPGT+12)*4. A value of 0xC (recommended) sets the minimum IPG at 96 bit-times per the standard. The minimum allowed setting is 0xC.

0x00

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GTHG_FE_IPGR

Register description: 10/100 receive control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV IPGR1 RESV IPGR2

Table 95: GTHG_FE_IPGR



14:8 IPGR1 R/W This field is used in half-duplex mode for transmitting non-back-to-back packets. This field should be set to 0x6.

0x00


6:0 IPGR2 R/W This field is used in half-duplex mode for transmitting non-back-to-back packets. This field should be set to 0xF.

0x00

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GTH_FE_CLRT

GTH_FE_MAXF

Register description: 10/100 collision retry


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED COL_WIN RESERVED RETRY

Table 96: GTH_FE_CLRT



13:8 COL_WIN R/W This field represents the slot time or collision window during which collisions occur in properly configured networks. Since the collision window starts at the beginning of transmission, the preamble and SFD is included. Its default of 0x37 (55) corresponds to the count of frame bytes at the end of the window.

0x37


3:0 RETRY R/W This field specifies the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The standard specifies the attempt limit to be 0x0F (15).

0xF

Register description: 10/100 maximum receive frame size


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAXF

Table 97: GTH_FE_MAXF



15:0 MAXF R/W This resets to 0x05EE, which represents a maximum receive frame of 1517 octets. An untagged maximum size Ethernet frame is 1517 octets. A tagged frame adds four octets for a total of 1521 octets. If a shorter maximum length restriction is desired, program this 16-bit field.

Note: If a proprietary header is allowed, this field should be adjusted accordingly. For example, if 12-byte headers are prepended to frames, MAXFR should be set to 1531 octets. This would allow the maximum VLAN tagged frame plus the 12-byte header.

0x05EE

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GTH_FE_SUPP

Register description: 10/100 support


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV RESERVED SPEED RESERVED BIT_MODE

Table 98: GTH_FE_SUPP




8 SPEED R/W Operating speed of the MII0 = 10 Mbps mode1 = 100 Mbps mode

0


0 BIT_MODE R/W ENDEC mode where the clock is the bit clock0 = Disable ENDEC mode1 = Enable ENDEC mode

0

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GTH_FE_EXCESSIVE_DEFER_LIMIT

ESA0

Register description: 10/100 excessive deferral limit

Register offset: 0x00g0p20F (g = block number [0, 1], p = port number [0–0xB])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LIMIT

Table 99: GTH_FE_EXCESSIVE_DEFER_LIMIT



15:0 LIMIT R/W Excessive Deferral Limit Value (programmed to (4*MAX_FRAME-1).

If FE_SUPP.BIT_MODE is set to 1’b1, then this register should be programmed to 16 × (MAX_FRAME) – 1.

0x17B7

Register description: 10/100 station address


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STAD0

Table 100: ESA0



15:0 STAD0 R/W Bits [15:0] of the programmable Station ID address for the port.

Used as the source address whenever the port sends a PAUSE frame. PAUSE frames directed to this address or to the reserved address 01:80:C2:00:00:01 are detected (and are acted upon if the MAC is configured to honor PAUSE frames).

Undefined

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ESA1

ESA2



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STAD0

Table 101: ESA1



15:0 STAD1 R/W Bits [31:16] of the programmable Station ID address for the port.

Used as the source address whenever the port sends a PAUSE frame. PAUSE frames directed to this address or to the reserved address 01:80:C2:00:00:01 are detected (and are acted upon if the MAC is configured to honor PAUSE frames).

Undefined



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STAD0

Table 102: ESA2



15:0 STAD2 R/W Bits [47:32] of the programmable Station ID address for the port. Used as the source address whenever the port sends a PAUSE frame. PAUSE frames directed to this address or to the reserved address 01:80:C2:00:00:01 are detected (and are acted upon if the MAC is configured to honor PAUSE frames).

Undefined

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GE_PORT_CONFIG

Register description: GbE port configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CLK_OUT_EN

SIG_DET_SEL

MAC_CRS_SEL

SPEED_SEL JAM_EN

Table 103: GE_PORT_CONFIG



5 CLK_OUT_EN R/W Clock output to SerDes0 = Disable1 = Enable

1

4 SIG_DET_SEL R/W Signal detect select

0 = Internal SerDes output1 = Connect signal detect from external fiber module

0

3 MAC_CRS_SEL R/W MAC CRS select0 = Internal SerDes output (default)1 = CRS from external PHY

0

2:1 SPEED_SEL R/W Speed select00 = 10 Mbps01 = 100 Mbps10 = 1000 Mbps11 = Reserved

0x1

0 JAM_EN R/W Half-duplex jam0 = Disable1 = Enable

0

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GE_EGR_PKT_DROP_CTRL

PAUSE_CONTROL

Register description: Egress drop control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED FLUSH

Table 104: GE_EGR_PKT_DROP_CTRL



0 FLUSH R/W Flush/drop the packets within each GbE port

0 = Normal operation1 = Enable

0

Register description: PAUSE frame control. This controls the GE ports only, not the HG/XE port.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ENA VALUE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VALUE

Table 105: PAUSE_CONTROL



17 ENA R/W Extra pause frames


0

16:0 VALUE R/W Pause quanta. Each bit in this register represents 512 bit-times. Values of 0 and 1 are illegal.

0x00000

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MAC_TX_STATUS

GPORT_CONFIG

Register description: MAC transmit status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED TX_FIFO_ERR

Table 106: MAC_TX_STATUS



0 TX_FIFO_ERR RO Transmit FIFO error 0

Register description: GPORT configuration

Register offset: 0x00g80000 (g = block number [0, 1], p = port number [0–0xB])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CLR_CNT

GPORT_EN

Table 107: GPORT_CONFIG



1 CLR_COUNT R/W Clear all twelve port statistics counters in this block

0 = Do not clear counters1 = Clear counters

0

0 GPORT_EN R/W Port enable0 = Disable1 = Enable

0

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GPORT_RSV_MASK

GPORT_STAT_UPDATE_MASK

Register description: Receive stats vector mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESV MASK

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

Table 108: GPORT_RSV_MASK



30:16 MASK R/W Controls purging of certain packet types received from the MAC 0x0438

15:0 RESERVED RO Reserved –

Register description: Receive statistics update mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESV MASK

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

Table 109: GPORT_STAT_UPDATE_MASK



30:16 MASK R/W Control which events should have the statistic counters update in the ingress 0x0438


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GPORT_CNTMAXSIZE

GPORT_TPID

Register description: Statistics counter maximum size


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CNTMAXSIZE

Table 110: GPORT_CNTMAXSIZE



13:0 CNTMAXSIZE R/W The maximum packet size that is used in statistic counter updates. Default to 1518. 0x05EE

Register description: TPID for VLAN tagged packets


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TPID

Table 111: GPORT_TPID



15:0 TPID R/W The TPID used to detect VLAN-tagged packets. This is used by the MAC TX and RX counters to keep track of the tagged packets.

0x8100

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Section 6: XG Port Registers

MAC_CTRL

Register description: XG MAC control

Register offset: 0x00g00000 (g = block number [2, 3, 4, 5])

Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RMT_LOOP

LCL_LOOP

RXEN TXEN

Table 112: MAC_CTRL



3 RMT_LOOP R/W Remote loopback mode from the XGMII receive to XGMII transmit. Data sent from a remote port and is received by the HiGig+ port is internally looped to the HiGig+ transmit and sent back to the remote port.0 = Normal operation1 = Enable remote loopback

0

2 LCL_LOOP R/W Local loopback mode from the Transmit FIFO to the Receive FIFO. Note that this cannot be enabled if the XGXS PHY is in loopback.0 = Normal operation1 = Enable local loopback

0

1 RXEN R/W Receiver enable0 = Disable1 = Enable

0

0 TXEN R/W Transmitter enable


0

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MAC_XGXS_CTRL

Register description: XGXS control


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED LCREFEN

RSTFLTRBYP

RX_LANE_SWAP

TX_LANE_SWAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PLL_BYP

RMT_LOOP

AFIFO_RST

TX_FIFO_RSTL

IDDQ PWR_DN

HW_RSTL

MODE

Table 113: MAC_XGXS_CTRL



19 LCREFEN R/W Select clock from LCPLL (must be set to 1) 0

18 RSTFLTRBYP R/W Set to 1 to reset filter bypass 0

17 RX_LANE_SWAP R/W Receive lane swap 0

16 TX_LANE_SWAP R/W Transmit lane swap 0


10 PLL_BYP R/W PLL bypass

0 = Normal operation1 = Bypass reference clock PLL and run transmit and receive clocks from the reference clock pin.

0

9 RMT_LOOP R/W Remote loopback


0

8 AFIFO_RST R/W Transmit FIFO reset0 = Do not reset the TX FIFO on an under/overflow.1 = Automatically reset the TX FIFO on an under/overflow.

1

7 TX_FIFO_RSTL R/W Transmit FIFO reset0 = Reset the TX FIFO1 = Normal operation

1

6 IDDQ R/W Power down

0 = Normal operation1 = Power down analog clocks, but leave analog section powered-up

1

5 PWR_DN R/W Power down0 = Normal operation1 = Shutdown digital clocks

1

4 HW_RSTL R/W Hard reset0 = Reset asserted1 = Reset deasserted

0

3:0 MODE R/W Clock compensation mode

0 = With clock compensation1 = Without clock compensation

0x1

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MAC_XGXS_STAT

Register description: XGXS status


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BRK_LINK

RMT_FLT

TX_FIFO_ERR

TX_ACT

TX_PLL_LOCK

SEQ_DONE

RX_ACT

LINK

Table 114: MAC_XGXS_STAT



7 BRK_LINK RO LSS remote link, break link status Undefined

6 RMT_FLT RO LSS remote link, remote fault Undefined

5 TX_FIFO_ER RO Transmit FIFO under/over-run error Undefined

4 TX_ACT RO Transmit activity Undefined

3 TX_PLL_LOCK RO TX PLL locked Undefined

2 SEQ_DONE RO Analog initialization sequence done Undefined

1 RX_ACT RO Receive activity Undefined

0 LINK RO Link status Undefined

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MAC_CNTMAXSZ

Register description: Statisticss counter maximum packet size

Register offset: x00g00005 (g = block number [2, 3, 4, 5])

Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESRVED CNTMAXSZ

Table 115: MAC_CNTMAXSZ



13:0 CNTMAXSZ R/W The maximum size of the packet received/transmitted that increments, if appropriate, IRMCA, IRBCA, IRFCS, IRXCF, IRXPF, IRXUO, IROVR, IRJBR, ITMCA, ITBCA, ITFCS, ITXPF, and ITOVR.

0x05EE

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MAC_TXCTRL

Register description: Transmit control


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ANY_START

DISCARD

PAUSE_EN

THROT_DENOM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THROT_DENO

M

THROT_NUM AVG_IPG CRC_MODE HDR_MODE

Table 116: MAC_TXCTRL



25 ANY_START R/W Any start character

0 = /start/ required to start a packet, per the XGMII specification.1 = Allow any non-idle character to start a packet.

0

24 DISCARD R/W Transmit discard (transmit must be enabled)0 = Transmit packets1 = Accept packets from the host, but do not transmit.

0

23 PAUSE_EN R/W Send PAUSE packets whenever TxPause input is true.0 = Disable1 = Enable PAUSE frame transmission.

0

22:15 THROT_DENOM R/W Number of bytes to transmit before adding TX THROT_NUM bytes to the IPG. 0x00

14:9 THROT_NUM R/W Number of bytes of extra inter-packet gap to be forced whenever TX THROT_DENOM bytes have been transmitted.

0x00

8:4 AVG_IPG R/W Average inter-packet gap that the transmitter maintains when presented with a continuous data stream. Individual inter-packet gaps vary in length (±3) from the average, as necessary, to meet XGMII restrictions on alignment of the /start/ symbol. The valid range is 8–31.

0xC

3:2 CRC_MODE R/W CRC mode0x0 = Append — CRC is appended to the data0x1 = Keep — CRC is passed through0x2 = Replace — CRC is replaced with that computed by the MAC0x3 = Reserved Attempts to write this value results in Replace being written

0x2

1:0 HDR_MODE R/W Header mode0x0 = IEEE Ethernet format0x1 = HiGig+— HiGig+ format0x2 = Reserved0x3 = Reserved

0x0

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MAC_TXMACSA

MAC_TXMAXSZ

Register description: PAUSE frames source MAC address


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

SA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SA

Table 117: MAC_TXMACSA



47:0 SA R/W This is the MAC SA in PAUSE packets transmitted by the MAC. Undefined

Register description: Maximum transmit packet size


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED SZ

Table 118: MAC_TXMAXSZ



13:0 SZ R/W Maximum packet size in bytes transmitted by the MAC. If the system tries to send a packet larger than specified by this register, the 10G MAC stops accepting data and asserts an error on the outgoing packet.The legal range is 64 to 16360, inclusive. The size includes the added 8-byte preamble in IEEE mode, but it does not include the CRC in APPEND mode.

0x05EE

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MAC_TXPSETHR

Register description: Transmit PAUSE threshold. Applicable for HG/XE ports only.

Register offset: 0x00g0000A (g = block number [2, 3, 4, 5])

Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

XON

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XOFF

Table 119: MAC_TXPSETHR



31:16 XON R/W Threshold for pause timer before XON is sent 0xFFFF

15:0 XOFF R/W Threshold for pause timer to cause XOFF to be resent 0xC000

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MAC_RXCTRL

Register description: Receive control


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ANY_START

RX_PASS_CTRL

RX_PAUS_EN

STRICT_PRMB

L

IGNORE_CRC

STRIP_CRC

HDR_MODE

Table 120: MAC_RXCTRL



7 ANY_START R/W Any start character0 = /start/ required to start a packet, per the XGMII specification.1 = Allow any non-idle character to start a packet.

0

6 RX_PASS_CTRL R/W MAC Control packets

0 = Do not pass MAC-control packets to the system.1 = MAC-control packets are passed to the system.

0

5 RX_PAUSEN R/W Receive pause enable0 = Disable1 = Received PAUSE packets inhibit transmission.

1

4 STRICT_PRMBL R/W Preamble mode0 = Non IEEE ethernet format1 = IEEE Ethernet format

1

3 IGNORE_CRC R/W Ignore CRC errors

0 = Do not ignore CRC errors 1 = Ignore CRC errors

0

2 STRIP_CRC R/W Strip CRC0 = Check CRC, do not strip CRC field1 = Check CRC, strip CRC field

1

1:0 HDR_MODE R/W Header mode0x0 = IEEE Ethernet format0x1 = HiGig+—HiGig+ format0x2 = Reserved0x3 = Reserved

0x0

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MAC_RXMACSA

MAC_RXMAXSZ

Register description: Receive MAC address for PAUSE frames


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

SA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SA

Table 121: MAC_RXMACSA



47:0 SA R/W Destination Address recognized for MAC control packets. This is in addition to the standard 0x0180C2000001.

Undefined

Register description: Receive maximum packet size


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED SZ

Table 122: MAC_RXMAXSZ



13:0 SZ R/W Maximum byte size of packets received by the MAC. Packets larger than this size are truncated and flagged as an error.The legal range is 64 to 16360, inclusive. This does not include the preamble in IEEE mode or CRC in STRIP mode.

0x05EE

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MAC_RXLSSCTRL

Register description: –


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RF_DIS

LF_DIS

Table 123: MAC_RXLSSCTRL



1 RF_DIS R/W Remote fault disable0 = When a remote fault LSS message is received, a continuous stream of IDLES are transmitted to the link partner.1 = Disable processing of LSS message type: Remote Fault.

0

0 LF_DIS R/W Local fault disable0 = When a local fault LSS message is received, a continuous stream of remote fault LSS messages are transmitted to the link partner.1 = Disable enable processing of LSS message type: Local Fault.

0

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MAC_RXLSSSTAT

Register description: –


Bit Number

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RF_STAT

LF_STAT

Table 124: MAC_RXLSSSTAT



1 RF_STAT RO Remote fault status0 = Remote fault messages are not being received.1 = Remote fault LSS messages are being received.

0

0 LF_STAT RO Local fault status0 = Local fault messages are not being received.1 = Local fault LSS messages are being received.

0

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XPORT_CONFIG

Register description: XPORT configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BMAC_RESET

HON_PAUS_FOR_E2E

MY_MODID

E2E_IBP_EN

E2E_HOL_

EN

XPAUS_EN

HG_MODE

XP_EN

Table 125: XPORT_CONFIG



12 BMAC_RESET R/W BigMAC enable

0 = Normal operation1 = Reset MAC

0

11 HON_PAUS_FORE2E

R/W Honor PAUSE frames for E2E0 = Send E2E packets, even though the local port may be paused1 = No E2E packets are transmitted if the local port is paused

0

10:5 MY_MODID R/W My Module ID 0x00

4 E2E_IBP_EN R/W E2E ingress backpressure enable

0 = Disable1 = Enable E2E IBP packet transmission

0

3 E2E_HOL_EN R/W E2E HOL enable0 = Disable1 = Enable E2E HOL packet transmission

0

2 XPAUS_EN R/W XPORT PAUSE enable0 = Disable1 = Enable XPORT pause

0

1 HG_MODE R/W HiGig+ mode enable

0 = Disable1 = XPORT is HiGig+ mode enabled

0

0 XP_EN R/W XPORT enable0 = Disable1 = XPORT is enabled

0

Note: MY_MOID for Xports must be defined here.

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XPAUSE_TX_PKT_XOFF_VAL

Register description: Pause xoff timer value


XPAUSE_WATCHDOG_INIT_VAL

Register description:

Register offset:

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XOFF_VAL

Table 126: XPAUSE_TX_PKT_XOFF_VAL



15:0 XOFF_VAL R/W Pause quanta value used for XOFF pause frame packet transmitted by the XPORT for end-to-end flow control

0xFFFF

Register description: XPORT PAUSE watchdog initial timer loading value


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INIT_VAL

Table 127: XPAUSE_WATCHDOG_INIT_VAL



15:0 INIT_VAL R/W Initial value of the watchdog timer used for retransmission of XOFF pause frames for end-to-end flow control.

0xFFFF

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XPAUSE_WATCHDOG_THRESH

A watchdog timer is used to control the retransmission of XOFF pause frames for end-to-end flow control. The initial valueof the watchdog timer is programmed to XPAUSE_WATCHDOG_INIT_VAL and is decremented each 512 bit-times. Whenthe watchdog timer value reaches this programmed threshold, an XOFF pause frame is retransmitted.

Register description: XPORT PAUSE watchdog XOFF retransmit timer threshold


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THRESH

Table 128: XPAUSE_WATCHDOG_THRESH



15:0 THRESH R/W Used to retransmit XOFF pause frame when the watchdog timer value equals this threshold.

0x7FFF

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XPAUSE_MH0

This register specifies the module header used for pause frames transmitted by the XPORT. The format is described below:

[31:24] SOP

[23:22] HGI

[21:16] RESERVED

[20:18] HDR_EXT_LEN

[17] SRC_MODID_6 (MSB)

[16] DST_MODID_6 (MSB)

[15:8] VID_HIGH

[7:0] VID_LOW

The following settings are required:

• SOP = 0xFB

• HGI = 0x10

• RESERVED = 0

• HDR_EXT_LEN = 0

The SRC_MODID should match the XPORT_CONFIG.MY_MODID setting. The VID fields should be programmed to a validVLAN.

Register description: XPORT PAUSE MH bytes 0–3


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_0_3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_0_3

Table 129: XPAUSE_MH0


31:0 MH_BYTES_0_3 R/W XPORT PAUSE Module Header bytes 0–3 0x00000000

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XPAUSE_MH1

This register specifies the module header used for pause frames transmitted by the XPORT. The format is described below:

[31:27] SRC_MODID (4:0)

[26:24] OPCODE

[23:22] PFM

[21:16]] SRC_PORT_TGID

[15:11] DST_PORT

[10:8] CoS

[7:6] HDR_FMT

[5] CNG

[4:0] DST_MODID (4:0)


• OPCODE = 2

• CoS = 7

PFM, SRC_PORT_TGID, DST_PORT, HDR_FMT, DST_MODID, and CNG can be set to 0. Since the opcode = 2, thepacket is considered a broadcast/DLF by the fabric, hence the DST_MODID is not used. The SRC_MODID should matchthe setting in XPORT_CONFIG.MY_MODID.



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_4_7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_4_7




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XPAUSE_MH2

This register specifies the module header used for pause frames transmitted by the XPORT. This register represents thethird DWord in the HiGig+ header module and should be set to 0x00000000.

XPAUSE_D0

This register specifies the first set of four bytes of the Ethernet frame used for pause frames transmitted by the XPORT. Theformat is described below:

[31:0] DA MAC Address [48:16]

The DA MAC Address programmed must match the XIBP_RX_DA_MS and XIBP_RX_DA_LS settings in the remotemodules.



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_8_11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_8_11




Register description: XPORT PAUSE data bytes 0–3


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_0_3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_0_3

Table 132: XPAUSE_D0


31:0 DATA_BYTES_0_3 R/W XPORT PAUSE data bytes 0–3 0x0180C200

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XPAUSE_D1

This register specifies the second set of four bytes of the Ethernet frame used for pause frames transmitted by the XPORT.The format is described below:


[15:0] SA MAC Address [47:32]

The DA MAC Address programmed must match the IPAUSE_RX_DA_MS and IPAUSE_RX_DA_LS settings in the remotemodules.

XPAUSE_D2

This register specifies the third set of four bytes of the Ethernet frame used for pause frames transmitted by the IPIC. Theformat is described below:




Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_4_7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_4_7



31:0 DATA_BYTES_4_7 R/W XPORT PAUSE data bytes 4–7 0x00010000



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_8_11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_8_11




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XPAUSE_D3

This register specifies the fourth set of four bytes of the Ethernet frame used for pause frames transmitted by the XPORT.The format is described below:

[31:16] Length/Type

[15:0] MAC Control Opcode

The Length/Type programmed must match the XPAUSE_RX_LENGTH_TYPE field, and the MAC Control Opcode mustmatch the XPAUSE_RX_OPCODE settings in the remote modules.



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_12_15

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_12_15




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XHOL_MH0

This register specifies the module header used for HOL frames transmitted by the XPORT. The format is described below:

[31:24] SOP

[23:22] HGI

[21:16] RESERVED

[20:18] HDR_EXT_LEN



[15:8] VID_HIGH

[7:0] VID_LOW


• SOP = 0xFB

• HGI = 0x10

• RESERVED = 0

• HDR_EXT_LEN = 0


Register description: XPORT E2E HOL packet MH bytes 0–3

Register offset: 0x00g8000B (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_0_3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_0_3

Table 136: XHOL_MH0


31:0 MH_BYTES_0_3 R/W XPORT PAUSE Module Header bytes 0–3 0xFB800FFE

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XHOL_MH1

This register specifies the module header used for HOL frames transmitted by the XPORT. The format is described below:

[31:27] SRC_MODID (4:0)

[26:24] OPCODE

[23:22] PFM


[15:11] DST_PORT

[10:8] CoS

[7:6] HDR_FMT

[5] CNG

[4:0] DST_MODID (4:0)


• OPCODE = 2

• CoS = 7

PFM, SRC_PORT_TGID, DST_PORT, HDR_FMT, DST_MODID, and CNG can be set to 0. Since OPCODE = 2, the packetis considered a broadcast/DLF by the fabric, hence the DST_MODID is not used. The SRC_MODID should match the settingin XPORT_CONFIG.MY_MODID.


Register offset: 0x00g8000C (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_4_7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_4_7

Table 137: XHOL_MH1


31:0 MH_BYTES_4_7 R/W XPORT HOL Module Header bytes 4–7 0x20000000

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XHOL_MH2

This register specifies the module header used for HOL frames transmitted by the XPORT. This register represents the thirdDWord in the HiGig+ header module and should be set to 0x00000000.

XHOL_D0

This register specifies the first four bytes of the Ethernet frame used for HOL frames transmitted by the XPORT. The formatis described below:


The DA MAC Address programmed must match the XHOL_RX_DA_MS and the XHOL_RX_DA_LS settings in the remotemodules.


Register offset: 0x00g8000D (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_8_11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_8_11

Table 138: XHOL_MH2


31:0 MH_BYTES_8_11 R/W XPORT HOL Module Header bytes 8–11 0x00000000

Register description: XPORT HOL data bytes 0–3

Register offset: 0x00g8000E (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_0_3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_0_3

Table 139: XHOL_D0


31:0 DATA_BYTES_0_3 R/W XPORT HOL Data bytes 0–3 0xFFFFFFFF

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XHOL_D1

This register specifies the second four bytes of the Ethernet frame used for HOL frames transmitted by the XPORT. Theformat is described below:



The DA MAC Address programmed must match the XHOL_RX_DA_MS and the XHOL_RX_DA_LS settings in the remotemodules.

XHOL_D2

This register specifies the third four bytes of the Ethernet frame used for HOL frames transmitted by the IPIC. The format isdescribed below:



Register offset: 0x00g8000F (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_4_7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_4_7

Table 140: XHOL_D1


31:0 DATA_BYTES_4_7 R/W XPORT HOL data bytes 4–7 0xFFFF0000



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_8_11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_8_11

Table 141: XHOL_D2


31:0 DATA_BYTES_8_11 R/W XPORT HOL data bytes 8–11 0x00000001

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XHOL_D3

This register specifies the fourth four bytes of the Ethernet frame used for HOL frames transmitted by the XPORT. The formatis described below:

[31:16] Length/Type


The Length/Type programmed must match the XHOL_RX_LENGTH_TYPE field and the MAC Control Opcode must matchthe XHOL_RX_OPCODE settings in the remote modules.



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_12_15

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_12_15

Table 142: XHOL_D3


31:0 DATA_BYTES_12_15 R/W XPORT HOL data bytes 12–15 0x88080001

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XIBP_MH0

This register specifies the module header used for IBP frames transmitted by the XPORT for end-to-end flow control. Theformat is described below:

[31:24] SOP

[23:22] HGI

[21:16] RESERVED

[20:18] HDR_EXT_LEN



[15:8] VID_HIGH

[7:0] VID_LOW


• SOP = 0xFB

• HGI = 0x10

• RESERVED = 0

• HDR_EXT_LEN = 0


Register description: XPORT E2E IBP packet MH bytes 0–3


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_0_3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_0_3

Table 143: XIBP_MH0


31:0 MH_BYTES_0_3 R/W XPORT E2E IBP packet MH bytes 0–3 0xFB800FFE

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XIBP_MH1

This register specifies the module header used for IBP frames transmitted by the XPORT for end-to-end flow control. Theformat is described below:

[31:27] SRC_MODID (4:0)

[26:24] OPCODE

[23:22] PFM


[15:11] DST_PORT

[10:8] CoS

[7:6] HDR_FMT

[5] CNG

[4:0] DST_MODID (4:0)


• OPCODE = 2

• CoS = 7

PFM, SRC_PORT_TGID, DST_PORT, HDR_FMT, DST_MODID, and CNG can be set to 0. Since OPCODE = 2, the packetis considered a broadcast/DLF by the fabric and hence the DST_MODID is not used. The SRC_MODID should match thesetting in XPORT_CONFIG.MY_MODID.



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_4_7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_4_7

Table 144: XIBP_MH1


31:0 MH_BYTES_4_7 R/W XPORT E2E IBP packet MH bytes 4–7 0x10000000

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XIBP_MH2

This register specifies the module header used for IBP frames transmitted by the XPORT for end-to-end flow control. Thisregister represents the third DWord in the HiGig+ header module and should be set to 0x00000000.

XIBP_D0

This register specifies the first four bytes of the Ethernet frame used for IBP frames transmitted by the XPORT for end-to-end flow control. The format is described below:


The DA MAC Address programmed must match the XIBP_RX_DA_MS and XIBP_RX_DA_LS settings in the remotemodules.



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MH_BYTES_8_11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MH_BYTES_8_11

Table 145: XIBP_MH2


31:0 MH_BYTES_8_11 R/W XPORT E2E IBP packet MH bytes 8–11 0x00000000

Register description: XPORT E2E IBP Data bytes 0–3


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_0_3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_0_3

Table 146: XIBP_D0


31:0 DATA_BYTES_0_3 R/W XPORT E2E IBP Data bytes 0–3 0xFFFFFFFF

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XIBP_D1




The DA MAC Address programmed must match the IPAUSE_RX_DA_MS and IPAUSE_RX_DA_LS settings in the remotemodules.

XIBP_D2





Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_4_7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_4_7

Table 147: XIBP_D1


31:0 DATA_BYTES_4_7 R/W XPORT E2E IBP data bytes 4–7 0xFFFF0000



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_8_11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_8_11

Table 148: XIBP_D2


31:0 DATA_BYTES_8_11 R/W XPORT E2E IBP data bytes 8–11 0x00000001

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XIBP_D3


[31:16] Length/Type


The Length/Type programmed must match the XPAUSE_RX_LENGTH_TYPE field and the MAC Control Opcode mustmatch the XPAUSE_RX_OPCODE settings in the remote modules.

XPAUSE_RX_DA_MS

The XPAUSE_RX_DA_MS and XPAUSE_RX_DA_LS settings should match the DA MAC Address programmed in theXPAUSE_D0 and XPAUSE_D1 registers in the remote modules.



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA_BYTES_12_15

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA_BYTES_12_15

Table 149: XIBP_D3


31:0 DATA_BYTES_12_15 R/W XPORT E2E IBP data bytes 12–15 0x70000000

Register description: XPORT PAUSE RX packet DA


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA

Table 150: XPAUSE_RX_DA_MS



15:0 DA R/W XPORT RX packet expected DA [47:32] 0x0180

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XPAUSE_RX_DA_LS

The XPAUSE_RX_DA_MS and XPAUSE_RX_DA_LS settings should match the DA MAC Address programmed in theXPAUSE_D0 and XPAUSE_D1 registers in the remote modules.

XPAUSE_RX_LENGTH_TYPE

The XPAUSE_RX_LENGTH_TYPE setting should match the Length/Type setting programmed in XPAUSE_D3 register inthe remote modules.

Register description: XPORT PAUSE RX packet DA


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA

Table 151: XPAUSE_RX_DA_LS


31:0 DA R/W XPORT RX packet expected DA [31:0] 0xC2000001

Register description: XPORT PAUSE RX packet expected Length/Type field

Register offset: 0x00g8001B (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENGTH_TYPE

Table 152: XPAUSE_RX_LENGTH_TYPE



15:0 LENGTH_TYPE R/W Receive pause frame expected length/type field 0x8808

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XPAUSE_RX_OPCODE

The XPAUSE_RX_OPCODE setting should match the MAC Control Opcode setting programmed in XPAUSE_D3 registerin the remote modules.

XP_EGR_PKT_DROP_CTL

Register description: PORT PAUSE RX packet expected opcode field

Register offset: 0x00g8001C (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCPODE

Table 153: XPAUSE_RX_OPCODE



15:0 OPCODE R/W XPORT PAUSE RX packet expected Opcode field 0x0001

Register description: Flush enable control of XPORT register

Register offset: 0x00g8001D (g = block number [2, 3, 4, 5])

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED FLUSH

Table 154: XP_EGR_PKT_DROP_CTL



0 FLUSH R/W Flush enable bit to drop packets in XPORT


0

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Section 7: Ingress Pipeline Registers

AUX_ARB_CONTROL

Register description: Auxiliary arbiter control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CLK_GRAN FP_REFRESH_EN

L2_MOD_FIFO_

EN

L2_MOD_FIFO_LOCK

Table 155: AUX_ARB_CONTROL



4:3 CLK_GRAN R/W Clock granularity for aging 0x3

2 FP_REFRESH_EN R/W Enables sending FP refreshes down the pipeline0 = Do not send1 = Send FP refresh

0

1 L2_MOD_FIFO_EN R/W Enables tracking the L2_MOD_FIFO—cause learns/ages to get blocked when full 0

0 L2_MOD_FIFO_

LOCK

R/W L2 FIFO lock

0 = Do not lock1 = Locks the L2_MOD_FIFO

0

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ING_HW_RESET_CONTROL_1

ING_HW_RESET_CONTROL_2

Register description: Ingress hardware reset control 1


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED OFFSET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED STAGE_NUMBER

Table 156: ING_HW_RESET_CONTROL_1



25:6 OFFSET R/W 20-bit starting offset of table for memory 0x0000000

5:0 STAGE_NUMBER R/W IP stage for the memory table 0x00

Register description: Ingress hardware reset control 2


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED DONE VALID RESET_ALL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

COUNT

Table 157: ING_HW_RESET_CONTROL_2



18 DONE R/W Set by arbiter to indicate memory table writes have completed0 = Not done1 = Memory table write complete

0

17 VALID R/W Set by software to trigger memory initialization

0 = Normal operation1 = Start memory initialization

0

16 RESET_ALL R/W Indicates all memories in all stages should be initialized (independent of stage or table number)

0

15:0 COUNT R/W Number of entries of memory to initialize 0x0000

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L2_AGE_TIMER

Register description: L2 table aging timer control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED AGE_EN

AGE_VAL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AGE_VAL

Table 158: L2_AGE_TIMER



20 AGE_EN R/W Address aging enable0 = Disable1 = Enable

0

19:0 AGE_VAL R/W Value is the age timer in units of 1 second to age dynamic entries. Default is 300 seconds.When aging is first enabled, it may take up to three times the AGE_VAL for aging to occur because AGE_ENA is asynchronous to the internal timers.Note: IEEE 802.1d specification range is 10 to 1,000,000 seconds

0x12C

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PER_PORT_AGE_CONTROL

Register description: Per port address aging control. This register controls software initiated aging, which allows thesoftware to purge all static and dynamic entries for a given VLAN or port from the L2 table.

To use th is featu re hardware ( t ime-based), ag ing must be d isab led by set t ingL2_AGE_TIMER.AGE_ENA to 0. Hardware aging may be re-enabled after the software initiatedaging is complete.

Set PPA_MODE to select the fields to match and action taken.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED CMPLT START EXCL_STATIC

PPA_MODE VLAN_ID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VLAN_ID MODULE_ID TGID_PORT

Table 159: PER_PORT_AGE_CONTROL



29 CMPLT R/W Per-port aging complete. Indicates that software initiaged aging is complete. Software should clear this bit when START is written to 1. Hardware will set this bit to 1 when the aging process is complete.0 = Not complete1 = Complete

0

28 START R/W Initiate per-port aging. Software should write this bit to 1 to start software initiaged aging. This bit will automatically be cleared when the aging process has completed.0 = Do not start1 = Start per-port aging

0

27 EXCL_STATIC R/W Exclude static entries

0 = Include1 = Exclude static entries from deletion/replacement

0

26:24 PPA_MODE R/W Indicates selection criteria; deletion versus replacement0x0 = PORTMOD_DEL—If match module ID and port/TGID, then delete entry0x1 = VLAN_DEL—If match VLAN ID, then delete entry0x2 = PORTMOD_VLAN_DEL—If match VLAN ID, module ID, and port/TGID, then delete entry0x4 = PORTMOD_REPL—If match module ID and port/TGID, then replace module ID/port from PER_PORT_REPL_CONTROL0x5 = VLAN_REPL—If match VLAN ID, then replace module ID/port from PER_PORT_REPL_CONTROL0x6 = PORTMOD_VLAN_REPL—If match VLAN ID, module ID, and port/TGID, then replace module ID/port from PER_PORT_REPL_CONTROL

0x0

23:12 VLAN_ID R/W Indicates the VLAN ID to purge. 0x000

11:6 MODULE_ID R/W Indicates the module ID to purge. This field is used with the TGID_PORT field to uniquly identify a module/port to age. If the TGID_PORT field indicates a trunk group, then this field is not used.

0x00

5:0 TGID_PORT R/W Indicates the port to purge. This field is used with the MODULE_ID field to uniquely identify a port or trunk group to age.If the MSB of this field is 0, the lower five bits of this field indicate a port.

If the MSB of this field is 1, the lower five bits of this field indicates a trunk group (TGID). This is used to age entries specific to a given trunk group.

0x00

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ING_CONFIG

Register description: Ingress configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED APPLY_EGR_

MASK_ON_L2

APPLY_EGR_

MASK_ON_L3

CVLAN_CFI-AS_

CNG

STACK_MODE FB_A0_COMPATIBLE

EN_FP_

FOR_MIRR_

PKT

SNAP_OTHER_DEC_

EN

RSVD DRACO_15_MIRR

L3SH_EN

L2DH_EN

TRUNK_128

DT_MODE

Table 160: ING_CONFIG



13 APPLY_EGR_MASK_ON_L2

R/W Apply Egress mask for L2 switched packets 1

12 APPLY_EGR_MASK_ON_L3

R/W Apply Egress mask for L3 switched packets 1

11 CVLAN_CFI-AS_CNG R/W CFI CNG map for customer tag 0

10:9 STACK_MODE R/W Stacking mode.0x0 = STACK_FB—Stacking with XGS 30x1 = STACK_56700x2 = STACK_56750x3 = RESERVED

0x0

8 FB_A0_COMPATIBLE R/W Disables source MODID checks for mirror packets on HiGig when in XGS 3 style of mirroring.

0

7 STNMOVE_ON_L2SRC_DISC

R/W Perform station movement on L2 source discard packets.0 = Disable1 = Enable

0

6 SNAP_OTHER_DEC_EN

R/W Decode SNAP packets with nonzero OUI for protocol-based VLAN.0 = Disable1 = Enable

0


4 DRACO_15_MIRR R/W BCM5695 mirroring mode enable0 = XGS 3 mirroring mode enable1 = BCM5695 mirroring mode enable

0

3 L3SH_EN R/W Controls the update of the HIT bit in the L3 table upon an IP source address match.0 = Do not update L3 table hit bit1 = Update the L3 table hit bitHit bit in the L3 table is always updated upon a destination IP match.

0

2 L2DH_EN R/W L2 destination hit bit enable0 = Do not update hit bit on dst match1 = Update the L2 table hit bit on a dst match

0

1 TRUNK_128 R/W Enable 128 trunk groups0 = Disable1 = Enable

0

0 DT_MODE R/W Double tagging enable


0

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DOS_CONTROL

Register description: Denial of service control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED DROP_SIP_EQ_DIP

MIN_TCP_HDR_SZ

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MIN_TCP_HDR_

SZ

BIG_ICMP_PKT_SZ IPV4_FIRST_FRAG_

EN

TCP_FLAG_CHK_

EN

L4_PORT_CHK_

EN

TCP_FRAG_CHK_

EN

IPMC_CHK_

EN

Table 161: DOS_CONTROL



29 DROP_DIP_EQ_SIP R/W Drop IPv4/IPv6 packets if the SIP == DIP

0 = Do not drop1 = Drop

0

28:21 MIN_TCP_HDR_SZ R/W Minimum TCP header length allowed (minimum 0 bytes, maximum 255 bytes) 0x14

20:5 BIG_ICMP_PKT_SZ R/W Maximum length ICMP packet allowed before dropping (maximum 1023 bytes) 0x200

4 IPV4_FIRST_FRAG_EN

R/W Enable checking on first fragment IP packets


0

3 TCP_FLAG_CHK_EN R/W Enable checking TCP DOS attacks on invalid flags0 = Disable1 = Enable. The following packets are dropped:• TCP SYN flag = 1 & source port < 1024• TCP control flags = 0 & sequence # = 0

• TCP FIN, URG, PSH bits set & sequence # = 0• TCP SYN & FIN bits set

0

2 L4_PORT_CHK_EN R/W Enable checking TCP/UDP DOS attack for dropping packet if TCP/UDP source port == destination port0 = Disable1 = Enable

0

1 TCP_FRAG_CHK_EN R/W Enable checking TCP DOS fragment attack

0 = Disable1 = Enable. The following packets will be dropped:

• First TCP fragments that have a TCP header < MIN_TCP_HDR_SZ• TCP fragments with offset value of 1

0

0 ICMP_CHK_EN R/W Enable ICMP DOS attack checks

0 = Disable1 = Enable. The following packets are dropped:

• ICMPv6 ping packets with payload size > DOS_CONTROL2.BIG_ICMPV6_PKT_SZ

• ICMP ping packets with payload size > BIG_ICMP_PKT_SZ

• Fragmented ICMP packets

0

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DOS_CONTROL_2

VLAN_CTRL

Register description: Denial of service control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIG_ICMPV6_PKT_SIZE

Table 162: DOS_CONTROL_2



15:0 BIG_ICMPV6_PKT _SIZE

R/W Maximum length ICMPv6 ping packet allowed before dropping (maximum of 16 KB) 0x0200

Register description: VLAN control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED INNER_TPID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INNER_TPID USE_LEARN_

VID

LEARN_VID

Table 163: VLAN_CTRL



28:13 INNER_TPID R/W TPID for inner VLAN used for double-tagging modes only 0x8100

12 USE_LEARN_VID R/W USE LEARN_VID field from this register for ARL learning0 = Disable1 = Use the LEARN_VID field for learning/look-ups

0

11:0 LEARN_VID R/W LEARN_VID for learning/look-ups 0x000

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HASH_CONTROL

Register description: HASH control. Use this register to control port selection when the destination is a trunk group.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED USE_UDP_TCP_

PORTS

ENA_DRACO

_15_HASH

L3_HASH_SELECT L2_VLAN_MAC_HASH_SEL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

L2_VLAN_MAC_HASH_

SEL

ECMP_HASH_SEL

ECMP_HASH_USE_DIP

ECMP_HASH_UDF UC_TRUNK_HASH_

USE_SRC_PORT

NON_UC_

TRUNK_HASH_

DST_EN

NON_UC_

TRUNK_HASH_

SRC_EN

NON_UC_

TRUNK_HASH_MOD_PORT_

EN

Table 164: HASH_CONTROL



22 USE_TCP_UDP_PORTS

R/W Use TCP/UDP ports for ECMP unicast trunk hashing


0

21 ENA_DRACO_15_HASH

R/W BCM5695 hashing for unicast trunking0 = Disable1 = Enable

0

20:18 L3_HASH_SEL R/W Selects hashing algorithm used for L3 table lookups0x0 = Reserved0x1 = CRC32_UPPER—Upper bits of CRC-320x2 = CRC32_LOWER—Lower bits of CRC-320x3 = LSB—Always return LSB of key as the hash0x4 = CRC16_LOWER—Lower bits of CRC-160x5 = CRC16_UPPER—Upper bits of CRC-16

0x2

17:15 L2_AND_VLAN_MAC_HASH_SELECT

R/W Selects hashing algorithm used for L2 table lookups0x0 = Reserved0x1 = CRC32_UPPER—Upper bits of CRC-320x2 = CRC32_LOWER—Lower bits of CRC-320x3 = LSB—Always return LSB of key as the hash0x4 = CRC16_LOWER—Lower bits of CRC-160x5 = CRC16_UPPER—Upper bits of CRC-16

0x2

14:13 ECMP_HASH_SEL R/W Selects ECMP hashing algorithm0x0 = Reserved0x1 = CRC32_UPPER—Upper bits of CRC-320x2 = CRC32_LOWER—Lower bits of CRC-320x3 = LSB—Always return LSB of key as the hash

0x2

12 ECMP_HASH_USE_DIP

R/W Use DIP for ECMP hashing0 = Disable1 = Enable

0

11:4 ECMP_HASH_UDF R/W ECMP hash offset 0x00

3 UC_TRUNK_HASH_USE_SRC_PORT

R/W Use SRC port in unicast trunk hash


0

2 NON_UC_TRUNK_HASH_DST_EN

R/W Include dest MAC or dest IP into non-unicast trunk block mask hashing0 = Disable1 = Enable

0

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1 NON_UC_TRUNK_HASH_SRC_EN

R/W Include source MAC or source IP into non-unicast trunk block mask hashing0 = Disable1 = Enable

0

0 NON_UC_TRUNK_HASH_MOD_PORT_EN

R/W Include MODID/port into non-unicast trunk block mask hashing


0

Table 164: HASH_CONTROL


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UDF_ETHERTYPE_MATCH

UDF_IPPROTO_MATCH

Register description: UDF Ethertype Match register (used to select unique UDF offsets for different EtherTypes)

Register offset: 0x0278001a–0x02780021

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ENABLE L2 PACKETFORMAT

RESV

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ETHERTYPE

Table 165: UDF_ETHERTYPE_MATCH


31:20 RESERVED – Reserved –

19 ENABLE R/W Enables UDF ethertype match 0

18:17 L2_PACKET_FORMAT R/W L2 packet format to match for UDF ethertype match –


15:0 ETHERTYPE R/W Programmable ethertype to match for UDF ethertype match 0x0000

Register description: UDF IP Protocol Matching register (Select unique UDF offsets for different IP protocols)

Register offset: 0x0278022–0x027803

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED IPV4ENABLE

IPB6ENABLE

PROTOCOL

Table 166: UDF_ETHERTYPE_MATCH



9 IPV4ENABLE R/W Enable this UDF matching mechanism for IPv4 0

8 IPB6ENABLE R/W Enable this UDF matching mechanism for IPv6 –

7:0 PROTOCOL R/W IP protocol to match 0x00

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PER_PORT_REPL_CONTROL

This register is used along with PER_PORT_AGE_CONTROL to replace the module ID and port/trunk group in L2 tableentries. MODULE_ID and PORT_TGID fields in this register determine the value of the replaced fields.

L2_MOD_FIFO_CNT

Register description: Replacement control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED MODULE_ID PORT_TGID

Table 167: PER_PORT_REPL_CONTROL



11:6 MODULE_ID R/W Module ID 0x00

5:0 PORT_TGID R/W Port/TGID 0x00

Register description: L2_MOD FIFO count

Register offset: 0x0678000A

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED NUM_ENTRIES

Table 168: L2_MOD_FIFO_CNT



4:0 NUM_ENTRIES R/W A count of the number of entries in the L2_MOD_FIFO. This is actually the hardware write pointer, so it points to the last entry in the buffer.

0x00

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L2_ENTRY_PARITY_CONTROL

L2_ENTRY_PARITY_STATUS

Register description: L2 Entry Parity Control register


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PARITY_EN

PARITY_IRQ_

EN

Table 169: L2_ENTRY_PARITY_CONTROL



1 PARITY_EN R/W This bit enables parity checking for the L2_ENTRY table. 0

0 PARITY_IRQ_EN R/W This bit is AND’d with the PARITY_ERR bit of the PARITY_STATUS register to generate the parity IRQ. The PARITY_ERR and BUCKET_IDX/ENTRY_BM are sticky while this bit is set. Clearing this bit clears the PARITY_ERR bit.

–

Register description: L2 entry parity status register

Register offset: 0x0678000D

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BUCKET_IDX

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUCKET_IDX ENTRY_BM PARITY_IRQ_

EN

Table 170: L2_ENTRY_PARITY_STATUS



19:9 BUCKET_IDX RO This field indicates the index to the bucket in which the parity error was detected. 0x000

8:1 ENTRY_BM RO This bitmap indicates the entries that had parity errors. Bits [7:0] correspond to entries 7..0.

0x00

0 PARITY_ERR RO When set, this bit indicates that a parity error has been detected. 0

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L3_DEFIP_CAM_ENABLE

Register description: CAM enable


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CAM_5_EN

CAM_4_EN

CAM_3_EN

CAM_2_EN

CAM_1_EN

CAM_0_EN

Table 171: L3_DEFIP_CAM_ENABLE



5 CAM_5_EN R/W L3_DEFIP_CAM_ENABLE for L3_DEFIP slice 50 = Disable1 = Enable

1


1

3 CAM_3_EN R/W L3_DEFIP_CAM_ENABLE for L3_DEFIP slice 3


1


1


1

0 CAM_0_EN R/W L3_DEFIP_CAM_ENABLE for L3_DEFIP slice 0


1

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L3_ENTRY_PARITY_CONTROL

L3_ENTRY_PARITY_STATUS

Register description: L3 Entry Parity Control register

Register offset: 0x0878000B

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PARITY_EN

PARITY_IRQ_

EN

Table 172: L3_ENTRY_PARITY_CONTROL



1 PARITY_EN R/W This bit enables parity checking for the L3_ENTRY table. 0

0 PARITY_IRQ_EN R/W This bit is AND’d with the PARITY_ERR bit of the PARITY_STATUS register to generate the parity IRQ. The PARITY_ERR and BUCKET_IDX/ENTRY_BM are sticky while this bit is set. Clearing this bit clears the PARITY_ERR bit.

–

Register description: L3 entry parity status register


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BUCKET_IDX

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUCKET_IDX ENTRY_BM PARITY_ERR

Table 173: L3_ENTRY_PARITY_STATUS



19:9 BUCKET_IDX RO This field indicates the index to the bucket in which the parity error was detected. 0x000

8:1 ENTRY_BM RO This bitmap indicates the entries that had parity errors. Bits [7:0] correspond to entries 7..0.

0x00


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L3_DEFIP_PARITY_CONTROL

L3_DEFIP_PARITY_STATUS

Register description: L3 DEFIP parity control register


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PARITY_EN

PARITY_IRQ_

EN

Table 174: L3_DEFIP_PARITY_CONTROL



1 PARITY_EN R/W This bit enables parity checking for the L3_DEFIP RAM table. 0

0 PARITY_IRQ_EN R/W This bit is AND'd with the PARITY_ERR bit of the PARITY_STATUS register to generate the parity IRQ. The PARITY_ERR and MEMORY_IDX are sticky while this bit is set. Clearing this bit clears the PARITY_ERR bit.

–

Register description: L3 DEFIP parity status register


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED MEMORY_IDX PARITY_ERR

Table 175: L3_DEFIP_PARITY_STATUS



13:1 MEMORY_IDX RO This field indicates the index to the bucket in which the parity error was detected. 0x0000


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CNG_MAP

Register description: CNG mapping

Register offset: 0x0B7pp000

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED RESERVED RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRIORITY7_CNG PRIORITY6_CNG PRIORITY5_CNG PRIORITY4_CNG PRIORITY3_CNG PRIORITY2_CNG PRIORITY1_CNG PRIORITY0_CNG

Table 176: CNG_MAP





15:14 PRIORITY7_CNG R/W Maps the priority(7) to a default CNG (congestion value for untrusted ports). 0x0








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BCAST_STORM_CONTROL

Each port has a counter that tracks the number of broadcast packets received per second. The counter is cleared once persecond. If the broadcast rate control is enabled, the port discards all broadcast packets received when the counter is greateror equal to the programmed THRESHOLD.

Register description: Broadcast storm control (per port)

Register offset: 0x0B7pp001 (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ENA THRESHOLD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THRESHOLD

Table 177: BCAST_STORM_CONTROL



25 ENA R/W Storm control enable


0

24:0 THRESHOLD R/W Broadcast packets rate limit in packets per second (pps) 0

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MCAST_STORM_CONTROL

Each port has a counter that tracks the number of multicast packets received per second. The counter is cleared once persecond. If the multicast rate control is enabled, the port discards all multicast packets received when the counter is greateror equal to the programmed THRESHOLD.

Register description: Multicast storm control (per port)


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THRESHOLD

Table 178: MCAST_STORM_CONTROL





0

24:0 THRESHOLD R/W Multicast packets rate limit, in packets per second (pps) 0

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DLF_STORM_CONTROL

Each port has a counter that tracks the number of DLF packets received per second. The counter is cleared once per second.If the DLF rate control is enabled, the port discards all DLF packets received when the counter is greater or equal to theprogrammed THRESHOLD.

Register description: Destination look-up (DLF) storm control (per port)


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THRESHOLD

Table 179: DLF_STORM_CONTROL





0

24:0 THRESHOLD R/W DLF packets rate limit in packets per second (pps) 0

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PROTOCOL_PKT_CONTROL

Register description: Protocol packet control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ARP_REPLY_DROP

ARP_REPLY_

TO_CPU

ARP_REQ_DROP

ARP_REQ_TO_CPU

ND_PKT__DROP

ND_PKT_TO_CPU

IGMP_PKT__DROP

IGMP_PKT_TO_CPU

MLD_PKT__DROP

MLD_PKT_TO_CPU

IPV4_RESV_

MC_PKT__DROP

IPV4_RESV_

MC_PKT__TO_CPU

IPV6_RESV_

MC_PKT__DROP

IPV6_RESV_

MC_PKT__TO_CPU

DHCP_PKT__DROP

DHCP_PKT_TO_CPU

Table 180: PROTOCOL_PKT_CONTROL



15 ARP_REPLY_DROP R/W ARP reply drop control0 = Do not drop1 = Drop

0

14 ARP_REPLY_TOCPU R/W ARP reply CPU control

0 = Do not send to CPU1 = Send to CPU

0

13 ARP_REQ_DROP R/W ARP request drop control0 = Do not drop1 = Drop

0

12 ARP_REQ_TOCPU R/W ARP request CPU control0 = Do not send to CPU1 = Send to CPU

0

11 ND_PKT_DROP R/W ND packet drop control


0

10 ND_PKT_TOCPU R/W ND packet CPU control0 = Do not send to CPU1 = Send to CPU

0

9 IGMP_PKT_DROP R/W IGMP packet drop control0 = Do not drop1 = Drop

0

8 IGMP_PKT_TOCPU R/W IGMP packet CPU control


0

7 MLD_PKT_DROP R/W MLD packet drop control0 = Do not drop1 = Drop

0

6 MLD_PKT_TOCPU R/W MLD packet CPU control0 = Do not send to CPU1 = Send to CPU

0

5 IPV4_RESV_MC_PKT_DROP

R/W IPv4 reserved multicast packet drop control


0

4 IPV4_RESV_MC_PKT_TOCPU

R/W IPv4 reserved multicast packet CPU control0 = Do not send to CPU1 = Send to CPU

0

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LTDPROTOCOL_PKT_CONTROL identifies each of the packet types with the following criteria:

• ARP Packet

- ETHERTYPE == 0x0806 || 0x8035

- Protocol == IPv4

• ARP Request

- ARP Packet

- ARP Opcode == 0x1 || 0x3

• ARP Reply

- ARP Packet

- NOT ARP Request

- DA must be in L2_ENTRY with L3 bit set

• IGMP Packet

- IPv4 Packet

- IPv4 header Protocol Type == IGMP (0x02)

• ND Packet

- IPv6 Packet

- IPv6 header Protocol Type == ICMP V6 (0x3a)

- ICMP Type == 0x85 - 0x89

• MLD Packet

- IPv6 Packet

- IPv6 header Protocol Type == ICMP V6 (0x3a)

- ICMP Type == 0x82 - 0x84

• IPv4 Reserved MC

- IPv4 Packet

- IPv4 DIP = 224.0.0.x

• IPv6 Reserved MC

- IPv6 Packet

- IPv6 DIP = ff0X:0:0:0:0:0:0:0

• DHCP

- IPv4 || IPv6 Packet

- Header Protocol = UDP

- (SPORT == 0x43 && DPORT == 0x44) || (SPORT == 0x44 && DPORT == 0x43)

3 IPV6_RESV_MC_PKT_DROP

R/W IPv6 reserved multicast packet drop control0 = Do not drop1 = Drop

0

2 IPV6_RESV_MC_PKT_TOCPU

R/W IPv6 reserved multicast packet CPU control


0

1 DHCP_PKT_DROP R/W DHCP packet drop control0 = Do not drop1 = Drop

0

0 DHCP_PKT_TOCPU R/W DHCP packet CPU control0 = Do not send to CPU1 = Send to CPU

0

Table 180: PROTOCOL_PKT_CONTROL


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CPU_CONTROL_1

Register description: CPU control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED NIP_L3ERR_

TOCPU

L3_MTU_FAIL_TOCPU

PARITY_ERR_TOCPU

L3_SLOW_PATH_TOCPU

ICMP_RED_

TOCPU

ICMP_TTL_ERR_

TOCPU

L3UC_TTL_ERR_

TOCPU

DOS_ATT_

TOCPU

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TUN_ERR_

TOCPU

MART_ADDR_TOCPU

V6L3_ERR_

TOCPU

SRC_RTE_

TOCPU

IPMC_PORT_MISS_TOCPU

V4L3_DST_MISS_TOCPU

V6L3_DST_MISS_TOCPU

UNRES_

L3SRC_TOCPU

UVLAN_TOCPU

IPMC_ERR_

TOCPU

V4L3_ERR_

TOCPU

UUCAST_

TOCPU

UMC_TOCPU

UIPMC_TOCPU

NON_STAT_MOV_

TOCPU

STAT_MOV_

TOCPU

Table 181: CPU_CONTROL_1



23 NIP_L3ERR_TOCPU R/W Enable NON-IP l3 error send to CPU 0

22 L3_MTU_FAIL_TOCPU R/W Enable L3 MTU fail to CPU 0

21 PARITY_ERR_TOCPU R/W Enable Parity Error to CPU 0

20 L3_SLOW_PATH_TOCPU R/W L3 slow path to CPU enable

0 = Do not send to CPU1 = Enable

0

19 ICMP_RED_TOCPU R/W ICMP redirect packets to CPU enable0 = Do not send to CPU1 = Enable

0

18 IPMC_TTL_ERR_TOCPU R/W IPMC TTL error packets to CPU enable0 = Do not send to CPU1 = Enable

0

17 L3UC_TTL_ERR_TOCPU R/W L3 unicast TTL error packets to CPU enable


0

16 DOS_ATT_TOCPU R/W DoS attack packets to CPU enable. This applies to packets where checks are enabled in DOS_CONTROL.


0

15 TUN_ERR_TOCPU R/W Tunnel error packets to CPU enable0 = Do not send to CPU1 = Enable

0

14 MART_ADDR_TOCPU R/W Martian address packets to CPU enable0 = Do not send to CPU1 = Enable

0

13 V6L3_ERR_TOCPU R/W IPv6 L3 error packets to CPU enable


0

12 SRC_RTE_TOCPU R/W Source route packets to CPU enable (pkt.SA[40] = = 1)0 = Do not send to CPU1 = Enable

0

11 IPMC_PORT_MISS_TOCPU R/W IPMC port mismatch to CPU enable0 = Do not send to CPU1 = Enable

0

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10 V4L3_DST_MISS_TOCPU R/W IPv4 L3 destination miss packets to CPU enable0 = Do not send to CPU1 = Enable

0

9 V6L3_DST_MISS_TOCPU R/W IPv6 L3 destination miss packets to CPU enable


0

8 UNRES_L3SRC_TOCPU R/W Unresolved L3 source packets to CPU enable0 = Do not send to CPU1 = Enable

0

7 UVLAN_TOCPU R/W Unknown VLAN packets to CPU enable0 = Do not send to CPU1 = Enable

0

6 IPMC_ERR_TOCPU R/W IPMC error packets to CPU enable0 = Do not send to CPU1 = Enable

0

5 V4L3_ERR_TOCPU R/W IPv4 L3 error packets to CPU enable0 = Do not send to CPU1 = Enable

0

4 UUCAST_TOCPU R/W Unknown unicast packets to CPU enable


0

3 UMC_TOCPU R/W Unknown multicast packets to CPU enable0 = Do not send to CPU1 = Enable

0

2 UIPMC_TOCPU R/W Unknown IPMC packets to CPU enable0 = Do not send to CPU1 = Enable

0

1 NON_STAT_MOV_TOCPU R/W Non-static station movement packets to CPU enable


0

0 STAT_MOV_TOCPU R/W Static station movement packets to CPU enable0 = Do not send to CPU1 = Enable

0



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ING_IPMC_PTR_CTRL

Register description: IPMC pointer control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ENA UPPER_LIMIT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UPPER_LIMIT LOWER_LIMIT

Table 182: ING_IPMC_PTR_CTRL



20 ENA R/W IPMC Index Increment Mode Enable. Controls the IPMC index increment feature for all IPMC-replicated packet transmit to HiGig port. IPMC index needs to be within the range defined by IPMCIdxHighMarker and IPMCIdxLowMarker. The new IPMC Index send will be the original IPMC Index added with the replicated packet number. For example:first packet—new IPMC index = original IPMC index + 1second packet—new IPMC index = original IPMC index + 2....n-th packet—new IPMC index = original IPMC index + n

0 = IPMC index increment mode disable1 = IPMC index increment mode enable

0

19:10 UPPER_LIMIT R/W IPMC index high marker 0x000

9:0 LOWER_LIMIT R/W IPMC index low marker 0x000

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FP_SLICE_ENABLE

Register description: ContentAware™ slice enable

Register offset: 0x0C78000B

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FP_LOOKUP_ENA__SL15

FP_LOOKUP_ENA__SL14

FP_LOOKUP_ENA_

SL13

FP_LOOKUP_ENA__SL12

FP_LOOKUP_ENA_

SL11

FP_LOOKUP_ENA_

SL10

FP_LOOKUP_ENA_

SL9

FP_LOOKUP_ENA_

SL8

FP_LOOKUP_ENA_

SL7

FP_LOOKUP_ENA_

SL6

FP_LOOKUP_ENA_

SL5

FP_LOOKUP_ENA_

SL4

FP_LOOKUP_ENA_

SL3

FP_LOOKUP_ENA_

SL2

FP_LOOKUP_ENA_

SL1

FP_LOOKUP_ENA_

SL0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FP_SLICE_ENA_SL15

FP_SLICE_ENA_SL14

FP_SLICE_ENA_SL13

FP_SLICE_ENA_SL12

FP_SLICE_ENA_SL11

FP_SLICE_ENA_SL10

FP_SLICE_ENA_SL9

FP_SLICE_ENA_SL8

FP_SLICE_ENA_SL7

FP_SLICE_ENA_SL6

FP_SLICE_ENA_SL5

FP_SLICE_ENA_SL4

FP_SLICE_ENA_SL3

FP_SLICE_ENA_SL2

FP_SLICE_ENA_SL1

FP_SLICE_ENA_SL0

Table 183: FP_SLICE_ENABLE


31 FP_LOOKUP_ENA_SL15 R/W FP lookup enable for slice 150 = Disable slice1 = Enable slice

0

30 FP_LOOKUP_ENA_SL14 R/W FP lookup enable for slice 14

0 = Disable slice1 = Enable slice

0


0


0



0


0


0



0


0


0



0


0

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0



0


0


0

15 FP_SLICE_ENA_SL15 R/W FP slice enable for slice 150 = Disable slice1 = Enable slice

0


0

13 FP_SLICE_ENA_SL13 R/W FP slice enable for slice 13


0


0


0



0


0


0



0


0


0



0


0


0



0



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0



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FP_CAM_CONTROL_UPPER

Register description: FFP CAM control (upper)


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED FP_CAM_CTRL_SLICE15 FP_CAM_CTRL_SLICE14 FP_CAM_CTRL_SLICE13

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FP_CAM_CTRL_SLICE

13

FP_CAM_CTRL_SLICE12 FP_CAM_CTRL_SLICE11 FP_CAM_CTRL_SLICE10 FP_CAM_CTRL_SLICE9 FP_CAM_CTRL_SLICE8

Table 184: FP_CAM_CONTROL_UPPER



23:21 FP_CAM_CTRL_SLICE15 R/W FFP CAM control for slice 15 0x0








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FP_CAM_CONTROL_LOWER

Register description: FFP CAM control (lower)

Register offset: 0x0C78000B

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED FP_CAM_CTRL_SLICE7 FP_CAM_CTRL_SLICE6 FP_CAM_CTRL_SLICE5

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FP_CAM_CTRL_SLICE

5

FP_CAM_CTRL_SLICE4 FP_CAM_CTRL_SLICE3 FP_CAM_CTRL_SLICE2 FP_CAM_CTRL_SLICE1 FP_CAM_CTRL_SLICE0

Table 185: FP_CAM_CONTROL_LOWER











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FP_SLICE_CONFIG

Register description: FP slice configuration register

Register offset: 0x0c780017

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

SLICE_15_

MODE

SLICE_14_MODE SLICE_13_MODE SLICE_12_MODE RESERVED

SLICE_11_

MODE

SLICE_10_MODE SLICE_9_MODE SLICE_8_MODE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

SLICE_7_

MODE

SLICE_6_MODE SLICE_5_MODE SLICE_4_MODE RESERVED

SLICE_3_

MODE

SLICE_2_MODE SLICE_1_MODE SLICE_0_MODE

Table 186: FP_SLICE_CONFIG


31 RESERVED – Reserved –

30 SLICE_15_MODE R/W Configuration for slice 150 = Single wide1 = Double wide (with slice 14)

0

29:28 SLICE_14_MODE R/W Configuration for slice 1400 = Single wide01 = Double wide (with SLICE 15) 10 = Triple wide (with SLICES 12 and 13)11 = N/A

0x0


0x0

25:24 SLICE_12_MODE R/W Configuration for slice 12

00 = Single wide01 = Double wide (with SLICE 13) 10 = Triple wide (with SLICES 13 and 14)11 = N/A

0x0


22 SLICE_11_MODE R/W Configuration for slice 11

0 = Single wide1 = Double wide (with slice 10)

0


0x0



0x0


0x0


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0x0


0x0


0x0



0



0x0


0x0


0x0

Table 186: FP_SLICE_CONFIG


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FP_F4_SELECT

Register description: FP F4 select register


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SLICE_15_F4

SLICE_14_F4

SLICE_13_F4

SLICE_12_F4

SLICE_11_F4

SLICE_10_F4

SLICE_9_F4

SLICE_8_F4

SLICE_7_F4

SLICE_6_F4

SLICE_5_F4

SLICE_4_F4

SLICE_3_F4

SLICE_2_F4

SLICE_1_F4

SLICE_0_F4

Table 187: FP_F4_SELECT


15 SLICE_15_F4 R/W CONTROL for F4 selector for SLICE 15

0 = SRC_PORT_NUMBER1 = PKT_FORMAT

0

14 SLICE_14_F4 R/W CONTROL for F4 selector for SLICE 140 = SRC_PORT_NUMBER1 = PKT_FORMAT

0


0



0


0


0



0


0


0



0


0


0



0

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0


0

Table 187: FP_F4_SELECT


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FP_METER_CONTROL

UNKNOWN_UCAST_BLOCK_MASK

Register description: Additional bytes to add to each packet for metering to account for IFG

Register offset: 0x0C78000C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PACKET_IFG_BYTES

Table 188: FP_METER_CONTROL



4:0 PACKET_IFG_BYTES R/W Bytes to add in addition to the packet byte count for metering 0x00

Register description: Unknown unicast packets block mask

Register offset: 0x0E7pp100 (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BLK_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLK_BITMAP

Table 189: UNKNOWN_UCAST_BLOCK_MASK



28:0 BLK_BITMAP R/W Bitmap of ports for which unknown unicast packets are to be blocked

0 = Do not block1 = Block

0x00000000

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UNKNOWN_MCAST_BLOCK_MASK

BCAST_BLOCK_MASK

Register description: Unknown multicast packets block mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BLK_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLK_BITMAP

Table 190: UNKNOWN_MCAST_BLOCK_MASK



28:0 BLK_BITMAP R/W Bitmap of ports for which unknown multicast packets are to be blocked


0x00000000

Register description: Broadcast packet block mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BLK_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLK_BITMAP

Table 191: BCAST_BLOCK_MASK



28:0 BLK_BITMAP R/W Bitmap of ports for which broadcast packets are to be blocked


0x00000000

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MIRROR_CONTROL

Register description: Mirror control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED SRC_MODID_BLOCK_MIRROR_COPY

SRC_MODID_BLOCK_MIRROR_ONLY_PKT

NON_UC_EM_MTP_INDEX

EM_MTP_INDEX IM_MTP_INDEX M_ENA

Table 192: MIRROR_CONTROL



8 SRC_MODID_BLOCK_MIRROR_COPY

R/W Apply the source MODID block masks, programmed in SRC_MODID_BLOCK table, for MTP of HiGig packets with MH.M = 1, MH, MO = 0, MH.MD = 0 ports

0

7 SRC_MODID_BLOCK_MIRROR_ONLY_PKT

R/W Apply the source MODID block masks, programmed in SRC_MODID_BLOCK table, for MTP of HiGig packets with MH.M = 1, MH,MO = 1, MH.MD = 0 ports

0

6:5 NON_UC_EM_MTP_INDEX

R/W Non-unicast egress mirror-to-port index 0x0

4:3 EM_MTP_INDEX R/W Egress mirror mirror-to-port index 0x0

2:1 IM_MTP_INDEX R/W Ingress mirror mirror-to-port index 0x0

0 M_ENA R/W Mirror enable0 = Disable1 = Enable

0

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EMIRROR_CONTROL

SFLOW_ING_THRESHOLD

Register description: Broadcast packet block mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 193: EMIRROR_CONTROL



28:0 BITMAP R/W Egress mirror bitmap

0 = Do not egress mirror this port1 = Egress mirror this port

0x00000000

Register description: SFLOW ingress threshold


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ENA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THRESHOLD

Table 194: SFLOW_ING_THRESHOLD



16 ENA R/W Enable SFLOW ingress


0

15:0 THRESHOLD R/W SFLOW ingress threshold value 0x0000

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SFLOW_EGR_THRESHOLD

COS_SEL

Register description: SFLOW egress threshold


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ENA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

THRESHOLD

Table 195: SFLOW_EGR_THRESHOLD



16 ENA R/W Enable SFLOW egress


0

15:0 THRESHOLD R/W SFLOW egress threshold value 0x0000

Register description: Priority to CoS mapping

Register offset: 0x0E7pp10A (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED CoS7 CoS6 CoS5

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CoS5 CoS4 CoS3 CoS2 CoS1 CoS0

Table 196: COS_SEL



23:21 CoS7 R/W Priority 7 packets are mapped to this CoS 0x0








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EGR_MTU_SIZE

Register description: Egress maximum transmit unit size


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED L3_MTU_SIZE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

L3_MTU_SIZE MTU_SIZE

Table 197: EGR_MTU_SIZE



27:14 L3_MTU_SIZE R/W Egress ports L3 MTU limit 0x3FFF

13:0 MTU_SIZE R/W Maximum transmit unit size 0x3FFF

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HIGIG_TRUNK_GROUP

Register description: HiGig+ trunk group

Register offset: 0x0E780108

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED HG_TRUNK_ID1_P3

HG_TRUNK_ID1_P2

HG_TRUNK_ID1_P1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HG_TRUNK_ID1_P0

HG_TRUNK_ID0_P3

HG_TRUNK_ID0_P2

HG_TRUNK_ID1_P1

HG_TRUNK_ID1_P0

HG_TRUNK_RTAG1 HG_TRUNK_RTAG0

Table 198: HIGIG_TRUNK_GROUP



21:20 HG_TRUNK1_P3 R/W Member 3 of HiGig+ trunk ID 1 0x0








5:3 HG_TRUNK_RTAG1 R/W RTAG selection for trunk ID 1 (see below for bit definition) 0x0

2:0 HG_TRUNK_RTAG0 R/W RTAG selection for trunk ID 0. HiGig+ trunk ID #1 RTAG (for encoding values see TRUNK_GROUP.RTAG field)0x0 = ZERO—Hash entry always zero0x1 = SA—BCM5695 hashing is based on SA, otherwise, based on SA, VLAN, Ethertype, and source module ID/port0x2 = DA—BCM5695 hashing is based on DA, otherwise, based on DA, VLAN, Ethertype, and source module ID/port0x3 = SA_DA—BCM5695 hashing, based on SA/DA, otherwise, based on SA/DA, VLAN, Ethertype, and source module ID/port0x4 = SIP—BCM5695 hashing is based on SIP, otherwise, based on SIP and source TCP/UDP port0x5 = DIP—BCM5695 hashing is based on DIP, otherwise, based on DIP and destination TCP/UDP port0x6 = SIP_DIP—BCM5695 hashing is based on SIP/DIP, otherwise, based on SIP/DIP and source/destination TCP/UDP port0x7 = Source port based trunk selection. Selection is specified in USER_TRUNK_HASH_SELECT and IUSER_TRUNK_HASH_SELECT.

0x0

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HIGIG_TRUNK_CONTROL

Register description: HiGig+ trunk control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ACTIVE_PORT_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HIGIG_TRUNK_BITMAP1 HIGIG_TRUNK_BITMAP0 HIGIG_TRUNK

3

HIGIG_TRUNK

_ID3

HIGIG_TRUNK

2

HIGIG_TRUNK

_ID2

HIGIG_TRUNK

1

HIGIG_TRUNK

_ID1

HIGIG_TRUNK

0

HIGIG_TRUNK

_ID0

Table 199: HIGIG_TRUNK_CONTROL



19:16 ACTIVE_PORT_BITMAP R/W HiGig ports on which active traffic needs to go out 0xF

15:12 HIGIG_TRUNK_BITMAP1 R/W HiGig trunk bitmap for trunk group 1 0x0

11:8 HIGIG_TRUNK_BITMAP0 R/W HiGig trunk bitmap for trunk group 0 0x0

7 HIGIG_TRUNK3 R/W HiGig T-bit for port 27 0

6 HIGIG_TRUNK_ID3 R/W HiGig trunk ID for port 27 0







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EPC_LINK_BMAP

This register contains a bitmap for all the ports in the spanning tree’s forwarding state. This register is used by the ARL logicto determine whether the port is in the forwarding state. After all forwarding decisions have been made, the ingress portperforms a bitwise AND operation of the intended port bitmap with the EPC_LINK_BMAP.PORT_BITMAP field. Packets areonly sent to ports with the appropriate bit in the bitmap set.

BKP_DISC_BMAP

Register description: Link status port bitmap

Register offset: 0x0E78010B

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED PORT_BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 200: EPC_LINK_BMAP



28:0 PORT_BITMAP R/W Link Enable. Bitmap of the forwarding status individual ports, with one bit for each of the ports.0 = Port is not in a forwarding state and transfer to the port is not possible.1 = Port is in a forwarding state and transfer to the port is possible.

0x0000000

Register description: Backpressure discard status

Register offset: 0x0E78010C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 201: BKP_DISC_BMAP



28:0 PORT_BITMAP R/W Backpressure. Bitmap showing the individual ports that are discarding incoming packets, due to backpressure.0 = Port is not discarding packets due to the backpressure limit.1 = Port is discarding packets due to the backpressure limit.This field should not be written during normal operation. It is automatically updated by the BCM56500 device.

0x0000000

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HOL_STAT_BMAP

Register description: HOL status

Register offset: 0x0E78010D CoS00x0E78010E CoS10x0E78010F CoS20x0E780110 CoS30x0E780111 CoS40x0E780112 CoS50x0E780113 CoS60x0E780114 CoS7

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 202: HOL_STAT_BMAP



28:0 PORT_BITMAP R/W Bitmap showing the HOL blocking status of a port, with one bit for each of the ports.

0 = Port is not in HOL blocking state and transfer to the port is possible1 = Port is in HOL blocking state and transfer to the port is not possible

This field should not be written during normal operation. It is automatically updated by the BCM56500 device.

0x0000000

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CPU_CONTROL_2

Register description: Controls priority for packets destined to the CPU


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED CPU_MIRROR_PRI CPU_ICMP_REDIRECT_PRI

CPU_FPCOPY_PRI

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CPU_FP_

COPY_PRI

CPU_MTU_FAIL_PRI CPU_DEFAULT_PRI CPU_SFLOW_PRI CPU_LKUPFAIL_PRI CPU_PROTOCOL_PRI




23:21 CPU_MIRROR_PRI R/W The priority used when a packet is sent to the CPU due to mirroring. 0x0

20:18 CPU_ICMP_REDIRECT_PRI

R/W The priority used when a packet is sent to the CPU because of an ICMP redirect. 0x0

17:15 CPU_FPCOPY_PRI R/W The priority used when a packet is sent to the CPU due to the FFP action = copy_to_cpu.

0x0

14:12 CPU_MTUFAIL_PRI R/W The priority used when a packet is sent to the CPU because the MTU check failed. 0x0

11:9 CPU_DEFAULT_PRI R/W This priority is used when the packet is being sent to the CPU for reasons other than those listed in this register.

0x0

8:6 CPU_SFLOW_PRI R/W The priority when a SFLOW packet is sent to the CPU. 0x0

5:3 CPU_LKUPFAIL_PRI R/W The priority used when a packet is sent to the CPU because it is an unknown SA or unknown DA.

0x0

2:0 CPU_PROTOCOL_PRI R/W The priority used for control packets, including BPDUs. This priority applies to the destination address ranges:

01:80:C2:00:00:00 to 01:80:C2:00:00:0F, and 01:80:C2:00:00:20 to 01:80:C2:00:00:2F.

0x0

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SFLOW_ING_RAND_SEED

SFLOW_EGR_RAND_SEED

Register description: SFLOW ingress random seed generator


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED SEED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEED

Table 204: SFLOW_ING_RAND_SEED



24:0 SEED R/W Seed for random-number generator (ingress SFLOW) 0x0000001

Register description: SFLOW egress random seed generator


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED SEED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEED

Table 205: SFLOW_EGR_RAND_SEED



24:0 SEED R/W Seed for random-number generator (egress SFLOW) 0x0000002

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HOLD_COS_PORT_SELECT

HOLD_COS[0:7]

Register description: Egress HOL Drop CoS Counter Port Select


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PORT_NUM

Table 206: HOLD_COS_PORT_SELECT



4:0 PORT_NUM R/W Port number 0x00

Register description: Egress HOL drop COS[0:7] counters

Register offset: COS0 - 0x0E780015COS1 - 0x0E780016COS2 - 0x0E780017COS3 - 0x0E780018COS4 - 0x0E780019COS5 - 0x0E78001ACOS6 - 0x0E78001BCOS7 - 0x0E78001C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



25:0 COUNT R/W Incremented for each packet drop due to Head Of Line blocking per egress port COS

0X0000000

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CPU_PRIORITY_SEL

Register description: Priority to CoS mapping for the CPU. This setting is applied to all ports in the device. Packets ingresswith a preset priority. This priority can then be remapped to another priority prior of hitting theCPU_COS_SEL register. The CPU_PRIORITY_SEL register is to be used to remap ingress packetsthat are DLF, Multicast and Broadcast types. Unicast packets do not use this register. Unicastpackets will directly use the CPU_COS_SEL register.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED PRI7 PRI6 PRI5

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRI5 PRI4 PRI3 PRI2 PRI1 PRI0

Table 207: CPU_PRIORITY_SEL



23:21 PRI7 R/W Priority 7 packets are mapped to this CoS. 0x0








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CPU_COS_SEL

Register description: Priority to CoS mapping for the CPU. This setting is applied to all ports in the device. A Unicastpacket with a preset priority is remapped using this register. DLF, Multicast, and Broadcast packetsget priority from CPU_PRIORITY_SEL register. The CPU_PRIORITY_SEL register is thenremapped into CPU_COS_SEL register. The final value of the CPU_COS_SEL register is then sentto the MMU to determine packet flow.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 208: CPU_COS_SEL



23:21 CoS7 R/W Priority 7 packets are mapped to this CoS. 0x0








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RDBGC[0:8]_SELECT

Register description: Trigger select register for receive debug counters

Register offset: RDBGC0_SELECT – 0x0E780020RDBGC1_SELECT – 0x0E780021RDBGC2_SELECT – 0x0E780022RDBGC3_SELECT – 0x0E780023RDBGC4_SELECT – 0x0E780024RDBGC5_SELECT – 0x0E780025RDBGC6_SELECT – 0x0E780026RDBGC7_SELECT – 0x0E780027RDBGC8_SELECT – 0x0E780028

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED RHGMC RHUGC VLANDR

RTUNE RTUN MTUERR

DSFRAG

DSICMP DSL4HE DSL3HE IRIBP IRHOL IRPSE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDROP RIMDR RFILDR IMBP PDISC RPORTD

RUC RDISC IMRP6 RIPHE8 RIPC6 RIPD6 IMRP4 RIPHE4 RIPC4 RIPD4

Table 209: RDBGC[0:8]_SELECT



28 RHGMC R/W Received HiGig lookup MC Packets 0

27 RHUGC R/W Received HiGig lookup UC Packets 0

26 VLANDR R/W Increment counter for receive VLAN drops 0

25 RTUNE R/W Increment counter for receive tunnel error packets 0

24 RTUN R/W Increment counter for receive tunnel packets 0

23 MTUERR R/W Increment counter for packets trapped to CPU due to egress L3 MTU violation 0

22 DSFRAG R/W Increment counter for DOS fragment error packets 0

21 DSICMP R/W Increment counter for DOS ICMP error packets 0

20 DSL4HE R/W Increment counter for DOS L4 header error packets 0

19 DSL3HE R/W Increment counter for DOS L3 header error packets 0

18 IRIBP R/W Increment counter for HiGig End-to-End IBP receive packet counter 0

17 IRHOL R/W Increment counter for HiGig End-to-End HOL receive packet counter 0

16 IRPSE R/W Increment counter for HiGig IPIC pause receive counter 0

15 RDROP R/W Increment counter for packets dropped due to port bitmap of zero condition 0

14 RIMDR R/W Increment counter for multicast (L2 + L3) packets that are dropped 0

13 RFILDR R/W Increment counter for packets dropped by the Content Aware Engine 0

12 IMBP R/W Increment counter for bridged multicast packets 0

11 PDISC R/W Increment counter for receive policy discard (i.e. DST_DISCARD, SRC_DISCARD, RATE_CONTROL, etc.)

0

10 RPORTD R/W Increment counter for packets dropped when ingress port is not in forwarding state 0

9 RUC R/W Increment counter for Good received unicast (L2 + L3) 0

8 RDISC R/W Increment counter for packets discarded due to IBP discard or CBP full 0

7 IMRP6 R/W Increment counter for Routed IPv6 multicast packets 0

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6 RIPHE6 R/W Increment counter for packets with IPv6 header error (IPv6 martian error addresses + link local)

0

5 RIPC6 R/W Increment counter for Good received L3 IPv6 packets (includes tunneled) 0

4 RIPD6 R/W Increment counter for IPv6 L3 discards 0

3 IMRP4 R/W Increment counter for routed IPv4 multicast packets 0

2 RIPHE4 R/W Increment counter for packets with IPv4 header error. (Martian error address + unicast with class D + multicast & ~ClassD)

0

1 RIPC4 R/W Increment counter for good received L3 IPv4 packets (includes tunneled) 0

0 RIPD4 R/W Increment counter for IPv4 L3 discards 0

Table 209: RDBGC[0:8]_SELECT (Cont.)


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IPMC_MTU_CONFIG

IPMC_L3_MTU_[0:7]

Register description: Used to program mode bit to be backward compatible for MTU checks.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED HELIX_FBB0_MTU_MODE

Table 210: IPMC_MTU_CONFIG



0 HELIX_FBB0_MTU_MODE

R/W 0 – BCM56500 B0 mode1 – BCM56300/BCM56100 mode

0

Register description: L3 MTU table (8 × 14)

Register offset: IPMC_L3_MTU_0 - 0x0E780123IPMC_L3_MTU_1 - 0x0E780124IPMC_L3_MTU_2 - 0x0E780125IPMC_L3_MTU_3 - 0x0E780126IPMC_L3_MTU_4 - 0x0E780127IPMC_L3_MTU_5 - 0x0E780128IPMC_L3_MTU_6 - 0x0E780129IPMC_L3_MTU_7 - 0x0E78012A

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED MTU_LEN

Table 211: IPMC_L3_MTU_[0:7]



13:0 MTU_LEN R/W L3 MTU length 0x3FFF

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IPMC_L2_MTU_[0:7]

ING_MISC_CONFIG

Register description: L2 MTU table (8 × 14)

Register offset: IPMC_L2_MTU_0 - 0x0E78012BIPMC_L2_MTU_1 - 0x0E78012CIPMC_L2_MTU_2 - 0x0E78012DIPMC_L2_MTU_3 - 0x0E78012EIPMC_L2_MTU_4 - 0x0E78012FIPMC_L2_MTU_5 - 0x0E780130IPMC_L2_MTU_6 - 0x0E780131IPMC_L2_MTU_7 - 0x0E780132

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED MTU_LEN

Table 212: IPMC_L2_MTU_[0:7]



13:0 MTU_LEN R/W L2 MTU length 0x3FFF

Register description: Additional configuration bits that influence trunk behavior for HG trunks and various block masks.


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED USE_DEST_PORT

APPLY_SRCMOD_BLOCK_ON_UC_

ONLY

APPLY_EGR_

MASK_ON_UC_

ONLY

Table 213: ING_MISC_CONFIG



2 USE_DEST_PORT R/W Use the last two bits of destination port for Higig trunk. Used when RTAG = 7. 0

1 APPLY_SRCMOD_BLOCK_ON_UC_ONLY

S 1 = Apply src_mod block only on Unicast 0

0 APPLY_EGR_MASK_ON_UC_ONLY

R/W 1 = Apply egress mask only on Unicast 0

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USER_TRUNK_HASH_SELECT

Register description: User-configured trunk hash value selection. This register is used when an RTAG value of 7 isspecified in TRUNK_GROUP and HIGIG_TRUNK_GROUP


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED TRUNK_CFG_VAL

Table 214: USER_TRUNK_HASH_SELECT



2:0 TRUNK_CFG_VAL R/W This value specifies the nth member of the trunk group this port will transmit to. –

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Section 8: Ingress (Hi) Pipeline Registers

IE2E_CONTROL

Register description: End-to-end control

Register offset: 0x018pp005 (p = port)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED IBP_EN

HOL_EN

IBP_TOCPU

HOL_TOCPU

Table 215: IE2E_CONTROL



3 IBP_EN R/W End-to-end IBP messages are detected in the Ingress Pipeline.0 = Disable1 = Enable detection of IBP messages

0

2 HOL_EN R/W End-to-end HOL messages are detected in Ingress Pipeline.0 = Disable1 = Enable detection of HOL message

0

1 IBP_TOCPU R/W IBP messages sent to the CPU

0 = Do not send to CPU1 = Send IBP E2E messages to the CPU

0

0 HOL_TOCPU R/W HOL messages sent to the CPU0 = Do not send to the CPU1 = Send HOL E2E messages to the CPU

0

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HG_LOOKUP

Register description: HiGig Lookup register to hold virtual port parameters.

Register offset: 0x028pp019 (p=port)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED HG_LOOKU

P_ENABL

E

HYBRID_MODE_ENABL

E

DST_HG_LOOKUP_BITMAP USE_MH_PKT_PRI

USE_MH_VID

USE_MH_INTERNAL_

PRI

REMOVE_MH_SRC_PORT

LOOKUP_WITH

_MH_SRC_PORT

Table 216: HG_LOOKUP



10 HG_LOOKUP_ENABLE R/W HG lookup enable per port 0

9 HYBRID_MODE_ENABLE

R/W Allow HG switching and HG lookup—used for proxy support 0

8:5 DST_HG_LOOKUP_BITMAP

R/W Bitmap indicating if the dst_port of MH is eligible for HG lookup 0x0

4 USE_MH_PKT_PRI R/W Indicates to use module header pkt_pri or from the tables 0

3 USE_MH_VID R/W Indicates to use module header vid or from the tables 0

2 USE_MH_INTERNAL_PRI

R/W Indicates to use module header int_pri or from the tables 0

1 REMOVE_MH_SRC_PORT

R/W This is to remove MH_SRC_PORT from L2 Bitmap 0

0 LOOKUP_WITH_MH_SRC_PORT

R/W Pick up port parameters using MH_SRC_PORT 0

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E2E_HOL_RX_DA_MS

E2E_HOL_RX_DA_LS

Register description: End-to-end HOL MSB DA


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA

Table 217: E2E_HOL_RX_DA_MS



15:0 DA R/W XPORT RX packet expected DA [47:32] for E2E HOL messages 0x0000

Register description: E2E HOL LSB DA


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA

Table 218: E2E_HOL_RX_DA_LS


31:0 DA R/W XPORT RX packet expected DA [31:0] for E2E HOL messages 0x00000000

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E2E_HOL_RX_LENGTH_TYPE

E2E_HOL_RX_OPCODE

Register description: End-to-end HOL length/type


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENGTH_TYPE

Table 219: E2E_HOL_RX_LENGTH_TYPE



15:0 LENGTH_TYPE R/W Receive pause frame expected length/type field for E2E HOL messages 0x0000

Register description: End-to-end HOL Opcode register


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCPODE



15:0 OPCODE R/W XPORT RX packet expected OPCODE field for E2E HOL messages 0x0000

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E2E_IBP_RX_DA_MS

E2E_IBP_RX_DA_LS

Register description: End-to-end IBP MSB DA


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA

Table 220: E2E_IBP_RX_DA_MS



15:0 DA R/W XPORT RX packet expected DA [47:32] for E2E IBP messages 0x0000

Register description: E2E IBP LSB DA


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA

Table 221: E2E_IBP_RX_DA_LS


31:0 DA R/W XPORT RX packet expected DA [31:0] for E2E IBP messages 0x00000000

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E2E_IBP_RX_LENGTH_TYPE

E2E_IBP_RX_OPCODE

Register description: End-to-end IBP length/type


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENGTH_TYPE

Table 222: E2E_IBP_RX_LENGTH_TYPE



15:0 LENGTH_TYPE R/W Receive pause frame expected length/type field for E2E IBP messages 0x0000

Register description: End-to-end IBP opcode


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCPODE

Table 223: E2E_IBP_RX_OPCODE



15:0 OPCODE R/W XPORT RX packet expected Opcode field for E2E IBP messages 0x0000

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ICONTROL_OPCODE_BITMAP

IUNKNOWN_UCAST_BLOCK_MASK

Register description: HiGig+ control packet switching bitmap


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BITMAP

Table 224: ICONTROL_OPCODE_BITMAP



4:0 BITMAP R/W HiGig+ control opcode redirection 0x00

Register description: Unknown unicast block mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 225: IUNKNOWN_UCAST_BLOCK_MASK



28:0 BITMAP R/W Bitmap of ports that should not receive unknown unicast packets

0 = Allow1 = Block

0x00000000

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IUNKNOWN_MCAST_BLOCK_MASK

IBCAST_BLOCK_MASK

Register description: Unknown Multicast Block Mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 226: IUNKNOWN_MCAST_BLOCK_MASK



28:0 BITMAP R/W Bitmap of ports that should not receive unknown multicast packets

0 = Allow1 = Block

0x00000000

Register description: Broadcast Block Mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 227: IBCAST_BLOCK_MASK



28:0 BITMAP R/W Bitmap of ports which should not receive broadcast packets

0 = Allow1 = Block

0x00000000

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IMIRROR_CONTROL

IEMIRROR_CONTROL

Register description: Mirror control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED SRC_MODID_BLOCK_MIRROR_COPY

SRC_MODID_BLOCK_MIRROR_ONLY_PKT

NON_UC_EM_MTP_INDEX

EM_MTP_INDEX IM_MTP_INDEX M_EN

Table 228: IMIRROR_CONTROL



8 SRC_MODID_BLOCK_MIRROR_COPY

R/W Apply the source MODID block masks, programmed in SRC_MODID_BLOCK table, for MTP of HiGig packets with MH.M=1, MH,MO=0, MH.MD=0 ports.

0

7 SRC_MODID_BLOCK_MIRROR_ONLY_PKT

R/W Apply the source MODID block masks, programmed in SRC_MODID_BLOCK table, for MTP of HiGig packets with MH.M=1, MH,MO=1, MH.MD=0 ports.

0

6:5 NON_UC_EM_MTP_INDEX

R/W Non-unicast egress mirror-to-port (MTP) index 0x0

4:3 EM_MTP_INDEX R/W Egress mirror MTP index 0x0

2:1 IM_MTP_INDEX R/W Ingress mirror MTP index 0x0

0 M_ENABLE R/W Mirror enable0 = Disable1 = Enable mirroring

0

Register description: Egress mirror bitmap


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BITMAP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BITMAP

Table 229: IEMIRROR_CONTROL



28:0 BITMAP R/W Egress mirroring port bitmap 0x00000000

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ICOS_SEL

This register maps the IEEE 802.1p priority value to one of the eight CoS queues. The CoS value assigned to an incomingpacket may be derived from the priority field in the tag header, filtering results, and so on.

IMIRROR_BITMAP

Register description: CoS Queue Mapping

Register offset: 0x0E8pp10A (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 230: ICOS_SEL



23:21 CoS7 R/W Priority 7 is mapped to this CoS. 0x0








Register description: Alternate bitmap/path to MTP for mirroring


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BITMAP

Table 231: IMIRROR_BITMAP



3:0 BITMAP R/W HiGig port bitmap for egress mirror packets 0x0

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Section 9: Egress Pipeline Registers

EGR_HW_RESET_CONTROL_0

This register is for controlling the HW Table Initialization feature of the Egress Pipeline. This register should be programmedbefore programming the EGR_HW_RESET_CONTROL_1 register.

Register description: Hardware reset control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED START_ADDRESS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

START_ADDRESS STAGE_NUMBER

Table 232: EGR_HW_RESET_CONTROL_0



25:6 START_ADDRESS R/W Start address. 20-bit starting address for the memory. Hardware starts incrementing from this address until EGR_HW_RESET_CONTROL_1.COUNT is completed. START_ADDRESS is relevant even when EGR_HW_RESET_CONTROL_1.RESET_ALL bit is set.

0x000000

5:0 STAGE_NUMBER R/W Stage Number where table to be reset is located. This is not used when EGR_HW_RESET_CONTROL_1.RESET_ALL bit is set.

0x00

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EGR_HW_RESET_CONTROL_1

Register description: Control for the HW table initialization feature of the Egress Pipeline


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED DONE VALID RST_ALL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

COUNT

Table 233: EGR_HW_RESET_CONTROL_1



18 DONE R/W After the hardware has issued memory reset commands equal to COUNT times, it sets the DONE bit. Software can poll this bit from time-to-time and whenever it is set, and software should reset the DONE and VALID bits to 0. This ends the hardware Reset Sequence of memories in the hardware.

0

17 VALID R/W Valid0 = Normal operation1 = Start HW table initialization

0

16 RST_ALL R/W Reset all

0 = Normal operation1 = ALL tables in the Egress Pipeline are reset for COUNT entries.

STAGE_NUMBER is ignored when this bit is set.

0

15:0 COUNT R/W Count of entries that need to be reset starting from EGR_HW_RESET_CONTROL_0.START_ADDRESS.

0x2000

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EGR_PORT

Register description: Configuration register for a port. This is different for each GbE and 10 GbE port.

Register offset: 0x019pp002 (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD MY_MODID EM_SRCMOD_CHANGE

RESERVED PRE_CPU_TAG

EN_EFILTE

R

PORT_TYPE

Table 234: EGR_PORT



14:9 MY_MODID R/W Module ID of this chip 0x00

8 EM_SRCMOD_CHANGE

R/W Change SRC_MODID for the egress mirrored packets going out of the HiGig port0 = Disable1 = Enable

0


3 PRE_CPU_TAG R/W Preserve the tag for packets destined to the CPU0 = Do not preserve tags1 = Preserve tags

0

2 EN_EFILTER R/W Enable egress VLAN membership check0 = Disable1 = Enable

0

1:0 PORT_TYPE R/W Specifies the type of the port.

Bit[0] of PORT_TYPE field is the HIGIG_BIT. If it is set, then the port is in HiGig+ mode.

0 = GbE/10 GE/CPU port1 = HiGig+ port

Bit[1] of PORT_TYPE field is NNI_BIT. If it is set, then the port is NNI port, else it is an UNI port.

0 = UNI port1 = NNI port

0x0

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EGR_VLAN_CONTROL_1

Register description: Egress VLAN control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED VT_MISS_UT_DROP

OUTER_TPID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OUTER_TPID VT_MISS_DROP

VT_EN

Table 235: EGR_VLAN_CONTROL_1



18 VT_MISS_UT_DROP R/W If this bit is set, a lookup in the vxlt cam table results in a miss, and the packet is untagged due to the EGR_VLAN untagged bitmap settings, the packet is dropped. This bit is only meaningful when VT_ENABLE is set.

0

17:2 OUTER_TPID R/W TPID to identify the outer tag. This TPID is also used when packet modification stages add a VLAN tag to the packet.

0x8100

1 VT_MISS_DROP R/W VLAN translation miss0 = Do not drop1 = A VLAN translation lookup in the VXLT CAM table results in a miss, then the packet is dropped. Valid only when VT_EN = 1.

0

0 VT_EN R/W VLAN Translate enable0 = Disable1 = Enable. The VID and priority are obtained from the VXLT CAM.

0

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EGR_CONFIG

Register description: Egress configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INNER_TPID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LEARN_VID USE_LEARN_

VID

RSVD DRACO_15_MIR

DT_MODE

Table 236: EGR_CONFIG


31:16 INNER_TPID R/W Inner TPID 0x8100

15:4 LEARN_VID R/W Learn VID—VLAN ID used for learning and lookup when USE_LEARN_VID = 1. 0x000

3 USE_LEARN_VID R/W Use LEARN_VID

0 = Normal operation1 = All packets (both tagged and untagged) received on the port use the LEARN_VID field from this register for address learning and lookup.

0


1 DRACO_15_MIR R/W BCM5695 mirroring mode0 = Enable XGS 3 style mirroring1 = Enable BCM5695 style mirroring

0

0 DT_MODE R/W Double tagging enable0 = Disable1 = Enable double tagging

0

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EGR_CONFIG_1

Register description: Egress configuration 1


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED STACK_MODE MH_PFM FORCE_STATIC_MH_PFM

IPMC_ROUTE_SAME_VLAN

RING_MODE

Table 237: EGR_CONFIG_1



6:5 STACK_MODE R/W Enable to connect 5670/75s in ring topology

0x0 = STACK_FBÒ—Stacking with XGS 30x1 = STACK_5670—Stacking with BCM56700x2 = STACK_5675—Stacking with BCM56750x3 = Reserved

0x0

4:3 MH_PFM R/W PFM to be used to construct the module header 0x0

2 FORCE_STATIC_MH_PFM

R/W Forces MH_PFM in the module header for packets going to HiGig port


0

1 IPMC_ROUTE_SAME_VLAN

R/W IPMC route packets on the same VLAN enable.0 = Do not allow1 = Allow IPMC replicated packet, which has the same VLAN as the incoming packet’s VLAN

0

0 RING_MODE R/W Ring mode enable0 = No ring connection1 = XGS 3 devices are connected in a ring

0

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EGR_IPMC_CFG2

Register description: Configuration Register for IPMC related modifications


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV VID UNTAG DIS_SA_

REPL

DIS_TTL_DECR

Table 238: EGR_IPMC_CFG2



14:3 VID R/W VLAN ID—For an IPMC L3 routed packet, if the UNTAG bit is set and the packet VID matches this field, then the VLAN tag is removed from the packet. For L3 packets, the packet VID is obtained from the L3 interface table.

0x0000

2 UNTAG R/W Send the IPMC routed packet untagged0 = Tag1 = Untag

0

1 DIS_SA_REPL R/W Disable SA replacement for IPMC routed packets0 = Enable1 = Disable the SA replacement

0

0 DIS_TTL_DECR R/W Disable TTL decrement for IPMC routed packets

0 = Enable1 = Disable TTL decrement

0

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EGR_PORT_L3UC_MODS

Register description: Configuration register for L3 unicast-related modifications


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED L3_UC_

VLAN_DIS

L3_UC_TTL_DIS

L3_UC_DA_DIS

L3_UC_SA_DIS

Table 239: EGR_PORT_L3UC_MODS



3 L3_UC_VLAN_DIS R/W Disable the outer VID replacement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable outer VID replacement for L3UC packets

0

2 L3_UC_TTL_DIS R/W Disable the TTL decrement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable the TTL decrement for L3UC packets

0

1 L3_UC_DA_DIS R/W Disable the DA replacement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable the DA replacement for L3UC packets

0

0 L3_UC_SA_DIS R/W Disable the SA replacement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable the SA replacement for L3UC packets

0

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EGR_TUNNEL_CONTROL

Global ID value for tunnel packets. This value is passed in the packet whenever tunnel is encapsulated in a packet in thetransmit pipeline.

EGR_TUNNEL_ID_MASK

Register description: Egress tunnel control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

START_IPV4_ID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IPV4_ID

Table 240: EGR_TUNNEL_CONTROL


31:16 START_IPV4_ID RO Start IPv4 ID. This represents the initial value written into the IPV4_ID field. It is updated by the hardware after the IPV4_ID field is written and remains constant, even though the IPV4_ID changes with each encapped packet.

0x000000

15:0 IPV4_ID R/W This value is incremented with each encapped packet. The IPV4_ID is initially set by the CPU/software.

0x0000

Register description: Egress tunnel ID mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IPV4_ID_MASK

Table 241: EGR_TUNNEL_ID_MASK



15:0 IPV4_ID_MASK R/W Global ID mask to be used before inserting the tag into the packet. 0x0000

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EGR_TUNNEL_PIMDR1_CFG0

For PIMSM-DR1 type tunnel packets, MS 4 bytes are specified here.


Register description: Egress tunnel PIM-DR1 configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MS_PIMSM_HDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MS_PIMSM_HDR

Table 242: EGR_TUNNEL_PIMDR1_CFG0


31:0 MS_PIMSM_HDR RO Specifies the MS 32 bits of the PIMSM-DR1 Header that needs to be inserted in the packet if a tunnel table search results in a packet encap.

0x000000



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LS_PIMSM_HDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LS_PIMSM_HDR



31:0 LS_PIMSM_HDR RO Specifies the LS 32 bits of the PIMSM-DR1 Header that needs to be inserted in the packet if a tunnel table search results in a packet encap.

0x000000

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For PIMSM-DR1 type tunnel packets, MS 4 bytes are specified here.




Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MS_PIMSM_HDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MS_PIMSM_HDR



31:0 MS_PIMSM_HDR RO Specifies the MS 32 bits of the PIMSM-DR2 Header that needs to be inserted in the packet if a tunnel table search results in a packet encap.

0x000000



Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LS_PIMSM_HDR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LS_PIMSM_HDR



31:0 LS_PIMSM_HDR RO Specifies the LS 32 bits of the PIMSM-DR2 Header that needs to be inserted in the packet if a tunnel table search results in a packet encap.

0x000000

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EGR_RSPAN_VLAN_TAG

Register description: Egress RSPAN VLAN tag

Register offset: 0x099pp000

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TAG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TAG

Table 246: EGR_RSPAN_VLAN_TAG


31:0 TAG R/W This field contains the entire 4-byte tag to be added to the packet for RSPAN.TAG[31:16] = TPIDTAG[15:13] = PriorityTAG[12] = CFITAG[11:0] = VID.

If TAG = 0, then no RSPAN tag is added.

0x000000

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EGR_ENABLE

EGR_SHAPING_CONTROL

Register description: Egress enable

Register offset: 0x0A9pp100 (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PRT_EN

Table 247: EGR_ENABLE



0 PRT_EN R/W Port enable0 = Disable1 = Enable

0

Register description: Specifies control fields egress for the shaping counter


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PACKET_IFG_BYTES

Table 248: EGR_SHAPING_CONTROL



4:0 PACKET_IFG_BYTES R/W Number of preamble and IFG bytes to be added in the shaping counters. 0x00

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TDBGC[0:11]_SELECT

Register description: Trigger select register for transmit debug counters

Register offset: TDBGC0_SELECT – 0x0A980020TDBGC1_SELECT – 0x0A980021TDBGC2_SELECT – 0x0A980022TDBGC3_SELECT – 0x0A980023TDBGC4_SELECT – 0x0A980024TDBGC5_SELECT – 0x0A980025TDBGC6_SELECT – 0x0A980026TDBGC7_SELECT – 0x0A980027TDBGC8_SELECT – 0x0A980028TDBGC9_SELECT – 0x0A980029TDBGC10_SELECT – 0x0A98002ATDBGC11_SELECT – 0x0A98002B

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED THGMC THGUC TSIPL TMIRR TPKTD TL2MCD TAGED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TSTGD TVXLTMD

TVLAND

TVLAN TCFID TTTLD TTNLE TTNL TIPMCD6

TGIPMC6

TIPD6 TGIP6 TIPMCD4

TGIPMC4

TIPD4 TGIP4

Table 249: TDBGC[0:11]_SELECT



22 THGMC R/W Transmitted HiGig looked-up L3MC packets. 0

21 THGUC R/W Transmitted HiGig looked-up L3UC packets. 0

20 TSIPL R/W SIP link local drop flag 0

19 TMIRR R/W Mirroring flag 0

18 TPKTD R/W Increment for packet dropped due to any condition. 0

17 TL2MCD R/W Increment counter for L2 MC packet drops. 0

16 TAGED R/W Increment counter for packets dropped due to packet aging. 0

15 TSTGD R/W Increment counter for packet drops due to spanning tree state not in forwarding state.

0

14 TVXLTMD R/W Increment counter for packet drops due to miss in VXLT table. 0

13 TVLAND R/W Increment counter for packets dropped due to invalid VLAN. 0

12 TVLAN R/W Increment counter for VLAN tagged packets transmitted. 0

11 TCFID R/W Increment counter for packets dropped when CFI bit is set and packet is untagged or L3_switched for IPMC counter.

0

10 TTTLD R/W Increment counter for packets dropped due to TTL threshold counter. 0

9 TTNLE R/W Increment counter for transmit tunnel error (inner v6 is not 6to4 or ISATAP for automatic tunnel encapsulation).

0

8 TTNL R/W Increment counter for transmitted tunnel packets. 0

7 TIPMCD6 R/W Increment counter for IPv6 IPMC aged and dropped packets. 0

6 TGIPMC6 R/W Increment counter for good transmitted IPv6 IPMC packets. 0

5 TIPD6 R/W Increment counter for IPv6 L3 UC aged and dropped packets. 0

4 TGIP6 R/W Increment counter for good transmitted IPv6 L3 UC packets. 0

3 TIPMCD4 R/W Increment counter for IPv4 IPMC aged and dropped packets. 0

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2 TGIPMC4 R/W Increment counter for good transmitted IPv4 IPMC packets. 0

1 TIPD4 R/W Increment counter for IPv4 L3 UC aged and dropped packets. 0

0 TGIP4 R/W Increment counter for transmitted IPv4 L3 UC packets. 0

Table 249: TDBGC[0:11]_SELECT


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Section 10: Egress (Hi) Pipeline Registers

IEGR_PORT

Register description: Configuration register for a port. This is different for each GbE or 10 GbE port.

Register offset: 0x01App002 (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD MY_MODID EM_SRCMOD_CHANGE

RESERVED PRE_CPU_TAG

EN_EFILTE

R

PORT_TYPE

Table 250: IEGR_PORT



14:9 MY_MODID R/W Module ID of this chip 0x00

8 EM_SRCMOD_CHANGE

R/W Change SRC_MODID for the egress mirrored packets going out of the HiGig port0 = Disable1 = Enable

0


3 PRE_CPU_TAG R/W Preserve the tag for packets destined to the CPU0 = Do not preserve tags1 = Preserve tags

0

2 EN_EFILTER R/W Enable egress VLAN membership check0 = Disable1 = Enable

0

1:0 PORT_TYPE R/W Specifies the type of the port.

Bit[0] of PORT_TYPE field is the HIGIG_BIT. If it is set, then the port is in HiGig+ mode.

0 = GbE/10 GbE/CPU port1 = HiGig+ port

Bit[1] of PORT_TYPE field is NNI_BIT. If it is set, then the port is NNI port, else it is an UNI port.

0 = UNI port1 = NNI port

0x0

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IEGR_PORT_L3UC_MODS

Register description: Configuration register for IPMC-related modifications

Register offset: 0x06App002 (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED L3_UC_VLAN_D

IS

L3_UC_TTL_DI

S

L3_UC_DA_DIS

L3_UC_SA_DIS

Table 251: IEGR_PORT_L3UC_MODS



3 L3_UC_VLAN_DIS R/W Disable the outer VID replacement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable outer VID replacement for L3UC packets

0

2 L3_UC_TTL_DIS R/W Disable the TTL decrement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable the TTL decrement for L3UC packets

0

1 L3_UC_DA_DIS R/W Disable the DA replacement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable the DA replacement for L3UC packets

0

0 L3_UC_SA_DIS R/W Disable the SA replacement for L3UC packets coming from a particular port. This register is indexed in EP based on the src_port_num.0 = Enable1 = Disable the SA replacement for L3UC packets

0

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Section 11: BroadSAFE Registers

BSAFE_GLB_TIMER

System Time Register. The value in this timer is used by the µHSM to determine when the time-based keys expire. The timetick is stored in this register and is set to 0 at reset. The time tick increments in 1-second increments, continuously from reset.The value of this register can only be initialized once after each hardware reset. Subsequent write operations to this registerthrough the register-access interface do not have any effect.

Register description: BroadSAFE global timer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TIME_TICK

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIME_TICK

Table 252: BSAFE_GLB_TIMER


31:0 TIME_TICK R/W The relative time tick register. This register is disabled at reset. It remains at zero, until it is being programmed to a nonzero value.The value of this register can only be initialized once after each hardware reset. Subsequent write operations to this register through the register-access interface does not have any effect.

This field is write-once protected. It can only be written one time by an SBus write access. Further write attempts are ignored by µHSM (Read Only)

0x00000000

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BSAFE_GLB_PRESCALE

The reference clock (refclk) input is prescaled to provide a nominal 1-second clock tick used to increment theBSAFE_GLB_TIMER register. The reference clock is divided by four in the reference-clock domain, then synchronized tothe core-clock domain. The core-clock input must be equal to or greater than the reference-clock input for all frequencies.The divide by 4 ensures that the reference clock is properly sampled. Therefore, the time tick is calculated as follows: period= (refclk period * PRESCALE * 4). When the reference clock is 6.25 MHz, the prescalar should have the value 0x17D784.When the reference clock is 62.5 MHz, the prescalar should have the value 0xEE6B28. This register is write-once protected.It can only be written one time by an SBus write access. Further write attempts are ignored by µHSM

Register description: BroadSAFE global prescaler


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED PRESCALE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRESCALE

Table 253: BSAFE_GLB_PRESCALE



23:0 PRESCALE R/W Prescalar value for the system time tick. The default value assumes a 6.25-MHz reference system clock input.The value of this register can only be initialized once after each hardware reset. Subsequent write operations to this register through the register access interface do not have any effect (Read Only).

0x17D784

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BSAFE_GLB_UHSM_CFG

The µHSM configuration register allows the µHSM to be configured securely by the HSM. The most common use for thisfunction is the in-field upgrade capability for export controls. Upon each power-on reset or hardware reset of the µHSM, theembedded microcontroller reads the default initial value of this register from the NVM and sets the register content. Theregister content can be subsequently updated via the uHSM_LD_CFG command. The functionality of the µHSM isdetermined by the current value of the register.

Register description: BroadSAFE global µHSM configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UHSM_CFG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UHSM_CFG

Table 254: BSAFE_GLB_UHSM_CFG


31:0 UHSM_CFG R/W The secure µHSM configuration values. The predefined flags are specified in the uHSM_INIT_DEVICEKEY command. The initial values of these bits are set via the "uHSM_INIT_DEVICEKEY (uhsm_config, prod_config, authorization)" command in the Configuration Input field. The values of these bits can be changed in-field by a manufacturer's authorized signature (Read Only).

0x00000000

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BSAFE_GLB_PROD_CFG

The device configuration register allows the system to be configured securely by the HSM. For example, a higherperformance capability can be shipped, disabled, and then upgraded via a secure communication message in the field toincrease performance. These bits are used to disable the feature or performance capability in the system (or on-chip). Uponeach power-on reset or hardware reset of the µHSM, the embedded microcontroller reads the default initial value of thisregister from the NVM, and sets the register content. The register content can be subsequently updated via theuHSM_LD_CFG command. The functionality of the µHSM is determined by the current value of the register. The content ofthis register is brought out to the µHSM interface so that the external system hardware can be configured.

Register description: BroadSAFE global product configuration

Register offset: 0x00B8020C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PROD_CFG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PROD_CFG

Table 255: BSAFE_GLB_PROD_CFG


31:0 PROD_CFG R/W Secure product configuration values. The usage is system-dependent for each bit. The initial values of these bits are set via the “uHSM_INIT_DEVICEKEY (uhsm_config, prod_config, authorization)” command in the Configuration Input field. The values of these bits can be changed in-field by a manufacturer's authorized signature (Read Only).

0x00000000

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BSAFE_GLB_DEV_STATUS

Register description: BroadSAFE global device status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PROD_CFG_VLD

RESV KS_ACT

INIT_DONE

INIT_KEY INIT_DONE

Table 256: BSAFE_GLB_DEV_STATUS



7 PROD_CFG_VLD RO This flag is set when the prod_config register is initialized with the value stored in NVM. Setting this flag informs the external world that the content of the prod_config register is good to be sampled.

0


5 KS_ACTIVE RO Key session active0 = Not active1 = Key session setup has been completed and the session is active.

0

4 INIT_DONE RO Key initialization

0 = Initialization not complete1 = Indicates that initialization has been completed.

0

3:2 INIT_KEY RO Indicates status directly from the security bits of the OTP array that the device key is initialized.

0x0

1:0 BUSY RO These bits lock out access to the command registers. It indicates that the μHSM block is busy processing a command. On reset, these bits indicate busy until the master controller is ready to accept commands (INIT_DONE = 1).

0x0

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BSAFE_GLB_CMD_CTRL

This register is used to control the command interface for the µHSM. The values in this register are used to control theGLB_CMD_DATA_IN and the GLB_CMD_DATA_OUT data input registers.

Register description: BroadSAFE global command and control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REV_ID RESERVED GPEN

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV GPO RESV GPI SOFT_RST

RESERVED CMD_OSYNC

CMD_ORDY

CMD_ISYNC

CMD_IRDY

Table 257: BSAFE_GLB_CMD_CTRL


31:24 REV_ID R/W Revision ID

The µHSM revision identification. This revision identifier can potentially be the same for multiple chips as it identifies the version of the µHSM only. The µHSM master controller sets these bits from a value stored in ROM.

0x00


18:16 GPEN RO General purpose enableControls the enable signal on the bidirectional GPIO[2:0] pins.

0x0


14:12 GPO RO General purpose outputThe GPIO[2:0] output values, set by the master controller.

0x0


10:8 GPI RO General purpose input—The input value of the GPIO[2:0] pins. 0x0

7 SOFT_RST R/W Initiates a soft reset of the µHSM block. The state of the entire block is cleared to the power-on reset values. The soft reset can be initiated by the local host via the external interface or the master controller.

0


3 CMD_OSYNC Command output syncThis bit is set high to indicate the start of a command packet response from the µHSM. It is lowered on the last word of the command packet to indicate the end of the response.

0

2 CMD_ORDY RO Command output readyIndicates that the GLB_CMD_DATA_OUT register contains valid data.

0

1 CMD_ISYNC Command input syncThis bit is set high to indicate the start of a command packet to the µHSM. It is lowered to 0 on the last word of the command packet.

0

0 CMD_IRDY RO Command input readyIndicates that the GLB_CMD_DATA_IN register is ready to accept data from the local interface.

0

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BSAFE_GLB_CMD_DATA_IN

BSAFE_GLB_CMD_DATA_OUT

Register description: BroadSAFE global command data input


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CMD_DIN

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CMD_DIN

Table 258: BSAFE_GLB_CMD_DATA_IN


31:0 CMD_DIN R/W Command data input. Input data for command processing to the µHSM. 0xDEADBEEF

Register description: BroadSAFE global command data output

Register offset: 0x00B8021C

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CMD_DOUT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CMD_DOUT

Table 259: BSAFE_GLB_CMD_DATA_OUT


31:0 CMD_DOUT R/W Command data output. Output data for command processing from the µHSM. 0x00000000

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BSAFE_GLB_INT_CTRL

Register description: BroadSAFE global interrupt control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED INTR_SRC_EN RESERVED SRC_SAL

RESV SRC_RDY

SRC_CERR

SRC_CDONE

Table 260: BSAFE_GLB_INT_CTRL



12:8 INTR_SRC_EN R/W Interrupt source enableThe interrupt mask register. Each bit corresponds to an individual interrupt source defined in SRC_xxxx[3:0].

0x00


4 SRC_SAL RO Security assurance logic

Indicates that the SAL has triggered an interrupt. The SAL status register should be read for more information.

0


2 SRC_RDY RO Source readyIndicates that the µHSM is ready to accept a command.

0

1 SRC_CERR RO Command errorIndicates that the µHSM has completed a command that returns a nonzero return code.

0

0 SRC_CDONE RO Command doneIndicates that the µHSM has completed a command.

0

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Section 12: Memory Management Unit (MMU) Registers

IBPPKTSETLIMIT

Register description: Ingress backpressure packet limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESETLIMITSEL PKTSETLIMIT

Table 261: IBPPKTSETLIMIT



15:14 RESETLIMITSEL R/W IBP packet reset threshold select option. When the backpressure status is set, the packet counts must fall below this threshold in order to clear the backpressure status. 2’b00 = 75.0% of IBP Packet Set Limit2’b01 = 50.0% of IBP Packet Set Limit2’b10 = 25.0% of IBP Packet Set Limit2’b11 = 12.5% of IBP Packet Set Limit

0x1

13:0 PKTSETLIMIT R/W Ingress backpressure packet threshold. This is the number of packets an ingress port may occupy before entering the IBP state.

0x278

Note: Do not modify this register with traffic on.

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IBPPKTCOUNT

IBPCELLSETLIMIT

Register description: Ingress backpressure packet count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PKTCOUNT

Table 262: IBPPKTCOUNT



13:0 PKTCOUNT RO Ingress packet count. Number of packets stored per ingress port. 0x0000

Register description: Ingress backpressure cell limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESETLIMITSEL CELLSETLIMIT

Table 263: IBPCELLSETLIMIT



15:14 RESETLIMITSEL R/W IBP cell reset threshold select option. When the backpressure status is set, the cell count must fall below this threshold in order to clear the backpressure status.2’b00 = 75.0% of IBP Cell Set Limit2’b01 = 50.0% of IBP Cell Set Limit2’b10 = 25.0% of IBP Cell Set Limit2’b11 = 12.5% of IBP Cell Set Limit

0x1

13:0 CELLSETLIMIT R/W Ingress backpressure cell threshold. This is the number of cells an ingress port may occupy before entering the IBP state.

0x231


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IBPDISCARDSETLIMIT

IBPCELLCOUNT

Register description: Ingress backpressure cell discard limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED DISCARDSETLIMIT

Table 264: IBPDISCARDSETLIMIT



13:0 DISCARDSETLIMIT R/W Backpressure discard threshold for each ingress port’s cell count. When an ingress port’s cell count is above DISCARDSETLIMIT, all incoming packets from this port are discarded. The DISCARDSETLIMIT should be greater than the IBPCELLSETLIMIT to prevent unexpected behavior.

0x331


Register description: Ingress backpressure packet count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CELLCOUNT

Table 265: IBPCELLCOUNT



13:0 CELLCOUNT RO Ingress cell count. Number of cells stored per ingress port. 0x0000

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E2EIBPPKTSETLIMIT

E2EIBPPKTCOUNT

Register description: End-to-end ingress backpressure packet limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 266: E2EIBPPKTSETLIMIT



15:14 RESETLIMITSEL R/W IBP packet reset threshold select option. When the backpressure status is set, the packet count must fall below this threshold in order to clear the backpressure status. 2’b00 = 75.0% of E2E IBP Packet Set Limit2’b01 = 50.0% of E2E IBP Packet Set Limit2’b10 = 25.0% of E2E IBP Packet Set Limit2’b11 = 12.5% of E2E IBP Packet Set Limit

0x1

13:0 PKTSETLIMIT R/W Backpressure packet high threshold for all remote ports in remote modules. In units of packets per port.

0x0015


Register description: End-to-end ingress backpressure packet count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PKTCOUNT

Table 267: E2EIBPPKTCOUNT



13:0 PKTCOUNT RO Ingress packet count for all remote ports in remote modules. Number of packets stored per ingress port.

0x0000

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E2EIBPCELLSETLIMIT

E2EIBPDISCARDSETLIMIT

Register description: End-to-end ingress backpressure cell limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 268: E2EIBPCELLSETLIMIT



15:14 RESETLIMITSEL R/W IBP cell reset threshold select option. When the backpressure status is set, the cell count must fall below this threshold in order to clear the backpressure status.2’b00 = 75.0% of E2E IBP Cell Set Limit2’b01 = 50.0% of E2E IBP Cell Set Limit2’b10 = 25.0% of E2E IBP Cell Set Limit2’b11 = 12.5% of E2E IBP Cell Set Limit

0x1

13:0 CELLSETLIMIT R/W Backpressure cell high threshold for all remote ports in remote modules. In units of cells per port.

0x00DD


Register description: End-to-end ingress backpressure cell discard limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED DISCARDSETLIMIT

Table 269: E2EIBPDISCARDSETLIMIT



13:0 DISCARDSETLIMIT R/W E2E IBP flow control discard threshold for all local ingress ports cell counts. When an ingress port’s cell count is above the Discard Set Limit, all incoming packets from this port are discarded. The Discard Limit must be set above the IBPCELLSETLIMIT to prevent unexpected behavior. This limit represents an absolute value and is not related to E2EIBPCELLSETLIMIT. Unit is the number of cells per port.

0x331


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E2EIBPCELLCOUNT

Register description: End-to-end ingress backpressure cell count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CELLCOUNT

Table 270: E2EIBPCELLCOUNT



13:0 CELLCOUNT RO Ingress cell count for all remote ports in remote modules. Number of cells stored per ingress port.

0x0000

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BKPMETERINGCONFIG

Register description: Backpressure metering configuration

Register offset: 0x006pp00A (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED BKP_DISC_

EN

REFRESH_COUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REFRESH_COUNT DISCARD_THD RESUME_THD PAUSE_THD

Table 271: BKPMETERINGCONFIG



26 BKP_DISC_EN R/W Backpressure metering discard message enable0 = Disable1 = Enable Backpressure Warning Message to discard packet from this ingress port when the Backpressure Metering bucket count is above the Discard Threshold.

0

25:8 REFRESH_COUNT R/W Refresh count for Backpressure Metering bucket. Each unit represents a refresh rate of 64 Kbps (minimum granularity). To use the backpressure metering feature, MISCCONFIG.METERING_CLK_EN = 1.

0

7:6 DISCARD_THD R/W Resume threshold for discarding packet on Backpressure Metering bucket of an ingress port.

When the bucket count hits the Resume Threshold, it sends out a Backpressure Warning Status Clear Message. This threshold selects the number over the PAUSE_THD. 2’b00 = 75% of PAUSE_THD above PAUSE_THD2’b01 = 50% of PAUSE_THD above PAUSE_THD2’b10 = 25% of PAUSE_THD above PAUSE_THD2’b11 = 12.5% of PAUSE_THD above PAUSE_THD

0x0

5:4 RESUME_THD R/W Resume threshold for resume reception on pause metering of an ingress port.When the Bucket Count hits the Resume Threshold, it sends out a Backpressure Warning Status Clearing Message. This threshold must not be over the size of Bucket Count.

2’b00 = 75% of PAUSE_THD2’b01 = 50% of PAUSE_THD2’b10 = 25% of PAUSE_THD2’b11 = 12.5% of PAUSE_THD

0x0

3:0 PAUSE_THD R/W Pause threshold for start pause on pause metering of an ingress port.When Bucket Count falls below Pause Threshold, it sends out a Backpressure Warning Status Message. This threshold must not exceed the size of Bucket Count.4\’b0000: Disable4\’b0001: 32 Kbits4\’b0010: 64 Kbits4\’b0011: 128 Kbits4\’b0100: 256 Kbits4\’b0101: 512 Kbits4\’b0110: 1 Mbits4\’b0111: 2 Mbits4\’b1000: 4 Mbits4\’b1001: 8 Mbits4\’b1010: 16 Mbits4\’b1011: 32 Mbits4\’b1100: 64 Mbits4\’b1101: 128 Mbits4\’b1110: Not available4\’b1111: Not available

0x0

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BKPMETERINGBUCKET

Register description: Backpressure metering bucket count

Register offset: 0x006pp00B (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED IN_PROF_FLAG

BUCKET_COUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUCKET_COUNT

Table 272: BKPMETERINGBUCKET



29 IN_PROFILE_FLAG RO In-profile flag, indicates the current state of the Backpressure Metering bucket0 = In profile1 = Out of profile (polarity backwards based upon bit name)

0

28:0 BUCKET_COUNT RO Pause metering bucket count 0x00000000

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HOLCOSPKTSETLIMIT

Register description: HOL CoS packet limit (per port)

Register offset: 0x006pp010 (p = port number: CoS0)0x006pp011 (p = port number: CoS1)0x006pp012 (p = port number: CoS2)0x006pp013 (p = port number: CoS3)0x006pp014 (p = port number: CoS4)0x006pp015 (p = port number: CoS5)0x006pp016 (p = port number: CoS6)0x006pp017 (p = port number: CoS7)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 273: HOLCOSPKTSETLIMIT



15:14 RESETLIMITSEL R/W HOL packet reset threshold select option. When the HOL status is set, the packet counts must fall below this threshold in order to clear back the HOL status.2’b00 = 75.0% of HOL Packet Set Limit2’b01 = 50.0% of HOL Packet Set Limit2’b10 = 25.0% of HOL Packet Set Limit2’b11 = 12.5% of HOL Packet Set Limit

0x1

13:0 PKTSETLIMIT R/W HOL packet high threshold per CoS, per port. The CoS n HOL status are generated when a packet count exceeds this limit.

Do not set this limit lower than MISCCONFIG.SKIDMARKER or it is treated as zero size for this CoS n.

Note: The sum of the values from all CoS queues for a given egress port cannot exceed 2k XQ pointers.

Note: The sum of CMIC’s PKTSETLIMIT for all CoS queues cannot exceed 1.5k XQ pointers.

0x100


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CNGCOSPKTLIMIT0

Register description: CNG CoS packet limit

Register offset: 0x006pp018 (p = port number: CoS0)0x006pp019 (p = port number: CoS1)0x006pp01A (p = port number: CoS2)0x006pp01B (p = port number: CoS3)0x006pp01C (p = port number: CoS4)0x006pp01D (p = port number: CoS5)0x006pp01E (p = port number: CoS6)0x006pp01F (p = port number: CoS7)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CNGPKTSETLIMIT0

Table 274: CNGCOSPKTLIMIT0



10:0 CNGPKTSETLIMIT R/W CNG0 Set Limit for CoS n for an egress port. When the packet count is above this limit, incoming packets carried congestion color red (CNG[1:0] == 2’b01) are dropped.This limit must be set lower than HOLCOSPKTSETLIMIT of the same port to ensure dropping CNG0 packets occur before HOL. The number of packets allowed for CNG0 packet per egress port of CoS n.

0x80


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CNGCOSPKTLIMIT1

Register description: CNG CoS packet limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CNGPKTSETLIMIT1

Table 275: CNGCOSPKTLIMIT1



10:0 CNGPKTSETLIMIT R/W CNG1 Set Limit for CoS n for an egress port. When the packet count is above this limit, the incoming packet carried congestion color yellow (CNG[1:0] == 2’b11) is dropped. This limit must be set lower than HOLCOSPKTSETLIMIT of the same port to ensure dropping CNG1 packets occurs before HOL. The number of packets allowed for CNG1 packets per egress port of CoS n.

0x80


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COSPKTCOUNT

Register description: CoS packet count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PKTCOUNT

Table 276: COSPKTCOUNT



10:0 PKTCOUNT RO Packet Count for egress port for CoS nThis is the current number of packets in the XQ of CoS n for this egress port. Number of packets per egress port for CoS n.

0x000

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LWMCOSCELLSETLIMIT

Register description: Low water marker CoS cell limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Table 277: LWMCOSCELLSETLIMIT



15:14 RESETLIMITSEL R/W In Dynamic Memory mode, the HOL CELL Status Reset Threshold is defined by the DYNCELLSETLIMIT.RESETLIMITSEL field as a percentage of low water marker (LWM). The LCCOUNT for a given CoS must fall below the LWM before the HOL CELL blocking is cleared.

In non-Dynamic Memory mode, this is the HOL Cell Reset Threshold for an egress port. In the HOL state, the LCCOUNT must fall below the Reset Threshold to reset the HOL condition. 2’b00 = 75.0% of HOL Cell Set Limit2’b01 = 50.0% of HOL Cell Set Limit2’b10 = 25.0% of HOL Cell Set Limit2’b11 = 12.5% of HOL Cell Set Limit

0x1

13:0 CELLSETLIMIT R/W In Dynamic Memory mode, this register represents the guaranteed number of cells scheduled for CoS n on this egress port. When the COSLCCOUNT crosses this limit, it goes into the dynamic cell area where it is shared by other CoS and other ports. The Dynamic Memory Mode register must be set for this limit to be in effect. In non-Dynamic Memory mode, this is the HOL Cell high water threshold for egress port packet of CoS n (that is, the number of cells per egress port of CoS n). Do not set this register to 0 in non-Dynamic Memory mode.

0x0100


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COSLCCOUNT

Register description: CoS cell count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED LCOUNT

Table 278: COSLCCOUNT



13:0 LCCOUNT RO Cell Count for egress port per CoS. Number of accumulated cells per egress port of each CoS.

0x0000

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DYNCELLLIMIT

Register description: Dynamic cell limit


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED DYN_CELL_RST_LIMIT_

SEL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DYNCELLRSTLIMIT_SEL

DYNCELLLIMIT

Table 279: DYNCELLLIMIT



16:14 DYNCELLRESET_LIMITSEL

R/W In Dynamic Memory mode, when in HOL condition, the COSLCCOUNT must be below this threshold to reset the HOL condition.3’b1xx = 100% of LOWWATERMARKER3’b000 = 75% of LOWWATERMARKER3’b001 = 50% of LOWWATERMARKER3’b010 = 25% of LOWWATERMARKER3’b011 = 12.5% of LOWWATERMARKERStatic Memory mode: This field is not used.

0x4

13:0 DYNCELLLIMIT R/W In Dynamic Memory mode, the total dynamic cells above the LOWWATERKER limit that can be used by a port for all CoS queues. Effectively, it is the HOL cell limit for a port.Static Memory Mode: This field is not used.

0x400


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DYNCELLCOUNT

Register description: Dynamic memory mode cell count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED DYNAMICCELLCOUNT

Table 280: DYNCELLCOUNT



13:0 DYNAMICCELL_COUNT

RO Dynamic Cell Count for each egress port across all CoS queues. Total number of cells used above the LWM limits. Valid only in Dynamic Memory mode.

0x0000

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XQEMPTY

Register description: Transaction queue empty


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CoS7 CoS6 CoS5 CoS4 CoS3 CoS2 CoS1 CoS0

Table 281: XQEMPTY



7 CoS7 RO CoS 7 status

0 = Not empty1 = CoS 7 has no entries for this port.

0

6 CoS6 RO CoS 6 status0 = Not empty1 = CoS 6 has no entries for this port.

0


0



0


0


0



0


0

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EGRESSCELLREQUESTCOUNT

Counter needs to reset when resetting the egress port.

XQCOSARBSEL

Register description: Egress cell request count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED REQUESTCOUNT

Table 282: EGRESSCELLREQUESTCOUNT



3:0 REQUESTCOUNT RO Egress Cell request counter 0x0

Register description: Scheduler control


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED COSARB

Table 283: XQCOSARBSEL



1:0 COSARB R/W Scheduler Control Options

2’b00 = Strict priority among valid CoS (default value)2’b01 = Round Robin Queueing among valid CoS2’b10 = Weighted Round Robin Queueing (WRR) scheduling according to WRR weight2’b11 = Deficit Round Robin Queueing (DRR) scheduling according to WRR weight

0x0

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WRRWEIGHTS

Register description: Weighted round robin weights


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

COS7WEIGHT COS6WEIGHT COS5WEIGHT COS4WEIGHT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

COS3WEIGHT COS2WEIGHT COS1WEIGHT COS0WEIGHT

Table 284: WRRWEIGHTS


31:28 COS7WEIGHT R/W See COS0WEIGHT description 0x8







3:0 COS0WEIGHT R/W When Weighted Round Robin is selected, this register is the CoS 0 weight, which defines the number of packets that can be transmitted in a single round. If the value is 0, this CoS is serviced as strict priority scheduling.When Deficit Round Robin Queueing is selected, this register is CoS 0, which defines the number of bytes that can be transmitted in a single round run. If the value is 0, this CoS is serviced as strict priority scheduling.

COS0Weight = 0x0: Strict priorityCOS0Weight = 0x1: 10 KBCOS0Weight = 0x2: 20 KBCOS0Weight = 0x3: 40 KBCOS0Weight = 0x4: 80 KBCOS0Weight = 0x5: 160 KBCOS0Weight = 0x6: 320 KBCOS0Weight = 0x7: 640 KBCOS0Weight = 0x8: 1280 KBCOS0Weight = 0x9: 2560 KBCOS0Weight = 0xa: 5120 KBCOS0Weight = 0xb: 10 MBCOS0Weight = 0xc: 20 MBCOS0Weight = 0xd: 40 MBCOS0Weight = 0xe: 80 MBCOS0Weight = 0xf: 160 MB

0x1

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EGRDROPPKTCOUNT

CNGDROPCOUNT0

Register description: Egress dropped packet count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DROPPEDPKTCOUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DROPPEDPKTCOUNT

Table 285: EGRDROPPKTCOUNT


31:0 DROPPEDPKTCOUNT RO This is a per egress port-based counter and it counts the number of whole packets dropped by the MMU that will not be passed to the egress port. The MMU counts packets only if the port bitmap of the received packet is nonzero and not purged.

The reasons for MMU to drop packets:• CBP memory full.• IBP Cell count over IBPDISCARDSETLIMIT

• HOL Cell count over HOLCOSxCELLSETLIMIT• HOL Packet count over HOLCOSxPKTSETLIMIT• HOL Packet count over CNGCOSxPKTSETLIMIT0 and Packet with CNG[1:0] = 2’b01

• HOL Packet count over CNGCOSxPKTSETLIMIT1 and Packet with CNG[1:0] = 2’b11• Single cell packet (64~128 bytes) purged by Ingress Pipeline.For packets that are dropped when some number of cells of the packet have already been admitted to the MMU, this packet is not be counted by this counter.

0x00000000

Register description: CNG drop count

Register offset: 0x00p0p048 (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DROPPKTCOUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DROPPKTCOUNT

Table 286: CNGDROPCOUNT0


31:0 DROPPKTCOUNT RO Dropped Packet Count increments for congestion color red dropped packets for each egress port when the HOLPktCount exceeds the CNG0 Packet Set Limit. This is a per-port-based counter collecting all packets for this port on different CoS. Number of packets per egress port.

0x00000000

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CNGDROPCOUNT1

Register description: CNG drop count


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DROPPKTCOUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DROPPKTCOUNT

Table 287: CNGDROPCOUNT1


31:0 DROPPKTCOUNT RO Dropped Packet Count increments for congestion color red dropped packets for each egress port when the HOLPktCount exceeds the CNG1 Packet Set Limit. This is a per-port-based counter collecting all packets for this port on different CoS. Number of packets per egress port.

0x00000000

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IPMCREPLICATIONCOUNT

Register description: IPMC packet replication count

Register offset: 0x006pp04A (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REPL_SRCH_

FAIL

REPL_COUNT

_EN

REPL_OVER_LIMIT

REPL_COS REPL_LIMIT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REPL_LIMIT REPL_COUNT

Table 288: IPMCREPLICATIONCOUNT


31 REPL_SRCH_FAIL RO IPMC replication search failure0 = Search did not fail.1 = IPMC replication group or VLAN search failureThis bit is cleared on a read.

0

30 REPL_COUNT_EN R/W Per-port enable to start counting IPMC replication for specific CoS


0

29 REPL_OVER_LIMIT RO Replication over limit status register for replication over limit0 = Replication within limit1 = Replication over limit—A memfail message is issued.This bit is cleared on a read.

0

28:26 REPL_COS R/W Selected CoS 0x0

25:13 REPL_LIMIT R/W Replication Limit is used on each replication counter. Increments for each IPMC packet replicated for the specified CoS (REPL_COS). An S-bus memfail interrupt is issued (REPLICATION_COUNT_EN==1) when the replication counted > REPL_LIMIT. If this limit is set to 0 or over 4096, the internal limit is 4k.

0x0000

12:0 REPL_COUNT RO Replication Counter for a specified CoS of each egress port. The number of packets doing IPMC replication. The counter counts any replicated packet for the specified CoS on that egress port.The counter keeps the total number of whole replication if it is over its replication limit. If the limit is not reached for any IPMC replication, the counter is reset at the end of replication.

For the case of replication count over 8191, the counter does not overflow, but stays as 8191.

0x0000

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ASFPORTSPEED

Register description: Alternative store and forward port speed

Register offset: 0x006pp04C (p = port number)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PORTSPEED

Table 289: ASFPORTSPEED



2:0 PORTSPEED R/W Port speed for Alternative Stored and Forward mode

3’b000 = Port is not participating in ASF mode on both ingressing/egressing.3’b001 = 10 Mbps half-duplex3’b010 = 10 Mbps full-duplex3’b011 = 100 Mbps half-duplex3’b100 = 100 Mbps full-duplex3’b101 = 1 Gbps full-duplex3’b110 = 10 Gbps full-duplex3’b111 = 12 Gbps full-duplex

0x0

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MINBUCKETCONFIG

Register description: Minimum bucket configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED MIN_REFRESH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MIN_REFRESH MIN_HI_THD_SEL MIN_LO_THD_SEL

Table 290: MINBUCKETCONFIG



25:8 MIN_REFRESH R/W Refresh count for minimum rate bucket. Each unit is represented by 0.5 bit of a refresh rate of 64 kbps. To use min bucket feature, MISCCONFIG.METERING_CLK_EN = 1.

0x00000

7:4 MIN_HI_THD_SEL R/W High Threshold for minimum rate bucket4’b0000: Disable4’b0001: 32 Kbits4’b0010: 64 Kbits4’b0011: 128 Kbits4’b0100: 256 Kbits4’b0101: 512 Kbits4’b0110: 1 Mbits4’b0111: 2 Mbits4’b1000: 4 Mbits4’b1001: 8 Mbits4’b1010: 16 Mbits4’b1011: 32 Mbits4’b1100: 64 Mbits4’b1101: 128 Mbits4’b1110: Not available4’b1111: Not available

0x0

3:0 MIN_LO_THD_SEL R/W Low Threshold for minimum rate bucket.4’b0000 = Disable4’b0001 = 32 Kbits4’b0010 = 64 Kbits4’b0011 = 128 Kbits4’b0100 = 256 Kbits4’b0101 = 512 Kbits4’b0110 = 1 Mbits4’b0111 = 2 Mbits4’b1000 = 4 Mbits4’b1001 = 8 Mbits4’b1010 = 16 Mbits4’b1011 = 32 Mbits4’b1100 = 64 Mbits4’b1101 = 128 Mbits4’b1110 = Not available4’b1111 = Not available

0x0

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MINBUCKET

Register description: Minimum bucket


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


MIN_BUCKET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MIN_BUCKET

Table 291: MINBUCKET



29 IN_PROF_FLAG RO In profile flag. Indicates the current state of the minimum rate bucket.0 = Out of profile (minimum bw not satisfied)1 = In profile (minimum bw satisfied)

1

28:0 MIN_BUCKET R/W Minimum rate bucket, in units of 0.5 bit 0x00000000

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MAXBUCKETCONFIG

Register description: Maximum bucket configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED MAX_REFRESH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAX_REFRESH MAX_THD_SEL

Table 292: MAXBUCKETCONFIG



21:4 MAX_REFRESH R/W Maximum refresh. Refresh count for maximum rate bucket. Each unit is represented by 0.5 bit of a refresh rate of 64 Kbps. To use the maximum bucket feature, MISCCONFIG.METERING_CLK_EN = 1.

00000

3:0 MAX_THD_SEL R/W Maximum threshold select. Threshold for maximum rate bucket.4’b0000: Disable4’b0001: 32 Kbits4’b0010: 64 Kbits4’b0011: 128 Kbits4’b0100: 256 Kbits4’b0101: 512 Kbits4’b0110: 1 Mbits4’b0111: 2 Mbits4’b1000: 4 Mbits4’b1001: 8 Mbits4’b1010: 16 Mbits4’b1011: 32 Mbits4’b1100: 64 Mbits4’b1101: 128 Mbits4’b1110: Not available4’b1111: Not available

0x0

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MAXBUCKET

Register description: Maximum bucket

Register offset: 0x006pp068 (p = port number: CoS0)0x006pp069 (p = port number: CoS1)0x00p0p06A (p = port number: CoS2)0x006pp06B (p = port number: CoS3)0x006pp06C (p = port number: CoS4)0x006pp06D (p = port number: CoS5)0x006pp06E (p = port number: CoS6)0x006pp06F (p = port number: CoS7)

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


MAX_BUCKET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAX_BUCKET

Table 293: MAXBUCKET



29 IN_PROF_FLAG RO In profile flag. Indicates the current state of the maximum rate bucket.0 = Out of profile (maximum bw not exceeded)1 = In profile (maximum bw exceeded)

0

28:0 MAX_BUCKET R/W Maximum rate bucket, in units of 0.5 bit 0x00000000

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EGRMETERINGCONFIG

Register description: Egress metering configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED REFRESH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REFRESH THD_SEL

Table 294: EGRMETERINGCONFIG



21:4 REFRESH R/W Refresh count for metering rate bucket. Each unit is represented by 0.5 bit of a refresh rate of 64 Kbps. To use the maximum bucket feature, MISCCONFIG.METERING_CLK_EN = 1.

00000

3:0 THD_SEL R/W Threshold select. Threshold for metering rate bucket.4’b0000: Disable4’b0001: 32 Kbits4’b0010: 64 Kbits4’b0011: 128 Kbits4’b0100: 256 Kbits4’b0101: 512 Kbits4’b0110: 1 Mbits4’b0111: 2 Mbits4’b1000: 4 Mbits4’b1001: 8 Mbits4’b1010: 16 Mbits4’b1011: 32 Mbits4’b1100: 64 Mbits4’b1101: 128 Mbits4’b1110: Not available4’b1111: Not available

0x0

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EGRMETERINGBUCKET

XQPARITYERRORPTR

Register description: Egress metering bucket threshold


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


BUCKET

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUCKET

Table 295: EGRMETERINGBUCKET



29 IN_PROF_FLAG RO In profile flag. Indicates the current state of the metering rate bucket.0 = In profile1 = Out of profile

0

28:0 BUCKET R/W Maximum rate bucket, in units of 0.5 bit 0x00000000

Register description: Transaction queue parity error pointer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED XQPARITYERRORPKTPTR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XQPARITYERRORPKTPTR XQPARITYERRORPTR

Table 296: XQPARITYERRORPTR



24:11 XQPARITYERRORPKTPTR

RO Transaction queue parity error packet pointer. Keeps the abandoned XQ parity-error memory read data's packet pointer.

0x0000

10:0 XQPARITYERRORPTR

RO Transaction queue parity error pointer. Keeps the abandoned XQ parity-error memory address

0x000

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IBPBKPSTATUS

E2EIBPBKPSTATUS

Register description: Ingress backpressure status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 297: IBPBKPSTATUS



28:0 PORT_BITMAP RO Current Backpressure warning status 0x00000000

Register description: End-to-end backpressure status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 298: E2EIBPBKPSTATUS



28:0 PORT_BITMAP RO Current E2E port backpressure warning status, which is the summary of E2EIBPFC status from the remote module.

0x00000000

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BKPMETERINGSTATUS

IBPDISCSTATUS

Register description: Backpressure metering status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 299: BKPMETERINGSTATUS



28:0 PORT_BITMAP RO Current Backpressure Metering status 0x00000000

Register description: Ingress backpressure discard status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 300: IBPDISCSTATUS



28:0 PORT_BITMAP RO Current IBP discard status 0x00000000

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E2EIBPDISCSTATUS

BKPMETERINGDISCSTATUS

Register description: End-to-end ingress backpressure discard status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 301: E2EIBPDISCSTATUS



28:0 PORT_BITMAP RO Current E2E IBP discard status 0x00000000

Register description: Backpressure metering discard status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 302: BKPMETERINGDISCSTATUS



28:0 PORT_BITMAP RO Current Backpressure Metering discard status 0x00000000

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RXE2EIBPBKPSTATUS

HOLCOSSTATUS

Register description: Remote end-to-end ingress backpressure discard status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 303: RXE2EIBPBKPSTATUS



28:0 PORT_BITMAP RO E2E IBP status received from remote module through E2E IBP packet 0x00000000

Register description: HOL CoS status

Register offset: 0x00680008: CoS00x00680009: CoS10x0068000A: CoS20x0068000B: CoS30x0068000C: CoS40x0068000D: CoS50x0068000E: CoS60x0068000F: CoS7

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PORT_BITMAP

Table 304: HOLCOSSTATUS



28:0 PORT_BITMAP RO Current CoS n HOL Cell status 0x00000000

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CFAPCONFIG

CFAPREADPOINTER

Register description: CFAP configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV CFAP_INIT

CFAP_POOLSIZE

Table 305: CFAPCONFIG



14 CFAP_INIT R/W Reinitialize CFAP Memory0 = Normal operation1 = Reinitialize CFAP pointer prefetch process after user had rearranged CFAP memory

0

13:0 CFAP_POOLSIZE R/W Maximum number of cell pointers of CBP memory. Do NOT set this above the RESET VALUE. It causes unexpected behavior of the MMU.

0x17FF

Register description: CFAP read pointer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV CBP_FULL

CFAP_READ_PTR

Table 306: CFAPREADPOINTER



14 CBP_FULL RO CBP full status0 = Not full1 = Full

0

13:0 CFAP_READ_PTR RO The current number of cells outstanding in the CBP memory 0x0000

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CFAPFULLTHRESHOLD

PKTAGINGTIMER

Register description: CFAP full threshold


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED CFAPFULLRESETPOINT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CFAPFULLRESETPOINT

CFAPFULLSETPOINT

Table 307: CFAPFULLTHRESHOLD



27:14 CFAPFULLRESET_POINT

R/W CFAP FULL Reset Point defines the threshold of exiting CFAP FULL condition. CFAP is not full when CFAP Read Pointer is below this limit.

0x1700

13:0 CFAPFULLSET_POINT

R/W CFAP FULL Set Point defines the threshold of entering CFAP FULL condition. CFAP is full when CFAP Read Pointer is above this limit.

0x1770

Register description: Packet aging timer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED AGE_TICK_SEL

DURATIONSELECT

Table 308: PKTAGINGTIMER



13 AGETICKSEL R/W Age timer tick select0 = Each DURATIONSELECT value is in units of 125 µs ticks.1 = Each DURATIONSELECT value is in units of 500 ms ticks.

0

12:0 DURATIONSELECT R/W Duration select

Determines the interval that the age timer gets incremented. After the DURATIONSELECT number of the clock timer ticks (pulses), the age timer is incremented by 1. The packet aging function is disabled when this register is set to 0 and is disabled by default after a power-on reset.

0x0000

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PKTAGINGLIMIT

Register description: Packet aging limit. This register is a per CoS queue control for packet aging. The time before apacket is aged out is given by the following equation: (7 – k – 1) * m * n < t < (7 – k) * m * nwhere: Packet aging time = t PKTAGINGLIMIT.AGINGLIMITCSx = k PKTAGINGTIMER.AGETICKSEL = m, where m = 500 ms or 125 µs PKTAGINGTIMER.DURATIONSELECT = n


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED AGINGLIMITCOS7 AGINGLIMITCOS6 AGINGLIMITCOS5

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AGINGLIMITCO

S5

AGINGLIMITCOS4 AGINGLIMITCOS3 AGINGLIMITCOS2 AGINGLIMITCOS1 AGINGLIMITCOS0

Table 309: PKTAGINGLIMIT



23:21 AGINGLIMITCOS7 R/W Packet aging timer limit for CoS 7. See description for AGINGLIMITCOS0. 0x0







2:0 AGINGLIMITCOS0 R/W Packet aging timer limit for CoS 0. Selects the packet lifetime within the switch.Valid numbers are from 0 to 5. Do not set value to 6 or 7, as this may cause packet early aging.

0x0

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MISCCONFIG

Register description: Miscellaneous configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED STACK_MODE HG_GE_PORT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HG_GE_PORT PARITY_CHK_E

N

IPMC_IND_MO

DE

METERING_CLK_EN

SLAM_MEM

HOLMAXTIMER SKIDMARKER CELLCRCCHECKEN

CLRDROPCTR

DRACO_1_5_MIRRORING_MODE_EN

DYNAMIC_

MEMORY_EN

Table 310: MISCCONFIG



18:17 STACK_MODE R/W Stacking Mode

0x0 = STACK_FB—Stacking with XGS 30x1 = STACK_5670—Stacking with BCM56700x2 = STACK_5675—Stacking with BCM56750x3 = RESERVED

0x0

16:13 HG_GE_PORT R/W For ports 24–270 = HG port1 = XGE port

0x0

12 PARITY_CHECK_EN R/W Enable the MMU, checking the parity of memory readout data.

0: Disable memory parity check1: Enable memory parity check

1

11 IPMC_IND_MODE R/W IPMC_IND_MODE enables an egress port to send out one extra L2 packet with L3 IPMC packets when a packet is tagged for both L2 and L3 switching.

0: Disable sending extra l2 packet1: Enable sending extra l2 packet

0

10 METERING_CLK_EN R/W METERING_CLK_EN enables metering 7.8125 µs refresh tick to flow into egress port metering, min/max bucket and ingress backpressure metering function.

0: Disable refresh tick1: Enable refresh tick

0

9 SLAM_MEM R/W Memory slamming enable0 = Normal operation1 = Interrupts the CFAP and CCP power-on initialization. Subsequently, users are able to slam CFAP and CCP memories with the desired value.

When memory slamming is done, users need to write 1 into CFAPINIT bit in CFAPCONFIG register to complete CFAP and CCP initialization.

This register should not be programmed while the traffic is running. It may generate unexpected results.

0

8:6 HOLMAXTIMER R/W HOL Maximum Timer for sending periodic HOL CoSx and IBP discard status to the Ingress Pipeline. In units of microseconds.

0 = No periodic status sent to the Ingress Pipeline. Only send upon status change.Default value is disable.

0x0

5:4 SKIDMARKER R/W SkidMarker for each HOL Packet Counter, reserved value for the packets already in the transition to be accepted by the MMU XQ. The values of SkidMarker are:2’b00 = 4 packets2’b01 = 5 packets2’b10 = 6 packets2’b11 = 7 packets

0x0

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3 CELLCRCCHECKEN R/W MMU cell data CRC checking enable. To detect MMU internal memory failures during operation. Failure Cell Pointer can be retrieved from the CELLCRCERRPOINTER register. The Failure pointer count can be retrieved from CELLCRCERRCOUNT register. This CRC checking function can detect both Cell CRC errors and CBP Header parity errors.0 = Disable sending SBus Memfail messages based on cell CRC errors1 = Enable sending SBus Memfail message based on Cell CRC errors and CBP Header parity errors. On cell CRC errors, the egress port is informed of the status and the packet will be corrupted.

0

2 CLRDROPCTR R/W Clear All Drop Packet Counters

0 = Normal operation1 = Clear port drop counters: DROPPEDPKTCOUNT, CNG0DROPCOUNT, CNG1DROPCOUNT and CELLCRCERRCOUNTA read always returns 0.

0

1 DRACO_1_5_MIRRORING_MODE_EN

R/W BCM5695 mirroring mode enable0 = XGS 3 mirroring mode enable1 = BCM5695 mirroring mode enable

0

0 DYNAMIC_MEMORY_EN

R/W Dynamic Memory Mode Enable. HOL cell limit behavior (dynamic sharing of CBP).

0 = Disable1 = Enable Dynamic Memory mode

1

Table 310: MISCCONFIG (Cont.)


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E2ECONFIG

Register description: End-to-end configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED SEND_RX_E2E_BKP_E

N

REMOTE_SRCMODID E2E_MAXTIMER_SEL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

E2E_MAXTIMER_SEL

E2E_MINTIMER_SEL XPORT27_SEND_E2E_

HOL

XPORT26_SEND_E2E_

HOL

XPORT25_SEND_E2E_

HOL

XPORT24_SEND_E2E_

HOL

E2E_HOL_EN

XPORT27_SEND_E2E_

IBP

XPORT26_SEND_E2E_

IBP

XPORT25_SEND_E2E_

IBP

XPORT24_SEND_E2E_

IBP

E2E_IBP_EN

Table 311: E2ECONFIG



24 SEND_RX_E2E_BKP_EN

R/W SEND_RXBKP_EN received E2E BKP status to GPORT/XPORT enable.

0 = Send rx bkp status disable1 = Send rx bkp status enable

1

23:18 REMOTE_SRCMODID

R/W Remote source module ID for E2E IBP Cell/Packet Count of remote module. All 29 ports in this module are accounted for E2E IBP purposes.

0x1

17:14 E2E_MAXTIMER_SEL R/W E2E_MAXTIMER_SEL is the timing constraint to control how a second E2E IBP/HOL packet is sent out even if there is no status change. It starts counting after an E2E IBP/HOL packet is sent and expires at the selected time. When the timer expires, it sends out one IBP/HOL packet to sync out the remote module status.0 = Max Timer Disable1 = 16 µs2 = 32 µs3 = 64 µs4 = 128 µs5 = 256 µs6 = 512 µs7 = 1 ms8 = 2 ms9 = 4 ms10 = 8 ms11 = 16 ms12 = 32 ms13 = 64 ms14 = 128 ms15 = 256 ms

0xA

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13:10 E2E_MINTIMER_SEL R/W E2E_MINTIMER_SEL is the timing constraint to control how frequently a second E2E IBP/HOL packet can be sent out. It starts counting after an E2E IBP/HOL packet is sent and expires at the selected time. E2E IBP/HOL packets are not sent before the timer expires.0: Min Timer Disable1: 16 µs2: 32 µs3: 64 µs4: 128 µs5: 256 µs6: 512 µs7: 1 ms8: 2 ms9: 4 ms10: 8 ms11: 16 ms12: 32 ms13: 64 ms14: 128 ms15: 256 ms

0x3

9 XPORT27_SEND_E2E_HOL

R/W XPORT E2E messages0 = XPORT27 cannot send E2E HOL message frames.1 = XPORT27 can send E2E HOL message frame.

0


R/W XPORT E2E messages

0 = XPORT26 cannot send E2E HOL message frames.1 = XPORT26 can send E2E HOL message frame.

0



0



0

5 E2E_HOL_EN R/W E2E HOL Mode Enable

0: To Disable E2E HOL mode1: To Enable E2E HOL mode

0

4 XPORT27_SEND_E2E_IBP

R/W XPORT E2E messages0 = XPORT27 cannot send E2E IBP message frames.1 = XPORT27 can send E2E IBP message frame.

0



0


R/W XPORT E2E messages

0 = XPORT25 cannot send E2E IBP message frames.1 = XPORT25 can send E2E IBP message frame.

0



0

0 E2E_IBP_EN R/W E2E IBP Mode Enable0 = Disable E2E IBP Mode1 = Enable E2E IBP Mode

0

Table 311: E2ECONFIG (Cont.)


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ASFCONFIG

Register description: Alternative store and forward mode


IPV6IPMCIDXINCONFIG

Register description: Alternative store and forward mode


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ASF_CELL_NUM ASF_EN

Table 312: ASFCONFIG



4:1 ASF_CELL_NUM R/W Alternative Store and Forward cell number. Received cell number when Alternative Store and Forward mode is enabled.Number of cells for early transmission. Recommended value for ASF_CELL_NUM is 7.Valid values are from 5 to 15. Programing the ASF_CELL_NUM < 5, results in holding until receiving 5 cells to start.

0x7

0 ASF_EN R/W Alternative Store and Forward mode enable. The MMU dispatches a packet to the egress transaction queue when it has received the number of cells specified in the ASF_CELL_NUM field. This results in reduced switch latency.0 = Disable1 = Enable Alternative Store and Forward mode

0

Register description: IPMC index increment configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED IPMCIDXINCEN

IPMCIDXHIGHMARKER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IPMCIDXHIGHMARKER IPMCIDXLOWMARKER

Table 313: IPV6IPMCIDXINCONFIG



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20 IPMCIDXINCEN R/W IPMC Index Increment Mode Enable bit controls the IPMC index increment feature for all IPMC replicated packets transmitted to HiGig port. The IPMC index needs to be within the range defined by IPMCIdxHighMarker and IPMCIdxLowMarker. The new IPMC index is the original IPMC index added with the replicated packet number. For example: First packet—new IPMC index = original IPMC index + 1Second packet—new IPMC index = original IPMC index + 2....n-th packet—new IPMC index = original IPMC index + n

0 = IPMC Index Increment Mode disable1 = IPMC Index Increment Mode enable

0

19:10 IPMCIDXHIGHMARKER R/W IPMC index high marker 0x000

9:0 IPMCIDXLOWMARKER R/W IPMC index low marker 0x000



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IPV4IPMCIDXINCONFIG

Register description: IPMC index increment configuration


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED IPMCIDXINCEN

IPMCIDXHIGHMARKER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IPMCIDXHIGHMARKER IPMCIDXLOWMARKER




20 IPMCIDXINCEN R/W IPMC Index Increment Mode Enable bit controls the IPMC index increment feature for all IPMC replicated packets transmitted to HiGig port. The IPMC index needs to be within the range defined by IPMCIdxHighMarker and IPMCIdxLowMarker. The new IPMC index is the original IPMC index added with the replicated packet number.

For example: First packet—new IPMC index = original IPMC index + 1Second packet—new IPMC index = original IPMC index + 2....n-th packet—new IPMC index = original IPMC index + n0 = IPMC Index Increment Mode disable1 = IPMC Index Increment Mode enable

0

19:10 IPMCIDXHIGHMARKER R/W IPMC index high marker 0x000

9:0 IPMCIDXLOWMARKER R/W IPMC index low marker 0x000

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TOTALDYNCELLLIMIT

In Dynamic Memory mode, each CoS/port HOL status is reset when the TOTALDYNCELLCOUNT is under the threshold,the DYNAMICCELLCOUNT is under the DYNCELLLIMIT, COSLCCOUNT is under the LWMCELLLIMIT, andCOSPKTCOUNT is under the HOLCOSPKTRESETLIMIT.

TOTALDYNCELLUSED

Register description: Total dynamic cell limit

Register offset: 0x0068001A

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TOTALDYNCELLRESETLIMITSEL

TOTALDYNCELLLIMIT

Table 315: TOTALDYNCELLLIMIT



15:14 TOTALDYNCELLRESETLIMITSEL

R/W Total Dynamic Cell Reset Limit for MMU. To reset CBP Full, TOTALDYNCELLUSED must be under the reset threshold.

2’b000 = 75% of TOTALDYNCELLLIMIT2’b001 = 50% of TOTALDYNCELLLIMIT2’b010 = 25% of TOTALDYNCELLLIMIT2’b011 = 12.5% of TOTALDYNCELLLIMIT

0x0

13:0 TOTALDYNCELLLIMIT R/W Total Dynamic Cell Limit for CBP memory. This represents the total dynamic cells that can be used by all ports and CoS.

0x1F00


Register description: Total dynamic cells used

Register offset: 0x0068001B

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED TOTALDYNCELLUSED

Table 316: TOTALDYNCELLUSED



13:0 TOTALDYNCELLUSED RO Total dynamic cells used. Total Dynamic Cell Count for CBP memory. This represents the total dynamic cells that are being used by all port and CoS queues.

0x0000

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CMICMINTIMER

CMICTXCOSMASK

Register description: CMIC min timer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CMICMINTIMER

Table 317: CMICMINTIMER



2:0 CMICMINTIMER R/W CMIC Minimum Timer inserts a slot for packets transmitted from the MMU to the CMIC port. The values of CMICMinTimer counts in units of microseconds.If the value is set to 0, then CMIC arbitration is disabled.

0x0

Register description: CMIC transmit CoS mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CMICTXCOSMASK

Table 318: CMICTXCOSMASK



7:0 CMICTXCOSMASK R/W This CoS Mask is sent from the CMIC to the MMU to indicate which CoS packets the CPU wants to receive.0 = Allow packets1 = Block packets

0x00

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MMUPORTENABLE

Register description: MMU port enable


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED MMUPORTENABLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MMUPORTENABLE

Table 319: MMUPORTENABLE



28:0 MMUPORTENABLE R/W The MMU port enable controls which MMU egress port can accept packets.

0 = MMU egress port does not accept packets.1 = MMU egress port accepts packets (normal operation).

0x1FFFFFFF

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EGRTXPKTCTRCONFIG[7:0]

Register description: Egress transmit packet counter configuration

Register offset: 0x00680020 – EGRTXPKTCTRCONFIG00x00680021 – EGRTXPKTCTRCONFIG10x00680022 – EGRTXPKTCTRCONFIG20x00680023 – EGRTXPKTCTRCONFIG30x00680024 – EGRTXPKTCTRCONFIG40x00680025 – EGRTXPKTCTRCONFIG50x00680026 – EGRTXPKTCTRCONFIG60x00680027 – EGRTXPKTCTRCONFIG7

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV TXPKTCOUNT_SEL

TXCOSNUM TXIPORTNUM TXEPORTNUM

Table 320: EGRTXPKTCTRCONFIG[7:0]



14:13 TXPKTCOUNT_SEL R/W Transmit Packet Counter Select. Controls the way the EGRTXPKTCTR0 counts packets.

2’b00 = Disable, not counting2’b01 = Counts packets transmitted by the egress port specified in TXEPORTNUM with CoS specified in TXCOSNUM2’b10 = Counts packets received on the ingress port specified in TXIPORTNUM with CoS specified in TXCOSNUM2’b11 = Counts packets received and transmitted by the port specified in TXIPORTNUM, TXEPORTNUM with CoS specified in TXCOSNUM

0x0

12:10 TXCOSNUM – Egress CoS number. When TXPKTCOUNT_SEL is enabled, the packet transmit counter EGRTXPKTCTR increments on all of the packets to be transmitted from the specified CoS.

0x0

9:5 TXIPORTNUM R/W Ingress port number. When TXPKTCOUNT_SEL is enabled, the packet counter EGRTXPKTCTR increments on all packets received on this ingress port.

0x00

4:0 TXEPORTNUM R/W Egress port number. When TXPKTCOUNT_SEL is enabled, the packet transit counter EGRTXPKTCTR increments on all of the packets transmitted by this egress port.

0x00

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EGRTXPKTCTR[7:0]

Register description: Egress transmit packet counter configuration

Register offset: 0x00680028 – EGRTXPKTCTR00x00680029 – EGRTXPKTCTR10x0068002A – EGRTXPKTCTR20x0068002B – EGRTXPKTCTR30x0068002C – EGRTXPKTCTR40x0068002D – EGRTXPKTCTR50x0068002E – EGRTXPKTCTR60x0068002F – EGRTXPKTCTR7

Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TXPKTCOUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TXPKTCOUNT

Table 321: EGRTXPKTCTR[7:0]


31:0 TXPKTCOUNT RO Transmit Packet Counter. When EGRTXPKTCTRCONFIG.TXPKTCOUNT_SEL is configured, this packet counter increments on all packets transmitted by the specified egress port with the specified CoS.

0x00000000

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MEMFAILINTMASK

Register description: Memory fail interrupt mask


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED IPMCREP

OVERLIMIT

ERRORINT

MASK

CCPPARITYERROR

INTMASK

CFAPPARITYERROR

INTMASK

XQPARITYERROR

INTMASK

CBPCELLHDR

PARITYERROR

INTMASK

CBPPKTHDR

PARITYERROR

INTMASK

CRCERROR

INTMASK

CELLNOTIPINTMASK

SOFTRESET

INTMASK

CFAPFAILINTMASK

Table 322: MEMFAILINTMASK



9 IPMCREPOVERLIMITERRORINTMASK

R/W IPMC packet replication over the limit mask

0 = Disable1 = Enable MMU MemFail interrupt

0

8 CCPPARITYERRORINTMASK

R/W MMU CCP parity error mask0 = Disable1 = Enable MMU MemFail interrupt

0

7 CFAPPARITYERRORINTMASK

R/W MMU CFAP parity error mask0 = Disable1 = Enable MMU MemFail interrupt

0

6 XQPARITYERRORINTMASK

R/W MMU XQ parity error mask


0

5 CBPCELLHDRPARITYERRORINTMASK

R/W CBP cell header parity error mask0 = Disable1 = Enable MMU MemFail interrupt

0

4 CBPPKTHDRPARITYERRORINTMASK

R/W CBP packet header parity error mask0 = Disable1 = Enable MMU MemFail interrupt

0

3 CRCERRORINTMASK R/W CRC error mask


0

2 CELLNOTIPINTMASK R/W Cell not in packet mask0 = Disable1 = Enable MMU MemFail interrupt

0

1 SOFTRESETINTMASK R/W Soft reset mask0 = Disable1 = Enable MMU MemFail interrupt

0

0 CFAPFAILINTMASK R/W CFAP fail mask


0

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MEMFAILINTSTATUS

The status bits remain set until cleared by a register read.

Register description: Memory fail interrupt status


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED MEMFAILINTCOUNT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MEMFAILINTCOUNT IPMCREP

OVERLIMIT

ERROR

CCPPARITYERROR

CFAPPARITYERROR

XQPARITYERROR

CBPCELLHDR

PARITYERROR

CBPPKTHDR

PARITYERROR

CRCERROR

CELLNOTIP

SOFTRESET

CFAPFAIL

Table 323: MEMFAILINTSTATUS



25:10 MEMFAILINTCOUNT RO Memory Fail Message Counter. Increments on memory fail events. 0x0000

9 IPMCREPOVERLIMITERROR

RO IPMC packet replication over the limit0 = No error1 = Condition detected

0

8 CCPPARITYERROR RO MMU CCP parity error

0 = No error1 = Condition detected

0

7 CFAPPARITYERROR RO MMU CFAP parity error mask0 = No error1 = Condition detected

0

6 XQPARITYERROR RO MMU XQ parity error0 = No error1 = Condition detected

0

5 CBPCELLHDRPARITYERROR

RO CBP cell header parity error


0

4 CBPPKTHDRPARITYERROR

RO CBP packet header parity error0 = No error1 = Condition detected

0

3 CRCERROR RO CRC error0 = No error1 = Condition detected

0

2 CELLNOTIP RO Cell not in packet error


0

1 SOFTRESET RO Soft reset error0 = No error1 = Condition detected

0

0 CFAPFAIL RO CFAP fail error0 = No error1 = Condition detected

0

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CBPCELLCRCERRPTR

CBPCELLHDRPARITYERRPTR

Register description: CBP cell CRC error pointer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV ERRORPOINTER

Table 324: CBPCELLCRCERRPTR



13:0 ERRORPOINTER RO CBP Data Memory. Cell CRC error pointer indicates first failure memory location. 0x0000

Register description: CBP cell header parity error pointer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED ERROREDNEXTCELLPOINTER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ERROREDNEXTCELLPOINTER

ERRORPOINTER

Table 325: CBPCELLHDRPARITYERRPTR



27:14 ERROREDNEXTCELLPOINTER

RO CBP Cell Header Memory parity error next cell pointer is the abandoned next cell pointer.

0x0000

13:0 ERRORPOINTER RO CBP Cell Header Memory parity error pointer is the error cell header pointer. 0x0000

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CBPPKTHDRPARITYERRPTR

SOFTRESETPBM

Register description: CBP packet header parity error pointer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV ERRORPOINTER

Table 326: CBPPKTHDRPARITYERRPTR



13:0 ERRORPOINTER RO CBP Packet Header Memory parity error pointer is the error cell header pointer. 0x0000

Register description: Soft reset error bitmap


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED SOFTRESETPBM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SOFTRESETPBM

Table 327: SOFTRESETPBM



28:0 SOFTRESETPBM RO Ingress Port Bitmap indicates which ingress port(s) are generating a software reset error. The bitmap is cleared upon a register read.

0x00000000

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IPMCREPOVERLMTPBM

XQPARITYERRORPBM

Register description: IPMC packet replication is over the limit (port bitmap)


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED IPMCREPOVERLMTPBM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IPMCREPOVERLMTPBM

Table 328: IPMCREPOVERLMTPBM



28:0 IPMCREPOVERLMTPBM

RO Egress Port Bitmap indicates which IPMC Replication egress port is over the replication limit (error). The bitmap is cleared upon a register read.

0x00000000

Register description: Transaction queue parity error port bitmap


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED XQPARITYERRORPBM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XQPARITYERRORPBM

Table 329: XQPARITYERRORPBM



28:0 XQPARITYERRORPBM

RO Egress Port Bitmap indicates which egress port has detected an XQ parity error. The bitmap is cleared upon a register read.

0x00000000

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CFAPPARITYERRORPTR

CCPPARITYERRORPTR

Register description: MMU CFAP parity error pointer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV CFAPPARITYERRORPTR

Table 330: CFAPPARITYERRORPTR



13:0 CFAPPARITYERRORPTR

RO MMU CFAP memory parity error pointer indicates the most current CFAP parity error pointer.

0x0000

Register description: MMU CCP parity error pointer


Bit Number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV CCPARITYERRORPTR

Table 331: CCPPARITYERRORPTR



13:0 CCPPARITYERRORPTR

RO MMU CCP memory parity error pointer indicates the most current CCP parity error pointer.

0x0000

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Section 13: GbE Por t Internal PHY RegistersThere are two 12-port SerDes cores in the BCM56500. This register can be accessed through the CMIC_MIIM_PARAMregister, with INTERNAL_SEL = 1 for the appropriate PHY address.

The PHY registers are broken into two blocks:

• Block 0 is for IEEE and non-IEEE controls.

• Block 1 is a non-IEEE block, where the analog section of the SerDes is controlled.

To access Block 1, write to the block number into the Block Address register at address 0x1F (reserved on each block).

INT PHY Address Description

00h BCM56500 GbE port 0, (SerDes Module 0 Port 1)




: :

: :




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REGISTER MAP

Table 332: GbE Port Internal PHY Register Map

Address Block Number Register Name Description

00h 0 MII CONTROL MII Control register

01h 0 MIISTATUS MII Status register

02h–03h 0 – Reserved

04h 0 AUTONEGADV Auto-Negotiation Advertisement register

05h 0 AUTONEGLINKPARTNERABILITY

Auto-Negotiation Link Partner Ability register

06h 0 AUTONEGEXPANSION Auto-Negotiation Expansion register

07h–0Eh 0 – Reserved

0Fh 0 EXTENDEDSTATUS Extended status

10h 0 1000XCONTROL1 1000XControl 1 register




14h 0 1000XSTATUS1 1000XStatus 1 register



17h–1Eh 0 – Reserved

10h 1 ANALOG_TX Analog TX

11h 1 ANALOG_RX_1 Analog RX 1

12h–13h 1 – Reserved

1Fh BLOCKADDRESS Block Address register

Abbreviation Description

R/W Read/write

RO Read only

LH Latches high value (until read)

LL Latches low value (until read)

H Forced high

L Forced low

SC Self-clearing

CR Clear on read

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MII CONTROL

Register description: MII Control register

Register offset: 0x00 (block = 0)

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RST_SW

LOOP_BACK

SPD[0] AN_EN PWR_DN

RESV RESTART_AN

FDX COL_TEST_

EN

SPD[1] RESERVED

Table 333: CONTROL


15 RST_SW R/W PHY reset0 = Normal operation1 = PHY reset

0

14 LOOPBACK R/W Local loopback enable. Data sends by the MAC will loop back at the MAC interface.0 = Normal operation1 = Loopback enable

0

13 SPD[0] R/W Speed[0] of manual speed[1:0] (SGMII only)

1X = 1000 Mbps01 = 100 Mbps00 = 10 MbpsNote: Register ignored for 1000BASE-X operation.

0

12 AN_EN R/W Auto-negotiation (AN) enable0 = Disable1 = Enable AN

1

11 PWRDN R/W Power-down enable0 = Normal operation1 = Low-power mode enable

0

10 RESERVED RO Reserved Write 0, ignore read 0

9 RESTART_AN R/W Restart AN0 = Normal operation1 = Restart the AN process

0

8 FDX R/W Full-duplex0 = Half-duplex1 = Full-duplex

0

7 COL_TEST_EN R/W Collision test enable

0 = Normal operation1 = Collision test mode enable

0

6 SPD[1] R/W Speed[1] of manual speed[1:0] (SGMII only)1X = 1000 Mbps01 = 100 Mbps00 = 10 Mbps

Note: register ignored for 1000BASE-X operation.

1

5:0 RESERVED RO Reserved Write 0, ignore read. 0x00

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MIISTATUS

Register description: MII Status register


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

100BASE_T4

100BASEX_FDX

100BASEX_HD

X

10BASET_FDX

10BASET_HDX

100BASE_T2_F

DX

100BASE_T2_H

DX

EXT_STATUS

RESV MF_PREAMBLE_SUPPRESSI

ON

AN_COMPLT

RF AN_ABILITY

LINK_STATUS

JABBER_DETE

CT

EXT_CAPABILIT

Y

Table 334: MIISTATUS


15 100BASE_T4 RO 0 = Not capable1 =100BASE-T4 capable

0

14 100BASEX_FDX RO 0 = Not capable1 = 100BASE-X full-duplex capable

0

13 100BASEX_HDX RO 0 = Not capable1 = 100BASE-X half-duplex capable

0

12 10BASET_FDX RO 0 = Not capable1 = 10BASE-T full-duplex capable

0

11 10BASET_HDX RO 0 = Not capable1 = 10BASE-T half-duplex capable

0

10 100BASET2_FDX RO 0 = Not capable1 = 100BASE-T2 full-duplex capable

0

9 100BASET2_HDX RO 0 = Not capable1 = 100BASE-T2 half-duplex capable

0

8 EXT_STATUS RO 0 = No extended status1 = Extended status in register 0x0F

1

7 RESERVED RO Reserved Write 0, ignore read 0

6 MF_PREAMBLE_SUPPRESSION

RO 0 = PHY does not accept management frames with preamble suppressed.1 = PHY accepts management frames with preamble suppressed.

1

5 AN_COMPLT RO Auto-negotiation complete0 = Not done1 = AN complete

0

4 RF RO Remote fault0 = No fault detected1 = Remote fault detected

0

3 AN_ABILITY RO Auto-negotiation ability

0 = Not capable of AN1 = AN capable

1

2 LINK_STATUS RO Link status0 = Link fail1 = Good link

0

1 JABBER_DETECT RO Jabber detect0 = Not detected1 = Jabber detected

0

0 EXT_CAPABILITY RO Extended capability

0 = Supports basic register set only1 = Extended register capabilities supported

1

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AUTONEGADV

Register description: Auto-negotiation advertisement register


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NEXT_PG

RESV RF RESERVED PAUSE HDX FDX RESERVED

Table 335: AUTONEGADV


15 NEXT_PG RO Next page 0

14 RESERVED RO Reserved. Write as 0, ignore read. 0

13:12 RF R/W Remote fault2’b00 = No fault2’b01 = Link failure2’b10 = Offline2’b11 = Auto-negotiation error

0x0

11:9 RESERVED RO Reserved—Write 0, ignore read 0x0

8:7 PAUSE R/W Pause2’b00 = No pause2’b01 = Asymmetric pause2’b10 = Asymmetric pause towards link partner2’b11 = Both symmetric and asymmetric pause, towards local device

0x0

6 HDX R/W Half-duplex0 = Do not advertise half-duplex1 = Advertise half-duplex

1

5 FDX R/W Full-duplex0 = Do not advertise full-duplex1 = Advertise full-duplex

1


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AUTONEGLINKPARTNERABILITY

Register description: Auto-negotiation link partner ability register


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NEXT_PG

ACK RF RESERVED PAUSE HDX FDX RESERVED SGMII

Table 336: AUTONEGLINKPARTNERABILITY


15 NEXT_PG RO Next page 0

14 ACK RO 0 = Link partner has not received link code word1 = Link partner has received link code word

0

13:12 RF RO Remote fault2’b00 = No fault2’b01 = Link failure2’b10 = Offline2’b11 = AN error

0x0


8:7 PAUSE RO Pause2’b00 = No pause2’b01 = Asymmetric pause2’b10 = Asymmetric pause towards link partner2’b11 = Both symmetric and asymmetric pause towards local device

0x0

6 HDX RO Half-duplex

0 = Do not advertise half-duplex1 = Advertise half-duplex

0

5 FDX RO Full-duplex0 = Do not advertise full-duplex1 = Advertise full-duplex

0

4:1 RESERVED RO Reserved. Write as 0, ignore read 0x0

0 SGMII RO SGMII mode

0 = Fiber mode1 = SGMII mode

0

Note: When the link partner is in SGMII mode (bit [0] = 1), then:

• [15] = link

• [14] = acknowledge

• [12] = duplex

• [11:10] = speed

The other bits are reserved and should be zero.

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AUTONEGEXPANSION

EXTENDEDSTATUS

Register description: Auto-negotiation expansion register


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED NP_ABILITY

PG_REC

RESV

Table 337: AUTONEGEXPANSION



2 NP_ABILITY RO Next page ability0 = Local device is not next page able.1 = Local device is next page able.

0

1 PG_REC RO Page received0 = New link code word has not been received.1 = New link code word has been received.

0

0 RESERVED RO Reserved—Write 0, ignore read 0

Register description: Extended status register

Register offset: 0x0F (block = 0)

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1000BASEX_FD

X

1000BASEX_H

DX

1000BASET_FD

X

1000BASET_H

DX

RESERVED

Table 338: EXTENDEDSTATUS


15 1000BASEX_FDX RO 0 = Not capable1 = 1000BASE-X full-duplex capable

1

14 1000BASEX_HDX RO 0 = Not capable1 = 1000BASE-X half-duplex capable

1

13 1000BASET_FDX RO 0 = Not capable1 = 1000BASE-T full-duplex capable

0

12 1000BASET_HDX RO 0 = Not capable1 = 1000BASE-T half-duplex capable

0

11:0 RESERVED RO Reserved. Write as 0, ignore read. 0x000

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1000XCONTROL1

Register description: 1000BASE-X control 1


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV DIS_SD_FILTE

R

MSTR_MDIO_PHY_SEL

SERDES_TX_AMP_OV

R

SEL_RX_PKTS_FOR_C

NTR

REMOTE_LPBK

ZERO_CD_

PHASE

CD_EN CRC_DIS

DIS_PLL_PWR

DN

SGMII_MSTR

AUTODET_EN

INVER_SD

SD_EN TBI FIBER

Table 339: 1000XCONTROL1



14 DIS_SD_FILTER R/W 0 = Filter signal detect from pin before using for synchronization1 = Disable filter for signal detect

0

13 MSTR_MDIO_PHY_SEL R/W 0 = Normal operation1 = All MDIO write accesses to PHY address 00000 writes this PHY in addition to its own PHY address.

0

12 SERDES_TX_AMP_OVR R/W 0 = Normal operation (selected by SGMII or fiber mode)1 = Override SerDes transmit amplitude from register 1*10h bit 14

0

11 SEL_RX_PKTSFOR_CNTR

R/W 0 = Select CRC errors for 0*17h counter1 = Select received packets for 0*17h counter

0

10 REMOTE_LPBK R/W 0 = Normal operation1 = Enable remote loopback (operates in 10/100/1000 speed). The data is looped back at the GMII interface, prior reaching to the MAC.

0

9 ZERO_CD_PHASE R/W 0 = Normal operation1 = Force comma detector phase to zero

0

8 CD_EN R/W 0 = Disable comma detection1 = Enable comma detection

0

7 CRC_DIS R/W 0 = Enable CRC checker1 = Disable CRC checker by gating the clock to save power

0

6 DIS_PLL_PWRDN R/W 0 = PLL is powered down when register 0.11 is set1 = PLL is never powered down. (use this when the MAC/switch uses the pll_clk125 output)

0

5 SGMII_MSTR R/W 0 = Normal operation1 = SGMII mode operates in PHY mode. If auto-negotiation is enabled, then the local device sends out the following auto-negotiation code word:[15] = 1[14] = ACK[13] = 0[12] = Register 0.8[11] = Register 0.6[10] = Register 0.13[9:0] = 0000000001To disable the link, set register 0.11 = 1To enable the link, set register 0.11 = 0

0

4 AUTODET_EN R/W 0 = Disable auto-detection (fiber or SGMII mode is set according to bit 0 of this register)1 = Enable auto-detection (fiber and SGMII mode switches each time an auto-negotiation page is received with the wrong selector field in bit 0.)

0

3 INVERT_SD R/W 0 = Use signal detect from pin1 = Invert signal detect from pin

0

2 SD_EN R/W 0 = Ignore signal detect from pin1 = Signal detect from pin must be set in order to achieve synchronization. In SGMII, the signal detect is always ignored regardless of the setting of this bit.

0

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1 TBI R/W 0 = GMII interface1 = 10-bit interface

0

0 FIBER R/W 0 = SGMII mode1 = Fiber mode (1000X)

0

Table 339: 1000XCONTROL1 (Cont.)


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1000XCONTROL2



Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESVERVED DIS_CARRIER_

EXT

RESERVED DIS_RF_SENS

E

EN_AN_ERR_TI

MER

FILTER_FORCE_LINK

DIS_FALSE_LI

NK

EN_PAR_DET



15:8 RESERVED RO Reserved—Write 0, ignore read 0

7 DIS_CARRIER_EXT R/W 0 = Normal operation1 = Disable carrier extension in PCS receive

0

6:5 RESERVED RO Reserved—Write 0, ignore read 0

4 DIS_RF_SENSE R/W 0 = Automatically detect remote faults and send remote fault status to link partner via auto-negotiation when fiber mode is selected. SGMII does not support remote faults.1 = Disable automatic sensing of remote faults such as auto-negotiation error

0

3 EN_AN_ERR_TIMER R/W 0 = Normal operation1 = Enable auto-negotiation error timer. Error occurs when timer expires in ability-detect, ACK-detect, or idle-detect. When the error occurs, config words of all zeros are sent until an ability match occurs, then the auto-negotiation enable state is entered.

0

2 FILTER_FORCE_LINK R/W 0 = Normal operation1 = Sync-status must be set for a solid 10 ms before a valid link is established when auto-negotiation is disabled. (This is useful in fiber applications where the user does not have the signal detect pin connected to the fiber module and auto-negotiation is turned off.)

0

1 DIS_FALSE_LINK R/W 0 = Normal operation1 = Do not allow link to be established when auto-negotiation is disabled and when receiving auto-negotiation code words. The link will only be established in this case after idles are received. (This bit does not need to be set if bit 0 is set.)

0

0 EN_PAR_DET R/W 0 = Disable1 = Enable parallel detection. (This turns auto-negotiation on and off as needed to properly link up with the link partner. The idles and auto-negotiation code words received from the link partner are used to make this decision.)

1

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1000XCONTROL3



Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESV RXFIFO_GMII_

RST

DIS_TX_CRS

INV_EXT_PHY_

CRS

EXT_PHY_CRS

JAM_FLASE_C

RS

BLK_TXEN

FORCE_TXFIFO_ON

BYP_TXFIFO_1

000

FREQ_LOCK_ELAS_TX

FREQ_LOCK_ELAS_RX

EARLY_PRE_TX

EARLY_PRE_R

X

FIFO_ELAS_TX_RX

TXFIFO_RST




14 RXFIFO_GMII_RST R/W 0 = Normal operation1 = Reset receive FIFO and data_out_1000. FIFO remains in reset until this bit is cleared with a software write.

0

13 DIS_TX_CRS R/W 0 = Normal operation1 = Disable generating CRS from transmitting in half-duplex mode. Only receiving generates CRS.

1

12 INV_EXT_PHY_CRS R/W 0 = Use Receive CRS From PHY pin1 = Invert Receive CRS From PHY pin

1

11 EXT_PHY_CRS R/W 0 = Normal operation

1 = Use external pin for the PHY’s Receive Only CRS output. (This is useful in SGMII 10/100 half-duplex applications to reduce the collision domain latency. Requires a PHY which generates a Receive Only CRS output to a pin.)

1

10 JAM_FALSE_CRS R/W 0 = Normal operation1 = Change false carriers received into packets with preamble only (not necessary if MAC uses CRS to determine collision)

0

9 BLK_TXEN R/W 0 = Normal operation1 = Block TXEN when necessary to guarantee an IPG of at least 6.5 bytes in 10/100 mode and 7 bytes in 1000 mode

0

8 FORCE_TXFIFO_ON R/W 0 = Normal operation1 = Force transmit FIFO to free-run in gigabit mode (requires clk_in and pll_clk125 to be frequency locked)

0

7 BYP_TXFIFO_1000 R/W 0 = Normal operation1 = Bypass transmit FIFO in gigabit mode. (This is useful for fiber or gigabit-only applications where the MAC is using the pll_clk125 as the clk_in port. User must meet timing to the pll_clk125 domain).

0

6 FREQ_LOCK_ELAS_TX

R/W 0 = Normal operation1 = Minimum FIFO latency to properly handle a clock that is frequency locked, but out of phase. (Overrides bits [2:1] of this register.)Note: pll_clk125 and clk_in must be using the same crystal.

0

5 FREQ_LOCK_ELAS_RX

R/W 0 = Normal operation1 = Minimum FIFO latency to properly handle a clock which is frequency locked, but out of phase. (Not necessary if MAC uses CRS to determine collision; overrides bits [2:1] of this register).Note: MAC and PHY must be using the same crystal for this mode to be enabled.

0

4 EARLY_PRE_TX R/W 0 = Normal operation1 = Send extra bytes of preamble to avoid FIFO latency. (Not necessary if MAC uses CRS to determine collision.)

0

3 EARLY_PRE_RX R/W 0 = Normal operation1 = Send extra bytes of preamble to avoid FIFO latency. (Used in half-duplex applications to reduce collision-domain latency. MAC must send 5 bytes or less of preamble to avoid non-compliant behavior.)

0

2:1 FIFO_ELAS_TX_RX R/W 00 = Supports packets up to 5 KB01 = Supports packets up to 10 KB1X = Supports packets up to 13.5 KB

0x0

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0 TXFIFO_RST R/W 0 = Normal operation1 = Reset transmit FIFO. FIFO remains in reset until this bit is cleared with a software write.

0

Table 341: 1000XCONTROL3 (Cont.)


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1000XCONTROL4



Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ZERO_DATA_OUT_1000

CLEAR_LINKDN

EN_LATCH_LIN

KDN

LINK_FORCE

DIG_RESET

ANA_PLL_LOCK_OVR_

VAL

EN_ANA_PLL_LOCK_

OVR

DIG_PLL_LOCK_OVR_

VAL

EN_DIG_PLL_LOCK_O

VR

ANA_SD_OVR_VAL

EN_ANA_SD_OVR




10 ZERO_DATA_OUT_1000 R/W 0 = Normal operation1 = Zero data_out_1000 when speed is not 1000 Mbps

0

9 CLEAR_LINKDN R/W 0 = Normal operation1 = Clear latching of link down. Latch_linkdown status bit is register 0*16h bit[[10] enable_latch_linkdown control bit is bit[8] of this register.

0

8 EN_LATCH_LINKDN R/W 0 = Normal operation1 = Enable latching of link when link is down. Transmit FIFO, receive FIFO and data_out_1000 to remain in reset state until bit[9] of this register is 1.

0

7 LINK_FORCE R/W 0 = Normal operation1 = Force link on

0

6 DIG_RESET R/W 0 = Normal operation1 = Resets digital logic datapath. MII registers are not in reset state.

0

5 ANA_PLL_LOCK_OVR_VAL

R/W PLL lock status bit override value 0

4 EN_ANA_PLL_LOCK_OVR R/W 0 = Override PLL lock status bit with bit [5] of this register1 = Use PLL lock status bit from analog directly in analog reset logic

0

3 DIG_PLL_LOCK_OVR_VAL

R/W PLL lock status bit override value 0

2 EN_DIG_PLL_LOCK_OVR R/W 0 = Override PLL lock status bit with bit [3] of this register1 = Use PLL lock status bit from analog directly in digital logic

0

1 ANA_SD_OVR_VAL R/W Analog signal-detect status bit override value 0

0 EN_ANA_SD_OVR R/W 0 = Override analog signal-detect status with bit [1] of this register1 = Use analog signal detect

1

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1000XSTATUS1

Register description: 1000BASE-X status 1


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TXFIFO_ERR

RXFIFO_ERR

FALSE_CRS

CRC_ERR

TX_ERR

RX_ERR

CRS_EXT

EARLY_END_E

XT

LINK_CHG

PAUSE_RES_R

X

PAUSE_RES_T

X

SPEED_STATUS DUPLEX_STAT

LINK_STAT

SGMII_MODE

Table 343: 1000XSTATUS1


15 TXFIFO_ERR RO 0 = No transmit FIFO error detected since last read1 = Transmit FIFO error detected since last read

0

14 RXFIFO_ERR RO 0 = No receive FIFO error detected since last read1 = Receive FIFO error detected since last read

0

13 FALSE_CRS RO 0 = No false carrier detected since last read1 = False carrier detected since last read

0

12 CRC_ERR RO 0 = No CRC error detected since last read or detection is disabled via register 0*10h bit [7]1 = CRC error detected since last read

0

11 TX_ERR RO 0 = No transmit error code detected since last read1 = Transmit error code detected since last read (rx_data_error state in PCS receive fsm)

0

10 RX_ERR RO 0 = No receive error since last read1 = Receive error since last read (early_end state in PCS receive FSM)

0

9 CRS_EXT RO 0 = No carrier extend error since last read1 = Carrier extend error since last read (extend_err in PCS receive FSM)

0

8 EARLY_END_EXT RO 0 = No early end extension since last read1 = Early end extension since last read (early_end_ext in PCS receive FSM)

0

7 LINK_CHG RO 0 = Link status has not changed since last read1 = Link status has changed since last read

0

6 PAUSE_RES_RX RO 0 = Disable pause receive1 = Enable pause receive

0

5 PAUSE_RES_TX RO 0 = Disable pause transmit1 = Enable pause transmit

0

4:3 SPEED_STAT RO 00 = 10 Mbps01 = 100 Mbps1X = 1000 Mbps

0x0

2 DUPLEX_STAT RO 0 = Half-duplex1 = Full-duplex

0

1 LINK_STAT RO 0 = Link is down1 = Link is up

0

0 SGMII_MODE RO 0 = Fiber mode (1000BASE-X)1 = SGMII mode

0

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1000XSTATUS2



Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SGMII_MODE_

CHG

CONS_MISMAT

CH

AN_RES_ERR

SGMII_SEL_MI

S

SYNC_STAT_F

AIL

SYNC_STAT_O

K

RESERVED



15 SGMII_MODE_CHG RO 0 = SGMII mode has not changed since the last read (fixed in SGMII or fiber mode).1 = SGMII mode has changed since the last read (SGMII mode enabled or disabled).Note: This bit is useful when the auto-detection is enabled in register 0*10h bit [4].

0

14 CONS_MISMATCH RO 0 = Consistency mismatch has not been detected since the last read.1 = Consistency mismatch detected since last read.

0

13 AN_RES_ERR RO 0 = Auto-negotiation HCD error has not been detected since the last read.1 = Auto-negotiation HCD error detected since last read (HCD is none in fiber mode).

0

12 SGMII_SEL_MIS RO 0 = SGMII selector mismatch not detected since the last read.1 = SGMII selector mismatch detected since the last read (auto-negotiation page received from link partner with bit [0] = 0, while local device is in SGMII mode).

0

11 SYNC_STAT_FAIL RO 0 = SYNC_STATUS has not failed since the last read.1 = SYNC_STATUS has failed since the last read (synchronization has been lost).

0

10 SYNC_STAT_OK RO 0 = SYNC_STATUS ok has not been detected since the last read.1 = SYNC_STATUS ok detected since the last read (synchronization has been achieved).

0


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1000XSTATUS3



Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED SD ANA_SD

RESERVED





6 SD RO Signal detect direct from pin. 0

5 ANA_SD RO Analog signal-detect status bit

This status signal is the analog signal-detect status if register 0*13h bit [0] is set, otherwise, it is the value based on register 0*13h bit [1].

0



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ANALOG_TX

Register description: Analog Transmit Register. This register sets the amplitude and pre-emphasis of the SerDes. InSGMII mode, the driver_current and predriver_current are three bits. Broadcom recommends thatthese two values be set to be the same. The three bits allow roughly linear control over eight possiblecombinations of amplitude swing. Refer to the BCM56500 data sheet for details of the amplituderange. In a typical SGMII application where the device is connected to the PHY, then this register isrecommended to be set at 0xC820. In an application where the device is connected directly to a fibermodule, Broadcom recommends that this register set at 0xFE20.

Register offset: 0x10 (block = 1): Use the BLOCK_ADDRESS register (0x1F) to change the block number.

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DRIVER_CURRENT PREDRIVER_CURRENT PRE_COEF REG_EDGE_

SEL

BOOST_MODE

DRIVER_IDLE

LOOPBACK

RESET IDDQ

Table 346: ANALOG_TX


15:12 DRIVER_CURRENT R/W This setting may need to be changed from the default value if the transmitter is required to drive long trace lengths. The values for this setting increase in roughly linear increments corresponding to 500 mV–1200 mV.Note: Bit [14] is forced to 0 internally unless register 0*10h bit [12], or 0*10h bit[4], or 0*10h bit[0] is set to 1. When 0*10h bit [12] is 0, then the value is determined from the SGMII/fiber mode. Fiber internally sets the bit to 1 to the analog transmitter. SGMII clears the bit to 0 to the analog transmitter. The bits used are [15][13][12].

0xC

11:9 PREDRIVER_CURRENT R/W This setting may need to be changed from the default value if the transmitter is required to drive long trace lengths {pre_driver, tx_driver}. The values for this setting increase in roughly linear increments corresponding to 500 mV–1200 mV. The value for PREDRIVER_CURRENT should be the same as that of DRIVER_CURRENT.

0x4

8:6 PRE_COEF R/W Pre-emphasis coefficient. This setting may need to be changed from the default value if the transmitter is required to drive long trace lengths.

These three bits allow eight possible combinations, ranging from 0% to 50%. 0x7 is 50% and 0x0 is 0%. The granularity is roughly linear across the eight settings.

0x0

5 REG_EDGE_SEL R/W Reserved for factory testing only.

0 = Capture on falling edge1 = Capture on rising edge

1

4 BOOST_MODE R/W Reserved for factory testing only.0 = Disable transmit boost mode1 = Enable transmit boost mode

0

3 DRIVER_IDLE R/W 0 = Disable transmit driver idle1 = Enable transmit driver idle

0

2 LOOPBACK R/W 0 = Disable remote loopback1 = Enable remote loopback. The far end sends the data to the device and the data is looped back to the wire at the analog block prior reaching to the de-serializer. The data will not reach to the device MAC block. In order to use the remote loopback, both ANALOG_TX.LOOPBACK and ANALOG_RX_1.LOOPBACK must be set.

0

1 RESET R/W 0 = SerDes is not in reset.1 = SerDes is in reset.

0

0 IDDQ R/W 0 = SerDes is not in the IDDQ state.1 = SerDes is in the IDDQ state. The device is powered down.

0

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ANALOG_RX_1

Register description: Analog receive control 1


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TEST_SEL SD_THRES SD_EN LOOPBACK

REG_EDGE_S

EL

INTERP_BIAS_CURRENT CURRENT_REF_BIAS RESET IDDQ

Table 347: ANALOG_RX_1


15:13 TEST_SEL R/W Reserved—Write 0, ignore read 0x0

12:11 SD_THRES R/W Reserved—Write 0, ignore read 0x0

10 SD_EN R/W 0 = Disable signal detect1 = Enable signal detect

0

9 LOOPBACK R/W 0 = Disable remote loopback1 = Enable remote loopback. The far end sends the data to the device, and the data gets looped back to the wire at the analog block. The data will not reach to the device MAC block. In order to use the remote loopback, both ANALOG_TX.LOOPBACK and ANALOG_RX_1.LOOPBACK must be set.

0

8 REG_EDGE_SEL R/W 0 = RxData aligned on rising edge1 = RxData aligned on falling edge

1

7:5 INTERP_BIAS_CURRENT R/W Reserved—Write 0, ignore read 0x0

4:2 CURRENT_REF_BIAS R/W Reserved 0x0

1 RESET R/W 0 = SerDes is not in reset.1 = SerDes is in reset.

0

0 IDDQ R/W 0 = SerDes is not in the IDDQ state.1 = SerDes is in the IDDQ state. The device is powered down.

0

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BLOCKADDRESS

Register description: Block address number

Register offset: 0x1F

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BLK_NO

Table 348: BLOCKADDRESS



3:0 BLK_NO R/W Block offset value. Assign value to register 0x1F will move the offset block. For example register 0x10 is the ANALOG_TX register when assign register 0x1F = 0x1.0000 = Valid0001 = Valid0010–1111 = Reserved for future implementation

0x0

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Section 14: XG Port Internal PHY RegistersThere are four XAUI cores in the BCM56500. This register can be accessed through the CMIC_MIIM_PARAM register, withINTERNAL_SEL = 1 for the appropriate PHY address.

Table 349: Internal PHY Register Addresses

INT PHY Address Description

18h Port 24 (XAUI Module 0)

19h Port 25 (XAUI Module 1)

1Ah Port 26 (XAUI Module 2)

1Bh Port 27 (XAUI Module 3)

Table 350: Register Map

Addressa

a. Registers not listed are reserved.

Block Number Register Name Description

00h 0 IEEE_CONTROL1 IEEE Control 1

01h 0 IEEE_STATUS1 IEEE Status 1

04h 0 IEEE_SPEED_ABILITY IEEE Speed Ability

07h 0 IEEE_CONTROL 2 IEEE Control 2

08h 0 IEEE_STATUS2 IEEE Status 2

17h 60, 70, 80, 90, A0 TX_ACONTROL TXn AControl; n = 0, 1, 2, 3, A

10h B0, C0, D0, E0, F0 RX_STATUS RXn Status; n = 0,1, 2, 3, A

1Fh ALL BLOCKADDRESS Block Address register

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IEEE_CONTROL1

Register description: Control registers

Register offset: 0x0 (Block 0)

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RST_SW

RESV SPD_SEL1

RESV PWRDN_SW

RESERVED SPD_SEL2

SPEED_SEL[3:0] RESV GLB_LPBK

Table 351: IEEE_CONTROL1


15 RST_SW R/W Software reset

0 = Normal operation1 = Reset

0

14 RESERVED RO Reserved—Write 0, ignore read. 0

13 SPD_SEL1 R/W Speed select 1 1


11 PWRDN_SW R/W Power down0 = Normal operation1 = Power down mode enable

0

10:7 RESERVED RO Reserved—Write 0, ignore read. 0x0

6 SPD_SEL2 R/W Speed select 2 1

5:2 SPEED_SEL[3:0] RO Speed select 0x0


0 GLB_LPBK R/W Global loopback enable

0 = Normal operation1 = Loopback enable

0

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IEEE_STATUS1

IEEE_SPEED_ABILITY

Register description: Status register


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED LCL_FAULT

RESERVED LINK PWRDN_CAP

RESV

Table 352: IEEE_STATUS1



7 LCL_FAULT RO Local fault0 = No fault detected1 = Local fault detected

0


2 LINK RO Link status (latches link-down, cleared on read)

0 = Link-down1 = Link-up

0

1 PWRDN_CAP RO Power-down capable0 = Not able1 = Power-down capable

1


Register description: Speed capability


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED 10G_CAP

Table 353: IEEE_SPEED_ABILITY



0 10G_CAPABLE R/W 10G capable

0 = Not capable1 = 10G capable

1

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IEEE_CONTROL 2

Register description: Control register 2


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PMA_PMD_SEL

Table 354: IEEE_CONTROL 2



1:0 PMA_PMD_SEL R/W PMA/PMD select

0 = 10GBase CX4 PMA/PMD type1 = Reserved2 = Reserved3 = Reserved

0x0

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IEEE_STATUS2

Register description: Status register 2


Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DEV_PRESENT TX_FAULT_ABIL

ITY

RX_FAULT_AB

ILITY

TX_LOCAL_FAU

LT

RX_LOCAL_FA

ULT

EXT_ABILITIES

PMD_DIS_ABILI

TY

10GBASE_SR

10GBASE_LR

10GBASE_ER

10GBASE_LX4

10GBASE_SW

10GBASE_LW

10GBASE_EW

PMA_LOOPBK_ABILIT

Y

Table 355: IEEE_STATUS2


15:14 DEV_PRESENT RO Reserved—Write 0, ignore read. 0x2

13 TX_FAULT_ABILITY RO Reserved—Write 0, ignore read. 1

12 RX_FAULT_ABILITY RO Reserved–Write 0, ignore read. 1

11 TX_LOCAL_FAULT RO 0 = No fault detected1 = Local fault detected in TX path

0

10 RX_LOCAL_FAULT RO 0 = No fault detected1 = Local fault detected in TX path

0

9 EXT_ABILITIES RO Reserved—Write 0, ignore read. 1

8 PMD_DIS_ABILITY RO Reserved—Write 0, ignore read. 0

7 10GBASE_SR RO Reserved—Write 0, ignore read. 0

6 10GBASE_LR RO Reserved—Write 0, ignore read. 0

5 10GBASE_ER RO Reserved—Write 0, ignore read. 0

4 10GBASE_LX4 RO Reserved—Write 0, ignore read. 0

3 10GBASE_SW RO Reserved—Write 0, ignore read. 0

2 10GBASE_LW RO Reserved—Write 0, ignore read. 0

1 10GBASE_EW RO Reserved—Write 0, ignore read. 0

0 PMA_LOOPBK_ABLITY RO Reserved—Write 0, ignore read. 1

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TX_ACONTROL

Register description: Transmitter Control. Broadcom recommended that the driver current and pre-driver current areprogrammed to the same value. The pre-emphasis has four bits of setting, likewise for the driversettings. This gives 16 combinations.

For driver settings, the 16 combinations allow the transmitter to have amplitude ranging from around600 mV to 1200 mV pk-pk, in norminal condition such as 1.25V Vcc. The 4 bits allow almost a linearadjustment of the pk-pk voltage. Setting 0x0 is minimum output voltage and 0xF is maximum outputvoltage.

For pre-emphasis, there are also 4 bits, giving 16 possible combinations. 0x0 is minimum and 0xFis max. The maximum pre-emphasis 0xF will give you roughly 50% of pre-emphasis. The minimumpre-emphasis 0x0 will give you roughly 1–5% of pre-emphasis. This should be roughly linear alongthe 16 settings. Refer to the BCM56500 data sheet for a definition pre-emphasis.

Register offset: 0x17, blocks 0x60, 70, 80, 90, A0. Block 0x60 through 0x90 represents HG lane 0 through 3. Block0xA0 controls all four lanes simultaneously.

Note: The bit order is little-endian. Therefore, a value of 0x1 is greater than value of 0x8.

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PREEMPHASIS IDRIVER IPREDRIVER IFULLSPD ICBUF1T{0]

Table 356: TX_ACONTROL


15:12 PREEMPHASIS[0:3] R/W Pre-emphasis control [0:3]4’b1111 = max pre-emphasis4’b01114’b1011::4’b01004’b10004’b0000 = min pre-empahsis

0x0

11:8 IDRIVER[0:3] R/W Driver current [0:3]4’b1111 = max pre-emphasis4’b01114’b1011::4’b01004’b10004’b0000 = min pre-empahsis

0xD

7:4 IPREDRIVER[0:3] R/W Predriver current [0:3]

4’b1111 = max pre-emphasis4’b01114’b1011::4’b01004’b10004’b0000 = min pre-empahsis

0xD

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.

RX_STATUS

3:1 IFULLSPD R/W Reserved 0x0

0 ICBUF1T[0] R/W Reserved 0

Note: Bits in this register are reversed. For example, bit 15 represents the LSB and bit 12 represents the MSB forPREEMPHASIS.

Register description: Receiver status. Block 0xB0 through 0xE0 represents HG lane 0 through 3. Block 0xF0 reads statusfor all four lanes as a whole.

Register offset: 0x10, blocks 0xB0, 0xC0, 0xD0, 0xE0, 0xF0

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SD RESERVED RX_SEQ_DONE

RESERVED

Table 357: RX_STATUS


15 SD R/W Signal detect 0


12 RX_SEQ_DONE R/W RX sequence done 0


Table 356: TX_ACONTROL (Cont.)


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BLOCKADDRESS

Register description: Block address number

Register offset: 0x1F

Bit Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BLK_NO

Table 358: BLOCKADDRESS



7:0 BLK_NO R/W Block Number. Registers 00–0Fh and 1Fh are present on all block numbers. Assigning a value to register 0x1F will move the offset block. For example register 0x17 is the TX_ACONTROL register when assign register 0x1F = 0xA0.

0x00

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Section 15: Gigabit Port Statist ics (Counters)

OVERVIEW

This section covers the GbE port statistics counters. The BCM56500 device provides extensive support for networkmanagement in the form of counters to support the following management information base specifications:

• RMON Statistics Group (IETF RFC 2819)

• SMON MIB (IETF RFC 2613)

• SNMP Interface Group (IETF RFC 1213 & 2863)

• Ethernet-like MIB (IETF RFC 1643)

• Ethernet MIB (IEEE 802.3u)

• Bridge MIB (IETF RFC 1493)

• k = Device block (0 or 1). Block 0 represents the first 12 GbE ports, and block 1 represents the second 12 GbE ports.

• g = GbE port number (0, 1, ... , B)

GBE RECEIVE COUNTERS TABLE

Table 359: GbE Receive Counters Table

Name Address Width (bits) Description

GR64 0x00k0g000 32 Receive 64 Byte Frame Counter—incremented for each good or bad frame (includes FCS, Symbol, and Length/Type error).

GR127 0x00k0g001 32 Receive 65 to 127 Byte Frame Counter—incremented for each good or bad frame (includes FCS, Symbol, and Length/Type errors).





GRMGV 0x00k0g006 32 Receive 1519 to 1522 Byte Good VLAN Frame Counter—incremented for each good VLAN (excludes FCS errors) frame received, which is 1519 to 1522 bytes in length, inclusive (excluding framing bits, but including FCS bytes).

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GRPKT 0x00k0g00A 32 Receive Frame Counter—incremented for each frame received packet (includes bad packets, all Unicast, Broadcast, Multicast Packets, and MAC control packets).

GRBYT 0x00k0g00B 32 Receive Byte Counter—incremented by the byte count of frames received, including bad packets (excluding framing bits, but including FCS bytes).

Note: For truncated packets, the counter only countsup to MAXFR size.

GRMCA 0x00k0g00C 32 Receive Multicast Frame Counter—incremented for each multicast good frame (valid FCS, no code error and pass length field checks) of length 64 to cntMaxSize for untagged and (cntMaxSize + 4) for tagged received (excluding Broadcast frames).

GRBCA 0x00k0g00D 32 Receive Broadcast Frame Counter—incremented for each Broadcast good frame (valid FCS, no code error and pass length field checks) of length 64 to cntMaxSize for untagged and (cntMaxSize + 4) for tagged received (excluding multicast frames).

GRFCS 0x00k0g00E 32 Receive FCS Error Frame Counter—incremented for each frame received that is between 64 bytes, inclusive to cntMaxSize (cntMaxSize + 4 for VLAN tagged) bytes in length and contains a Frame Check Sequence error.

GRXCF 0x00k0g00F 32 Receive Control Frame Counter—incremented for each MAC Control frame received (PAUSE or Unsupported) of lengths 64 to cntMaxSize bytes.

GRXPF 0x00k0g010 32 Receive Pause Frame Counter—incremented for each valid MAC Pause frame received of lengths 64 to cntMaxSize bytes.

GRXUO 0x00k0g011 32 Receive Unsupported Opcode Frame Counter—incremented for each MAC Control frame received, which contains an opcode other than PAUSE of lengths 64 to cntMaxSize bytes.

GRALN 0x00k0g012 32 Receive Alignment Error Frame Counter. 10/100 mode only—incremented for each frame, which contains dribble nibble of length 64 to cntMaxSize bytes, inclusive.

Note: This counter will not increment since the interface between the PHY and the device is SGMII. This counter is only applicable when the interface is MII based.

Table 359: GbE Receive Counters Table (Cont.)


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GRFLR 0x00k0g013 32 Receive Length Out of Range Frame Counter—incremented for each good (valid FCS and no code error) frame received in which the IEEE 802.3 length field did not match the number of data bytes actually received, 46 to (cntMaxSize - 18) for untagged packets and 46 to (cntMaxSize - 18 + 4) for tagged packets. The actual data bytes received do not include DA, SA, Type/Length, and FCS fields. The counter is not incremented if the length field is not a valid IEEE 802.3 length (type/length > 0x600), such as an Ether Type value.

GRCDE 0x00k0g014 32 Receive Code Error Counter—incremented each time a valid carrier was present and at least one invalid data symbol was detected.

GRFCR 0x00k0g015 32 Receive False Carrier Counter—incremented each time a false carrier is detected during idle, as defined by RX_ER samples active and RXD is 0xE. The event is reported along with the statistics generated on the next received frame. Only one false carrier condition can be detected and logged between frames.

GROVR 0x00k0g016 32 Receive Oversized Frame Counter—incremented each time a frame is received, which exceeds cntMaxSize bytes (or cntMaxSize + 4 bytes if VLAN tagged) to MAXFR size, and contains a valid FCS and is otherwise well formed. This does not look at Range Length errors.

GRJBR 0x00k0g017 32 Receive Jabber Frame Counter—incremented for frames received, which exceeds cntMaxSize bytes (or cntMaxSize + 4 if VLAN tagged) to MAXFR size, and contains an invalid FCS or code error detected. This does not look at Range Length errors.

GRMTUE 0x00k0g018 32 Receive MTU Check Error Frame Counter—incremented for frames received, which exceeds MAXFR (Maximum Frame) in length and contains a valid or invalid FCS.

RRPKT 0x00k0g019 32 Receive RUNT Frame Counter—incremented each time a frame is received with a size between 10 to 63 bytes in length.

GRUND 0x00k0g01A 32 Receive Undersize Frame Counter—incremented each time a frame is received with a size between 10 to 63 bytes in length and contains a valid FCS. This does not look at Range Length errors.

GRFRG 0x00k0g01B 32 Receive Fragment Counter—incremented for each frame received with a size between 10 to 63 bytes in length and contains an invalid FCS or Alignment Errors. Includes integral and non-integral lengths.

GRBYT 0x00k0g01C 32 Receive Runt Byte Counter—incremented by the number of bytes received for runt packets.

Table 359: GbE Receive Counters Table (Cont.)


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GBE TRANSMIT COUNTERS TABLE

Table 360: GbE Transmit Counters Table


GT64 0x00k0g01D 32 Transmit 64 Byte Frame Counter—incremented for each good or bad frame (includes FCS, Symbol, and Length/Type error) transmitted, which is 64 bytes in length, inclusive (excluding framing bits, but including FCS bytes).

GT127 0x00k0g01E 32 Transmit 65 to 127 Byte Frame Counter—incremented for each good or bad frame (includes FCS, Symbol, and Length/Type errors) transmitted, which is 65 to 127 bytes in length, inclusive (excluding framing bits, but including FCS bytes).

GT255 0x00k0g01F 32 Transmit 128 to 255 Byte Frame Counter—incremented for each good or bad frame (includes FCS, Symbol, and Length/Type errors) transmitted, which is 128 to 255 bytes in length, inclusive (excluding framing bits, but including FCS bytes).

GT511 0x00k0g020 32 Transmit 256 to 511 Byte Frame Counter—incremented for each good or bad frame (includes FCS, Symbol, and Length/Type errors) transmitted, which is 256 to 511 bytes in length, inclusive (excluding framing bits, but including FCS bytes).



GTMGV 0x00k0g023 32 Transmit 1519 to 1522 Byte Good VLAN Frame Counter—incremented for each good VLAN frame (excludes FCS errors) transmitted, which is 1519 to 1522 bytes in length, inclusive (excluding framing bits, but including FCS bytes).


GT4095 0x00k0g025 32 Transmit 2048 to 4095 Byte Frame Counter—incremented for each good or bad frame (includes FCS, Symbol, and Length/Type errors) transmitted which is 2048 to 4095 bytes in length, inclusive (excluding framing bits but including FCS bytes).

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GTPKT 0x00k0g027 32 Transmit Frame Counter—incremented for each frame transmitted packet (includes bad packets, all unicast, broadcast, multicast, and MAC control packets).

GTMCA 0x00k0g028 32 Transmit Multicast Frame Counter—incremented for each valid Multicast frame transmitted (valid FCS) of lengths 64 to cntMaxSize for untagged and cntMaxSize + 4 for tagged (excluding Broadcast frames).

GTBCA 0x00k0g029 32 Transmit Broadcast Frame Counter—incremented for each valid Broadcast frame transmitted (valid FCS) of lengths 64 to cntMaxSize for untagged and cntMaxSize + 4 for tagged (excluding Multicast frames).

GTXPF 0x00k0g02A 32 Transmit Pause Control Frame Counter—incremented for each valid PAUSE MAC Control frame (valid FCS) transmitted of lengths 64 to cntMaxSize.

GTJBR 0x00k0g02B 32 Transmit Jabber Counter—incremented for each frame transmitted, which exceeds cntMaxSize (or cntMaxSize + 4 if VLAN tagged) in length and contains an invalid FCS.

GTFCS 0x00k0g02C 32 Transmit FCS Error Counter—incremented for each frame transmitted that is between 64 byte inclusive to cntMaxSize (cntMaxSize + 4 for VLAN tagged) bytes in length and contains a Frame Check Sequence Error.

Note: This counter is not incremented if a cell erroris detected.

GTXCF 0x00k0g02D 32 Transmit Control Frame Counter—incremented for each Control frame transmitted (PAUSE or Unsupported) of lengths 64 to cntMaxSize bytes.

GTOVR 0x00k0g02E 32 Transmit Oversize Packet Counter—incremented for each frame transmitted which exceeds cntMaxSize bytes (or cntMaxSize + 4 bytes if VLAN tagged) and contains a valid FCS.

GTDFR 0x00k0g02F 32 Transmit Single Deferral Frame Counter. 10/100 mode only—incremented for each frame, which was deferred on its first transmission attempt, and did not experience any subsequent collisions during transmission.

GTEDF 0x00k0g030 32 Transmit Multiple Deferral Frame Counter. 10/100 mode only—incremented for frames aborted, which were deferred for an excessive period of time and whose transmission was delayed due to busy medium, and the packet is waiting for > 2 * max_packet_time.

GTSCL 0x00k0g031 32 Transmit Single Collision Frame Counter. 10/100 mode only—incremented for each frame transmitted, which experienced exactly one collision during transmission.

Table 360: GbE Transmit Counters Table (Cont.)


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GTMCL 0x00k0g032 32 Transmit Multiple Collision Frame Counter. 10/100 mode only—incremented for each frame transmitted that experienced from 2–15 collisions (including any late collisions) during transmission.

GTLCL 0x00k0g033 32 Transmit Late Collision Frame Counter. 10/100 mode only—incremented for each frame transmitted, which experienced a late collision more than 512 bit-times during a transmission attempt.

GTXCL 0x00k0g034 32 Transmit Excessive Collision Frame Counter. 10/100 mode only—incremented for each frame that experienced 16 collisions during transmission and was aborted. This register should only be written during initialization.

GTFRG 0x00k0g035 32 Transmit Fragment Counter—incremented for each frame transmitted, which is less than 64 bytes in length and contains an invalid FCS, includes integral and non-integral lengths.

GTNCL 0x00k0g036 32 Transmit Total Collision Counter. 10/100 mode only—incremented by the number of collisions experienced during the transmission of a frame as defined as the simultaneous presence of signals on the DO and RD circuits (that is, transmitting and receiving at the same time).

GTBYT 0x00k0g037 32 Transmit Byte Counter—incremented by the number of bytes that were put on the wire, including fragments of frames that were involved with collisions. This count does not include the preamble/SFD or jam bytes.

Table 360: GbE Transmit Counters Table (Cont.)


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Section 16: XG Port Statistics (Counters)

HIGIG+™ PORT STATISTICS COUNTERS

This section covers the HiGig+ port statistics counters with the following address ranges 0x00P00000 to 0x00P00102.

• 0x00 indicates the base address.

• P indicates block numbers 2, 3, 4, and 5. Block 2 indicates HiGig+ port 0 and Block 5 indicates HiGig+ port 3.

• 00000 are the address space.

HIGIG+ TRANSMIT COUNTERS TABLE

Table 361: HiGig+ Transmit Counters Table


ITPKT 0x00p0000C 36 Transmit Packet Counter—the number of transmitted packets, including all unicast, broadcast and multicast packets, but not bad ones (for example, FCS error).

ITXPF 0x00p0000D 36 Transmit pause packet counter—the number of PAUSE control packets transmitted.

ITFCS 0x00p0000E 36 Transmit FCS(CRC) error counter—the number of transmitted packets: a) where 64 <= size <= txMaxSize bytes, b) containing an invalid CRC, and c) CRCMode == CRCKEEP.

ITMCA 0x00p0000F 36 Transmit multicast packet counter—the number of transmitted multicast packets, excluding broadcast packets.

ITBCA 0x00p00010 36 Transmit broadcast packet counter—the number of transmitted broadcast packets, excluding multicast packets.

ITFRG 0x00p00011 36 Transmit fragment counter—the number of transmitted packets where the size (with header or preamble) < 72 bytes.

ITOVR 0x00p00012 36 Transmit oversize packet counter—the number of transmitted packets where the size > txMaxSize bytes.

IT64 0x00p00013 36 Transmit 64-byte packet counter—the number of transmitted packets where the size = 64 bytes. Includes all packets, good and bad. Not incremented with ITMAX.

IT127 0x00p00014 36 Transmit 65-127 byte packet counter—the number of transmitted packets where 65 <= size <= 127 bytes. Includes all packets, good and bad. Not incremented with ITMAX.

IT255 0x00p00015 36 Transmit 128-255 Byte Packet Counter—the number of transmitted packets where 128 <= size <= 255 bytes. Includes all packets, good and bad. Not incremented with ITMAX.

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IT4095 0x00p0001A 36 Transmit 2048-4095 Byte Packet Counter—the number of transmitted packets where 2048 <= size <= 4095 bytes. Includes all packets, good and bad. Not incremented with ITMAX.

IT9216 0x00p0001B 36 Transmit 4096-9216 Byte Packet Counter—the number of transmitted packets where 4096 <= size <= 9216 bytes. Includes all packets, good and bad. Not incremented with ITMAX.

IT16383 0x00p0001C 36 Transmit 9217-16383 Byte Packet Counter—the number of transmitted packets where 9217 <= size <= 16383 bytes. Includes all packets, good and bad. Not incremented with ITMAX.

ITMAX 0x00p0001D 36 Transmit Max Size Packet Counter—the number of transmitted packets where size = MAC_TxMaxSz. Includes all packets, good and bad.

ITUFL 0x00p0001E 36 Transmit Underflow Counter—the number of transmitted packets, which encountered a MAC under run (TX Sync FIFO runs out of data before the end of a packet).

ITERR 0x00p0001F 36 Transmit Error Packet Counter—the number of transmitted packets with an error (if any word of the packet had the FTXError bit set).

ITBYT 0x00p00020 42 Transmit Byte Counter—the number of bytes received for transmission.

Table 361: HiGig+ Transmit Counters Table (Cont.)


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HIGIG+ RECEIVE COUNTERS TABLE

Table 362: HiGig+ Receive Counters Table


IR64 0x00p00026 36 Receive 64 Byte Packet Counter—the number of packets received where size = 64 bytes. Includes all packets, good and bad. Not incremented with IRMAX.

IR127 0x00p00027 36 Receive 65-127 Byte Packet Counter—the number of packets received where 65 <= size <= 127 bytes. Includes all packets, good and bad. Not incremented with IRMAX.



IR1023 0x00p0002A 36 Receive 512-1023 Byte Packet Counter—the number of packets received where 512 <= size <= 1023 bytes. Includes all packets, good and bad. Not incremented with IRMAX.

IR1518 0x00p0002B 36 Receive 1024-1518 Byte Packet Counter—the number of packets received where 1024 <= size <= 1518 bytes. Includes all packets, good and bad. Not incremented with IRMAX.

IR2047 0x00p0002C 36 Receive 1519-2047 Byte Packet Counter—the number of packets received where 1519 <= size <= 2047 bytes. Includes all packets, good and bad. Not incremented with IRMAX.

IR4095 0x00p0002D 36 Receive 2048-4095 Byte Packet Counter—the number of packets received where 2048 <= size <= 4095 bytes. Includes all packets, good and bad. Not incremented with IRMAX.

IR9216 0x00p0002E 36 Receive 4096-9216 Byte Packet Counter—the number of packets received where 4096 <= size <= 9216 bytes. Includes all packets, good and bad. Not incremented with IRMAX.

IR16383 0x00p0002F 36 Receive 9217-16383 Byte Packet Counter—the number of packets received where 9217 <= size <= 16383 bytes. Includes all packets, good and bad. Not incremented with IRMAX.

IRMAX 0x00p00030 36 Receive Max Size Packet Counter—the number of packets received where size = rxMaxSize bytes. Includes all packets, good and bad.

IRPKT 0x00p00031 36 Receive Packet Counter—the number of packets received where size >= 64 bytes. Includes bad packets, all unicast, broadcast, multicast and MAC control packets.

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IRFCS 0x00p00032 36 Receive FCS (CRC) Error Packet Counter—the number of packets received where:a) 64 <= size <= rxMaxSize bytes, and b) contain an invalid CRC.

IRMCA 0x00p00033 36 Receive multicast packet counter—the number of multicast packets received where 64 <= size <= rxMaxSize bytes. Excludes broadcast and MAC control packets.

IRBCA 0x00p00034 36 Receive broadcast packet counter—the number of broadcast packets received where 64 <= size <= rxMaxSize bytes. Excludes multicast and MAC control packets.

IRXCF 0x00p00035 36 Receive control packet counter—the number of MAC control packets received where: a) size >= 64 bytes, b) DA!=0x0180C@000001 or DA! = MACSA, and c) PROTOCOL TYPE == 0x8808.

IRXPF 0x00p00036 36 Receive PAUSE packet counter—the number of PAUSE control packets received where: a) size >= 64 bytes, b) DA = 0x0180C@000001 or DA = MACSA, c) PROTOCOL TYPE = 0x8808, and d) opcode = 1.

IRXUO 0x00p00037 36 Receive PAUSE packet counter—the number of MAC Control packets received where: a) size >= 64 bytes, b) DA = 0x0180C@000001 or DA = MACSA, c) PROTOCOL TYPE = 0x8808, and d) opcode! = 1.

IRJBR 0x00p00038 36 Receive jabber packer counter—the number of packets received where: a) size > rxMaxSize bytes and b) contain an invalid CRC.

IROVR 0x00p00039 36 Receive oversize packet counter—the number of packets received where: a) size > rxMaxSize bytes, b) contain a valid CRC and c) contains no other errors.

IRFLR 0x00p0003A 36 Receive length out-of-range packet counter—the number of packets received where:a) contain a valid CRC, b) size >= 64 bytes and c) data length did not match the IEEE 802.3 LENGTH/TYPE field.

IRMEG 0x00p0003B 36 Receive MTU size check failed good packet counter—the number of packets received that contain a valid CRC and size > rxMaxSize.

IRMEB 0x00p0003C 36 Receive MTU size check failed bad packet counter—the number of packets received that contain an invalid CRC and size > rxMaxSize.

Table 362: HiGig+ Receive Counters Table (Cont.)


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IRBYT 0x00p0003D 42 Receive byte counter—the number of bytes from packets received, including bad packets. The framing bits are not counted but CRC is.

IRUND 0x00p0003E 42 Received undersize packet counter—the number of packets received where:a) size < 64 bytes,b) contains a valid CRC and c) contains no other errors.

IRFRG 0x00p0003F 42 Receive fragment counter—the number of packets received where: a) 9 <= size <= 63 bytes and b) contain an invalid CRC.

IRERBYT 0x00p00040 42 Receive error byte counter—the number of packets received with the /ERROR/ control symbol in the XGMII interface.

IRERPKT 0x00p00041 42 Received framing error counter—the number of packets received with any control symbol, other than /ERROR/, on the XGMII interface.

IRJUNK 0x00p00042 42 Received inter-packet junk counter—the number of inter-packet gaps between the control symbol /START/ and any other than /IDLE/ on the XGMII interface. Includes packets such that 1 <= size <= 8 bytes.

XTPSE 0x00p00100 32 Transmit Pause control frame counter under XPORT pausing mode. Incremented for each PAUSE packet transmitted when XPORT pausing is enabled.

XTHOL 0x00p00101 32 Transmit end-to-end HOL packet counter. Incremented for each E2E HOL packet transmitted.

XTIBP 0x00p00102 32 Transmit end-to-end IBP packet counter. Incremented for each E2E IBP packet transmitted.

Table 362: HiGig+ Receive Counters Table (Cont.)


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Section 17: Miscel laneous CountersThis section covers:

• L3 Packet counters

• General Packet counters

• MMU Packet counters

L3 PACKET COUNTERS

Table 363 provides the information for the L3 Packet counters. Each port has its own counter. The counter’s addresses arelocated in 0x0E7ppXXX, where:

• 0x0E7 is the base address.

• pp indicates the port number, ranging from 0 to 27. Port 0 is the first GbE port, port 23 is the last GbE port, port 24 is thefirst HiGig+ port, and port 27 is the last HiGig+ port.

• XXX indicates the address space.

Table 363: L3 Packet Counters


RIPD4 0x0E7pp000 26 Receive IPv4 L3 Discard Packet Counter.Incremented for each packet addressed to the L3 interface, which are discarded due to: • L3 bit is not set.

• L3 packet is not found in the table.

• TTL = 0.

• IP checksum is invalid, etc.

RIPC4 0x0E7pp001 26 Receive IPv4 L3 Unicast Frame Counter. Incremented for each unicast packet received for L3 switching that are not sent to the CPU's software stack for processing.

RIPHE4 0x0E7pp002 26 Receive IPv4 L3 IP Header Error Packet Counter. Incremented for each IP packet addressed to the L3 interface, but discarded due to errors in their IP headers, including bad checksum and DIP = 0. Only packets that are not sent to the CPU are counted.

IMRP4 0x0E7pp003 26 Receive IPv4 L3 routed multicast packets. Incremented for each IP packet addressed to the L3 interface that is routed.

RIPD6 0x0E7pp004 26 Receive IPv6 L3 Discard Packet Counter. Incremented for each packet addressed to the L3 interface, which are discarded due to: • L3 bit is not set.

• L3 packet is not found in the table.

• TTL = 0.

• IP checksum is invalid, etc.

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RIPC6 0x0E7pp005 26 Receive IPv6 L3 Unicast Frame Counter. Incremented for each unicast packet received for L3 switching that are not sent to the CPU's software stack for processing.

RIPHE6 0x0E7pp006 26 Receive IPv6 L3 IP Header Error Packet Counter. Incremented for each IP packet addressed to the L3 interface, but discarded due to errors in their IP headers, including bad checksum and DIP = 0. Only packets that are not sent to the CPU are counted.

IMRP6 0x0E7pp007 26 Receive IPv6 L3 routed multicast packets. Incremented for each IPv6 packet addressed to the L3 interface that is routed.

Table 363: L3 Packet Counters (Cont.)


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GENERAL PACKET COUNTERS

The General Packet counters are applied to general packets that can be either L2 or L3 type. Each port has its own counter.The counter’s addresses are located in 0x0E7ppXXX:

• 0x0E7 is the base address.

• pp indicates the port number, ranging from 0 to 27. Port 0 is the first GbE port, port 23 is the last GbE port, port 24 is thefirst HiGig+ port, and port 27 is the last HiGig+ port.

• XXX indicates the address space.

Table 364: General Packet Counters


RDISC 0x0E7pp008 26 Receive Discard Packet CounterIncremented for each packet that is discarded for GBP full or backpressure discard.

RUC 0x0E7pp009 26 Receive Unicast CounterIncremented for each unicast packet received.

RPORTD 0x0E7pp00A 26 Port In Discard CounterIncremented when the spanning tree state is not in the forwarding state.

RDBGC0 0x0E7pp00B 26 Receive debug counter #0The RDBGC0_SELECT register is programmed to select which triggers increment this counter.

RDBGC1 0x0E7pp00C 26 Receive debug counter #1

The RDBGC1_SELECT register is programmed to select which triggers increment this counter.

RDBGC2 0x0E7pp00D 26 Receive debug counter #2


RDBGC3 0x0E7pp00E 26 Receive debug counter #3The RDBGC3_SELECT register is programmed to select which triggers increment this counter.

RDBGC4 0x0E7pp00F 26 Receive debug counter #4The RDBGC4_SELECT register is programmed to select which triggers increment this counter.

RDBGC5 0x0E7pp010 26 Receive debug counter #5


RDBGC6 0x0E7pp011 26 Receive debug counter #6The RDBGC6_SELECT register is programmed to select which triggers increment this counter.

RDBGC7 0x0E7pp012 26 Receive debug counter #7The RDBGC7_SELECT register is programmed to select which triggers increment this counter.

RDBGC8 0x0E7pp013 26 Receive debug counter #8


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HOLD 0x0E7pp014 26 Egress per port HOL Drop CounterIncremented for each packet drop due to Head Of Line blocking per egress port.

TDBGC0 0x0A9pp000 26 Transmit debug counter #0

The TDBGC0_SELECT register is programmed to select which triggers increment this counter.

TDBGC1 0x0A9pp001 26 Transmit debug counter #1The TDBGC1_SELECT register is programmed to select which triggers increment this counter.












TDBGC10 0x0A9pp00A 26 Transmit debug counter #10The TDBGC10_SELECT register is programmed to select which triggers increment this counter.

TDBGC11 0x0A9pp00B 26 Transmit debug counter #11The TDBGC11_SELECT register is programmed to select which triggers increment this counter.

TPCE 0x0A9pp00C 26 Egress Purge and Cell Error Drop Counter.

Incremented for each Packet drop due to a purge or cell error per egress port.Note: This counter will increment when the packet size is greater than 256 bytes.

Table 364: General Packet Counters (Cont.)


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MMU PACKET COUNTERS

The MMU Packet Counters are applied to packets that reside in the MMU. Each port has its own counter. The counter’saddresses are located in 0x006ppXXX:

• 0x006 is the base address.

• pp indicates port number, ranging from 0 to 27. Port 0 is the first GbE port, port 23 is the last GbE port, port 24 is thefirst HiGig+ port, and port 27 is the last HiGig+ port.

• XXX indicates address space.

Table 365: MMU Packet Counters


IBPPKTCOUNT 0x006pp001 14 Ingress packet count for all local ingress ports. The number of packets stored per ingress port in XQ memories.

IBPCELLCOUNT 0x006pp004 14 Ingress cell count for all local ingress ports. The number of cells stored per ingress port in CBP Memory.

E2EIBPPKTCOUNT 0x006pp006 14 Ingress packet count for all remote ports in remote module. The number of packets stored per ingress port.

E2EIBPCELLCOUNT 0x006pp009 14 Ingress cell count for all remote ports in remote module. The number of cells stored per ingress port.

COSPKTCOUNT 0x006pp028 11 This is a register array (offset in lower bits) indexed by CoS. For example, CoS0 locates at 0x006pp028 and CoS7 locates at 0x006pp02F. The Packet Count for egress port packet for CoS n: This is the current number of entries in XQ of CoS n for this egress port. The number of packets per egress port for CoS n.

COSLCCOUNT 0x006pp038 14 This is a register array (offset in lower bits) indexed by CoS. For example, CoS0 locates at 0x006pp038 and CoS7 locates at 0x006pp03F. The Cell Count for egress port packet of CoS n: The number of cells per egress port of CoS n.

DYNCELLCOUNT 0x006pp041 14 Dynamic Cell Count for each egress port.

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EGRDROPPKTCOUNT 0x006pp047 32 This is the egress port based counter and it counts the number of whole packets dropped by MMU and does not pass to egress port. MMU counts packets only if the port bitmap of the received packet is nonzero and not purged The reasons for MMU to drop packet:

• CBP memory full• IBP Cell count over IBPDISCARDSETLIMIT• HOL Cell count over

HOLCOSxCELLSETLIMIT• HOL Packet count over

HOLCOSxPKTSETLIMIT

• HOL Packet count over CNGCOSxPKTSETLIMIT0 and Packet with CNG[1:0] = 2’b01

• HOL Packet count over CNGCOSxPKTSETLIMIT1 and Packet with CNG[1:0] = 2’b11.

• Single cell packet (64–128 bytes) purged by Ingress Pipeline

For packets that are just dropped when some cells of the packet have already been admitted by MMU, this packet is not counted by MMU EGRDROPPKTCOUNT.

CNGDROPCOUNT0 0x006pp048 32 Dropped Packet Count accounts for congestion color red dropped packets for each egress port after its HOLPktCount over CNG0 Packet Set Limit. This is per-port-based counter collecting all packets for this port on different CoS. The number of packets per egress port.

CNGDROPCOUNT1 0x006pp049 32 Dropped Packet Count accounts for congestion color red dropped packets for each egress port after its HOLPktCount over CNG1 Packet Set Limit. This is per port-based counter collecting all packets for this port on different CoS. The number of packets per egress port.

IPMCREPLICATIONCOUNT 0x006pp04A 13 Replication Counter for a specified CoS of each egress port how many packets are doing IPMC replication. The Counter counts any replicated packet for the specified CoS on that egress port. The counter keeps the total number of whole replication if it is over its replication limit. If the limit is not reached for any IPMC replication, the counter resets at the end of replication. For the case of replication count over 8191, the counter will not overflow, but stays as 8191.

Table 365: MMU Packet Counters (Cont.)


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EGRTXPKTCTR[7:0]EGRTXPKTCTR0

0x00680028 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR0 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG0.


0x00680029 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR1 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG1.


0x0068002A 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR2 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG2.


0x0068002B 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR3 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG3.


0x0068002C 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR4 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG4.


0x0068002D 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR5 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG5.


0x0068002E 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR6 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG6.



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0x0068002F 32 Transmit Packet CounterWhen TXPKTCOUNT_SEL in EGRTXPKTCTR7 is selected, this transmit packet counter counts all the packets to be transmitted to a pre-configured egress port with pre-configurable CoS on EGRTXPKTCTRCONFIG7.



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Section 18: Switching Memories

MEMORY MAP

Table 366: Memory Map

Name Address Block Entries Description

L2_ENTRY 0x06700000 IPIPE 16384 Combined hardware-managed L2 entry table—includes L2_ENTRY, L2_HITDA, and L2_HITSA

L2_ENTRY_ONLY 0x06710000 IPIPE 16384 Hardware-managed L2_ENTRY table only—does not include L2_HITSA or L2_HITDA

L2_HITDA_ONLY 0x06720000 IPIPE 2048 Hardware-managed L2_HITDA_ONLY table—just the DA hit bits

L2_HITSA_ONLY 0x06730000 IPIPE 2048 Hardware-managed L2_HITSA_ONLY table—just the SA hit bits

L2_USER_ENTRY 0x06740000 IPIPE 128 Combined L2_ENTRY TCAM/Data RAM for guaranteed L2 entries and BPDUs

L2_USER_ENTRY_ONLY 0x06750000 IPIPE 128 TCAM for guaranteed L2 entries and BPDUs

L2_USER_ENTRY_DATA_ONLY 0x06760000 IPIPE 128 Data SRAM for L2_USER_ENTRY TCAM

L2_MOD_FIFO 0x06770000 IPIPE 16 FIFO for operations that MODify the L2_ENTRY table

L2MC 0x07700000 IPIPE 1024 L2 multicast table

PORT 0x01700000 IPIPE 29 Port table

IPORT_TABLE 0x01800000 IPIPE_HI 29 Port table

NONUCAST_TRUNK_BLOCK_MASK 0x0E760000 IPIPE 16 Multicast and broadcast trunk block mask table

PORT_TRUNK_EGRESS 0x0E710000 IPIPE 128 Trunk egress block mask table

EGRESS_MASK 0x0E700000 IPIPE 2048 Egress mask table

SRC_MODID_BLOCK 0x0E7A0000 IPIPE 320 Source MODID-based blocking mask table

ALTERNATE_EMIRROR_BITMAP 0x0E7B0000 IPIPE 64 Alternate egress mirror MTP bitmap table

PORT_MAC_BLOCK 0x0E740000 IPIPE 32 MAC block port bitmap table

VLAN_PROTOCOL 0x04700000 IPIPE 16 Holds data for protocol-based VLAN substitution—just the VLAN_PROTOCOL RAM

VLAN_PROTOCOL_DATA 0x04710000 IPIPE 464 Holds data for rrotocol-based VLAN substitution

VLAN_SUBNET 0x04720000 IPIPE 256 Composite table for IP subnet-based VLAN substitution

VLAN_SUBNET_ONLY 0x04730000 IPIPE 256 TCAM for IP subnet-based VLAN substitution

VLAN_SUBNET_DATA_ONLY 0x04740000 IPIPE 256 Holds data for IP subnet-based VLAN substitution

VLAN_MAC 0x04750000 IPIPE 1024 Holds key and data for MAC-based VLAN substitution

VLAN_XLATE 0x04760000 IPIPE 768 Composite table for VLAN trans of tagged packets

VLAN_XLATE_ONLY 0x04770000 IPIPE 768 BCAM for VLAN trans of tagged packets

VLAN_XLATE_DATA_ONLY 0x04780000 IPIPE 768 Data SRAM for VLAN_XLATE BCAM.

VLAN 0x05700000 IPIPE 4096 Contains controls associated with the 4K VLANs

VLAN_STG 0x05710000 IPIPE 256 Spanning tree group state table

EGR_VLAN 0x04910000 EPIPE 4096 Vlan membership table for Egress

EGR_VLAN_STG 0x04920000 EPIPE 256 Egress spanning tree stage table

EGR_VLAN_XLATE 0x05910000 EPIPE 768 Egress VLAN translate CAM-RAM combined view

EGR_VLAN_XLATE_ONLY 0x05920000 EPIPE 768 Egress VLAN translate CAM only

EGR_VLAN_XLATE_DATA_ONLY 0x05930000 EPIPE 768 Egress VLAN translate data table only

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TRUNK_GROUP 0x0E720000 IPIPE 128 Trunk group table

TRUNK_BITMAP 0x0E730000 IPIPE 128 Trunk bitmap table

MODPORT_MAP 0x0E750000 IPIPE 64 Module port mapping table

DSCP_TABLE 0x08700000 IPIPE 64 Diff Serv Code Point table

EGR_DSCP_TABLE 0x05970000 EPIPE 32 Egress DSCP table to select the new DSCP for outer tunnel header packets

EGR_DSCP_ECN_MAP 0x05980000 EPIPE 64 Egress DSCP table to select the new DSCP for outer tunnel header packets

EGR_IP_TUNNEL 0x05940000 EPIPE 128 Egress IP tunnel table—used to make new tunnel header

L3_TUNNEL 0x02700000 IPIPE 128 L3 tunnel table TCAM

L3_ENTRY_ONLY 0x08720000 IPIPE 8192 L3 routing table view—no hit bits

L3_ENTRY_IPV4_UNICAST 0x08730000 IPIPE 8192 L3 routing table IPV4 unicast view

L3_ENTRY_IPV4_MULTICAST 0x08740000 IPIPE 8192 L3 routing table IPV4 multicast view

L3_ENTRY_IPV6_UNICAST 0x08750000 IPIPE 4096 L3 routing table IPV6 unicast view

L3_ENTRY_IPV6_MULTICAST 0x08760000 IPIPE 2048 L3 routing table IPV6 multicast view

L3_ENTRY_VALID_ONLY 0x08770000 IPIPE 1024 L3 routing table valid-bits-only view—organized into buckets.

L3_IPMC 0x09700000 IPIPE 1024 L3 IPMC table

L3_DEFIP 0x0A700000 IPIPE 6144 L3 default IP route (LPM) TCAM view with data and hit bits

L3_DEFIP_ONLY 0x0A710000 IPIPE 6144 L3 default IP route (LPM) TCAM only view

L3_DEFIP_DATA_ONLY 0x0A720000 IPIPE 6144 L3 default IP route (LPM) Data SRAM for the L3_DEFIP TCAM

L3_ENTRY_HIT_ONLY 0x0B710000 IPIPE 1024 L3 hit bit table

L3_DEFIP_HIT_ONLY 0x0B720000 IPIPE 6144 L3_DEFIP hit bit table

L3_ECMP 0x0D700000 IPIPE 2048 L3 equal cost multipath table

EGR_L3_NEXT_HOP 0x03910000 EPIPE 8192 Next hop table

EGR_L3_INTF 0x03920000 EPIPE 4096 L3 Interface table

ING_L3_NEXT_HOP 0x0D710000 IPIPE 8192 Reduced version of L3_NEXT_HOP table—used to provide just mod and port/TGID

IPV6_PROXY_ENABLE 0x02730000 IPIPE 64 IPv6 proxy lookup enable

LPORT 0x02740000 IPIPE 29 LPort Table

IPMC_GROUP0 0x0A660000 MMU 1024 IPMC VLAN group table 0



IPMC_GROUP3 0x0A66C000 MMU 1024 IPMC VLAN group table 3




Table 366: Memory Map (Cont.)


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MEMORY TABLES

L2_ENTRY TABLE–L2X

IPMC_GROUP7 0x0A67C000 MMU 1024 IPMC VLAN group table 7

IPMC_VLAN 0x0A680000 MMU 2048 IPMC VLAN LSB bitmap table RAM

IM_MTP_INDEX 0x0E780000 IPIPE 4 Ingress mirror to port table

EM_MTP_INDEX 0x0E790000 IPIPE 4 Egress mirror to port table

EGR_IM_MTP_INDEX 0x05950000 EPIPE 32 Mirror to Port table to be used for IM tagged packets.

EGR_EM_MTP_INDEX 0x05960000 EPIPE 32 Mirror to Port table to be used for EM tagged packets.

SOURCE_TRUNK_MAP 0x02710000 IPIPE 2048 Source Trunk Map Table

E2E_HOL_STATUS 0x0E770000 IPIPE 64 Remote Module End-to-End HOL Status Table

BSAFE_CMD_DATA_IN 0x00B10000 BSAFE 256 Command Data Out register

BSAFE_CMD_DATA_OUT 0x00B20000 BSAFE 256 Command Data Out register

UDF_OFFSET 0x02720000 IPIPE 96 FP UDF offset table

FP_PORT_FIELD_SEL 0x0B700000 IPIPE 29 Field Select value for each slice in the FP

IFP_PORT_FIELD_SEL 0x0B800000 IPIPE_HI 29 Field Select value for each slice in the FP

FP_RANGE_CHECK 0x0C700000 IPIPE 16 Range Check values for FP

FP_TCAM 0x0C720000 IPIPE 2048 TCAM for FP

FP_TCAM_PLUS_POLICY 0x0C740000 IPIPE 2048 TCAM and Policy Table view for FP

FP_POLICY_TABLE 0x0C750000 IPIPE 2048 Policy table for determining actions in the FP

FP_METER_TABLE 0x0C760000 IPIPE 2048 Meter table structures for the FP

FP_COUNTER_TABLE 0x0C770000 IPIPE 2048 Counter table for the FP

Description: Combined hardware-managed L2 entry table. Includes L2_ENTRY, L2_HITDA, and L2_HITSA.

This table and the three tables it includes are hashed tables. To manipulate and look up entries inthe table, please use S-channel Message OPCODES L2_INS, L2_DEL and FB_L2_LKUP.Bits 67– 78 designate the destination of the packet. Under different conditions these bits will servedifferent purposes. When the destination is a trunk port, the bits will represent TGID_LO, T, TGID_HI,and REMOTE_TRUNK. When the destination is an L2 multicast group, L2MC_PTR will be used.Finally, when the destination is a single port, TGID_PORT and MODULE_ID will be used.

Minimum index: 0

Maximum index: 16383

Address: 0x06700000

Table 366: Memory Map (Cont.)


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Table 367: L2_ENTRY Table–L2X

Bit(s) Name Description

92 HITSA Source hit update bitThis bit is set if there is a match with the source address. It is used in hardware aging mechanism. If this bit is not set for AGE TIME duration, then this entry is purged by the aging process.

91 HITDA Destination hit update bit

This bit is set if there is a match with the destination address. It is used in aging mechanism. If this bit is not set for AGE TIME duration, then this entry is purged out by the aging process.

90 EVEN_PARITY Even parity for the L2_ENTRY RAM fields

89 VALID Indicates that the entry is valid

88 MIRROR Mirror bit

When set to 1, enables packet to be mirrored based on MAC address. Requires similar programming to egress mirroring.

87 RPE Remap Priority Enable bit0 = Do not use the IEEE 802.1p priority from L2_ENTRY.PRI. Recommended setting when the priority is to be obtained from the VLAN tables or the PORT table for untagged packets.1 = Use the IEEE 802.1p priority from the l2_ENTRY.PRI field. This overwrites any priority obtained from the VLAN tables or the default priority from the PORT table. This is applicable for untagged packets and for tagged packets when PORT.MAP_TAG_PKT_PRIORITY = 1.

86 STATIC_BIT Indicates entry is software-programmed and static. Entry cannot be purged by hardware aging.

85 RESERVED Reserved

84:80 MAC_BLOCK_INDEX MAC block indexThis field indicates the index into the PORT_MAC_BLOCK table.

79 L3 Identifies this entry as the result of L3 interface configuration. The MAC address in this entry is an L3 interface MAC address; any packet addressed to this MAC address needs to be routed.

78:73 MODULE_ID Module ID

78 REMOTE_TRUNK Remote Trunk bit indicates HiGig+ packet with remote MODID. This bit is only effective when the address is learned on a trunk port.

76:67 L2MC_PTR L2MC pointer (overlay)This 10-bit value is the direct index into the L2MC table when the destination of an L2 packet is a multicast address.

74:73 TGID_HI Trunk group ID high bits (overlay)

72:67 TGID_PORT Port identifier

72 T Trunk bit (overlay)Indicates associated MAC address was learned on a trunk port.

71:67 TGID_LO Trunk group ID, low bits (overlay)Trunk group ID identifies the trunk group to which the port belongs.

66 SCP Source CoS priority

If this bit is set in the matched source entry, then source CoS has priority over destination CoS.

65 SRC_DISCARD Source discardThis bit identifies whether the packets should be discarded based on source address.

1 = Discard on source

64 DST_DISCARD Destination discardThis bit identifies whether the packets should be discarded based on destination address.

1 = Discard on destination

63 CPU CPU bitSends packet to the CPU when set. Uses CPU_CONTROL_2.CPU_DEFAULT_PRIORITY for internal CoS.

62:60 PRI PriorityIdentifies the priority of this packet. Used when L2_ENTRY.PRE = 1.

59:48 VLAN_ID VLAN ID

47:0 MAC_ADDR MAC address

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L2_ENTRY_ONLY TABLE

Description: Hardware-managed L2_ENTRY table only. Does not include L2_HITSA or L2_HITDA.

Minimum index: 0

Maximum index: 16383

Address: 0x06710000

Table 368: L2_ENTRY_ONLY


92 HITSA Source hit update bitThis bit is set if there is a match with the source address. It is used in hardware aging mechanism. If this bit is not set for AGE TIME duration, then this entry is purged by the aging process.

91 HITDA Destination hit update bitThis bit is set if there is a match with destination address. It is used in aging mechanism. If this bit is not set for AGE TIME duration, then this entry is purged out by the aging process.

90 ODD_PARITY Odd parity for the L2_ENTRY RAM fields


88 MIRROR Mirror bitWhen set to 1, enables packet to be mirrored based on MAC address. Requires similar programming to egress mirroring.

87 RPE Remap Priority Enable bit

0 = Do not use the IEEE 802.1p priority from L2_ENTRY.PRI. Recommended setting when the priority is to be obtained from the VLAN tables or the PORT table for untagged packets.1 = Use the IEEE 802.1p priority from the L2_ENTRY.PRI field. This overwrites any priority obtained from the VLAN tables or the default priority from the PORT table. This is applicable for untagged packets and for tagged packets when PORT.MAP_TAG_PKT_PRIORITY = 1.

86 STATIC_BIT Indicates entry is software-programmed and static. Entry cannot be purged by hardware aging.


84:80 MAC_BLOCK_INDEX MAC block index

79 L3 Indicates an L3 entry


78 REMOTE_TRUNK Remote Trunk bit indicates HiGig+ packet with remote MODID

76:67 L2MC_PTR L2MC pointer (overlay)This 10-bit value is the direct index into the L2MC table when the destination of a L2 packet is a multicast address.

74:73 TGID_HI Trunk group ID high bits (overlay)

72:67 TGID_PORT Port identifier

72 T Trunk bit overlayIndicates associated MAC address was learned on a trunk port.

71:67 TGID_LO Trunk group ID, low bits (overlay)

Trunk group ID identifies the trunk group which the port belongs.

66 SCP SCP bit

65 SRC_DISCARD Source discard

This bit identifies whether the packets should be discarded based on source address.1 = Discard on source

64 DST_DISCARD Destination discard

This bit identifies whether the packets should be discarded based on destination address.1 = Discard on destination

63 CPU CPU bit

Uses CPU_CONTROL_2.CPU_DEFAULT_PRIORITY for internal CoS.

62:60 PRI PriorityIdentifies the priority of this packet. Used when L2_ENTRY.RPE = 1.

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Table 368: L2_ENTRY_ONLY (Cont.)


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L2_HITDA_ONLY TABLE

L2_HITSA_ONLY TABLE

Description: Hardware-managed L2_HITDA_ONLY table. Just the DA hit bits.

Minimum index: 0

Maximum index: 2047

Address: 0x06720000

Table 369: L2_HITDA_ONLY


7 HITDA_7 Hit bit set on destination MAC address hits








Description: Hardware-managed L2_HITSA_ONLY table. Just the SA hit bits.

Minimum index: 0

Maximum index: 2047

Address: 0x06730000

Table 370: L2_HITSA_ONLY


7 HITSA_7 Hit bit set on source MAC address hits








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L2_USER_ENTRY TABLE

Description: Combined L2_ENTRY TCAM/Data RAM for guaranteed L2 entries and BPDUs

Minimum index: 0

Maximum index: 127

Address: 0x06740000

Note: L2_USER_ENTRY table entries must be programmed by software; they cannot be learned dynamically.This table is not affected by the hardware aging process.

Table 371: L2_USER_ENTRY


141 BPDU When set to 1, indicates entry is a BPDU address.


134:129 PORT_TGID Port or TGIDIf the most significant bit is not set, then the lower 5-bit field indicates the port number on which the associated MAC address is learned.If the most significant bit is set, then this field indicates that the associated MAC address is learned on a trunk port.

128 DST_DISCARD Destination discardIdentifies if the packet should be discarded based on the destination address.

0 = Do not discard1 = Discard

127 MIRROR Mirror bitWhen set to 1, enables the packet to be mirrored based on MAC address. Requires similar programming to egress mirroring.

126 RPE Remap Priority Enable bit0 = Do not use the IEEE 802.1p priority from L2_USER_ENTRY.PRI. Recommended setting when the priority is to be obtained from the VLAN tables or the PORT table for untagged packets.1 = Use the IEEE 802.1p priority from the L2_USER_ENTRY.PRI field. This overwrites any priority obtained from the VLAN tables or the default priority from the PORT table. This is applicable for untagged packets and for tagged packets when PORT.MAP_TAG_PKT_PRIORITY = 1.

125 L3 Indicates an L3 entry. When set, it indicates an L3 entry.

124 CPU CPU bit

Send packet to CPU with CPU_CONTROL_2.CPU_DEFAULT_PRI for internal CoS.

123:121 PRI Identifies the priority of this packet. Used when L2_USER_ENTRY.RPE = 1.

120:61 MASK Mask for the {VLAN_ID, MAC_ADDR}




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L2_USER_ENTRY_ONLY TABLE

Description: TCAM for guaranteed L2 entries and BPDUs

Minimum index: 0

Maximum index: 127

Address: 0x06750000

Table 372: L2_USER_ENTRY_ONLY


120:61 MASK Mask for the {VLAN_ID, MAC_ADDR}




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L2_USER_ENTRY_DATA_ONLY TABLE

Description: Data SRAM for L2_USER_ENTRY TCAM

Minimum index: 0

Maximum index: 127

Address: 0x06760000

Note: L2_USER_ENTRY_DATA_ONLY table entries must be programmed by software; they cannot be learneddynamically. This table is not affected by the hardware aging process.

Table 373: L2_USER_ENTRY_DATA_ONLY


20 BPDU When set to 1, indicates entry is a BPDU address.


13:8 PORT_TGID Port or TGIDIf the most significant bit is not set, then the lower 5-bit field indicates the port number on which the associated MAC address is learned.

7 DST_DISCARD Destination discardIdentifies if packet should be discarded based on destination address.

0 = Do not discard1 = Discard

6 MIRROR Mirror bitWhen set to 1, enables packet to be mirrored based on MAC address. Requires similar programming to egress mirroring.

5 RPE Remap Priority Enable bit0 = Do not use the IEEE 802.1p priority from L2_USER_ENTRY.PRI. Recommended setting when the priority is to be obtained from the VLAN tables or the PORT table for untagged packets.1 = Use the IEEE 802.1p priority from the L2_USER_ENTRY.PRI field. This overwrites any priority obtained from the VLAN tables or the default priority from the PORT table. This is applicable for untagged packets and for tagged packets when PORT.MAP_TAG_PKT_PRIORITY = 1.

4 L3 Indicates an L3 entry. When set, it indicates an L3 entry.

3 CPU CPU bit

Send packet to CPU with CPU_CONTROL_2.CPU_DEFAULT_PRI for internal CoS.

2:0 PRI Identifies the priority of this packet. Used when L2_USER_ENTRY.RPE = 1.

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L2_MOD_FIFO TABLE

L2MC TABLE

Description: FIFO for operations that modify the L2_ENTRY table

Minimum index: 0

Maximum index: 15

Address: 0x06770000

Table 374: L2_MOD_FIFO


106:16 WR_DATA Overlay for WRITE operations. All the L2_ENTRY fields specified in the L2_ENTRY_ONLY view. Valid if OPER is set to 00.

24:16 DELETE_OR_REPL_BM Overlay for DELETE or PPA REPLACE operations. Bitmap for bucket entries affected. Valid if OPER is set to 11 or 10.

14:5 BUCKET_IDX Index to the bucket of the L2_ENTRY table affected.

4:2 ENTRY_IDX Index to the entry of the L2_ENTRY table modified. Valid only for WRITE operations.

1:0 OPER Operation type: 11 = DELETE10 = PPA_REPLACE00 = WRITE01 = Reserved

Description: The multicast table is 1024 entries deep and 32 bits wide. If the destination MAC address is amulticast address, then the result of the destination lookup is a 10-bit index (L2MC_PTR) into thistable. The result of the direct index into the L2 multicast table is a bitmap that indicates which portson the local switch should receive the packet. The MC Port Bitmap is qualified with the VLAN bitmap.The MC Port bitmap is picked up from the L2MC table.

Minimum index: 0

Maximum index: 1023

Address: 0x07700000

Table 375: L2MC



30:2 PORT_BITMAP Multicast port membership

1:0 HIGIG_TRUNK_OVERRIDE HiGig trunk override indication

When set, indicates the HiGig port bitmap cannot be modified by HiGig trunking logic.

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PORT TABLE–PORT_TAB

Description: Port table. This table is used to control basic switching logic on a per port basis. The port numbercorresponds to the index starting at for index 0 to CMIC (CPU) for index 28. Indices 24–28 shouldbe kept the same as IPORT_TABLE (see “IPORT_TABLE Table” on page 320).

Minimum index: 0

Maximum index: 28

Address: 0x01700000

Table 376: PORT Table–PORT_TAB


67:66 RESERVED Reserved

65 ALLOW_SRC_MOD Allow packets with MH.SRC_MODID is same as MY_MODID

64 IGNORE_IPMC_L3_BITMAP Set this bit to disable L3 routing of IPMC packets on this port.

63 IGNORE_IPMC_L2_BITMAP Set this bit to disable L2 bridging of IPMC packets on this port.

62 PORT_BRIDGE When set to 1, the port supports L2 port bridging. The ability for a packet to be Layer 2 switched where the source destination ports are the same.

61 VLAN_PRECEDENCE VLAN precedence

0 = MAC-based has precedence over subnet-based VLANs1 = Subnet-based VLANs has precedence over MAC-based VLANs

60:45 OUTER_TPID Outer (switching) VLAN

44:39 MY_MODID Stacking module ID for this module

38 MAP_TAG_PACKET_PRIORITY When set to 1, allows for tagged packets to have the priority remapped by the L2/L3 tables when RPE = 1.

37 NNI_PORT Port is NNI port if set to 1, otherwise, UNI port

36 HIGIG_PACKET Port is HiGig+ port

35:24 PORT_VID Port-based VLAN ID

23 MAC_BASED_VID_ENABLE Enable MAC-based VLANs

22 SUBNET_BASED_VID_ENABLE Enable subnet-based VLANs

21 PASS_CONTROL_FRAMES 0 = Pause frames will be dropped and cannot be filtered1 = Pause frames will be dropped; however, they can be filtered by the ContentAware™ engine which can modify the forwarding port bitmap

20 PORT_DIS_UNTAG When set, drop all untagged and priority tagged non-BPDU packets

19 PORT_DIS_TAG When set, drop all tagged non-BPDU packets

18 DROP_BPDU Set to drop ingress BPDUs

17 V4L3_ENABLE IPv4 L3 enable


15 V4IPMC_ENABLE IPv4 IPMC enable


13 IPMC_DO_VLAN Controls whether the VLAN is used in the IPMC Lookup Process of the L3 table.

12:10 PORT_PRI Default port priority

9:7 CML CPU-managed learning. These modes are used when a source address is not found in the L2 tables

CML = 0 - Learn, do not send to CPU, forward the packetCML = 1 - No Learn, send to CPU, drop the packetCML = 2 - No Learn, do not send to CPU, forward the packetCML = 3 - No Learn, do not send to CPU, drop the packetCML = 4 - Learn, send to CPU, forward the packetCML = 5 - No Learn, send to CPU, forward the packetCML = 6 - ReservedCML = 7 - Reserved

6 MIRROR Enable ingress port mirroring

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5 EN_IFILTER Enable ingress filteringWhen it is set, enables ingress filtering for this port. If this bit is set, then the ingress port discards any frame received on that port whose VLAN classification does not include that port in its member set.

4 TRUST_DSCP_V6 Ingress port is the trusted port; trust incoming IPv6 DSCP

3 TRUST_DSCP_V4 Ingress port is the trusted port; trust incoming IPv4 DSCP

2 VT_ENABLE When set, it enables VLAN translation. Per device setting. All ports should be set the same.

1 VT_MISS_DROP When set, packets are dropped due to VLAN translation miss.

0 FILTER_ENABLE When set to 1, enable ContentAware Processing engine.

Note: MY_MODID for HiGig ports must be defined in IPORT_TABLE. MY_MODID for Xports must be defined in XPORT_CONFIG.

Table 376: PORT Table–PORT_TAB (Cont.)


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IPORT_TABLE TABLE

Description: Port table. This serves the same function as PORT, but is specific to HiGig+/10GE ports. Indices 24–28 of the PORT table (see “PORT Table–PORT_TAB” on page 318) should be configured to thesame settings as this table.

Minimum index: 24

Maximum index: 28

Address: 0x01800000

Table 377: IPORT_TABLE


67:66 RESERVED Reserved

65 ALLOW_SRC_MOD Allow packets with MH.SRC_MODID is same as MY_MODID

64 IGNORE_IPMC_L3_BITMAP Set this bit to disable L3 routing of IPMC packets on this port

63 IGNORE_IPMC_L2_BITMAP Set this bit to disable L2 bridging of IPMC packets on this port

62 PORT_BRIDGE When set to 1, the port supports L2 port bridging. The ability for a packet to be Layer 2 switched where the source destination ports are the same.

61 VLAN_PRECEDENCE VLAN precedence

0 = MAC-based VLANs have precedence over subnet-based VLANs1 = Subnet-based VLANs have precedence over MAC-based VLANs



38 MAP_TAG_PACKET_PRIORITY When set to 1, allows for tagged packets to have the priority remapped by the L2/L3 tables when RPE = 1.

37 NNI_PORT Port is an NNI port if set to 1, otherwise, a UNI port.

36 HIGIG_PACKET Port is a HiGig+ port.

35:24 PORT_VID Port-based VLAN ID



21 PASS_CONTROL_FRAMES 0 = Pause frames will be dropped and cannot be filtered.1 = Pause frames will be dropped; however, they can be filtered by the ContentAware engine which can modify the forwarding port bitmap.

20 PORT_DIS_UNTAG When set, drop all untagged and priority tagged non-BPDU packets.

19 PORT_DIS_TAG When set, drop all tagged non-BPDU packets.

18 DROP_BPDU When set, ingress drops BPDUs





13 IPMC_DO_VLAN Controls whether the VLAN is used in the IPMC Lookup Process of the L3 table

12:10 PORT_PRI Default port priority

9:7 CML CPU-managed learning. These modes are used when a source address is not found in the L2 tables.

CML = 0 - Learn, do not send to CPU, forward the packetCML = 1 - No Learn, send to CPU, drop the packetCML = 2 - No Learn, do not send to CPU, forward the packetCML = 3 - No Learn, do not send to CPU, drop the packetCML = 4 - Learn, send to CPU, forward the packetCML = 5 - No Learn, send to CPU, forward the packetCML = 6 - ReservedCML = 7 - Reserved

6 MIRROR Mirror enable

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5 RESERVED Reserved

4 TRUST_DSCP_V6 Ingress port is trusted port; trust incoming IPv6 DSCP

3 TRUST_DSCP_V4 Ingress port is trusted port; trust incoming IPv4 DSCP

2 VT_ENABLE When set, it enables VLAN translation.

1 VT_MISS_DROP When set, packets are dropped due to VLAN translation miss.

0 FILTER_ENABLE When set to 1, enable ContentAware Processing engine.

Note: MY_MODID for HiGig ports must be defined in IPORT_TABLE. MY_MODID for Xports must be defined in XPORT_CONFIG.

Table 377: IPORT_TABLE (Cont.)


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NONUCAST_TRUNK_BLOCK_MASK TABLE

The algorithm consists of three components: SA MAC/SIP, DA MAC/DIP, and Ingress Module ID/Port. Each of thesecomponents must be enabled in the HASH_CONTROL register for use in non-unicast trunk hashing. If not enabled, the valueof the component is 0 in the algorithm.

For IPMC: {SIP, DIP, Ingress Module ID/Port or Ingress TGID}

For broadcast, L2 multicast, DLF: {SA MAC, DA MAC, Ingress Module ID/Port or Ingress TGID}

PORT_TRUNK_EGRESS TABLE–TRUNK_EGR_MASK

If the packet originated from a non-trunk port on the local switch or from a remote module, then the Egress Mask table isused instead of the Port Trunk Egress table. The port trunk mask is selected via a 7-bit index into the Port Trunk Egresstable. The index is the TGID value obtained from the SOURCE_TRUNK_MAP table.

Description: Multicast and broadcast trunk block mask table for non-unicast packets. This table is used to loadbalance non-unicast traffic across different trunk port members. This is achieved by maskingdifferent trunk port members in each entry. The index to this table is the result of a non-unicasthashing algorithm.

Minimum index: 0

Maximum index: 15

Address: 0x0E760000

Table 378: NONUCAST_TRUNK_BLOCK_MASK


28:0 BLOCK_MASK Multicast/broadcast trunk block mask bitmap0 = Do not block1 = Block

Description: Trunk Egress Block Mask table provides a per-trunk blocking mask applied to the egress port bitmap.

Minimum index: 0

Maximum index: 127

Address: 0x0E710000

Table 379: PORT_TRUNK_EGRESS Table–TRUNK_EGR_MASK


28:0 TRUNK_EGRESS_MASK Egress block mask for trunk source port0 = Do not block1 = Block

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EGRESS_MASK TABLE–EGR_MASK

If the packet originated from a trunk port on the local switch or from a remote module, then the Port Trunk Egress table isused instead of the Egress Mask table. The port mask is selected via an 11-bit index into the Egress Mask table. The indexcomprises the source module ID (6 bits) and the source port (5 bits). If the ingress port is a HiGig link, then the Module IDand port are obtained from the Module Header. If the ingress port is not a HiGig link, then the local Module ID from the PORTtable and the ingress port are used.

Packets with matching Destination MODID will be dropped according to this register. The table is partitioned into 64 MODIDblocks of 32-bit bitmaps corresponding to the ingress ports on the chip. A value of 2 for index 32 means that packetsingressed on GE0 with a Destination MODID of 1 will be dropped if the destination port is GE1.

SRC_MODID_BLOCK

Packets ingressed from a HiGig or CPU port with matching Source MODID will be dropped according to this register. Thetable is partitioned into five 64 MODID blocks each corresponding to the four HiGig ports and the CPU port in the order ofHG0 - HG3, CPU. The masks correspond to egress ports to be blocked.

Description: Egress Mask table provides a per-port blocking mask applied to the egress port bitmap

Minimum index: 0

Maximum index: 2047

Address: 0x0E700000

Table 380: EGRESS_MASK Table–EGR_MASK


28:0 EGRESS_MASK Egress block mask bitmap for non-trunk source port0 = Do not block1 = Block

Description: Source MODID-based blocking

Minimum index: 0

Maximum index: 319

Address: 0x0E7A0000

Table 381: SRC_MODID_BLOCK


5 GE_PORT_BLOCK_MASK Block all GbE ports

4 CPU_POR_BLOCK_MASK Block mask for CPU port

3:0 HIGIG_XGE_PORT_BLOCK_MASK Block mask for HiGig/XE ports

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ALTERNATE_EMIRROR_BITMAP

This table is used when stacking with the BCM5675 and block masks are applied with egress mirroring enabled. The bitmapshould be programmed to the HiGig port that is not the ingress port, along the longer path to the MTP module. This registershould be set to all 0s when not needed.

PORT_MAC_BLOCK TABLE–MAC_BLOCK

Description: Alternate egress mirror MTP bitmap

Minimum index: 0

Maximum index: 63

Address: 0x0E7B0000

Table 382: ALTERNATE_EMIRROR_BITMAP


3:0 BITMAP HiGig port bitmap for egress mirror packets

Description: This table is indexed by MAC_BLOCK_INDEX, which it is picked up from L2_table upon source MACaddress lookup. The result is a mask, which controls the flooding of broadcast and multicast forknown source MAC addresses, to a specific set of ports.

Minimum index: 0

Maximum index: 31

Address: 0x0E740000

Table 383: PORT_MAC_BLOCK Table–MAC_BLOCK


28:0 MAC_BLOCK_MASK MAC block mask0 = Do not block1 = Block

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VLAN_PROTOCOL TABLE

Description: The VLAN_PROTOCOL table contains 16 entries that can be used by the GPIC ports for untaggedand priority-tagged (VLAN ID = 0) packets. The table is searched by looking for a FRAMETYPE andETHERTYPE match. Of the three FRAMETYPE bits (ETHERII, SNAP, and LLC), only one type maybe set per entry. ETHERTYPE match can be on the upper eight bits, lower eight bits, or the entirefield. The corresponding MATCHUPPER/MATCHLOWER bits must be set. If these bits are not set,then there can be no match. If there are multiple matches, there is no distinction between a full match(matching upper and lower bytes when both MATCHUPPER and MATCHLOWER are set) and apartial match (matching only the upper or lower byte when both MATCHUPPER and MATCHLOWERare set). This is treated as a multiple match. In general when multiple entries match, the one with thelowest index is used.

Example:

• IPv4: ETHERII = 1 or SNAP = 1 and ETHERTYPE = 0x0800

• IPX-LLC: LLC = 1 and ETHERTYPE = 0xE0E0

• IPX-RAW: LLC = 1 and ETHERTYPE = 0xFFFF

The index of the matched entry, along with the ingress port, is used to retrieve the VLAN_ID and PRIfrom the entries of the VLAN_PROTOCOL_DATA table. Priority-tagged packets do not use thepriority from the table entry.

Minimum index: 0

Maximum index: 15

Address: 0x04700000

Table 384: VLAN_PROTOCOL


20 MATCHUPPER Match upper eight bits of ETHERTYPE

19 MATCHLOWER Match lower eight bits of ETHERTYPE

18 ETHERII Packet is Ethernet 2-type packet.

17 SNAP Packet is SNAP-type packet.

16 LLC Packet is LLC-type packet.

15:0 ETHERTYPE Ethertype field—packet is IPv4, IPX-RAW, IPX-LLC, and so on.

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VLAN_PROTOCOL_DATA TABLE

VLAN_SUBNET TABLE

Description: The VLAN_PROTOCOL_DATA table is used for protocol-based VLANs. The VLAN_PROTOCOL_DATA entries are organized into fixed 16 entries per port block. Hence, the ingress port is used to first pick the corresponding port entries and then the index retrieved from the VLAN_PROTOCOL table is used to index into the 16 entries.

Minimum index: 0

Maximum index: 463

Address: 0x04710000

Table 385: VLAN_PROTOCOL_DATA



2:0 PRI Priority field

Description: Composite view of VLAN_SUBNET_ONLY and VLAN_SUBNET_DATA_ONLY

Minimum index: 0

Maximum index: 255

Address: 0x04720000

Table 386: VLAN_SUBNET




128:65 MASK IP subnet mask

64:1 IP_ADDR IP address key

0 VALID IP subnet mask

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VLAN_SUBNET_ONLY TABLE

VLAN_SUBNET_DATA_ONLY TABLE

Description: TCAM for IP subnet-based VLANs. This table will assign VLAN IDs to untagged and priority-taggedpackets based on the source IP address. For IPv4 addresses, the 32-bit SIP should be programmedinto IP_ADDR[32:1]. For IPv6 addresses, matching occurs only on the upper 64 bits, SIP[127:64]should be programmed into IP_ADDR[64:1]. When a hit occurs, the index of the matched entry isused to retrieve the VLAN_ID and PRI from the VLAN_SUBNET_DATA_ONLY table. Priority-taggedpackets do not use the priority from the table entry.

When initializing the VLAN_SUBNET table, use a mask of 0xFFFFFFFF. A mask of 0x0 results in allentries matching all of the time. If multiple matches occur, then the index from the lower numberedentry is used; hence, the IP addresses should be programmed in longest-prefix match order.

Minimum index: 0

Maximum index: 255

Address: 0x04730000

Table 387: VLAN_SUBNET_ONLY


128:65 MASK IP subnet mask

64:1 IP_ADDR IP address key

0 VALID IP subnet mask

Description: The VLAN_SUBNET_DATA table is used for the subnet-based VLANs. The table contains 256entries. All entries contain VLAN ID and priority values. In the subnet-based VLAN, the index isretrieved from the VLAN_SUBNET_ONLY table.

Minimum index: 0

Maximum index: 255

Address: 0x04740000

Table 388: VLAN_SUBNET_DATA_ONLY




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VLAN_MAC TABLE

Description: The VLAN_MAC table contains 1024 entries that can be used for untagged and priority-tagged(VLAN ID = 0) packets. The table is searched with a 10-bit value generated by hashing the sourceMAC address. Priority-tagged packets do not use the priority from the table entry.

Minimum index: 0

Maximum index: 1023

Address: 0x04750000

Table 389: VLAN_MAC


63 VALID VLAN ID

62:60 PRI Priority


47:0 MAC_ADDR MAC address key

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VLAN_XLATE TABLE

This table is used by UNI ports during Mapped Services mode which is enabled when PORT.VT_ENABLE = 1. If the packetTPID matches VLAN_CONTROL.INNER_TPID, then the packet is deemed to be tagged. The table is searched using thepacket VLAN ID and the ingress port. On a hit, the NEW_VLAN_ID is added as the Outer (SPVLAN) Tag if ADD_VID == 1,else the Inner (VLAN) Tag is replaced. If RPE = 1, then the new PRI value is used. If there is a translation miss, then thepacket can optionally be dropped (if VT_MISS_DROP=1 in PORT table) or have a SPVLAN tag added based on the VLANlookup tables (MAC, Subnet, Protocol, Port VLAN ID).

VLAN_XLATE_ONLY TABLE

Description: Composite view of VLAN_XLATE_ONLY and VLAN_XLATE_DATA_ONLY tables.

Minimum index: 0

Maximum index: 767

Address: 0x04760000

Table 390: VLAN_XLATE


34 ADD_VID Add the VLAN IDWhen this bit is set to 1, ingress adds outer VLAN (based on NEW_VLAN_ID) to the incoming packet.When this bit is set to 0, ingress replaces the VLAN tag of the incoming packet with a new VLAN (NEW_VLAN_ID_.

33:22 NEW_VLAN_ID VLAN ID to be assigned

This is the VLAN that is added or replaced based on the ADD_VID bit.

21:19 PRI Priority to be assignedThis is the priority of the new VLAN tag when the RPE bit is set to 1.

18 RPE Remap Priority Enable bitWhen this bit is set to 1, it uses the PRI field for the priority of the new VLAN tag.

17:6 OLD_VLAN_ID VLAN ID part of the key

When this bit is 0, the priority of the old VLAN tag is copied to the new VLAN tag.

5:1 PORT Source port part of the keyKey to this table is composed of OLD_VLAN_ID + PORT.


Description: Translation for VLAN Binary CAM of tagged packets

Minimum index: 0

Maximum index: 767

Address: 0x04770000

Table 391: VLAN_XLATE_ONLY


17:6 VLAN_ID VLAN ID part of the key

5:1 INGRESS_PORT Source port part of the key


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VLAN_XLATE_DATA_ONLY TABLE

VLAN TABLE–VLAN_TAB

Description: Data SRAM for VLAN_XLATE BCAM

Minimum index: 0

Maximum index: 767

Address: 0x04780000

Table 392: VLAN_XLATE_DATA_ONLY


16 ADD_VID Add the VLAN ID

15:4 NEW_VLAN_ID VLAN ID to be assigned

3:1 PRI Priority to be assigned


Description: Identifies the VLAN membership and associated spanning tree group. Support for IEEE 802.1QVLAN. Port Taggedness information is stored in the EGR_VLAN table.

Minimum index: 0

Maximum index: 4095

Address: 0x05700000

Table 393: VLAN Table–VLAN_TAB


41:40 PFM Port Filtering modeThese two bits indicate Port Filtering mode for multicast packets as follows:00 = Forward all group addresses. In this mode, all frames destined for group MAC addresses are forwarded according to the VLAN rules. The Port bitmap from the IEEE 802.1Q VLAN table is used for all packets.01 = Forward all unregistered group addresses. In this mode, if the group MAC address registration entries exists in the Multicast table, frames destined for that corresponding group MAC address will be forwarded, only on ports identified in the member port set, which is identified by the Port bitmap. If the group MAC address does not exist in the Multicast table, then Mode 0 filtering mechanism is used.10 = Filter all unregistered group addresses. In this mode, frames destined for group MAC addresses are forwarded only if such forwarding is explicitly permitted by a group address entry in the Multicast table. If the group MAC address exists in the Multicast table, then the packets are forwarded using the Port bitmap. Otherwise, the packets are dropped.11 = Unused.

39:32 STG Spanning tree group ID

31 VALID Valid VLAN ID

30:29 HIGIG_TRUNK_OVERRIDE HiGig trunk override indicationWhen set, indicates the HiGig port bitmap cannot be modified by HiGig trunking logic. Two bits: lower bit used with HiGig Trunk Group 0 and the upper for HiGig Trunk Group 1.

28:0 PORT_BITMAP VLAN port membership bitmap

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VLAN_STG TABLE–STG_TAB

The following are the spanning tree states:

• 0 = Disabled. All packets are dropped, including control packets, even BPDUs.

• 1 = Blocking. All control/BPDU packets are sent to the CPU, all other packets are dropped (no L2 address learning).

• 2 = Learning. All control/BPDU packets are sent to the CPU, all other packets are dropped (L2 addresses are learned).

• 3 = Forwarding. All control/BPDU packets are sent to the CPU, all other packets are forwarded as normal.

Description: Spanning Tree Group table is 256 entries deep. This table is indexed by Spanning Tree Group (STG)from the VLAN table and the ingress port number. It is used to get the spanning tree state of theingress port for a particular VLAN.

Minimum index: 0

Maximum index: 255

Address: 0x05710000

Table 394: VLAN_STG Table–STG_TAB


55:54 SP_TREE_PORT27 Spanning tree state for port 27




























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EGR_VLAN TABLE

Description: VLAN Membership table for egress indexed by the VLAN number. This is used to make sure theegress port is part of the VLAN that the packet is on.

Minimum index: 0

Maximum index: 4095

Address: 0x04910000

Table 395: EGR_VLAN


65 VALID Indicates the entry is valid,

64:57 STG Spanning tree group number. To be used for indexing VLAN_STG table.

56:28 PORT_BITMAP Indicates which port is a member of this VLAN. A bit for the CPU is needed.

27:0 UT_BITMAP Untagged Port bitmap. Indicates on which port the packet needs to be sent untagged. A bit for the CPU is not needed.

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EGR_VLAN_STG TABLE

The following are the spanning tree states:

• 0 = Disabled

• 1 = Blocking

• 2 = Learning

• 3 = Forwarding

On egress, non-BPDU packets may egress only if the port is in the forwarding state; otherwise, they are dropped. BPDUpackets may egress if the port is either in the blocking, learning, or forwarding state.

Description: The Egress Spanning Tree Group table is 256 entries deep. This table is indexed by Spanning TreeGroup (STG) from the EGR_VLAN table and the egress port number. It is used to get the spanningtree state of the egress port for a particular VLAN.

Minimum index: 0

Maximum index: 255

Address: 0x04920000

Table 396: EGR_VLAN_STG


55:54 SP_TREE_PORT27 Spanning tree state for Port 27



























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Table 396: EGR_VLAN_STG (Cont.)


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EGR_VLAN_XLATE TABLE

This table is used in the egress block of UNI ports during Mapped Services mode, which is enabled whenEGR_VLAN_CONTROL_1.VT_EN = 1. The table is searched using the packet VLAN ID and the egress port. On a hit, theNEW_VLAN_ID replaces the vlan_id of the packet. If RPE = 1, then the new PRI value is used for constructing the newVLAN tag.

If there is a translation miss, the packet can optionally be dropped (when EGR_VLAN_CONTROL_1.VT_MISS_DROP = 1)or the tag is removed (when EGR_VLAN_CONTROL_1.VT _MISS_DROP = 0).

Description: Egress VLAN translate CAM-RAM combined view

Minimum index: 0

Maximum index: 767

Address: 0x05910000

Table 397: EGR_VLAN_XLATE


33 RPE Remap priority enable bitWhen this bit is set to 1, it uses the PRI field for the priority of the new VLAN tag. When this bit is 0, it copies the priority of the old VLAN into the new VLAN.

32:30 PRI PRI priority to be used to translate the original priority

This is the priority of the new VLAN tag when RPE bit is set to 1.

29:18 NEW_VLAN_ID NEW_VLAN_ID VID to be used to translate the original packet, or so far constructed VID at the L3 stage.This replaces the VID of the packet in the egress before packet transmission.

17:13 PORT PORT destination port to be compared with respect to the input key. Input key to this table is composed of OLD_VLAN_ID + PORT.

12:1 OLD_VLAN_ID OLD_VLAN_ID VID to be compared with respect to the input key. Input key to this table is composed of OLD_VLAN_ID + PORT.

0 VALID VALID valid bit for the entry. It has to be the 0th bit in the CAM.

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EGR_VLAN_XLATE_ONLY TABLE

EGR_VLAN_XLATE_DATA_ONLY TABLE

Description: Egress VLAN translate CAM only

Minimum index: 0

Maximum index: 767

Address: 0x05920000

Table 398: EGR_VLAN_XLATE_ONLY


17:13 EGRESS_PORT Destination port to be compared with respect to the input key

12:1 VID VID to be compared with respect to the input key

0 VALID Valid bit for the entry. It has to be the 0th bit in the CAM.

Description: Egress VLAN translate data table only

Minimum index: 0

Maximum index: 767

Address: 0x05930000

Table 399: EGR_VLAN_XLATE_DATA_ONLY


15 RPE Remap priority enable

Used to determine if the VLAN_XLATE_DATA PRI needs to be replaced.

14:12 PRI Priority to be used to translate the original priority

11:0 NEW_VID VID to be used to translate the original packet, or so far constructed VID at the L3 stage

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TRUNK_GROUP TABLE

RTAG is used as the criterion to drive a trunk port index, which points to the egress port address (TPn) in the trunk group.The Firebolt supports trunking over stack link. The trunk group table is consistently accessed using a destination trunk group,and rather than bind the source RTAG to a table used solely for destination trunking (the trunk group table), the source RTAGis bound to the table used solely for source trunking (the trunk bitmap table). The RTAGs for each entry in the trunk bitmaptable must be identical to the RTAGs for each corresponding entry in the trunk group table.

Description: The trunk group table contains the information for up to 128 trunk groups. Each trunk group tableentry contains up to eight different ports, which can be trunked together. Each entry consists of eightport addresses of the member ports. Each trunk port address consists of a 6-bit module ID and 5-bitport number. Search this table with TGID to drive the trunk group.

Minimum index: 0

Maximum index: 127

Address: 0x0E720000

Table 400: TRUNK_GROUP


90:88 RTAG RTAG selection for trunk ID 0. HiGig+ trunk ID #1 RTAG (for encoding values seeTRUNK_GROUP.RTAG field)

• 0x0 = ZERO–Hash entry always zero• 0x1 = SA–BCM5695 hashing is based on SA, otherwise, based on SA, VLAN,

Ethertype, and source module ID/port

• 0x2 = DA–BCM5695 hashing is based on DA, otherwise, based on DA, VLAN, Ethertype, and source module ID/port

• 0x3 = SA_DA–BCM5695 hashing, based on SA/DA, otherwise, based on SA/DA, VLAN, Ethertype, and source module ID/port

• 0x4 = SIP–BCM5695 hashing is based on SIP, otherwise, based on SIP and source TCP/UDP port

• 0x5 = DIP–BCM5695 hashing is based on DIP, otherwise, based on DIP and destination TCP/UDP port

• 0x6 = SIP_DIP–BCM5695 hashing is based on SIP/DIP, otherwise, based on SIP/DIP and source/destination TCP/UDP port

• 0x7 = Source port based trunk selection. Selection is specified in USER_TRUNK_HASH_SELECT and IUSER_TRUNK_HASH_SELECT.

87:82 MODULE7 Module ID 7

81:77 PORT7 Trunk port 7















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TRUNK_BITMAP TABLE

The trunk bitmap table contains an RTAG field. The reason for this RTAG field is because the RTAG associated with thesource trunk group is required to construct an appropriate stack tag. The RTAGs for each entry in the trunk bitmap tablemust be identical to the RTAGs for each corresponding entry in the trunk group table.

MODPORT_MAP TABLE

The index to this table is the destination module ID of the ingress packet.

Description: The trunk group table is 128 entries deep and 32 bits wide, with one entry for each trunk group. (TheFirebolt can support 128 trunk groups). Each entry consists of a port bitmap of the member ports. Ifthe packet comes in from one of the trunk ports, the TGID is used as the index into this table to drivethe trunk group.

Minimum index: 0

Maximum index: 127

Address: 0x0E730000

Table 401: TRUNK_BITMAP


28:0 TRUNK_BITMAP Trunk group bitmapIdentifies all of the ports which are a member of the trunk group

Description: Module Port Mapping table

Minimum index: 0

Maximum index: 63

Address: 0x0E750000

Table 402: MODPORT_MAP


5:4 HIGIG_TRUNK_OVERRIDE HiGig+ trunk override

3:0 HIGIG_PORT_BITMAP HiGig+ destination port bitmap

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DSCP_TABLE TABLE

EGR_DSCP_TABLE TABLE

EGR_DSCP_ECN_MAP

Description: Provides the ability to remap the packet DSCP. This table is indexed by the packet DSCP.

Minimum index: 0

Maximum index: 63

Address: 0x08700000

Table 403: DSCP_TABLE


10:9 CNG Congestion bits

8:6 PRI Priority

5:0 DSCP New differentiated services code point

Description: Egress DSCP table to select the new DSCP for outer tunnel header packets. This table is indexedusing the internal priority of the packet appended by the CNG bits.

Minimum index: 0

Maximum index: 31

Address: 0x05970000

Table 404: EGR_DSCP_TABLE


5:0 DSCP New DSCP to be used for the outer tunnel header based on the incoming MMU priority and the DSCP_SEL field from the EGR_IP_TUNNEL table

Description: Egress DSCP Table to select the new dscp for outer tunnel header packets

Minimum index: 0

Maximum index: 63

Address: 0x05980000

Table 405: EGR_DSCP_ECN_MAP

Bit(s) Name R/W Description

0 ECN_MODE R/W Specifies the interpretation MODE to choose based on DSCP

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EGR_IP_TUNNEL TABLE

Description: Egress IP Tunnel table—used to make new Tunnel Header. The index into this table is specified inEGR_L3_INTF. See “EGR_L3_INTF Table” on page 353.

Minimum index: 0

Maximum index: 127

Address: 0x05940000

Table 406: EGR_IP_TUNNEL


133 IPV6_DF_SEL Specifies how to construct DF field if tunnel initiation is done for a v6 packet.0 = Set DF to 01 = Set DF to 1

132:131 IPV4_DF_SEL Specifies how to construct DF field if tunnel initiation is done for a v4 packet.

00 = Set DF to 001 = Set DF to 110 = Copy inner IP header DF to tunnel header11 = Copy inner IP header DF field to tunnel header

130:129 DSCP_SEL Specifies which DSCP to select to put in the outer tunnel header. Defines selection of DSCP.00 = Pick up from Tunnel table01 = Pick up from Packet (PICK_FROM_PACKET)10 = Pick up from DSCP table (PICK_FROM_DSCP_TABLE)11 = Reserved

128:123 DSCP Specifies what should be the new DSCP to be put in the tunnel header

122:120 TUNNEL_TYPE Specifies which tunnel protocol is supported by this entry

119:88 DIP Destination IP address to be used in the IP tunnel header

87:56 SIP Source IP address to be used in the IP tunnel header

55:48 TTL TTL to be used in the IP tunnel header

47:0 DEST_ADDR MAC DA to be used to change the packet MAC DA in case of IP tunneling

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L3_TUNNEL TABLE

Description: L3 Tunnel Table TCAM

Minimum index: 0

Maximum index: 127

Address: 0x02700000

Table 407: L3_TUNNEL


176 USE_TUNNEL_DSCP Trust DSCP per tunnel

175:164 IINTF L3 interface for this tunnel for IPMC switching

163:135 ALLOWED_PORT_BITMAP Port bitmap for this tunnel

134 DONOT_CHANGE_INNER_HDR_DSCP Set this bit to not change inner header's DSCP field

133 USE_OUTER_HDR_TTL Use IPv4 outer header’s TTL field

132 USE_OUTER_HDR_DSCP Use IPv4 outer header’s DSCP field

131 TUNNEL_TYPE Indicates whether the tunnel is an auto or configured tunnel• 0x0 = CONFIG—Configured tunnel• 0x1 = AUTO—Automatic tunnel

130:129 SUB_TUNNEL_TYPE When TUNNEL_TYPE field is set to 0x1, it indicates L3 tunnel type as shown below.

• 0x0 = IP6TO4—6to4 tunnel• 0x1 = ISATAP—ISATAP tunnel• 0x2 = RESERVED0—Reserved

• 0x3 = RESERVED1—ReservedWhen TUNNEL_TYPE field is set to 0x0, it indicates:• 0x1 = IPv4 payload is allowed (configured 6to4)

• 0x2 = IPv6 payload is allowed (configured IPv4 in IPv4)

128:97 DIP_MASK Destination IP address mask

96:65 SIP_MASK Source IP address mask

64:33 DIP Destination IP address for Tunnel table lookup

32:1 SIP Source IP address for Tunnel table lookup

0 VALID Valid bit for each TCAM entry

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L3_ENTRY_ONLY TABLE

Description: L3 routing table with fb_regs arch view. No hit bits. This table is a hashed table. To manipulate andlook up entries in the table, use S-channel Message OPCODES L3_INS, L3_DEL, andFB_L3_LKUP.

Minimum index: 0

Maximum index: 8191

Address: 0x08720000

Table 408: L3_ENTRY_ONLY


97 ODD_PARITY Odd parity for the L3_ENTRY RAM fields (i.e. excludes HIT bits).

96 VALID Indicates that the entry is valid.

95 DST_DISCARD Discard the packet on DIP match.0 = Disable1 = Enable

94:92 PRI Priority


90:78 NEXT_HOP_INDEX Index for the next hop (overlaid for IPMC packets becomes {IPMC_TUNNEL_TYPE[1:0], reserved, L3MC_INDEX[9:0]}).

90:89 IPMC_TUNNEL_TYPE Overlay for IPMC tunnel type

87:78 L3MC_INDEX Overlay for L3 MC index

77:66 VLAN_ID VLAN ID bits. Not used for this view

65 IPMC Indicates the entry is used for an IPMC route. Must be zero for this view.

64 V6 Indicates the entry is used for an IPv6 route. Must be zero for this view.

63:0 IP_ADDR 64 bits of IP address

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L3_ENTRY_IPV4_UNICAST TABLE

Description: L3 routing table IPV4 UNICAST view. This table is a hashed table. To manipulate and look up entriesin the table, use S-channel Message OPCODES L3_INS, L3_DEL, and FB_L3_LKUP.

Minimum index: 0

Maximum index: 8191

Address: 0x08730000

Table 409: L3_ENTRY_IPV4_UNICAST


98 HIT Hit bit for the entry.

97 EVEN_PARITY Even parity for the L3_ENTRY RAM fields, i.e. excludes HIT bits.


95 DST_DISCARD Discard the packet on DIP match.0 = Disable1 = Enable

94:92 PRI Priority.

91 RPE Remap Priority Enable bit.

90:78 NEXT_HOP_INDEX Index for the next hop (overlaid for IPMC packets becomes {IPMC_TUNNEL_TYPE[1:0], reserved, L3MC_INDEX[9:0]}).

77:66 VLAN_ID VLAN ID bits. Not used for this view.

65 IPMC Indicates the entry is used for an IPMC route. Must be zero for this view.

64 V6 Indicates the entry is used for an IPv6 route. Must be zero for this view.

63:32 IP_ADDR_UNUSED IP address bits not used for this view

31:0 IP_ADDR 32-bit IP address

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L3_ENTRY_IPV4_MULTICAST TABLE

Description: L3 routing table IPv4 multicast view. This table is a hashed table. To manipulate and look up entriesin the table, use S-channel Message OPCODES L3_INS, L3_DEL, and FB_L3_LKUP.

Minimum index: 0

Maximum index: 8191

Address: 0x08740000

Table 410: L3_ENTRY_IPV4_MULTICAST


98 HIT Hit bit for the entry.

97 EVEN_PARITY Even parity for the L3_ENTRY RAM fields, i.e. excludes HIT bits. (For non-A0 revisions only.)


95 DST_DISCARD Discard the packet on DIP match0 = Disable1 = Enable

94:92 PRI Priority


90:89 IPMC_TUNNEL_TYPE Tunnel type

88 NEXT_HOP_INDEX_UNUSED One bit of the NEXT_HOP_INDEX. Unused for this view.

87:78 L3MC_INDEX Index into the L3MC table

77:66 VLAN_ID VLAN ID bits

65 IPMC Indicates the entry is used for an IPMC route. Must be 1 for this view.

64 V6 Indicates the entry is used for an IPv6 route. Must be 0 for this view.

63:32 SOURCE_IP_ADDR 32-bit source IP address

31:0 GROUP_IP_ADDR 32-bit group IP address

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L3_ENTRY_IPV6_UNICAST TABLE

Description: L3 routing table IPV6 unicast view. This table is a hashed table. To manipulate and look up entriesin the table, use S-channel Message OPCODES L3_INS, L3_DEL, and FB_L3_LKUP.

Minimum index: 0

Maximum index: 4095

Address: 0x08750000

Table 411: L3_ENTRY_IPV6_UNICAST


197 HIT_1 Indicates that the entry is valid. Same value as HIT_0.


195 EVEN_PARITY_1 Even parity for the L3_ENTRY RAM fields entry 1, i.e. excludes HIT bit.

194 VALID_1 Indicates that the entry is valid. Same value as VALID_0.

193 DST_DISCARD_1 Discard the packet on DIP match. (For non-A0 revisions only.)

192:190 PRI_1 Priority. Same value as RPE_0. (For non-A0 revisions only.)

189 RPE_1 RPE bit. Same value as RPE_0. (For non-A0 revisions only.)

188:176 NEXT_HOP_INDEX_1 Index for the next hop. Same value as NEXT_HOP_INDEX_0.

175:164 VLAN_ID_UNUSED_1 VLAN ID bits. Not used for this view. (For non-A0 revisions only.)

163 IPMC_1 Indicates entry is used for an IPMC route. Must be zero for this view.

162 V6_1 Indicates entry is used for an IPv6 route. Must be 1 for this view.

161:98 IP_ADDR_UPR_64 Upper 64 bits of the IP address.

97 EVEN_PARITY_0 Even parity for the L3_ENTRY RAM fields entry 0, i.e. excludes HIT bit.

96 VALID_0 Indicates that the entry is valid. Same value as VALID_1.

95 DST_DISCARD_0 Discard the packet on DIP match.

94:92 PRI_0 Priority. Same value as RPE_1.

91 RPE_0 RPE bit. Same value as RPE_1.

90:78 NEXT_HOP_INDEX_0 Index for the next hop. Same value as NEXT_HOP_INDEX_1.

77:66 VLAN_ID_UNUSED_0 VLAN ID bits. Not used for this view.

65 IPMC_0 Indicates the entry is used for an IPMC route. Must be zero for this view.

64 V6_0 Indicates the entry is used for an IPv6 route. Must be 1 for this view.

63:0 IP_ADDR_LWR_64 Lower 64 bits of the IP address

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L3_ENTRY_IPV6_MULTICAST TABLE

Description: L3 routing table IPV6 multicast view. This table is a hashed table. To manipulate and look up entriesin the table, use S-channel Message OPCODES L3_INS, L3_DEL, and FB_L3_LKUP.

Minimum index: 0

Maximum index: 2047

Address: 0x08760000

Table 412: L3_ENTRY_IPV6_MULTICAST





392 HIT_0 Indicates that the entry is valid. (For non-A0 revisions only.)

391 EVEN_PARITY_3 Even parity for the L3_ENTRY RAM fields entry 3 (i.e. excludes HIT bit).

390 VALID_3 Indicates that the entry is valid. Same as the other VALID fields.


388:386 PRI_3 Priority. Same as the other PRI fields.

385 RPE_3 RPE bit. Same as the other RPE fields.

384:383 IPMC_TUNNEL_TYPE_3 Tunnel type. Same as the other IPMC_TUNNEL_TYPE fields.

382 NEXT_HOP_INDEX_UNUSED_3 One bit of the NEXT_HOP_INDEX. Unused for this view.

381:372 L3MC_INDEX_3 Index into the L3MC table. Same as the other 3 L3MC_INDEX fields.

371:360 VLAN_ID_3 VLAN ID bits. Same as the other three VLAN_ID fields in this view.

359 IPMC_3 Indicates entry is used for an IPMC route. Must be 1 for this view.


357:294 SOURCE_IP_ADDR_UPR_64 Upper 64 bits of the Source IP address.







284 NEXT_HOP_INDEX_UNUSED_2 One bit of the NEXT_HOP_INDEX, unused for this view.

283:274 L3MC_INDEX_2 Index into the L3MC table. Same as the other three L3MC_INDEX fields.




259:196 SOURCE_IP_ADDR_LWR_64 Lower 64 bits of the Source IP address.







186 NEXT_HOP_INDEX_UNUSED_1 One bit of the NEXT_HOP_INDEX, unused for this view.


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163 IPMC_1 Indicates the entry is used for an IPMC route. Must be 1 for this view.

162 V6_1 Indicates the entry is used for an IPv6 route. Must be 1 for this view.

161:154 GROUP_IP_ADDR_UNUSED IP address bits that are unused for this view.

153:98 GROUP_IP_ADDR_UPR_56 Lower 64 bits of the Group IP address.







88 NEXT_HOP_INDEX_UNUSED_0 One bit of the NEXT_HOP_INDEX. Unused for this view.


77:66 VLAN_ID_0 VLAN ID bits. Same as the other 3 VLAN_ID fields in this view.



63:0 GROUP_IP_ADDR_LWR_64 Lower 64 bits of the Group IP address.

Table 412: L3_ENTRY_IPV6_MULTICAST (Cont.)


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L3_ENTRY_VALID_ONLY TABLE

L3_IPMC TABLE

Description: L3 routing table Valid Bits only view, organized into buckets.

Minimum index: 0

Maximum index: 1023

Address: 0x08770000

Table 413: L3_ENTRY_VALID_ONLY


7 VALID_7 Indicates that the entry is valid.








Description: L3 IPMC table. The index into this table is specified by L3_MC bits in the L3_ENTRY tables.

Minimum index: 0

Maximum index: 1023

Address: 0x09700000

Table 414: L3_IPMC


74:73 IPMC_TUNNEL_TYPE Tunnel type of at least one of egress intf.

72:44 L3_BITMAP L3 port bitmap

43:15 L2_BITMAP L2 port bitmap



7:2 PORT_TGID Port or TGID

1:0 HIGIG_TRUNK_OVERRIDE HiGig+ Trunk Override bits

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L3_DEFIP TABLE

This table is shared between IPv4 AND IPV6. In IPv4, each half-entry can match a 32-bit address. Up to 12k addresses canbe matched in IPv4. In IPv6, each entry is used to match the upper 64 bits of an IPv6 address. Half-entry 1 corresponds tothe 32 MSB of the upper 64 bits, while half-entry 0 corresponds to the lower 32 bits of the upper 64 bits.

Description: L3 Default IP Route (LPM) TCAM view with data and hit bits

Minimum index: 0

Maximum index: 6143

Address: 0x0A700000

Table 415: L3_DEFIP


178 HIT1 Hit bit for half-entry 1

177 HIT0 Hit bit for half-entry 0

176 EVEN_PARITY Even parity for the L3_DEFIP RAM fields.

175 DST_DISCARD0 Discard packet on L3 DEFIP hit

174 RPE0 RPE bit for half-entry 0

173:171 PRI0 Priority for half-entry 0

170:166 ECMP_COUNT0 Number of ECMP routes in the group for half-entry 0.

167:155 NEXT_HOP_INDEX0 Next Hop Ptr—only valid for non ECMP routes.

165:155 ECMP_PTR0 Ptr to ECMP group within ECMP table for half-entry 0.

154 ECMP0 Indicates if the route for half-entry 0 uses ECMP.

153 DST_DISCARD1 Discard packet on L3 DEFIP hit

152 RPE1 RPE bit for half-entry 1

151:149 PRI1 Priority for half-entry 1

148:144 ECMP_COUNT1 Number of ECMP routes in the group for half-entry 1.

145:133 NEXT_HOP_INDEX1 Next Hop Ptr—only valid for non ECMP routes.

143:133 ECMP_PTR1 Ptr to ECMP group within ECMP table for half-entry 1.


131:100 MASK1 Subnet mask for half-entry 1

99:68 MASK0 Subnet mask for half-entry 0

67:36 IP_ADDR1 IP address bits for half-entry 1

35:4 IP_ADDR0 IP address bits for half-entry 0

3 MODE1 Indicates the contents of half-entry 1.0 = IPv41 = IPv6

2 MODE0 Indicates the contents of half-entry 0.

0 = IPv41 = IPv6

1 VALID1 Indicates half-entry 1 is valid.


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L3_DEFIP_ONLY TABLE

Description: L3 Default IP Route (LPM) TCAM-only view

Minimum index: 0

Maximum index: 6143

Address: 0x0A710000

Table 416: L3_DEFIP_ONLY


131:100 MASK1 Subnet mask for half-entry 1.

99:68 MASK0 Subnet mask for half-entry 0.

67:36 IP_ADDR1 IP address bits for half-entry 1.

35:4 IP_ADDR0 IP address bits for half-entry 0.

3 MODE1 Indicates the contents of half-entry 1.

0 = IPv41 = IPv6

2 MODE0 Indicates the contents of half-entry 0.0 = IPv41 = IPv6



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L3_DEFIP_DATA_ONLY TABLE

Description: L3 Default IP Route (LPM) Data SRAM for the L3_DEFIP TCAM

Minimum index: 0

Maximum index: 6143

Address: 0x0A720000

Table 417: L3_DEFIP_DATA_ONLY


44 EVEN_PARITY Even parity for the L3_DEFIP RAM fields.

43 DST_DISCARD0 Discard packet on L3 DEFIP hit.

42 RPE0 RPE bit for half-entry 0.

41:39 PRI0 Priority for half-entry 0.

38:34 ECMP_COUNT0 Number of ECMP routes in group for hal.f-entry 0.

35:23 NEXT_HOP_INDEX0 Next hop index pointer for half-entry 0.

33:23 ECMP_PTR0 Pointer to ECMP group within ECMP table for half-entry 0.


21 DST_DISCARD1 Discard packet on L3 DEFIP hit.

20 RPE1 RPE bit for half-entry 1.

19:17 PRI1 Priority for half-entry 1.

16:12 ECMP_COUNT1 Number of ECMP routes in group for half-entry 1.

13:1 NEXT_HOP_INDEX1 Next hop index pointer for half-entry 1.

11:1 ECMP_PTR1 Pointer to ECMP group within ECMP table for half-entry 1.


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L3_ENTRY_HIT_ONLY TABLE

L3_DEFIP_HIT_ONLY TABLE

L3_ECMP TABLE

Description: L3 Hit bit table

Minimum index: 0

Maximum index: 1023

Address: 0x0B710000

Table 418: L3_ENTRY_HIT_ONLY


7 HIT_7 Indicates that the entry has been hit.








Description: L3_DEFIP Hit bit table

Minimum index: 0

Maximum index: 6143

Address: 0x0B720000

Table 419: L3_DEFIP_HIT_ONLY


1 HIT1 Indicates that entry #1 has been hit.

0 HIT0 Indicates that entry #0 has been hit.

Description: L3 Equal Cos Multipath table

Minimum index: 0

Maximum index: 2047

Address: 0x0D700000

Table 420: L3_ECMP


12:0 NEXT_HOP Index of next hop for this ECMP route

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EGR_L3_NEXT_HOP TABLE

EGR_L3_INTF TABLE

Description: Next Hop table

Minimum index: 0

Maximum index: 8191

Address: 0x03910000

Table 421: EGR_L3_NEXT_HOP


59:12 MAC_ADDRESS MAC address to be used for DA replacement by L3UC or ContentAware™ modified packets

11:0 INTF_NUM Interface number to be used as index for L3_INTF table or VID for ContentAware packet change cases

Description: L3 Interface table

Minimum index: 0

Maximum index: 4095

Address: 0x03920000

Table 422: EGR_L3_INTF


75:28 MAC_ADDRESS MAC address to be used for SA replacement in the L3 modifications

27:20 TTL_THRESHOLD TTL threshold to be used for L3 TTL checks

19:8 VID VID to be used for L3 replacement

7 L2_SWITCH Indicates whether the packet needs to be only L2 Switched, and only L2 modifications need to be done.

6:0 TUNNEL_INDEX Tunnel Index to be used to index EGR_IP_TUNNEL table

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ING_L3_NEXT_HOP TABLE

IPV6_PROXY_ENABLE

Description: Reduced version of L3_NEXT_HOP table. Used to provide just mod and port/TGID.

Minimum index: 0

Maximum index: 8191

Address: 0x0D710000

Table 423: ING_L3_NEXT_HOP


24:13 VLAN_ID VLAN ID of next hop

12:7 MODULE_ID Module ID of next hop

6:1 PORT_TGID Port/TGID of next hop

0 L3UC_TUNNEL_TYPE Tunnel type

Description: IPv6 Proxy lookup enable. This table is indexed by the source module ID for HiGig lookup of IPv6IPMC packets.

Minimum index: 0

Maximum index: 63

Address: 0x02730000

Table 424: IPV6_PROXY_ENABLE


0 ENABLE Enable per source module ID

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LPORT

Description: This table is used for HiGig lookups. Only indices 24–28 are used. HiGig lookup must be enabled inHG_LOOKUP to utilize this table. See “HG_LOOKUP” on page 173.

Minimum index: 0

Maximum index: 28

Address: 0x02740000

Table 425: LPORT


67:66 RESERVED Reserved (spare) bit in the PORT_TABLE

65 ALLOW_SRC_MOD Allow packets with MH.SRC_MODID is same as MY_MODID.

64 IGNORE_IPMC_L3_BITMAP Set this bit to disable L3 routing of IPMC pkts on this port.

63 IGNORE_IPMC_L2_BITMAP Set this bit to disable L2 bridging of IPMC pkts on this port.

62 PORT_BRIDGE Allows L2 bridging to the incoming port.

61 VLAN_PRECEDENCE Determine the priorities for selecting VLAN (MAC-based, subnet-based VLANs)



38 MAP_TAG_PKT_PRIORITY Map the incoming packet priority

37 NNI_PORT Port is an NNI port if set to 1, otherwise, a UNI port.

36 HIGIG_PACKET Port is a HiGig port.

35:24 PORT_VID Port VLAN



21 PASS_CONTROL_FRAMES Pass pause frames through without dropping

20 PORT_DIS_UNTAG Drop all untagged packets

19 PORT_DIS_TAG Drop all tagged packets

18 DROP_BPDU When set, ingress drops BPDUs.





13 IPMC_DO_VLAN Unknown

12:10 PORT_PRI Port default priority?

9:7 CML CPU managed learning

6 MIRROR Mirror enable

5 RESERVED Reserved

4 TRUST_DSCP_V6 Ingress port is trusted port, trust incoming IPv6 DSCP

3 TRUST_DSCP_V4 Ingress port is trusted port, trust incoming IPv4 DSCP

2 VT_ENABLE VLAN translation enable

1 VT_MISS_DROP VLAN translation miss drop

0 FILTER_ENABLE Enable filtering

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IPMC_GROUP0 TABLE–MMU_IPMC_GROUP_TBL0


Description: The IPMC_GROUP table 0 is 1024 entries deep and supports a maximum of 1024 IPMC groups for IPMC replication. The table is indexed using the IPMC_PTR from the L3 table, and then the ingress port is used to pick the appropriate pointer. The 11-bit pointer retrieves points to an entry in the IPMC_VLAN table that contains the first set of VLANs for which the IPMC packets are to be replicated.

Minimum index: 0

Maximum index: 1023

Address: 0x0A660000

Table 426: IPMC_GROUP0 Table–MMU_IPMC_GROUP_TBL0


65:55 Port5_1stPtr 11-bit first pointer to LSB VLAN bitmap for port 5







Minimum index: 0

Maximum index: 1023

Address: 0x0A664000









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Minimum index: 0

Maximum index: 1023

Address: 0x0A668000










Minimum index: 0

Maximum index: 1023

Address: 0x0A66C000









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Minimum index: 0

Maximum index: 1023

Address: 0x0A670000




Description: The IPMC_GROUP table 5 is 1024 entries deep and supports a maximum of 1024 IPMC groups for IPMC replication. The table is indexed using the IPMC_PTR from the L3 table, and then the ingress port is used to pick the appropriate pointer. The 11-bit pointer retrieves points to an entry in the IPMC_VLAN table that contains the first set of VLANs for which the IPMC packets are to be replicated for.

Minimum index: 0

Maximum index: 1023

Address: 0x0A674000




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Minimum index: 0

Maximum index: 1023

Address: 0x0A678000





Minimum index: 0

Maximum index: 1023

Address: 0x0A67C000




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IPMC_VLAN TABLE–MMU_IPMC_VLAN_TBL

IM_MTP_INDEX TABLE

Description: IPMC VLAN LSB Bitmap table RAMThe IPMC_VLAN table is 2k entries deep and supports a maximum of 4k replications for a maximum of 32 IPMC groups, or 1k replications for 128 IPMC groups. The table is initially indexed using the pointer retrieved from IPMC_GROUP0– IPMC_GROUP7. Each 96-bit entry consists of 6 bits for the MSB of the new VLAN ID, a 64-bit LSB VLAN bitmap and a pointer to the next VLAN bitmap. The end of replication is signified by the pointer indexing back to its own entry. The LSB VLAN bitmap contains a 1 in the bit position for the LSB VLAN ID to be generated, and the bit position is converted into a hex value indicating the LSB 6 bits of the VLAN ID. For example, LSB_VLAN_BITMAP = 0x00000080, a 1 in bit position 7, and an MSB_VLAN = 0x4 results in a VLAN ID of 0x107. IPMC packet replication exhausts all 1s in the LSB_VLAN_BITMAP and then proceeds to set the VLAN bitmap entry indicated by NEXTPTR.

Minimum index: 0

Maximum index: 2047

Address: 0x0A680000

Table 434: IPMC_VLAN Table–MMU_IPMC_VLAN_TBL


80:75 MSB_VLAN 6-bit MSB for VLAN [11:6]

74:11 LSB_VLAN_BM 64-bit LSB VLAN bitmap

10:0 NextPtr 11 bits next VLAN bitmap pointer

Description: Ingress Mirror to Port table

Minimum index: 0

Maximum index: 3

Address: 0x0E780000

Table 435: IM_MTP_INDEX


11:6 MODULE_ID Mirror to port module ID

5:0 PORT_TGID Mirror to port port/TGID

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EM_MTP_INDEX TABLE

EGR_IM_MTP_INDEX TABLE

EGR_EM_MTP_INDEX TABLE

Description: Egress Mirror to Port table

Minimum index: 0

Maximum index: 3

Address: 0x0E790000

Table 436: EM_MTP_INDEX


11:6 MODULE_ID Mirror to port module ID

5:0 PORT_TGID Mirror to port port/TGID

Description: Mirror to Port table to be used for IM tagged packets. This table is divided into four contiguous groups of eight entries with each of the four groups corresponding to the MTP_INDEX specified by MIRROR_CONTROL (see “MIRROR_CONTROL” on page 154). All eight entries of the group must be programmed with the same values if the MTP is not a trunk group, otherwise the eight entries can correspond to members of the trunk group.

Minimum index: 0

Maximum index: 31

Address: 0x05950000

Table 437: EGR_IM_MTP_INDEX


10:6 MTP_DST_PORT DST_PORT field to be used in module header in case of mirroring

5:0 MTP_DST_MODID DST_MODID field to be used in the module header in case of mirroring

Description: Mirror to Port table. This table is divided into four contiguous groups of eight entries with each of thefour groups corresponding to the MTP_INDEX specified by MIRROR_CONTROL (see“MIRROR_CONTROL” on page 154). All eight entries of the group must be programmed with thesame values if the MTP is not a trunk group, otherwise the eight entries can correspond to membersof the trunk group.

Minimum index: 0

Maximum index: 31

Address: 0x05960000

Table 438: EGR_EM_MTP_INDEX


10:6 MTP_DST_PORT DST_PORT field to be used in module header in case of mirroring

5:0 MTP_DST_MODID DST_MODID field to be used in the module header in case of mirroring

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SOURCE_TRUNK_MAP TABLE–SOURCE_TRUNK_MAP_TABLE

E2E_HOL_STATUS TABLE

BSAFE_CMD_DATA_IN TABLE

Description: Source Trunk Map table. This table is indexed by modid(6 bits) concatenated with port number (5bits) to define whether the ingress port is a trunk port.

Minimum index: 0

Maximum index: 2047

Address: 0x02710000

Table 439: SOURCE_TRUNK_MAP Table–SOURCE_TRUNK_MAP_TABLE


8:2 TGID Source port TGID

1:0 PORT_TYPE Indicates source port type

0 = Normal Port1 = Trunk Port

Description: Remote Module End-to-end HOL Status table

Minimum index: 0

Maximum index: 63

Address: 0x0E770000

Table 440: E2E_HOL_STATUS


255:224 COS7_HOL_BITMAP CoS7 port bitmap








Description: Command Data Out Register

Minimum index: 0

Maximum index: 255

Address: 0x00B10000

Table 441: BSAFE_CMD_DATA_IN


31:0 CMD_DIN Input data for command processing to the µHSM

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BSAFE_CMD_DATA_OUT TABLE

UDF_OFFSET TABLE–FP_UDF_OFFSET

Description: Command Data Out register

Minimum index: 0

Maximum index: 255

Address: 0x00B20000

Table 442: BSAFE_CMD_DATA_OUT


31:0 CMD_DOUT Output data for command processing from the µHSM

Description: User Defined Field (UDF) offset table for the ContentAware engine

Minimum index: 0

Maximum index: 95

Address: 0x02720000

Table 443: UDF_OFFSET Table–FP_UDF_OFFSET


47 UDF2_ADD_IPV4_OPTIONS3 Control bit to enable adding the IPv4 header option length

46:42 UDF2_OFFSET3 Offset value for UDF2.3















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FP_PORT_FIELD_SEL TABLE

Description: Field select value for each slice in the ContentAware engine

Minimum index: 0

Maximum index: 28

Address: 0x0B700000

Table 444: FP_PORT_FIELD_SEL


159:157 SLICE15_F3 F3 field for slice 15





































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The three FPF fields in Table 445 corresponds to each of the three fields for each slice.












Table 445: Intelligent Protocol-Aware Selector Encoding

Name Settings

FPF1 3’b000—IP_TYPE(IPv4/IPv6)[30:29], PBM[28:0]3’b001—MH_Opcode[26:24], Src_Modid[23:18], Src_Port_TGID[17:12], Dst_Modid[11:6], Dst_Port_TGID[5:0]

3’b010—TCP/UDP Src Port[31:16], TCP/UDP Dst Port[15:0]3’b011—Ovid[31:16], Ivid[15:0] (Outer and Inner VLAN ID of 16 bits)3’b100—EtherType[31:16], Ovid[15:0] 3’b101 EtherType[23:8], IP_Protocol[7:0]

3’b110—Inner VLAN ID[31:16], Lookup Status[15:0]Lookup status bit definitions (16 bits)• TUNNEL_HIT [0] Tunnel table hit

• VXLT_HIT [1] VLAN translation hit• VALID_VLAN_ID [2] Valid VLAN• INGRESS_SPG_STATE [4:3] ingress port spanning tree state

• L2_SRC_HIT [5] L2 source lookup hit• L2_SRC_STATIC [6] L2 Source static bit• L2_DST_HIT [7] L2 Destination lookup hit

• L2_TABLE_DST_L3 [8]• L2_USER_ENTRY_HIT [9] L2 User Entry table hit• L3_UC_SRC_HIT [10] L3 source lookup hit

• L3_DST_HIT [11] L3 destination lookup hit• STARGV_HIT [12] IPMC table entry valid• LPM_HIT [13] LPM table lookup hit

• UNRESOLVED_SA [14] L2 source miss/station movement• DOS_ATTACK_PKT [15] Detected as DOS attack packet3’b111—IP_Info[31:29], Pkt_Res[28:25], MH_Ocode[24:22], IP_Type[21:20], Pkt_Format[19:16], Outer VLAN ID[15:0]

FPF2 4’b0000–SIP[127:96], DIP[95:64, IP_Protocol[63:56], L4_Src[55:40], L4_Dst[39:24], DSCP[23:16], IP_Flag[15:14], TCP_Control[13:8], TTL[7:0] 4’b0001–SIP[127:96], DIP[95:64], IP_Protocol[63:56], Range_Chk_Result[55:40], L4_Dst[39:24], DSCP[23:26], IP_Flag[15:14], TCP_Control[13:8], TTL[7:0] 4’b0010–SIP[127:96], DIP[96:64], IP_Protocol[63:56], Range_Chk_Result[55:40], L4_Src[39:24], DSCP[23:16], IP_Flag[15:14], TCP_Control[13:8], TTL[7:0] 4’b0011–IPv6 SIP[127:0] 4’b0100–IPv6 DIP[127:0] 4’b0101 IPv6_DIP_Upper64[113:50], NH[49:42], TC[41:34], FL[33:14], TTL[13:6], TCP_Control[5:0]

4’b0110–DA[127:80], SA[79:32], EtherType[31:16], Ovid[15:0] 4’b0111–SA[111:64], SIP[63:32], EtherType[31:16], Ovid[15:0] 4’b1000–DA[111:64], DIP[63:32], EtherType[31:16], Ovid[15:0]

4’b1001–UDF1[127:0] 4’b1010–UDF2[127:0]4’b1011-IPv6 DIP[127:64], IPv6 SIP[127:64]

Table 444: FP_PORT_FIELD_SEL (Cont.)


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FPF3 3’b000—IP_Info[15:13], Pkt_Res[12:9], IP_TYPE[8:6], Pkt_Format[5:0] 3’b001—MH_Ocode[14:12], Src_Modid[11:6], Src_Port_TGID[5:0]

3’b010—MH_Ocode[14:12], Dst_Modid,[11:6] Dst_Port_TGID[5:0] 3’b011—Lookup Status[15:0]Lookup status bit definitions (16 bits)

• TUNNEL_HIT [0] Tunnel table hit• VXLT_HIT [1] VLAN translation hit• VALID_VLAN_ID [2] Valid VLAN

• INGRESS_SPG_STATE [4:3] ingress port spanning tree state.• L2_SRC_HIT [5] L2 Source lookup hit• L2_SRC_STATIC [6] L2 source static bit

• L2_DST_HIT [7] L2 destination lookup hit• L2_TABLE_DST_L3 [8] Note: This bit is redefined. It should be treated as L3_ROUTEABLE_PKT

• L2_USER_ENTRY_HIT [9] L2 USER ENTRY table hit• L3_UC_SRC_HIT [10] L3 Source lookup hit• L3_DST_HIT [11] L3 Destination lookup hit

• STARGV_HIT [12] IPMC table entry valid• LPM_HIT [13] LPM table lookup hit• UNRESOLVED_SA [14] L2 Source miss/station movement

• DOS_ATTACK_PKT [15] Detected as DOS attack packet3’b100—DSCP[13:6],TCP_Control[5:0]3’b101—Outer VLAN ID[15:0]

3’b110—IP_Protocol[15:8], TOS[7:0]3’b111—Range_Chk_Results[15:0]

Table 445: Intelligent Protocol-Aware Selector Encoding (Cont.)

Name Settings

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IFP_PORT_FIELD_SEL TABLE

Description: Field select value for each slice in the ContentAware engine

Minimum index: 0

Maximum index: 24

Address: 0x0B800000

Table 446: IFP_PORT_FIELD_SEL







































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The three FPF fields in Table 447 corresponds to each of the three fields for each slice.












Table 447: Intelligent Protocol-Aware Selector Encoding

Name Settings

FPF1 3’b000—IP_TYPE(IPv4/IPv6)[30:29], PBM[28:0]3’b001—MH_Opcode[26:24], Src_Modid[23:18], Src_Port_TGID[17:12], Dst_Modid[11:6], Dst_Port_TGID[5:0]

3’b010—TCP/UDP Src Port[31:16], TCP/UDP Dst Port[15:0]3’b011—Ovid[31:16], Ivid[15:0] (Outer and Inner VLAN ID of 16 bits)3’b100—EtherType[31:16], Ovid[15:0] 3’b101 EtherType[23:8], IP_Protocol[7:0]

3’b110—Inner VLAN ID[31:16], Lookup Status[15:0]Lookup status bit definitions (16 bits)• TUNNEL_HIT [0] Tunnel table hit

• VXLT_HIT [1] VLAN translation hit• VALID_VLAN_ID [2] Valid VLAN• INGRESS_SPG_STATE [4:3] ingress port spanning tree state

• L2_SRC_HIT [5] L2 source lookup hit• L2_SRC_STATIC [6] L2 Source static bit• L2_DST_HIT [7] L2 Destination lookup hit

• L2_TABLE_DST_L3 [8]• L2_USER_ENTRY_HIT [9] L2 User Entry table hit• L3_UC_SRC_HIT [10] L3 source lookup hit

• L3_DST_HIT [11] L3 destination lookup hit• STARGV_HIT [12] IPMC table entry valid• LPM_HIT [13] LPM table lookup hit

• UNRESOLVED_SA [14] L2 source miss/station movement• DOS_ATTACK_PKT [15] Detected as DOS attack packet3’b111—IP_Info[31:29], Pkt_Res[28:25], MH_Ocode[24:22], IP_Type[21:20], Pkt_Format[19:16], Outer VLAN ID[15:0]

FPF2 4’b0000–SIP[127:96], DIP[95:64, IP_Protocol[63:56], L4_Src[55:40], L4_Dst[39:24], DSCP[23:16], IP_Flag[15:14], TCP_Control[13:8], TTL[7:0] 4’b0001–SIP[127:96], DIP[95:64], IP_Protocol[63:56], Range_Chk_Result[55:40], L4_Dst[39:24], DSCP[23:26], IP_Flag[15:14], TCP_Control[13:8], TTL[7:0] 4’b0010–SIP[127:96], DIP[96:64], IP_Protocol[63:56], Range_Chk_Result[55:40], L4_Src[39:24], DSCP[23:16], IP_Flag[15:14], TCP_Control[13:8], TTL[7:0] 4’b0011–IPv6 SIP[127:0] 4’b0100–IPv6 DIP[127:0] 4’b0101 IPv6_DIP_Upper64[113:50], NH[49:42], TC[41:34], FL[33:14], TTL[13:6], TCP_Control[5:0]

4’b0110–DA[127:80], SA[79:32], EtherType[31:16], Ovid[15:0] 4’b0111–SA[111:64], SIP[63:32], EtherType[31:16], Ovid[15:0] 4’b1000–DA[111:64], DIP[63:32], EtherType[31:16], Ovid[15:0]

4’b1001–UDF1[127:0] 4’b1010–UDF2[127:0]4’b1011-IPv6 DIP[127:64], IPv6 SIP[127:64]

Table 446: IFP_PORT_FIELD_SEL (Cont.)


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FP_RANGE_CHECK TABLE

FPF3 3’b000—IP_Info[15:13], Pkt_Res[12:9], IP_TYPE[8:6], Pkt_Format[5:0] 3’b001—MH_Ocode[14:12], Src_Modid[11:6], Src_Port_TGID[5:0]

3’b010—MH_Ocode[14:12], Dst_Modid,[11:6] Dst_Port_TGID[5:0] 3’b011—Lookup Status[15:0]Lookup status bit definitions (16 bits)

• TUNNEL_HIT [0] Tunnel table hit• VXLT_HIT [1] VLAN translation hit• VALID_VLAN_ID [2] Valid VLAN

• INGRESS_SPG_STATE [4:3] ingress port spanning tree state.• L2_SRC_HIT [5] L2 Source lookup hit• L2_SRC_STATIC [6] L2 source static bit

• L2_DST_HIT [7] L2 destination lookup hit• L2_TABLE_DST_L3 [8] Note: This bit is redefined. It should be treated as L3_ROUTEABLE_PKT

• L2_USER_ENTRY_HIT [9] L2 USER ENTRY table hit• L3_UC_SRC_HIT [10] L3 Source lookup hit• L3_DST_HIT [11] L3 Destination lookup hit

• STARGV_HIT [12] IPMC table entry valid• LPM_HIT [13] LPM table lookup hit• UNRESOLVED_SA [14] L2 Source miss/station movement

• DOS_ATTACK_PKT [15] Detected as DOS attack packet3’b100—DSCP[13:6],TCP_Control[5:0]3’b101—Outer VLAN ID[15:0]

3’b110—IP_Protocol[15:8], TOS[7:0]3’b111—Range_Chk_Results[15:0]

Description: Values for the range-checking mechanism that is separate from the ContentAware look-up engine.

There are 16 range checkers for matching source or destination UDP/TCP port numbers. The resulting bitmap can be used as input for the ContentAware look-up engine.

Minimum index: 0

Maximum index: 15

Address: 0x0C700000

Table 448: FP_RANGE_CHECK


33 SOURCE_DESTINATION_SELECT Selects whether the source or destination port is range-checked

32 ENABLE Enable range check

31:16 UPPER_BOUNDS Upper bounds of range to be checked

15:0 LOWER_BOUNDS Lower bounds of range to be checked

Table 447: Intelligent Protocol-Aware Selector Encoding (Cont.)

Name Settings

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FP_TCAM TABLE

Description: ContentAware Lookup Engine table that is 128 entries deep for each of the 16 BroadScale™ ContentAware look-up processors. A match to an entry results in the index being sent to the ContentAware policy engine.

Minimum index: 0

Maximum index: 2047

Address: 0x0C720000

Table 449: FP_TCAM


369:338 F1_MASK F1 field MASK



193 IPBM_SEL_MASK Used to indicate the Input Port Bitmap (IPBM) is applied to the TCAM MASK

192 RESERVED_MASK Reserved bit

191:187 F4_MASK F4 field mask

186 PACKET_TYPE_MASK Packet type mask

185:154 F1 F1 field

153:26 F2 F2 field

25:10 F3 F3 field

9 IPBM_SEL Used to indicate the IPBM is applied to the TCAM

8 RESERVED_KEY1 Reserved

7:3 F4 F4 field

2 PACKET_TYPE Indicates if the packet is a HiGig+ (1) or non HiGig+ (0) packet

1:0 VALID Valid bit

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FP_TCAM_PLUS_POLICY TABLE

Description: Composite view for ContentAware Policy engine and ContentAware Lookup engine.

Minimum index: 0

Maximum index: 2047

Address: 0x0C740000

Table 450: FP_TCAM_PLUS_POLICY


511 GREEN_TO_PID GREEN_TO_PID CONTROLS WHETHER PACKET_REDIRECTION and L3SW_CHANGE_MACDA_OR_VLAN are Green (0) or Color Independent (1) actions.

510 ECN_CNG Controls whether drop precedences sets the ECN or CNG bits.

509:506 CHANGE_PRIORITY 0001 = CHANGE_COS. Changes the COS for switched packets to NEWPRIORITY.

0010 = CHANGE_CPU_COS. Changes the CPU_COS for packets trapper (copied) to the CPU to NEWPRIORITY.

0100 = COPY_PKT_AND_INT_PRIORITY. Changes both packet and internal priority to the PRI field from the Inner tag.

0101 = CHANGE_PKT_AND_INT_PRIORITY_NEW. Changes both packet and internal priority to the NEWPRIORITY value.

0110 = CHANGE_PKT_AND_INT_PRIORITY_TOS. Changes both packet and internal priority to the TOS_FIELD value.

0111 = DONOT_CHANGE_PKT_AND_INT_PRIORITY. Overrides CHANGE_PKT_AND_INT_PRIORITY.

1000 = COPY_PKT_PRIORITY2. Changes packet priority only to PRI field from the Inner tag.

1001 = CHANGE_PKT_PRIORITY_NEW. Changes packet priority only to the NEWPRIORITY value.

1010 = CHANGE_PKT_PRIORITY_TOS. Changes packet priority only to the TOS_FIELD value.

1011 = DONOT_CHANGE_PKT_PRIORITY. Overrides CHANGE_PKT_PRIORITY.1100 = COPY_INT_PRIORITY2. Changes internal priority only to the PRI field from the Inner tag.1101 = CHANGE_INT_PRIORITY_NEW. Changes internal priority only to the NEWPRIORITY value.1110 = CHANGE_INT_PRIORITY_TOS. Changes internal priority only to the TOS_FIELD value.1111 = DONOT_CHANGE_INT_PRIORITY. Overrides CHANGE_INT_PRIORITY.

505:503 CHANGE_DSCP_TOS Applies to both IPv4 and IPv6 packets. To apply selectively, use IPv4 or IPv6 in packet format.

000 = No Op001 = New TOS010 = TOS from packet priority011 = New DSCP100 = Do not change DSCP or TOS101 = No Op110 = No Op111 = No Op

502:501 COPY_TO_CPU 00 = No Op10 = Do not copy11 = Override switch copy to CPU

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500:498 PACKET_REDIRECTION Applicable to all packet types:• Unicast

• Broadcast• Multicast• Unknown multicast

• Unknown unicast000 = No Op001 = Redirect. (REDIRECTION field is used to provide DST_MOD and DST_PORT.)010 = Do not redirect.011 = Replace_Port bitmap. (REDIRECTION field is used to provide port bitmap.)100 = Apply egress mask. When enabled, the REDIRECTION field will be used to mask out the egress port. For example, when this is set and REDIRECTION = 0x00000021, packets will not go out of port GE0 and GE5.101 = No Op110 = No Op111 = No Op

497 CHAIN 0 = No Op1 = CHAIN_TWO_SLICES

This is supported for an even/odd pair of BroadScale parallel ContentAware look-up processors only. Both ContentAware look-up processors need the CHAIN bit set. The even numbered look-up processor provides all of the actions and determines the counter and the meter updates.

496:495 DROP 00 = No Op01 = Drop10 = Do not drop11 = No Op

494 MIRROR_OVERRIDE Controls overriding mirror processing


493:492 MIRROR 00 = No Op01 = Ingress mirror10 = Egress mirror11 = Ingress and egress mirror

491:489 L3SW_CHANGE_MACDA_OR_VLAN

000 = No Op001 = Change VLAN010 = Do not change VLAN011 = No Op100 = Change MAC DA101 = Do not change MAC DA110 = L3 switch111 = Do not L3 switch

488:487 DROP_PRECEDENCE 00 = No Op01 = Green10 = Yellow11 = Red

486:485 RP_DROP 00 = No Op01 = Drop10 = Do not drop11 = No Op

484:483 RP_DROP_PRECEDENCE 00 = No Op01 = Green10 = Yellow11 = Red

482:481 RP_COPY_TO_CPU 00 = No Op01 = Copy10 = Do not copy11 = No Op

480 RP_CHANGE_DSCP Applies to both IPv4 and IPv6 packets. To apply selectively, use IPv4 or IPv6 in packet format.0 = No Op1 = RP new DSCP

Table 450: FP_TCAM_PLUS_POLICY (Cont.)


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479:478 YP_DROP 00 = No Op01 = Drop10 = Do not drop11 = No Op

477:476 YP_DROP_PRECEDENCE 00 = No Op01 = Green10 = Yellow11 = Red

475:474 YP_COPY_TO_CPU 00 = No Op01 = Copy10 = Do not copy11 = No Op

473 YP_CHANGE_DSCP Applies to both IPv4 and IPv6 packets. To apply selectively, use IPv4 or IPv6 in packet format.0 = No Op1 = YP new DSCP

472:467 COUNTER_INDEX Counter index

Supports 128 counters per BroadScale ContentAware look-up processor. Counters are organized into pairs of two counters per index

466:463 COUNTER_MODE Counter mode control

462:457 METER_INDEX_ODD Index for odd meters

456:451 METER_INDEX_EVEN Index for even meters

450 METER_UPDATE_ODD Update odd meter when set to 1

449 METER_UPDATE_EVEN Update even meter when set to 1

448 METER_TEST_ODD Use odd meter when set to 1

447 METER_TEST_EVEN Use even meter when set to 1

446:444 METER_PAIR_MODE Selects mode of operation for meters

443:441 NEWPRI New priority

440:435 NEWDSCP_TOS New DSCP TOS

434:429 RP_DSCP RP New DSCP

428:423 YP_DSCP YP New DSCP

422 DO_NOT_CHANGE_TTL Do not change TTL

421:415 MATCHED_RULE MATCHED_RULE

420 ECMP ECMP

419:415 ECMP_COUNT ECMP_COUNT

416:404 NEXT_HOP_INDEX Contains NEXT_HOP_INDEX, ECMP COUNT (4), and ECMP BIT for CHANGE_MAC_DA action, and CHANGE_VLAN ACTION and L3_SWITCH ACTION.

414:404 CLASSIFICATION_TAG 0 = NOOP1 = APPLY_CLASS_TAG

414:404 ECMP_PTR ECMP_PTR

403:375 REDIRECTION Bitmap for redirection actions. When CHAIN = 1 and BroadScale ContentAware look-up processor is odd, the lower seven bits are the CHAIN_INDEX, and the next higher bit is the Valid bit. The rest of the bits are unused.

382 CHAIN_VALID CHAIN_VALID

381:375 CHAIN_INDEX CHAIN_INDEX

374 MTP_INDEX_SPARE MTP_INDEX_SPARE

373:372 IM_MTP_INDEX MTP port index for ingress mirroring

371:370 EM_MTP_INDEX MTP port index for egress mirroring






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193 IPBM_SEL_MASK Used to indicate the Input Port bitmap (IPBM) is applied to the TCAM MASK

192 RESERVED_MASK Reserved bit

191:187 F4_MASK F4 mask

186 PACKET_TYPE_MASK Packet type mask

185:154 F1 F1 field

153:26 F2 F2 field

25:10 F3 F3 field

9 IPBM_SEL Used to indicate the IPBM is applied to the TCAM

8 RESERVED_KEY1 Reserve

7:3 F4 F4 field

2 PACKET_TYPE Indicates if the packet is a HiGig+ (1) or non HiGig+ (0) packet

1:0 VALID Valid bit



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FP_POLICY_TABLE TABLE

Description: Policy table for determining actions in the ContentAware Policy Engine that is divided into 16 slices—128 entries deep for each BroadScale.

Minimum index: 0

Maximum index: 2047

Address: 0x0C750000

Table 451: FP_POLICY_TABLE


141 GREEN_TO_PID GREEN_TO_PID controls whether PACKET_REDIRECTION and L3SW_CHANGE_MACDA_OR_VLAN are Green (0) or Color Independent (1) actions.

140 ECN_CNG Controls whether drop precendence sets ECN or CNG bits.

139:136 CHANGE_PRIORITY 0001 = CHANGE_COS. Changes the COS for switched packets to NEWPRIORITY.0010 = CHANGE_CPU_COS. Changes the CPU_COS for packets trapper (copied) to the CPU to NEWPRIORITY.0100 = COPY_PKT_AND_INT_PRIORITY. Changes both packet and internal priority to the PRI field from the Inner tag.0101 = CHANGE_PKT_AND_INT_PRIORITY_NEW. Changes both packet and internal priority to the NEWPRIORITY value.0110 = CHANGE_PKT_AND_INT_PRIORITY_TOS. Changes both packet and internal priority to the TOS_FIELD value.0111 = DONOT_CHANGE_PKT_AND_INT_PRIORITY. Overrides CHANGE_PKT_AND_INT_PRIORITY.1000 = COPY_PKT_PRIORITY2. Changes packet priority only to PRI field from the Inner tag.1001 = CHANGE_PKT_PRIORITY_NEW. Changes packet priority only to the NEWPRIORITY value.1010 = CHANGE_PKT_PRIORITY_TOS. Changes packet priority only to the TOS_FIELD value.1011 = DONOT_CHANGE_PKT_PRIORITY. Overrides CHANGE_PKT_PRIORITY.1100 = COPY_INT_PRIORITY2. Changes internal priority only to the PRI field from the Inner tag.1101 = CHANGE_INT_PRIORITY_NEW. Changes internal priority only to the NEWPRIORITY value.1110 = CHANGE_INT_PRIORITY_TOS. Changes internal priority only to the TOS_FIELD value.1111 = DONOT_CHANGE_INT_PRIORITY. Overrides CHANGE_INT_PRIORITY.

135:133 CHANGE_DSCP_TOS Applies to both IPv4 and IPv6 packets. To apply selectively, use IPv4 or IPv6 in packet format.

000 = No Op001 = New TOS010 = TOS from packet priority011 = New DSCP100 = Do not change DSCP or TOS101 = No Op110 = No Op111 = No Op

132:131 COPY_TO_CPU 00 = No Op01 = Copy10 = Do not copy11 = Override switch copy to CPU

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130:128 PACKET_REDIRECTION Applicable to all packet types:• Unicast

• Broadcast• Multicast• Unknown multicast

• Unknown unicast000 = No Op001 = Redirect010 = Do not redirect011 = Replace_Port bitmap100 = Apply egress mask101 = No Op110 = No Op111 = No Op

127 CHAIN 0 = No Op1 = CHAIN_TWO_SLICESThis is supported for an even odd pair of BroadScale parallel ContentAware look-up processors only. Both ContentAware look-up processors need the CHAIN bit set. The even numbered look-up processor provides all of the actions and determines the counter and the meter updates.

126:125 DROP 00 = No Op01 = Drop10 = Do not drop11 = No Op

124 MIRROR_OVERRIDE Controls overriding mirror processing0 = Disable1 = Enable

123:122 MIRROR 00 = No Op01 = Ingress mirror10 = Egress mirror11 = Ingress and egress mirror

121:119 L3SW_CHANGE_MACDA_OR_VLAN 000 = No Op001 = Change VLAN010 = Do not change VLAN011 = No Op100 = Change MAC DA101 = Do not change MAC DA110 = L3 switch111 = Do Not L3 switch

118:117 DROP_PRECEDENCE 00 = No Op01 = Green10 = Yellow11 = Red

116:115 RP_DROP 00 = No Op01 = Drop10 = Do not drop11 = No Op

114:113 RP_DROP_PRECEDENCE 00 = No Op01 = Green10 = Yellow11 = Red

112:111 RP_COPY_TO_CPU 00 = No Op01 = Copy10 = Do not copy11 = No Op

110 RP_CHANGE_DSCP Applies to both IPv4 and IPv6 packets. To apply selectively, use IPv4 or IPv6 in packet format.0 = No Op1 = RP new DSCP

109:108 YP_DROP 00 = No Op01 = Drop10 = Do not drop11 = No Op

Table 451: FP_POLICY_TABLE (Cont.)


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107:106 YP_DROP_PRECEDENCE 00 = No Op01 = Green10 = Yellow11 = Red

105:104 YP_COPY_TO_CPU 00 = No Op01 = Copy10 = Do not copy11 = No Op

103 YP_CHANGE_DSCP Applies to both IPv4 and IPv6 packets. To apply selectively, use IPv4 or IPv6 in packet format.

0 = No Op1 = YP new DSCP

102:97 COUNTER_INDEX Counter index.Supports 128 counters per BroadScale ContentAware look-up processor. Counters are organized into pairs of two counters per index.

96:93 COUNTER_MODE Counter mode control

92:87 METER_INDEX_ODD Index for odd meters

86:81 METER_INDEX_EVEN Index for even meters

80 METER_UPDATE_ODD Update odd meter when set to 1

79 METER_UPDATE_EVEN Update even meter when set to 1

78 METER_TEST_ODD Use odd meter when set to 1

77 METER_TEST_EVEN Use even meter when set to 1

76:74 METER_PAIR_MODE Selects mode of operation for meters

73:71 NEWPRI New priority

70:65 NEWDSCP_TOS New DSCP TOS

64:59 RP_DSCP RP new DSCP

58:53 YP_DSCP YP new DSCP

52:45 MATCHED_RULE MATCHED_RULE

52 DO_NOT_CHANGE_TTL Do not change TTL


50 ECMP ECMP

49:45 ECMP_COUNT ECMP_COUNT

46:34 NEXT_HOP_INDEX Contains NEXT_HOP_INDEX, ECMP COUNT (4), and ECMP BIT for CHANGE_MAC_DA action, and CHANGE_VLAN action and L3_SWITCH action.

44:34 CLASSIFICATION_TAG 0 = NOOP1 = APPLY_CLASS_TAG.

44:34 ECMP_PTR ECMP_PTR

33:5 REDIRECTION Bitmap for redirection actions. When CHAIN = 1 and BroadScale ContentAware lookup processor is odd, the lower seven bits are the CHAIN_INDEX, and the next higher bit is the Valid bit. The rest of the bits are unused.

12 CHAIN_VALID CHAIN_VALID

11:5 CHAIN_INDEX CHAIN_INDEX

4 MTP_INDEX_SPARE MTP_INDEX_SPARE

3:2 IM_MTP_INDEX MTP port index for ingress mirroring

1:0 EM_MTP_INDEX MTP port index for egress mirroring

Table 451: FP_POLICY_TABLE (Cont.)


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FP_METER_TABLE TABLE

FP_COUNTER_TABLE TABLE

Description: Meter table structures for the ContentAware Metering engine. The table is divided into 16 slices of 128 entries containing 64 odd meters and 64 even meters.

Minimum index: 0

Maximum index: 2047

Address: 0x0C760000

Table 452: FP_METER_TABLE


55:54 RESERVED_UNUSED Reserved

53 REFRESH_MODE 0 = trTCM refreshing mode1 = srTCM refreshing mode

52:34 REFRESHCOUNT Number of tokens added to BUCKETCOUNT every 7.8125 µS

33:30 BUCKETSIZE Maximum burst size: 4’d0: BUCKETSIZE = 4K4’d1: BUCKETSIZE = 8K4’d2: BUCKETSIZE = 16K4’d3: BUCKETSIZE = 32K4’d4: BUCKETSIZE = 64K4’d5: BUCKETSIZE = 128K4’d6: BUCKETSIZE = 256K4’d7: BUCKETSIZE = 512K4’d8: BUCKETSIZE = 1M4’d9: BUCKETSIZE = 2M4’d10: BUCKE_SIZE = 4M4’d11: BUCKETSIZE = 8M4’d12: BUCKETSIZE = 16M

29:0 BUCKETCOUNT Number of tokens available

Description: Counter table for the ContentAware Statistics engine. The entries are organized into 16 128 entry slices as indexed by the policy table. The LOWER_COUNTER is indexed by the policy table while the UPPER_COUNTER is indexed by the policy table value + 1.

Minimum index: 0

Maximum index: 2047

Address: 0x0C770000

Table 453: FP_COUNTER_TABLE


31:0 COUNTER Counter entries

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Section 19: DMA, Interrupts, and Endianess

PCI INTERRUPTS

The StrataXGS device uses the PCI_INTA interrupt line to generate interrupts for a variety of reasons. The list belowsummarizes these interrupts and the associated processing that should be performed by the Interrupt Service Routine (ISR)registered at startup. To avoid race conditions, the ISR should be installed and properly configured before any ports areenabled or before the StrataXGS device is brought online.

Two registers are provided to manage the interrupt state and sources:

• The Interrupt Mask Register, CMIC_IRQ_MASK, provides the mechanism to selectively enable and disable interruptsources.

• The Interrupt Status Register, CMIC_IRQ_STAT, provides the cause of the interrupt.

When receiving an interrupt, the CPU should read the CMIC_IRQ_STAT register, mask it with the contents of theCMIC_IRQ_MASK register, and then check which bits are set. Each bit represents a pending interrupt that must beprocessed and cleared.

Table 454 shows the actions that should be taken when an interrupt is received, and how to clear the interrupt conditionbefore returning.

Table 454: PCI Interrupts

IRQ_SCH_MSG_DONE

Description: S-channel command execution is complete.

Action: Wake up a semaphore that is being waited on by the task that started the S-channel operation. That task can then decode the S-channel response in the S-channel message buffers.

Clear: Write 0x01 to CMIC_SCHAN_CTRL, thereby resetting the CMIC_SCHAN_CTRL.MSG_DONE bit.

IRQ_MIIM_OP_DONE

Description: MIIM operation is complete.

Action: An MIIM operation is complete. Wake up a semaphore waited on by the task that started the MIIM operation.

Clear: Write 0x12 to CMIC_SCHAN_CTRL, resetting CMIC_SCHAN_CTRL.MIIM_OP_DONE.

IRQ_LINK_STAT_MOD

Description: Link status has changed on any one of the links

Action: Upon receiving this interrupt, you can read the read the CMIC_LINK_STAT register, which contains a bitmap of links that are currently up. Alternatively, you can schedule a task to perform a more sophisticated task that cannot be done in the interrupt routine, such as reading the PHY registers and determining the link speed that was auto-negotiated.

Clear: Write 0x08 to CMIC_SCHAN_CTRL, resetting CMIC_SCHAN_CTRL.LINK_STAT_MSG.

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IRQ_DESC_DONE0 through IRQ_DESC_DONE3

Description: DMA on the specified channel’s descriptor is complete.

Action: One or more DMA descriptors is complete. You can check the status bits in descriptor(s) to find out how many are complete, and possibly release the descriptor immediately or wait until later. You can also wake up a semaphore to notify the task that is handling DMAs.

Clear: Write 0x08, 0x09, 0x0a, or 0x0b to CMIC_DMA_STAT, resetting the DESC_DONE bit corresponding to channel 0 through 3, respectively.

IRQ_CHAIN_DONE 0–3

Description: DMA on the entire chain of descriptors on the specified channel is complete.

Action: A DMA chain is complete and the DMA has stopped. You can wake up a semaphore to notify a task that is handling DMAs.

Clear: Write 0x04, 0x05, 0x06, or 0x07 to CMIC_DMA_STAT, resetting the CHAIN_DONE bit corresponding to channel 0 through 3, respectively.

IRQ_PCI_PARITY_ERR

Description: Parity Error during PCI bus transaction.

Action: Log the occurrence of a PCI parity error.

Clear: Write 0x0a to CMIC_SCHAN_CTRL, resetting CMIC_SCHAN_CTRL.PCI_PARITY_ERR_CLR.

IRQ_PCI_FATAL_ERR

Description: Fatal Error during PCI bus transaction.

Action: Log the occurrence of a PCI fatal error.

Clear: Write 0x09 to CMIC_SCHAN_CTRL, resetting CMIC_SCHAN_CTRL.PCI_FATAL_ERR_CLR.

IRQ_SCHAN_ERR

Description: Messaging Error has occurred indication.

Action: Log the occurrence of an S-channel error. Read the CMIC_SCHAN_ERROR and include the relevant information in the error message.

Clear: Reading the CMIC_SCHAN_ERR register automatically clears the interrupt.

IRQ_I2C_INTR

Description: I2C operation related interrupts.

Action: An I2C interrupt has occurred. The I2C driver must process the complex state machine for mastering the I2C bus.

Clear: Set CMIC_I2C_CTRL.INT_FLAG to 0.

IRQ_L2_MOD_FIFO_NOT_EMPTY

Description: L2 MOD FIFO is full.

Action: Log a warning message or do nothing.

Clear: This interrupt remains pending as long as the MOD_FIFO is full. The handler must unmask the interrupt in the CMIC_IRQ_MASK register. Another task must re-enable the interrupt after the MOD_FIFO full condition is no longer present.

Table 454: PCI Interrupts (Cont.)

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IRQ_BSAFE_OP_DONE

Description: BroadSAFE operation complete.

Action: Wake up a semaphore that is being waited on by the task that started the BSAFE operation.

Clear: Set the CMIC_IRQ_MASK register to mask this interrupt until cleared by hardware.

IRQ_TSLAM_DONE

Description: Slam DMA operation complete.

Action: Wake up a semaphore that is being waited on by the task that started the slam DMA operation.

Clear: Write 0 to CMIC_SLAM_DMA_CFG.DONE.

IRQ_TDMA_DONE

Description: Table DMA operation complete.

Action: Wake up a semaphore that is being waited on by the task that started the table DMA operation.

Clear: Write 0 to CMIC_TABLE_DMA_CFG.DONE.

IRQ_MEM_FAIL

Description: MMU memory failed.

Action: Log a warning message or do nothing.

Clear: Set the CMIC_IRQ_MASK register to mask this interrupt until cleared by hardware.

IRQ_STAT_ITER_DONE

Description: Stats DMA iteration complete interrupt.

Action: Wake up a semaphore that is being waited on by the task that started the Stats DMA operation.

Clear: Write 0xD to CMIC_DMA_STAT.

Table 454: PCI Interrupts (Cont.)

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PACKET DATA TRANSFER

The StrataXGS device supports Packet DMA, Counter (Statistic) DMA, and Table DMA. The Packet DMA is for transferringpackets from/to the CPU. The counter DMA is for gathering the on-chip statistic counters and the Table DMA is helpful incopying any switch table to system memory.

DMA OPERATIONS

The StrataXGS CMIC supports a four-channel DMA controller that operates as a PCI bus master when:

• PCI Bus Master enable is set in the PCI Configuration space command register

• Packet DMA is enabled

Each of the four DMA channels can be configured for transmit or receive. Transmit indicates data transfer from PCI memoryto the StrataXGS (and possibly the network); receive indicates transfer from the StrataXGS to PCI memory. The DMAcontroller supports scatter/gather of packet data in PCI memory, and gather of DMA Control Blocks (DCBs). The DMAengines are programmed using DCBs in PCI memory, and the following CMIC PCI memory mapped registers:CMIC_CHx_DMA_DESC, CMIC_DMA_STAT and CMIC_DMA_CTRL.

The CMIC should provide support for three separate channels on the receive DMA and one for transmit DMA. This allowsmapping of the CoS queues into these three receive DMA channels. This is accomplished when system software providesthree sets of descriptors to be able to process all of the packets in the high-priority descriptor set before processing the low-priority descriptor set. Although four DMA channels are supported, only one can be in use (active) at a given point in timefor a given direction (transmit or receive).

PCI parity and fatal errors are tracked during master operations. In the event of such fatal errors, the DMA channel thatcaused the failure is reflected in the DMA Status and Control register: CMIC_DMA_STAT[30:29] for parity errors andCMIC_DMA_STAT[25:24] for fatal errors. All further DMA operations are suspended until the CPU explicitly clears thePCI_FATAL_ERROR bit in the Status and Control register (CMIC_SCHAN_CTRL[9]).

CoS Based DMA Receive (RX)—DMA Memory Write

The BCM56500 supports multiple simultaneous DMA memory write operations (RX) based on CoS. This allows the CPU toreceive packets based on CoS.

This feature is enabled by setting the COS_Rx_EN register to 1 (bit 24 in the CMIC_CONFIG register). Eight CoS queuesare supported. Each DMA channel has a bit to select the CoS that needs to be used for the receive DMA channel. More thanone CoS can be enabled for a given DMA channel. Note that if a specific CoS is not enabled through any DMA receivechannel, packets received with that CoS is purged by CMIC and is not to be transferred (written) to system memory.

To enable this feature, first select the DMA Write (receive) channels and program the CoS that each DMA channel is requiredto transfer. Next, enable COS_Rx_EN (set to 1). Finally enable the DMA Write channels. If there is more than one DMA Write(Rx) channel enabled, it must be enabled in a single write operation to the DMA control register.

Note: There should be a unique channel for each CoS/DMA RX Channel selected to receive packets. A specificCoS enabled through multiple receive DMA channels is a programming error and could result in hangs or otherundesired behavior.

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DMA REGISTERS

The DMA registers are a set of DMA control and status registers that program DMA transfers. They are:

• CMIC_DMA_DESC0—DMA Channel 0 descriptor address




These registers program the 32-bit DMA address in host system memory, where the respective descriptor chains reside.The CMIC_CHx_DMA_DESC registers can be programmed directly using PIO operations, or indirectly using DMAdescriptors with the RLD bit set.

CMIC_DMA_CTRL—DMA Control Register

This register controls the direction of the transfers, and the modification of the port bitmap based on CoS availability, linkstatus, HOL blocking status, and so forth. For control messages, such as BPDU, GMRP, and GVRP, the port bitmap shouldnot be modified.

CMIC_DMA_STAT—Status and Control Register

This register controls resetting of all DMA channels and enabling of DMA on each channel. As a status register, it is used tomonitor the activity of each of the channels, read the channel number that caused PCI parity or fatal errors, and trackcompletion of DMA transfer for a given descriptor and a given chain for each channel.

DMA DESCRIPTORS

The DMA controller uses chains of DMA Control Blocks (DCBs). With the BCM56500, an extended DCB is available that iscomprised of ten 32-bit words. This expanded descriptor is required for supporting more than 32 modules in a system. Theexpanded DCB is enabled by setting CONFIG.EXTENDED_DCB_ENABLE = 1. This DCB is used by the Broadcom SDKsoftware. The original DCB format can still be used; however, it is not supported by SDK on the BCM56500. The DCBcontains all of the information required for a packet data transfer. DCBs can be chained together to form a physicallycontiguous array, and/or linked to permit gathering of descriptor arrays from multiple independent locations in memory.DCBs must be aligned on 4-byte boundaries. Failure to do so results in undefined operation.

Each DMA channel operates independently with regards to DCBs, but if more than one channel is active for a given type ofoperation, interactions between them are undefined and will almost certainly result in incorrect operation.

Note: Byte-swapping in software may or may not be required. See “Hardware Endian Modes” on page 399 for moreinformation.

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Table 455 shows the format for the expanded DCB descriptor. All reserved bits should be initialized to be 0s.

• Blocks 0–4 and 10 are used for TX.

• All blocks are used for RX.

Table 455: DMA Control Block Format

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 MEMORY ADDESS

1 Reserved PURGE

PAUSE

STAT

HG RLD

SG C TRANSFER BYTE COUNT

2 SOP HGI CNG1

HDR_EXT_LEN

SRC_MODID_6

DST_MODID_6

VLAN_PRI VLAN_CFI

VID_HIGH VID_LOW

3 SRC_MODID[4:0] OPCODE PFM SRC_PORT_TGID DEST_PORT COS HDR_FMT

CNG

DST_MODID[4:0]

4 DST_T

DST_TGID INGRESS_TAGGED

MIRROR_ONLY

MIRROR_DONE

MIRROR

SRC_MOD_5

DST_MOD_5

L3 LABEL_PRESENT

VC_LABEL_19_16

VC_LABEL_15_8 VC_LABEL_7_0

5 ADD_VID

BPDU

CELL_ERROR

CHG_TOS

CPU_COS COS EMIRROR

IMIRROR

L3 INTF NUMBER L3IPMC

L3ONLY

L3UC

MTP_INDEX_HI

6 MTP_INDEX_L

O

PKT_AGED

PURGE_CELL

SRC_HG

SWITCH_PKT

CRC_REGEN

REASON

7 DECAP

MATCH_RULE NH_INDEX SRC_PORT DSCP_HI

8 DSCP_LO OUTER_PRI OUTER_CFI

OUTER_VID UNTAGGED

Reserved

9 RESERVED

10 DONE

Reserved ERR

START

END

TRANSFERRED BYTE COUNT

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Table 456: DMA Control Block Fields

Offset Bits Field Description

Block 0 [31:0] MEMORY ADDRESS 32-bit physical memory address in PCI space where data is read from (transmit operation), written to (receive operation), or the location of the next DCB to execute if RLD = 1. For more information of alignment requirements, see “DMA Alignment Requirements” on page 382.

Block 1 [31:23] RESERVED Reserved

Block 1 [22] PURGE Purge bit; when set to 1, this bit indicates that the packet is to be purged (TX).

Block 1 [21] PAUSE Pause frame; when set to 1, this bit indicates that the packet is a pause frame (TX).

Block 1 [20] STAT Update stats; when set to 1, stats are to be updated (TX).

Block 1 [19] HG HiGig bit; When set to 1, indicates packet with HiGig header (TX).

Block 1 [18] RLD Reload descriptor. For both transmit and receive functions, if 1, the memory address indicates the location of the next DCB to execute. This command essentially allows gathers of DCB arrays. If C = 1 (chaining) is also set, DMA execution continues uninterrupted. If C = 0, the CMIC_CHx_DMA_DESC register is reloaded with the value in DCB.MEMORY_ADDRESS, and DMA processing stops. This field is considered reserved and must be 0 if CMIC_CONFIG.SG_RELOAD_ENABLE is 0.

Block 1 [17] SG Scatter gather bit. For transmit functions, this bit indicates the next DCB that describes the same packet as the current DCB. For receive functions, this bit, if 1, indicates that the next DCB can be used to continue storing data for the current packet if the current DCB does not consume all of the data. If 0, at most the TRANSFERED_BYTE_COUNT bytes are stored from the packet, and any remaining data is discarded. This field is considered reserved and must be 0 if CMIC_CONFIG.SG_ENABLE is 0.

Block 1 [16] C Chain bit; when set to 1, this bit indicates that the next sequential descriptor is valid. If it is set to 0, it indicates that the current descriptor is the last of the chain of descriptors.

Block 1 [15:0] TRANSFER BYTE COUNT Byte count for the transfer. Maximum of 32 Kbytes per packet.

Block 2 [31:24] SOP Start-of-packet symbol

Block 2 [23:22] HGI HiGig+ Interface Format:00 = Reserved01 = Pure preamble, standard framing for 10 GbE10 = HiGig+ header11 = Reserved

The default length of the HiGig+ module header is 12 bytes. Any additional header bytes are indicated in the HDR_EXT_LEN field.

Block 2 [21] CNG_HIGH Congestion flag, set by the FFP of the ingress port

Block 2 [20:18] HDR_EXT_LEN Only valid if HGI == 2’b10. Each unit represents 4 bytes.

Block 2 [17] SRC_MODID_6 Source MODID[6]

Block 2 [16] DST_MODID_6 Destination MODID[6]

Block 2 [15:13] VLAN_PRI VLAN priority

Block 2 [12] VLAN_CFI VLAN CFI bit

Block 2 [11:8] VID_HIGH VLAN ID upper

Block 2 [7:0] VID_LOW VLAN ID lower

Block 3 [31:27] SRC_MODID[4:0] Source MODID[4:0]

Block 3 [26:24] OPCODE HiGig+ opcode, indicates the packet type. 000 = CPU-to-CPU packet 001 = known unicast 010 = bcast/DLF011 = L2 multicast 100 = L3 multicast101 = RESV 110 = RESV 111 = RESV.

Block 3 [23:22] PFM Port filtering mode, used for L2MC and IPMC packets

Block 3 [21:16] SRC_PORT_TGID Source port number or source TGID of the ingress port

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Block 3 [15:11] DEST_PORT Destination port for known unicast packets (opc=1)

Block 3 [10:8] COS Class of service priority

Block 3 [7:6] HDR_FMT Header type. Indicates overlay 1 or 2. 00 = overlay 1 (mirroring)01 = overlay 2 (classification tag)

Block 3 [5] CNG_LOW Congestion flag, set by the FFP of the ingress port

Block 3 [4:0] DST_MODID[4:0] Destination MODID[4:0]

Block 4 [31:16] CLASSIFICATION_TAG Classification tag (if HDR_FMT=1)

Block 4 [31] DST_T Destination trunk bit

Block 4 [30:28] DST_TGID Destination TGID

Block 4 [27] INGRESS_TAGGED Tagged packet was received at the ingress port

Block 4 [26] MIRROR_ONLY Mirror the packet

Block 4 [25] MIRROR_DONE Mirroring is done

Block 4 [24] MIRROR Mirror

Block 4 [23] SRC_MOD_5 Source MODID[5]

Block 4 [22] DST_MOD_5 Destination MODID[5]

Block 4 [21] L3 L3 packet

Block 4 [20] LABEL_PRESENT Packet contains a 20-bit VC label

Block 4 [19:16] VC_LABEL_19_16 VC Label [19:16]

Block 4 [15:8] VC_LABEL_15_8 VC Label [15:8] VFI & VFI Overlay RESV [7:6] VFI_HI [5:0]

Block 4 [7:0] VC_LABEL_7_0 VC Label [7:0] VFI & VFI Overlay VFI_LO [7:6] VFI_GROUP [5:3] OPCODE [2] MPLS_FLAGS [1:0]

Block 5 [31] ADD_VID VLAN ID added

Block 5 [30] BPDU BPDU packet

Block 5 [29] CELL_ERROR Cell CRC checksum error detected

Block 5 [28] CHG_TOS DSCP changed

Block 5 [27:25] CPU_COS CPU COS

Block 5 [24:22] COS Packet priority

Block 5 [21] EMIRROR Egress mirroring

Block 5 [20] IMIRROR Ingress mirroring

Block 5 [19:8] L3_INTF_NUMBER L3 interface number

Block 5 [7] L3IPMC L3 IPMC

Block 5 [6] L3_ONLY L3 only

Block 5 [5] L3_UC L3 UC

Block 5 [4:0] MTP_INDEX_HI Mirror-to-port index

Block 6 [31:30] MTP_INDEX_LO Mirror-to-port index

Block 6 [29] PKT_AGED Packet is aged

Block 6 [28] PURGE_CELL Packet is marked purged

Block 6 [27] SRC_HG Source is HiGig

Block 6 [26] SWITCH_PKT Switched packet

Block 6 [25] SRC_REGEN Regenerate CRC

Table 456: DMA Control Block Fields (Cont.)


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DMA ALIGNMENT REQUIREMENTS

The value of CMIC_CONFIG.IGNORE_ADR_ALIGN_EN controls the alignment requirements of the DMA controller.Regardless of the set t ing of th is va lue, receive operat ions requi re al l buf fers to be 4-byte a l igned(DCB.MEMORY_ADDRESS) and multiples of 4 bytes in length (DCB.TRANSFER_BYTE_COUNT). The DMA controller

Block 6 [24:0] REASON CPU opcode• L3_MTU_CHECK_FAIL, 22, bit 22—L3 MTU check fail to CPU

• PARITY_ERROR, 21, bit 21—Parity error on IP tables• L3_SLOWPATH, 20, bit 20—L3 slow path CPU processed packets• ICMP_REDIRECT, 19, bit 19—ICMP redirect copy to CPU

• MTU_CHECK_FAIL, 18, bit 18—L2 MTU check fail to CPU• CPU_TUNNEL_ERR, 17, bit 17—tunnel error trap to CPU• CPU_MARTIAN_ADDR, 16, bit 16—Martian address trap to CPU

• CPU_DOS_ATTACK, 15, bit 15—DOS attack trap to CPU• CPU_PROTOCOL_PKT, 14, bit 14—Protocol Packet• CPU_L3HDR_ERR, 13, bit 13—L3 header: IP options, TTL=0, !IPv4 etc.

• CPU_FFP, 12, bit1 2—FFP action: copy to CPU• CPU_IPMC_MISS, 11, bit 11—IPMC miss: {SIP, DIP} miss or DIP miss

• CPU_MC_MISS, 10, bit 10—MC miss• CPU_L3SRC_MOVE, 9, bit 9—Station movement: L3• CPU_L3DST_MISS, 8, bit 8—L3 DIP miss

• CPU_L3SRC_MISS, 7, bit 7—L3 SIP miss• CPU_SFLOW_DST, 6, bit 6—sFlow: Dst• CPU_SFLOW_SRC, 5, bit 5—sFlow: Src

• CPU_L2CPU, 4, bit 4—L2_TABLE: copy to CPU• CPU_L2MOVE, 3, bit 3—Station movement: L2• CPU_DLF, 2, bit 2—DLF

• CPU_SLF, 1, bit 1—SLF• CPU_UVLAN, 0, bit 0—CPU Learn bit is set in PTABLE and SA is learnt;

unknown VLAN; VID = 0xFFF

Block 7 [31] DECAP Decap IP tunneling packet

Block 7 [30:20] MATCH_RULE Matched rule

Block 7 [19:7] NH_INDEX Next hop index

Block 7 [6:2] SRC_PORT Source port

Block 7 [1:0] DSCP_HI New DSCP

Block 8 [31:26] DSCP_LO New DSCP

Block 8 [25:23] OUTER_PRI Outer VLAN priority

Block 8 [22] OUTER_CFI Outer VLAN CFI

Block 8 [21:9] OUTER_VID Outer VLAN ID

Block 8 [8] UNTAGGED Double tagged packet ingressed untagged


Block 9 [31:0] RESERVED Description

Block 10 [31] DONE When set, indicates that current DESCRIPTOR execution is complete—the DMA transfer is done (CPU RX).


Block 10 [18] ERR Internal packet error (used for RX only)

Block 10 [17] START Start of packet (used for RX only)

Block 10 [16] END End of packet (used for RX only)

Block 10 [15:0] TRANSFERRED_BYTE_COUNT Total transferred bytes

Table 456: DMA Control Block Fields (Cont.)


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always writes a full 4-byte quantity, but for a received packet that does not contain a multiple of 4 bytes, only the firstDCB.TRANSFERRED_BYTE _COUNT bytes are valid.

For transmit operations, if CMIC_CONFIG.IGNORE_ADR_ALIGN_EN is 0, DCB.MEMORY_ADDRESS must be aligned ona 4-byte boundary , bu t can ind ica te any number of by tes for DCB.TRANSFER_BYTE_COUNT. I fCMIC_CONFIG.MIS_ALIGN_DMA_EN = 1, DCB.MEMORY_ADDRESS can specify a buffer on an arbitrary alignment.

DCBs are always aligned on 4-byte boundaries.

DMA PROGRAMMING

The first step for all DMA operations, both transmit and receive, is to set up the DCBs in PCI memory.

• DCB.MEMORY_ADDRESS fields must be filled in for all operations.

DMA Transmit (Transmit)

• Memory Address—physical memory address visible in PCI space where packet or packet segment resided. See “DMAAlignment Requirements” on page 387 for valid address boundaries

• Transfer Byte Count—the total number of bytes to be transferred

• C—set to 1 to continue processing the next DCB

• S/G—set to 1 if the packet described by the current DCB is continued with the next DCB

• RLD—set to 1 to use MEMORY_ADDRESS to specify the location of the next DCB

• STAT—set to 1 if the stats are to be updated

• PAUSE—set to 1 if this packet is a pause frame

• PURGE—set to 1 if this packet is to be purged

• HG—set to 1 if this packet is a HG frame

• Blocks 2–4 specify HG module header if HG bit set to 1

• Transferred byte count—total number of bytes transferred

The CPU TX interface in XGS 3 has been modified so that packets from the CPU are processed by the ingress logic in muchthe same way as other ports. The CPU can send either a HiGig formatted packet or a standard ethernet packet, dependingupon how the HG bit is set in Block 0. If HG is set to 1, the following three blocks will contain the HiGig module header.

Table 457: “Transmit DCB Special Functions,” on page 388 describes the combinations of C, S/G, and RLD for transmitDCBs and their meaning.

Note: We recommend that all of the following to be enabled (set to 1) in CMIC_CONFIG:

• MIS_ALIGN_DMA_EN

• EN_SG_OPN

• EN_RLD_OPN

Table 457: Transmit DCB Special Functions

S/G RLD C Resulting Action

0 0 0 The current DCB describes the last segment of a packet; DMA processing ends after the current descriptor is complete. If enabled, DMA descriptor done and DMA chain done interrupts are posted on completion.

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DMA Receive (RX)

• Memory Address—address of memory location in PCI space to store packet (or part of a packet). Must be 4-bytealigned

• Transfer Byte Count—maximum number of bytes to transfer for this DCB

• C—set to 1 to continue processing next DCB

• S/G—set to 1 if the next DCB can be used to continue storing the same packet if the Transfer Byte Count is notsufficient to store the remainder of the packet

• RLD—set to 1 to use MEMORY ADDRESS to specify the location of the next DCB

All other fields should be initialized to 0 before starting the DMA operation.

Table 458 on page 389 describes the combinations of C, S/G, and RLD for receive DCBs and their meaning.

0 0 1 The current descriptor describes the last segment of a packet; DMA processing continues with the descriptor immediately following the current descriptor in memory after the current one is complete. If enabled, DMA descriptor done interrupt is posted on completion.

0 1 0 The DMA descriptor address register is reloaded with the address specified in the DCB.MEMORY_ADDRESS field. No packet data transfer is performed. This descriptor cannot be used to indicate the end of a packet if the previous DCB indicated S/G = 1. If enabled, DMA descriptor done and DMA chain done interrupts are posted on completion. After chain done is indicated, DCB processing can be continued at the new location by clearing the chain done indication in CMIC_DMA_STAT and re-enabling DMA in the CMIC_DMA_STAT register for the current channel.

0 1 1 No packet data transfer is performed. This descriptor cannot be used to indicate the end of a packet if the previous DCB indicated S/G = 1. If enabled, a DMA descriptor done interrupt is posted. DMA execution continues at the address specified in the DCB.MEMORY_ADDRESS field of the DCB.

1 0 0 The current DCB describes one segment in a multisegment packet. DMA processing ends after the current DCB is complete, but the packet is not complete and is not transmitted until a DCB is executed without the S/G bit set.

1 0 1 The current DCB describes one segment in a multi-segment packet. DMA processing continues with the DCB immediately following the current DCB in memory. If enabled, DMA descriptor done interrupt is posted.

1 1 0 The current DCB describes a continuation of a packet. The DMA address register is reloaded with the address specified in the DCB.MEMORY_ADDRESS field. No packet data transfer is performed. DMA processing ends after the current DCB is complete. If enabled, DMA descriptor done and DMA chain done interrupts are posted on completion.

1 1 1 The current DCB describes a continuation of a packet, and indicates the DMA controller should continue fetching DCBs at the address specified in the DCB.MEMORY_ADDRESS field. No packet data transfer is performed. If enabled, DMA descriptor done interrupt is posted.

Table 458: Receive DCB Special Functions


0 0 0 The current DCB describes the last buffer available for packet data. DMA processing ends after execution the current descriptor is complete. If enabled, DMA descriptor done and DMA chain done interrupts are posted on completion. If the length specified in the DCB.TRANSFER_BYTE_COUNT field is less than the number of bytes remaining in the current packet, then DCB.TRANSFER_BYTE_COUNT bytes are transferred and the DCB.EW bit is set to 0. The remainder of the packet is discarded.

Table 457: Transmit DCB Special Functions (Cont.)


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Next, set up the DMA control register (CMIC_DMA_CTRL) for the desired channel to indicate DMA Read or Write operation.

To start the DMA operation, set CMIC_DMA_STAT.CHx_DMA_EN to 1 for the appropriate channel. On completion of a DMAdescriptor, the DMA controller updates the status fields of the descriptor in memory, indicating the number of data bytestransferred from the network, the port which received this packet, and other control and status information.

The DMA execution continues if the next descriptor is valid and the first descriptor can be processed by the CPU. The CPUcan receive an interrupt after each descriptor operation is complete, or after all of the descriptors in the chain (array ofdescriptors with each successive CHAIN bit set) have completed.

When execution of a descriptor is complete, the CHx_DESC_DONE bit is set. After all the descriptors in a chain areexecuted, the CHx_CHAIN_DONE bit is set. No further operations on this specific channel takes place until the CPU clearsthe CHx_DESC_DONE or CHx_CHAIN_DONE bit.

0 0 1 The current DCB describes the last buffer available for the current packet. DMA processing continues with the descriptor immediately following the current descriptor in memory after the current one is complete. If enabled, the DMA descriptor done interrupt is posted on completion of the current DCB. If the length specified in the DCB.TRANSFER_BYTE_COUNT field is less than the number of bytes remaining in the current packet, then DCB.TRANSFER_BYTE_COUNT bytes are transferred and the DCB.EW bit is set to 0. The remainder of the packet is discarded.

0 1 0 DCB processing is set to continue with the DCB at the address specified in DCB.MEMORY_ADDRESS, but processing does not continue after the current DCB is complete. This descriptor cannot be used to indicate that the previous DCB described the last buffer for a packet. If enabled, DMA descriptor done and DMA chain done interrupts are posted on completion. No data transfer is performed. It is recommended that the S/G bit in a descriptor that indicates RLD = 1 be set to the same value as the DCB executed immediately before the current descriptor.

0 1 1 DCB processing continues with the DCB at the address specified in DCB.MEMORY_ADDRESS. This descriptor cannot be used to indicate that the previous DCB described the last buffer for a packet. If enabled, a DCB descriptor done interrupt is posted after the current DCB is complete.

1 0 0 The current DCB describes a buffer that can be used for any segment of a packet, first, middle, or end. The DMA controller stops processing after the current DCB is complete. If enabled, DMA descriptor done and/or DMA chain done interrupts are posted after the current DCB is complete. If the descriptor transfers the first segment of a packet DCB.SW is set to 1, if the last segment if a packet is transferred DCB.EW is set to 1. If DCB.EW is 0, the remainder of the packet is buffered in the StrataXGS until another DCB is executed by the DMA controller.

1 0 1 The current DCB describes a buffer that can be used for any segment of a packet, first, middle, or end. DMA processing continues with the DCB immediately following the current DCB. If the descriptor transfers the first segment of a packet DCB.SW is set to 1, if the last segment if a packet is transferred DCB.EW is set to 1. If DCB.EW is 0, then the next bytes of the packet are transferred on the next DCB that transfers data. If enabled, a DMA descriptor done interrupt is posted on completion of the DCB.

1 1 0 The current DCB indicates the next DCB executed is at the address specified by DCB.MEMORY_ADDRESS. Processing completes after the current DCB is finished. If the previous DCB indicated S/G = 1, and after completion DCB.EW was 0, then the next DCB (at DCB.MEMORY_ADDRESS) describes a continuation of the current packet. If enabled, DMA descriptor done and/or DMA chain done interrupts are posted upon completion of the DCB.

1 1 1 The current DCB directs the DMA controller to continue processing DCBs at the address specified by DCB.MEMORY_ADDRESS. If the previous DCB indicated S/G = 1, and the last segment of data associated with a packet was not transferred, the next DCB (located at DCB.MEMORY_ADDRESS) continues transferring data for the same packet. If enabled, a DMA descriptor done interrupt is posted.

Table 458: Receive DCB Special Functions (Cont.)


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There are other status bits in the DMA status register which indicate which channels are active, including a DMA channelerror code if a PCI parity or fatal error is detected.

Figure 2 shows the registers used in the packet data DMA mechanism.

Figure 2: Packet Data DMA Mechanism

11 10 9 8 7 6 5 4 3 2 1 021 20 19 1830 29 25 2431

CHn CHn 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

9 8 1 025 2431X X X X X X X

17 16RESERVEDRESERVEDRESERVEDRESERVED

0 = Disable DMA on CHn1 = Enable DMA on CHn0 = DMA chain not complete for CHn

0 = DMA not active on CHn1 = DMA active on CHn

0 = DMA descr. not complete on CHn1 = DMA descr. complete on CHn

1 = DMA chain complete for CHn

X

0 = Receive1 = Transmit0 = Modify port bitmap1 = Do not modify port bitmap

DMA STATUS AND CONTROL Register

DMA CONTROL Register

PCI parity error on DMA CHn

PCI fatal error on DMA CHn

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Figure 3 shows the packet data DMA transmit mechanism.

Figure 3: Packet Data DMA Transmit Mechanism

DMA CHANNEL n DESCRIPTOR ADDRESS Register

32 BIT MEMORY ADDRESS

DCB0C = 1, RLD = 0, S/G = 0

MEMORY_ADDRESS

DCB1C = 1, RLD = 0, S/G = 1

MEMORY_ADDRESS

DCB2C = 1, RLD = 0, S/G = 0

MEMORY_ADDRESS

DCB3C = 1, RLD = 1, S/G = 0

MEMORY_ADDRESS

PACKET 1

PACKET 2, SEGMENT 1

PACKET 2, SEGMENT 2 (last segment)

PACKET 3

DCB4C = 0, RLD = 0, S/G = 0MEMORY_ADDRESS

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Figure 4 shows the packet data DMA receive mechanism.

Figure 4: Packet Data DMA Receive Mechanism

CANCELLING AN ACTIVE DMA OPERATION

Active DMA operations can be cancelled if required. Use this sequence to stop an active DMA operation:

1. Set CMIC_DMA_STAT.CHx_DMA_EN to 0.

2. Set CMIC_DMA_CTRL.ABORT_DMA_CHx to 1 for the channel to stop.

3. Wait for CMIC_DMA_STAT.CHx_ACTIVE to clear (0).

4. Set CMIC_DMA_CTRL.ABORT_DMA_CHx to 0 for the channel being stopped.

5. Depending on the state of the DMA controller at the time the command was received, the DCB being processed can becompleted with a transferred byte count of 0. If enabled, Descriptor Done and Chain Done interrupts can be posted. Toclear completion status, also:

a. Set CMIC_DMA_STAT.CHx_DESC_DONE to 0.

b. Set CMIC_DMA_STAT.CHx_CHAIN_DONE to 0.

DMA CHANNEL n DESCRIPTOR ADDRESS Register

32 BIT MEMORY ADDRESS

DCB0C = 1, RLD = 0, S/G = 1

MEMORY_ADDRESS

DCB1C = 1, RLD = 0, S/G = 1

MEMORY_ADDRESS

DCB2C = 1, RLD = 1, S/G = 1

MEMORY_ADDRESS

PACKET BUFFER 1

PACKET BUFFER 2

DCB3C = 1, RLD = 0, S/G = 1

MEMORY_ADDRESS

DCB4C = 1, RLD = 0, S/G = 1

MEMORY_ADDRESS

DCB5C = 0, RLD = 0, S/G = 1

MEMORY_ADDRESS

PACKET BUFFER 4

PACKET BUFFER 3

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INTERRUPT DRIVEN DMA PROGRAMMING

The StrataXGS device supports two interrupts for each DMA channel: end-of-descriptor and end-of-chain. To receive theseinterrupts, the interrupt mask bits corresponding to the channel’s interrupts must be set to 1 in the interrupt mask register.The end-of-descriptor interrupt indicates that the DMA controller has completed a descriptor in a chain, while the end-of-chain interrupt indicates that the entire chain has been completed. Multiple end-of-descriptor interrupts can be seen by theprocessor as a single interrupt, requiring that software check the DMA status words in the descriptors to determine that theyare complete. The order of the end-of-descriptor and end-of-chain interrupt when the last DMA descriptor in a chain iscomplete is undefined, and must be handled by software.

Once a descriptor execution is complete, the descriptor is updated with the status of the operation. The CHx_DESC_DONEbit in CMIC_DMA_STAT (DMA Status register) is set to indicate completion of the current descriptor, and DMA operationcontinues as long as the next descriptor is valid and there are no PCI errors. The host CPU must handle any PCI errorsbefore DMA operations can proceed. The CHx_CHAIN_DONE bit in CMIC_DMA_STAT is set to indicate completion of theentire chain of descriptors. No further operations on this specific channel takes place until the host CPU clears this bit.

The end of descriptor interrupt handler must perform the following:

1. Clear CHx_DESC_DONE for interrupting channel in CMIC_DMA_STAT.

2. Inspect the DMA Status words in each of the chained descriptors. If DONE is set, process completion of packet transmitor receive.

The end-of-chain interrupt handler must perform the following:

1. Clear CHx_DMA_EN for interrupting channel in CMIC_DMA_STAT.

2. Clear CHx_CHAIN_DONE for interrupting channel in CMIC_DMA_STAT.

3. Process the completion of the DMA chain. If end-of-descriptor interrupts are also used, it can be necessary to considerthe end-of-chain interrupt to also indicate end-of-descriptor, depending on the order the interrupts are dispatched by theinterrupt handler.

Follow these steps to set up a DMA transfer:

1. Set up the DMA descriptor chain for the channel in memory.

2. Program the appropriate Descriptor Address register (CMIC_CHx_DMA_DESC) for the DMA channel to point to theDMA descriptor chain location.

3. Program the direction of the transfer and modifying of the port bitmap into the DMA Control register (CMIC_DMA_CTRL).

4. Enable the channel by setting the appropriate bit in the DMA Status and Control register (CMIC_DMA_STAT).

By programming the Interrupt Mask register (CMIC_IRQ_MASK), you can optionally specify that the host CPU is interruptedevery time a descriptor operation is completed, or only upon completion of execution of an entire chain of descriptors.

Note: Writing to the Descriptor Address register for a channel should be done only when DMA is disabled for thechannel and no DMA operation is in progress (as indicated by CMIC_DMA_CTRL).

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COUNTER DATA TRANSFER

The BCM56500 device contains a large number of packet statistics counters. There are 128 counters per port, includingGbE, HG, and CPU, totaling 3712. Since the GPIC counters are 32 bits, they are read and written using 32-bit data transfers.However, the IPIC counters are 36- or 42-bit counters and are always read and written using 64-bit data transfer.

Typically, S-channel operations perform internal register reads of counters. Some applications can require reading andprocessing all of the counter values at a particular interval. Scanning all of the counters over the S-channel requires, on theorder of, 50 milliseconds for a typical processor, with much of this time spent running at interrupt level. To reduce theoverhead for such applications, the StrataXGS device performs automatic transfers using the Counter DMA mechanism. Ablock diagram of the S-channel access is shown in the following figure.

Figure 5: S-Channel DMA Access

CMIC

MMU

GPIC

IPIC

ARL

CBP

CPU

CMIC = CPU Management Interface ControllerGPIC = Gigabit Port Interface ControllerIPIC = Interconnect Port Interface ControllerMMU = Memory Management UnitCBP = Common Buffer Pool

GE0

GE23

HG0

PCI S-C

ha

nne

l B

us

HG3

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Broadcom CorporationDocument 56500-PR100-R Counter Data Transfer Page 395

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The Counter DMA feature allows the CMIC to be configured to read a range of counter addresses for an arbitrary group ofports, and write the data into the host processor’s memory via DMA.

During the Counter DMA scan process, the CMIC internally issues S-channel read operations to read counter values. Toaccomplish this, access to the S-channel is shared with normal CPU access. The CPU can still perform its usual S-channeloperations, and it receives high-priority access to the S-channel.

COUNTER DMA REGISTERS

These are the CMIC registers that are used to program the counter DMA transfer.

Table 459: Counter DMA Resources

Register Address/Bit Description

CMIC_STAT_DMA_ADDR PCI_MBAR + 0x0164 This register gives the memory address where the Stats counters for each of the ports are written to.

CMIC_STAT_DMA_SETUP (PCI_MBAR + 0x0168) This register allows enable DMA, Counter timer, and timer values. The timer value indicating the number of time ticks to wait from the end of one scan of all of the stat registers to the beginning of the next scan.

CMIC_STAT_DMA_PORTS (PCI_MBAR + 0x016C) Stat Counter Port bitmap—indicating which port is qualified to scan

CMIC_STAT_DMA_ING_STATS_CFG (PCI_MBAR + 0x0460) DMA Ingress stats configuration register

CMIC_STAT_DMA_EGR_STATS_CFG (PCI_MBAR + 0x0464) DMA Egress stats configuration register

CMIC_STAT_DMA_MAC_STATS_CFG (PCI_MBAR + 0x0468) DMA MAC stats configuration register. Consists of GbE, HG, and CPU counters.

CMIC_STAT_DMA_PORT_TYPE_MAP (PCI_MBAR + 0x046C) Port type bitmap for stat DMA—indicating GbE or HG port

CMIC_STA_DMA_BLKNUM_MAP (PCI_MBAR + 0x0480 to 0x048C) Indicating which block to be used for the counters

CMIC_STA_DMA_PORTNUM_MAP (PCI_MBAR + 0x0490 to 0x49C) Indicating which port to be used for the counters

CMIC_IRQ_STAT Bit 20 Iteration Done Interrupt

CMIC_IRQ_MASK Bit 20 Iteration Done Interrupt Mask

CMIC_DMA_STATa

a. To atomically clear bit N in the CMIC_DMA_STAT register, write the value N to the register (for example, write 0x13 to clear the Counter DMA Done flag).

Bit 13 Counter DMA Done flag

CMIC_DMA_STATa Bit 14 Counter Iteration Done flag

CMIC_DMA_STAT1 Bit 17 Counter DMA Active

CMIC_CONFIG Bit 22 Abort Counter DMA

GPORT_CONFIG Bit 1 Clear counters

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DMA BUFFER ORGANIZATION

Allocate a suitable buffer for Counter DMA in cached or uncached memory, as required by your platform. The size of thebuffer is based on the port counts and the number of counters. For 24 GbE ports, the maximum number of bytes are: 24ports x 128 counters/port x 4 = 14848 bytes. The buffer must be aligned on a 32-bit boundary. For HG counters, the addressis accessed through a 64-bit boundary, compared to a 32-bit boundary for GbE and CPU counters. Therefore, for 4 HG ports,the maximum number of bytes are: 4 ports x 128 counters/port x 8 = 4096 bytes.

The base address of this buffer should be written into the CMIC_STAT_DMA_ADDR register prior to enabling Counter DMA.The organization of the buffer is shown in Table 460 on page 397, where ports are numbered from 0 to 23. The counter valuefor a given port number in Table 2 always start at an offset from the beginning of the buffer equal to the port number x 128 x 4.

PORT SELECTION

The CMIC can be configured to scan any subset of ports. Portions of the buffer corresponding to ports that are not includedfor scanning are not written by the CMIC. For example, if you are only scanning ports 0 to 7, only 4096 bytes of buffer spaceare necessary. Typically, the CMIC is configured to scan all ports. To configure the set of ports to scan, write the port bitmap(typically 0xFFFFFF) into the CMIC_STAT_DMA_PORTS register.

ADDRESS CONFIGURATION

The CMIC must be notified of the counter-address range to be read, using internal register addresses. The minimal rangeis always 0, while the maximum range is specified for the desired range. The counter ranges are located in three stages:Ingress Pipeline, Egress Pipeline, and MAC block. Figure 6 on page 398 illustrates the counter blocks and the associatedregister fields for the range setting. Refer to section on Statistics Counters for the address location of specific counters.

Table 460: Counter DMA Buffer Organization

Offset Counter

0x0100 Port 1 Counter 0



---- ----

0x02FC Port 1 Counter 127

To To

0x2E00 Port 24 Counter 0



---- ----

0x2FFC Port 24 Counter 127

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Figure 6: Counter Blocks

TIMER MODES

Counter DMA can be configured to scan all of the counters into memory at approximately regular intervals, or it can betriggered in one-shot mode to scan all the counters just once and then stop. The latter mode would be desirable in anapplication that needed to scan the counters at a software-controlled rate slower than that supported by the hardware timer,which has a maximum interval of 8.38 seconds.

To scan all the counters at a regular interval:

1. Program the interval into bits 29:16 of CMIC_STAT_DMA_SETUP

2. Set bit 30 (timer enable)

3. Set bit 31 (DMA enable)

The timer interval is a 14-bit quantity in units of 512µ, providing a maximum delay of 8.38 seconds between the end of onescan and the beginning of the next.

To scan all the counters just once and then stop, clear bit 30 of CMIC_STAT_DMA_SETUP (timer enable) and set bit 31(DMA enable). Then trigger a scan whenever desired by clearing bit 13 of CMIC_DMA_STAT (Counter DMA done). A scanis also triggered as soon as the enable bit is set, if bit 13 of CMIC_DMA_STAT is already clear.

To disable Counter DMA, clear bits 30 and 31 of CMIC_STAT_DMA_SETUP. Clear the CMIC_STAT_DMA_PORTS registerto speed up the scan, which is currently in progress (if any), then wait for bit 17 of CMIC_DMA_STAT to clear, indicating thescan in progress (if any) is complete.

CMIC_STAT_DMA_ING_STATS_CFGRegister

CMIC_STAT_DMA_EGR_STATS_CFGRegister

CMIC_STAT_DMA_MAC_STATS_CFGRegister

ing_stat_counters_num = 0x3F

ing_stat_counters_num = 0x00

egr_stat_counters_num = 0x3F

egr_stat_counters_num = 0x00

cpu_stats_port_num = [28:24]

mac_x_stat_counters_num = [14:8]

mac_g_stat_counters_num = [5:0]

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INTERRUPTS

Counter DMA sends an interrupt at the end of every scan iteration. Software can optionally unmask the interrupt and use itto wake up a thread to perform any desired counter processing, using the values in the counter buffer.

Bit 20 (STAT_DMA_DONE) in the interrupt request and interrupt mask registers (CMIC_IRQ_MASK) corresponds to theCounter DMA interrupt. The interrupt handler must acknowledge the interrupt by clearing bit 14 of CMIC_DMA_STAT(counter iteration done flag).

TABLE DATA TRANSFER (TABLE DMA)

The StrataXGS Device supports DMA of any switch table to system memory. The CPU can program the beat count (numberof DATA words: 32 bits) for the selected table, as well as the table size, table start address in the switch, and the startingsystem memory DMA address. This flexibility allows any memory table within the switch to be transferred to system memory.

HARDWARE ENDIAN MODES

When a processor accesses registers in the StrataXGS device over the PCI bus, or the StrataXGS masters the PCI bus toread or write host memory, the byte order becomes an important consideration. It is undesirable and inefficient if softwarehas to swap words.

Little-endian byte order is used by Intel® processors, and big-endian byte order is used by most other processors. The PCIbus used to interface the StrataXGS device to a processor is intrinsically little endian. The StrataXGS is designed toefficiently support all processors, whether they utilize little- or big-endian byte format, and whether they are used with anexternal or integrated PCI bridge that provides full or partial byte-swapping features.

To accomplish this, the StrataXGS device can be configured to swap or not swap various types of data transfers. The varioustypes of data transfers are defined in the next section.

Note: The maximum of 640 bits (20 beats) can be DMA at a time by the Table DMA feature underCMIC_TABLE_DMA_CFG register.

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Data Transfer Types

Endian issues affect these types of data transfer used in the StrataXGS device:

Swapping Requirements

Regardless of CPU endianness, packet DMA data always appears in host memory in big-endian format. Packet DMA datadoes not have a 32-bit organization, and is viewed as a byte stream. Historically, software is always written to expect big-endian format when accessing a network byte stream. Whenever software accesses a 2-byte or 4-byte quantity in the packetDMA data, it uses ntohs() and ntohl() on all platforms. These macros are programmed to swap on little-endian hosts and donothing on big-endian hosts. All data types used in the StrataXGS device (except packet DMA) are most naturally accessedby the processor using 32-bit loads and stores. CMIC registers, descriptor words, counter values, and ARL messagecontents all have 32-bit organization. When software running on the host CPU performs 32-bit accesses to this little-endiandata, the results are proper on a little-endian host CPU, but must be byte-swapped on a big-endian host CPU.

Swap Modes

To allow a big-endian CPU to avoid swapping accesses to PCI memory space, the CMIC can be configured to swap all suchaccesses. This feature (CMIC_ENDIANESS_SEL.PIO) can be enabled at initialization time on a big-endian processor, andthen software can read and write PCI memory space without worrying about swapping. This also causes PCI memoryaccesses to appear swapped on a PCI-bus analyzer.

To allow a big-endian CPU to avoid swapping accesses to the contents of non-packet DMA data, the CMIC can beconfigured to use big-endian format to load and store all non-packet DMA data in host memory. This feature(CMIC_ENDIANESS_SEL.DMA_OTHER) can be enabled at initialization time on a big-endian processor, and then softwarecan read and write non-packet DMA data without worrying about swapping.

The CMIC never swaps accesses to PCI configuration space. To do so would result in swapped configuration data appearingon the PCI bus, which might confuse PCI-bus analyzers or other bus devices. Also, PCI configuration cycles are rarely usedafter initial device configuration and are not a performance concern.

Table 461: Data Transfer Types

Field Description

PCI Config Space Generates special bus cycles used to configure PCI parameters such as base address registers.

PCI Memory Space Used to access CMIC registers, including the S-channel message buffer and ARL message buffers. Sometimes referred to as PIO (programmed I/O).

Packet DMA Refers to the CMIC transferring network packet data into or out of host memory.

Descriptor DMA Refers to the CMIC fetching descriptors out of host memory. The descriptors contain control and status words for packet DMA, some of which contain additional addresses pointing into host memory.

Counter DMA Refers to the CMIC mirroring the contents of MAC packet statistics counters into host memory.

Table DMA Refers to the CMIC copying switching table to the memory.

Non-packet DMA Used collectively to refer to Descriptor, Counter, and ARL Message DMA.

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Endian Select Register

The CMIC_ENDIANESS_SEL register is at direct-mapped address PCI_MBAR + 0x174. Software can initially configure theendian mode without worrying about the current byte-swapping mode by setting the desired flag bits in both the high andlow bytes of the value written. The PIO bit is bit 0, and the DMA_OTHER bit is bit 2. Therefore, on little-endian processors,the value 0x00000000 should be written to the CMIC_ENDIANESS_SEL register. On big-endian processors, the value0x05000005 should generally be written. A third bit called DMA_PACKET (bit 1) swaps packet DMA data. Since packet DMAdata is already big endian, this causes packet data to be read and written from host memory in little-endian format. This isusually undesirable and should be avoided unless the processor/bridge combination is swapping PCI data in an unusualway.

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Section 20: CMIC 2-Wire Serial Interface ( I2C Compatible)

There are two I2C operating modes:

• I2C Slave Only mode

• CPU-Controlled Master/Slave mode

I2C SLAVE ONLY MODE

In this mode, an external I2C master can program CMIC registers through the I2C interface. The CMIC only sees the I2Csignals SDA (data) and SCL (clock). The CMIC handles all aspects of the I2C core —Initialization, read/write control andstatus register, read/write data and I2C bus protocol.

The protocol for address and data selection is defined by the CMIC. This definition is in addition to the I2C protocol, whichdictates when start, stop, and other signals are generated.

The StrataXGS I2C data protocol format supported by CMIC is big endian for consistency with the I2C protocols supportedby other vendors. The registers to program are all little endian, with the exception of the rules table.

I2C WRITE PROTOCOL

The external master supplies the address of the register to write to and 32 bits of data (WDATA):

<CMIC SLAVE ADDR-W> <ADDR-MSB> <ADDR-LSB> <WDATA-3> <WDATA-2> <WDATA-1> <WDATA-0><ADDR-MSB>,<ADDR-LSB> is the CMIC register offset.

I2C READ PROTOCOL

The CMIC supports random read of any register, read of a register at the current address, and continuous burst read. If anaddress is required, the I2C master supplies the address. The CMIC supplies the READ data.

RANDOM READ

<CMIC SLAVE ADDR-W> <ADDR-MSB> <ADDR-LSB> <CMIC SLAVE ADDR-R> <rdata> <rdata> <rdata> <rdata>

READ AT CURRENT ADDRESS

<CMIC SLAVE ADDR –R> <rdata> <rdata> <rdata> <rdata>

Note: This is not required for managed (PCI-based) systems.

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CONTINUOUS BURST READ

Continuous burst read can be done at a random address or at the current address.

At a random address:

<CMIC SLAVE ADDR-W> <ADDR-MSB> <ADDR-LSB><CMIC SLAVE ADDR-R> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata>

At the current address:

<CMIC SLAVE ADDR-R> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata> <rdata>

In continuous external master read mode, CMIC automatically increments the address, fetches the contents of the newregister, and supplies the data to the external I2C master.

CPU CONTROLLED MASTER / SLAVE MODE

This mode is entered by enabling the PCI_2_I2C_EN bit in the CMIC configuration register. In this mode, the CPU candirectly program the I2C interface on the StrataXGS device.

In this mode, the I2C controller inside the StrataXGS device is programmed using PCI memory-mapped register access. Theprocessor interface provides access to six 8-bit registers: four read/write registers, one read-only register and one write-onlyregister.

CMIC_I2C_SLAVE_ADDR (PCI_MBAR + 0X120)

For 7-bit Addressing

SLA6–SLA0 is the 7-bit address of the I2C when in slave mode. When the I2C receives this address after a START condition,it enters slave mode. (SLA6 corresponds to the first bit received from the I2C bus.) If GCE is set to 1, the I2C also recognizesthe general call address (0x00).

Table 462: CMIC I2C Control Registers

Register Description Reset

CMIC_I2C_SLAVE_ADDR (PCI_MBAR + 0x120) Slave address 0x00

CMIC_I2C_XADDR (PCI_MBAR + 0x130) Extended slave address 0x00

CMIC_I2C_DATA (PCI_MBAR + 0x124) Data byte 0x00

CMIC_I2C_CTRL (PCI_MBAR + 0x128) Control register 0x00

CMIC_I2C_STAT (PCI_MBAR + 0x12C) Status register (read only) 0xF8

CMIC_I2C_CCR (PCI_MBAR + 0x12C) Clock control register (write only) Preset clock divider value

CMIC_I2C_RESET (PCI_MBAR + 0x13C) Software reset Sets the M I2C back to idle and the STP, STA and IFLG bits of the CNTR (Control) register to 0

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For 10-bit Addressing

When the received address starts with 0xF7–0xF0, the I2C recognizes this as corresponding to SLAX9 and SLAX8 of anextended address, and sends an ACK. (The device does not generate an interrupt at this point.) After the next byte of theaddress has been received, the I2C generates an interrupt and goes into slave mode.

CMIC_I2C_XADDR (PCI_MBAR + 0X130)

CMIC_I2C_DATA = PCI_MBAR + 0X124

This register contains the data byte/slave address to be transmitted or the data byte that has just been received. In transmitmode, the byte is sent the MSB first; in receive mode, the first bit received is placed in the MSB of the register. After eachbyte is transmitted, the DATA register contains the byte that was actually present on the bus, so that if arbitration is lost, itcontains the received byte.

Table 463: CMIC I2C Slave Addresses

Position7-bit Addresses

Extended AddressesBit Description

D7 SLA6 Slave address 1





D2 SLA1 Slave address SLAX9

D1 SLA0 Slave address SLAX8

D0 GCE General call address enable General call address enable

Table 464: CMIC I2C Extended Slave Addresses

Position Bit Description

D7 SLAX7 Extended slave address








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CMIC_I2C_CTRL = PCI_MBAR + 0X128

Bits 0 and 1 are read-only and are read back as 0.

IEN

When IEN is set to 1, the interrupt line (INTR) goes high when the IFLG bit is set. When IEN is cleared to 0, the interrupt linealways remains low.

ENAB

When ENAB = 0, the I2C bus does not respond to any address on the bus. When ENAB = 1, the I2C responds to calls to itsslave address and to the general call address if the GCE bit in the ADDR register is set.

This bit is used to enable slave-mode support. It should be set to 0 if only master mode is used.

STA

When STA is set to 1, the I2C enters master mode and sends a START condition on the bus when the bus is free. If the STAbit is set to 1 when the I2C is already in master mode and one or more bytes have been transmitted, then a repeated STARTcondition is sent. If the STA bit is set to 1 when the I2C is being accessed in slave mode, the I2C completes the data transferin slave mode and then enters master mode when the bus has been released.

The STA bit is cleared automatically after a START condition has been sent. Writing a 0 to this bit has no effect.

STP

If STP is set to 1 in master mode, a STOP condition is transmitted on the I2C bus. If the STP bit is set to 1 in slave mode,the I2C behaves as if a STOP condition has been received, but no STOP condition is transmitted on the I2C bus. If both STAand STP bits are set, the I2C first transmits the STOP condition (if in master mode) then transmits the START condition.

The STP bit is cleared automatically. Writing a 0 to this bit has no effect.

IFLG

IFLG is automatically set to 1 when any of 30 of the possible 31 I2C states is entered. The only state that does not set IFLGis state 0xF8 (see STAT Register section).

Table 465: CMIC I2C Interrupt Control Bits

Position Bit Description

D7 IEN Interrupt enable

D6 ENAB Bus enable

D5 STA Master mode start

D4 STP Master mode stop

D3 IFLG Interrupt flag

D2 AAK Assert acknowledge

D1 – Unused

D0 – Unused

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If IFLG is set to 1 and the IEN bit is set, the interrupt line goes high. When IFLG is set by the I2C, the low period of the I2Cbus clock line (SCL) is stretched and the data transfer is suspended. When 0 is written to IFLG, the interrupt line goes lowand the I2C clock line is released.

AAK

When AAK is set to 1, an Acknowledge (low level on SDA) is sent during the acknowledge clock pulse on the I2C bus if:

• Either the whole of a 7-bit slave address, or the first or the second byte of a 10-bit slave address has been received.

• The general call address has been received and the GCE bit in the ADDR register is set to 1.

• A data byte has been received in master or slave mode.

When AAK is cleared to 0, a Not Acknowledge (high level on SDA) is sent when a data byte is received in master or slavemode.

If AAK is set to 0 in the slave transmitter mode, the byte in the DATA register is assumed to be the last byte. After this bytehas been transmitted, the I2C enters state 0xC8 and then returns to the idle state.

The I2C does not respond as a slave unless AAK is set.

CMIC_I2C_STAT (PCI_MBAR + 0X12C)

This read-only register contains a 5-bit status code in the five MSBs; the three LSBs are always 0.

There are 31 possible status codes. When STAT contains the status code 0xF8, no relevant status information is available,no interrupt is generated, and the IFLG bit in the CNTR register is not set. All other status codes correspond to the state ofthe I2C.

When each of these states is entered, the corresponding status code appears in this register and the IFLG bit in the CNTRregister is set. When the IFLG bit is cleared, the status code returns to 0xF8. The 31 possible status codes are:

Table 466: CMIC I2C Status Codes

Code Status

0x00 Bus error

0x08 START condition transmitted

0x10 Repeated START condition transmitted

0x18 Address + write bit transmitted—ACK received

0x20 Address + write bit transmitted—ACK not received

0x28 Data byte transmitted in master mode—ACK received

0x30 Data byte transmitted in master mode—ACK not received

0x38 Arbitration lost in address or data byte

0x40 Address + read bit transmitted—ACK received

0x48 Address + read bit transmitted—ACK not received

0x50 Data byte received in master mode—ACK transmitted

0x58 Data byte received in master mode—not ACK transmitted

0x60 Slave address + write bit received—CK transmitted

0x68 Arbitration lost in address as master, slave address + write bit received—ACK transmitted

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If an illegal condition occurs on the I2C bus, the bus-error state is entered (status code 0x00). To recover from this state, theSTP bit in the CNTR register must be set and the IFLG bit cleared. The I2C then returns to the idle state; no STOP conditionis transmitted on the I2C bus.

The STP and STA bits can be set to 1 at the same time to recover from the bus error; the I2C then sends a START.

CCR REGISTER (PCI_MBAR + 0X12C)

The read-only register, CMIC_I2C_STAT is also accessed at this address.

This register is write-only. The seven LSBs control the clock frequency of CLKO, the output from the programmable clockdivider. (The input to the clock divider is FCLK.)

0x70 General Call address received, ACK transmitted

0x78 Arbitration lost in address as master, General Call address received—ACK transmitted

0x80 Data byte received after slave address received—ACK transmitted

0x88 Data byte received after slave address received—not ACK transmitted

0x90 Data byte received after General Call received—ACK transmitted

0x98 Data byte received after General Call received—not ACK transmitted

0xA0 STOP or repeated START condition received in slave mode

0xA8 Slave address + read bit received—ACK transmitted

0xB0 Arbitration lost in address as master, slave address + read bit received—ACK transmitted

0xB8 Data byte transmitted in slave mode—ACK received

0xC0 Data byte transmitted in slave mode—ACK not received

0xC8 Last byte transmitted in slave mode—ACK received

0xD0 Second address byte + write bit transmitted—ACK received

0xD8 Second address byte + write bit transmitted—ACK not received

0xE0 Second address byte + read bit transmitted—ACK received

0xE8 Second address byte + read bit transmitted—ACK not received

0xF8 No relevant status information—IFLG = 0

Table 467: CCR Register Bits

Position Bit

D7 –

D6 M3

D5 M2

D4 M1

D3 M0

D2 N2

D1 N1

Table 466: CMIC I2C Status Codes (Cont.)

Code Status

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The frequency of the I2C interface is given by:

where:

• F is the clock frequency of the I2C interface

• M is the value stored in CCR bits 3–6

• N is the value stored in CCR bits 0–2

• DIVIDEND is set in CMIC_RATE_ADJUST (see “CMIC_RATE_ADJUST” on page 38)

• DIVISOR is set in CMIC_RATE_ADJUST (see “CMIC_RATE_ADJUST” on page 38)

For the default values of CMIC_RATE_ADJUST, a 100-kHz I2C clock will require that M = 10 and N = 0.

Bus Clock Speed

The I2C bus is defined for bus clock speeds up to 100 Kbps (400 Kbps in fast-mode).

Clock Synchronization

If another device on the I2C bus drives the clock line when the I2C is in master mode, the I2C synchronizes its clock to theI2C bus clock. The high period of the clock is determined by the device that generates the shortest high-clock period. Thelow period of the clock is determined by the device that generates the longest low-clock period.

A slave can stretch the low period of the clock to slow down the bus master. The low period can also be stretched forhandshaking purposes. This can be done after each bit transfer or each byte transfer. The I2C stretches the clock after eachbyte transfer until the IFLG bit in the CNTR register is cleared.

Bus Arbitration

In master mode, the I2C checks that each transmitted logic 1 appears on the I2C bus as a logic 1. If another device on thebus overrules and pulls the SDA line low, arbitration is lost. If arbitration is lost during the transmission of a data byte or aNot Acknowledge bit, the I2C returns to the idle state. If arbitration is lost during the transmission of an address, the I2Cswitches to slave mode so that it can recognize its own slave address or the general call address.

OPERATING MODES

MASTER TRANSMIT

In the master transmit mode, the I2C transmits a number of bytes to a slave receiver.

The master transmit mode is entered by setting the STA bit to 1. The I2C then tests the I2C bus and transmits a STARTcondition when the bus is free. When a START condition has been transmitted, the IFLG bit is set and the status code in the

D0 N0

Table 467: CCR Register Bits (Cont.)

Position Bit

F 133MHz DIVIDEND×10 DIVISOR× M 1+( ) 2( ) N 1+( )( )----------------------------------------------------------------------------------=

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STAT register is 0x08. Before this interrupt is serviced, the DATA register must be loaded with either a 7-bit slave addressor the first part of a 10-bit slave address, with the LSB cleared to 0 to specify the transmit mode. The IFLG bit should nowbe cleared to 0 to prompt the transfer to continue.

After the 7-bit slave address (or the first part of a 10-bit address) plus the write bit have been transmitted, the IFLG is setagain. A number of status codes are possible in the STAT register, as shown in Table 468.

If 10-bit addressing is being used, then after the first part of a 10-bit address plus the write bit have been successfullytransmitted, the status code is 0x18 or 0x20.

After this interrupt has been serviced and the second part of the address is transmitted, the STAT register contains one ofthe following codes:

Table 468: STAT Register Status Codes and Meanings

Code I2C State Microprocessor Response Next I2C Action

0x18 Addr+W transmitted—ACK received For a 7-bit address:Write byte to DATA—clear IFLGOr set STA—clear IFLGOr set STP—clear IFLGOr set STA and STP—clear IFLG

For a 10-bit address:Write extended address byte to DATA—clear IFLG

Transmit data byte—receive ACKTransmit repeated START

Transmit STOPTransmit STOP then STARTTransmit extended address byte

0x20 Addr+W transmitted—ACK not received

As for code 0x18 As for code 0x18

0x38 Arbitration lost. Clear IFLGOr set STA—clear IFLG

Return to idleTransmit START when bus free

0x68 Arbitration lost, SLA+W received—ACK transmitted

Clear IFLG—AAK = 0Or clear IFLG—AAK = 1

Receive data byte—transmit not ACK

Receive data byte—transmit ACK

0x78 Arbitration lost, general call address received— ACK transmitted


0xB0 Arbitration lost, SLA+R received—ACK transmitted

Write byte to DATA—clear IFLG, AAK = 0

Or write byte to DATA—clear IFLG, AAK = 1

Transmit last byte—receive ACKTransmit data byte—receive ACK

Table 469: STAT Register Status Return Codes


0x38 Arbitration lost Clear IFLGOr set STA—clear IFLG


0x68 Arbitration lost, SLA+W received—ACK transmitted

Clear IFLG, AAK = 0Or clear IFLG—AAK = 1

Receive data byte—transmit not ACKReceive data byte—transmit ACK

0xB0 Arbitration lost, SLA+R received—ACK transmitted

Write byte to DATA—clear IFLG, AAK = 0Or write byte to DATA—clear IFLG, AAK = 1

Transmit last byte—receive ACKTransmit data byte—receive ACK

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If a repeated START condition has been transmitted, the status code is 0x10 instead of 0x08.

After each data byte has been transmitted, the IFLG is set and one of three status codes is in the STAT register.

When all bytes have been transmitted, the STP bit should be set by writing a 1 to this bit in the CNTR register. The I2C willthen transmit a STOP condition, clear the STP bit, and return to the idle state.

MASTER RECEIVE

In the master receive mode, the I2C receives a number of bytes from a slave transmitter.

After the START condition has been transmitted, the IFLG bit is set and the status code 0x08 is in the STAT register. TheDATA register should now be loaded with the slave address (or the first part of a 10-bit slave address), with the LSB set to1 to signify a read. The IFLG bit should now be cleared to 0 to prompt the transfer to continue.

When the 7-bit slave address (or the first part of a 10-bit address) and the read bit have been transmitted, the IFLG bit is setagain. A number of status codes are possible in the STAT register.

0xD0 Second Address byte + W transmitted—ACK received

Write byte to DATA—clear IFLGOr set STA—clear IFLGOr set STP—clear IFLGOr set STA and STP—clear IFLG

Transmit data byte—receive ACKTransmit repeated STARTTransmit STOPTransmit STOP then START

0xD8 Second Address byte + W transmitted—ACK not received

As for code 0xD0 As for code 0xD0

Table 470: STAT Register IFLG Return Codes


0x28 Data byte transmitted—ACK received

Write byte to DATA—clear IFLGOr set STA—clear IFLGOr set STP—clear IFLGOr set STA and STP—clear IFLG

Transmit data byte—receive ACKTransmit repeated STARTTransmit STOPTransmit START then STOP

0x30 Data byte transmitted—ACK not received


0x38 Arbitration lost Clear IFLGOr set STA—clear IFLG


Table 471: STAT Register Status Codes and Meanings (Master Receive)


0x40 Addr+R transmitted—ACK received

For a 7-bit address:

Clear IFLG—AAK = 0Or clear IFLG—AAK = 1For a 10-bit address:

Write extended address byte to DATA—clear IFLG

Receive data byte—transmit not ACKReceive data byte—transmit ACKTransmit extended address byte

Table 469: STAT Register Status Return Codes (Cont.)


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LTDIf 10-bit addressing is being used, then after the first part of a 10-bit address and the read bit have been successfullytransmitted, the status code is 0x40 or 0x48.

After this interrupt has been serviced and the second part of the address transmitted, the STAT register contains one of thecodes in Table 472.

If a repeated START condition has been transmitted, the status code is 10h instead of 0x08.

After each data byte has been received, IFLG is set and one of three status codes is in the STAT register:

0x48 Addr+R transmitted—ACK not received

Set STA—clear IFLGOr set STP—clear IFLGOr set STA and STP—clear IFLG

For a 10-bit address:Write extended address byte to DATA—clear IFLG

Transmit repeated STARTTransmit STOPTransmit STOP then STARTTransmit extended address byte

0x38 As for master transmit As for master transmit As for master transmit



0xB0 As for master transmit As for master transmit As for master transmit

Table 472: STAT Register Status Return Codes (Master Receive)





0xB0 As for master transmit As for master transmit As for master transmit

0xE0 Second Address byte + R transmitted—ACK received



0xE8 Second Address byte + R transmitted—ACK not received



Table 473: STAT Register IFLG Return Codes (Master Receive)


0x50 Data byte received—ACK transmitted

Read DATA—clear IFLG, AAK = 0or read DATA—clear IFLG, AAK = 1


0x58 Data byte received—not ACK transmitted

Read DATA, set STA, clear IFLGOr read DATA, set STP, clear IFLGOr read DATA, set STA and STP, clear IFLG

Transmit repeated STARTTransmit STOPTransmit STOP then START

0x38 Arbitration lost in not ACK bit As for master transmit As for master transmit

Table 471: STAT Register Status Codes and Meanings (Master Receive) (Cont.)


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When all bytes have been received, the STP bit should be set by writing a 1 to this bit in the CNTR register. The I2C transmitsa STOP condition, clears the STP bit, and returns to the idle state.

SLAVE TRANSMIT

In the slave transmit mode, a number of bytes are transmitted to a master receiver.

The I2C enters slave transmit mode when it receives its own slave address and a read bit after a START condition. The I2Cthen transmits an acknowledge bit and sets the IFLG bit in the CNTR register. The STAT register contains the status code0xA8.

Slave transmit mode can also be entered directly from a master mode if arbitration is lost in master mode during thetransmission of an address and the slave address and read bit are received. The status code in the STAT register is then0xB0.

The data byte to be transmitted should then be loaded into the DATA register and the IFLG cleared. When the I2C hastransmitted the byte and received an acknowledge, the IFLG is set and the STAT register contains 0xB8. Once the last byteto be transmitted has been loaded into the DATA register, the AAK bit should be cleared when the IFLG is cleared. After thelast byte has been transmitted, the IFLG is set and the STAT register contains 0xC8. The I2C then returns to the idle stateand the AAK bit must be set to 1 before the slave mode can be entered again.

If no acknowledge is received after transmitting a byte, the IFLG is set and the STAT register contains 0xC0. The I2C thenreturns to the idle state.

If the STOP condition is detected after an acknowledge bit, the I2C returns to the idle state.

SLAVE RECEIVE

In the slave receive mode, a number of data bytes are received from a master transmitter.

The I2C enters slave receive mode when it receives its own slave address and a write bit (LSB = 0) after a START condition.The I2C then transmits an acknowledge bit and sets the IFLG bit in the CNTR register: the STAT register then contains statuscode 0x60. The I2C also enters slave receive mode when it receives the general call address 0x00 (if the GCE bit in theADDR register is set). The status code is then 0x0.

Slave receive mode can also be entered directly from a master mode if arbitration is lost in master mode during thetransmission of an address and the slave address and write bit (or the general call address if bit GCE in the ADDR register

Note: Where the I2C has an extended slave address (signified by 0xF0–0xF7 in the ADDR register), it transmitsan acknowledge after the first address byte is received but no interrupt is generated, IFLG will not be set andthe status will not change. Only after the second address byte has been received will the I2C generate aninterrupt and set the IFLG bit and the status code as described above.

Note: Where the I2C has an extended SLAVE address (signified by 0xF0–0xF7 in the ADDR register), ittransmits an acknowledge after the first address byte is received but no interrupt is generated, IFLG is not setand the status does not change. Only after the second address byte has been received will the I2C generatean interrupt and set the IFLG bit and the status code as described above.

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is set to one) are received. The status code in the STAT register is then 0x68 if the slave address was received or 0x78 ifthe general call address was received. The IFLG bit must be cleared to 0 to allow the data transfer to continue.

If the AAK bit in the CNTR register is set to 1, then after each byte is received, an acknowledge bit (low level on SDA) istransmitted and the IFLG bit is set; the STAT register then contains status code 0x80 (or 0x90 if slave receive mode wasentered with the general call address). The received data byte can be read from the DATA register and the IFLG bit must becleared to allow the transfer to continue. When the STOP condition or a repeated START condition is detected after theacknowledge bit, then the IFLG bit is set and the STAT register contains status code 0xA0.

If the AAK bit is cleared to 0 during a transfer, the I2C transmits a Not Acknowledge bit (high level on SDA) after the nextbyte is received, and set the IFLG bit. The STAT register contains status code 0x88 (or 0x98 if slave receive mode wasentered with the general call address). When the IFLG bit has been cleared to 0, the I2C returns to the idle state.

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Section 21: LED Interface

PURPOSE OF LED INTERFACE

The StrataXGS device includes an advanced programmable LED processor to allow simple and complex LED designs inswitch systems.

LED SERIAL PORT

The interface to the LED status indicators is via a serial protocol carried out on two pins: LED_CLK and LED_DATA. Theonly mode supported is that which the BCM56500 calls the low-cost serial interface. If there are n LED status lights, theinterface causes n clocks shifting out data out-of-phase with respect to the LED_CLK. After all n bits have been shifted out,the LED_CLK and LED_DATA lines go idle until the next time the LED status is refreshed. Some external shift register isresponsible for holding the state of the LED status between scan (refresh) events. Although a given LED may temporarilyhold an inappropriate state during the scanout, scanning represents less than a 0.1% duty cycle and is not an issue.

Although the interface presented here is suitable for the low-cost implementation, one feature facilitates smarter interfacesas well. Just before a new burst of bits, the LED_DATA signal pulses once. A low-cost interface does not notice this pulsebecause it is not clocked. A smarter interface that needs some type of framing signal can notice the 0→1→0 transition onLED_DATA without any transitions on LED_CLK and can sync on that.

See Figure 7 for a diagram of the scanout behavior. A simple FPGA or a handful of MSI TTL shift-register parts suffice tocomplete the interface.

Figure 7: LED_CLK/LED_DATA Phase Relationship

LED_CLK

LED_DATA D D D Dn- Dn-

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Figure 8 is a diagram of the relationship of LED_CLK to LED_DATA

Figure 8: LED_CLK/LED_DATA Refresh Interval

Note that the LED_DATA output changes with the falling edge of LED_CLK, so that the positive edge of LED_CLK can beused to clock LED_DATA with ample set-up and hold margins. The LED_CLK period and the frequency of refresh eventsare tied to the chip’s CORECLK frequency and are hardwired.

TLEDCYC is nominally 200 ns (5 MHz). The high and low times for each phase of the clock is guaranteed to be at least 70 ns.The set-up and hold time of LED_DATA relative to the LED_CLK rising edge is a minimum of 50 ns. The drive current forLED_CLK and LED_DATA is 2 mA.

On a larger timescale, Figure 9 shows how the refresh bursts occur. LED_CLK and LED_DATA are both low during the largegaps between the scanout events. The refresh period is nominally 33 ms (30 Hz), but because it is slaved to the CORECLKfrequency, this varies in direct relationship.

Figure 9: LED_CLK/LED_DATA Refresh Interval

On reset, the interface clocks out three hundred 0 bits on the LED_DATA interface. Then it goes idle until the host processorconfigures the LED controller.

Note: If LED_CLK must drive many loads, it should be externally buffered.

LED_CLK

LED_DATA

TLEDCY TLEDLOW TLEDH

TSU THOLD

LED_CLK

LED_DATA

TLEDREF

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Figure 10 shows an example of how to asynchronously detect the first bit of the LED scanout, if that information is needed.The FirstBit signal is active at the rising edge of LED_CLK for the first data bit and inactive at all other rising edges ofLED_CLK. Of course, this is not the only possible implementation. If a higher-frequency clock is available, a small statemachine can look at LED_CLK and LED_DATA and decode this information as well.

Figure 10: LED_DATA Sync Bit Decode

Finally, Table 474 summarizes the timing specifications of the LED serial interface. The cycle time and refresh periodparameters are exactly the same as their nominal rating as long as the chip frequency is 133 MHz, and they vary up anddown directly with the core frequency. The hi/low/setup/hold numbers depend both on frequency and on rise and fall timesof the signals as well.

Table 474: LED_CLK/LED_DATA Timing Specifications

Parameter Minimum Nominal Maximum

TLEDCYC – 200 ns –

TLEDHI 70 ns 100 ns 130 ns

TLEDLOW 70 ns 100 ns 130 ns

TSU 50 ns 90 ns –

THOLD 50 ns 90 ns –

TLEDREF – 30 ms –

FirstBit1AR AR

D Q D Q

LED CLK

LED DATA

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LED PROCESSOR

The LED interface is a combination of hardwired control and programmable formatting. Hardwired logic divides down thecore frequency to produce an approximately 30-Hz LED refresh rate. The period is tied directly to the core frequency, so ifthe chip is run at a lower frequency, the LED refresh rate drops in direct proportion.

In each LED refresh period, the following chain of events occurs:

1 Hardware polls each of the ports to gather the most recent status.

2 This status is stored into the first 64 bytes of processor data RAM.

3 The processor is woken up and starts running the user program, starting at address 0x00.

4 The program inspects the status bits collected from all the ports. It reformats the data in any way it chooses (includingperhaps inspecting status bits located elsewhere in memory that have been established by a host processor). Itconstructs the serial scanout stream bit by bit and stores it into bytes 64–95 of data RAM.

5 The program indicates how many bits need to be shifted out, and then it halts.

6 Hardware shifts out n bits (the number specified in step 5) on the LED_CLK/LED_DATA serial interface, obeying all thetiming constraints.

7 The unit goes to sleep until the next LED refresh period begins.

The following sections provide more detail on the processor architecture and instruction set.

HOST INTERFACE

Before the LED processor can do any work, the host processor must initialize the program RAM for the LED processor andthen enable it to run.

Figure 11 on page 418 shows the registers of the LED processor that are visible to the host processor.

LED_CTRL contains only a single bit. On reset, this register is set to 0. When this bit is 0, the LED processor is preventedfrom running. After initializing the program RAM, this bit should be set to 1 to enable the control program to run.

The LED_STATUS register is read-only. The eight least significant bits contain the current program counter of the LEDprocessor; it can be useful for diagnosing if something has gone wrong with the program. Bit 8 is a flag that indicates whetherthe processor is running (1) or not (0). Bit 9 is a flag that indicates whether the processor is initializing (1) or not (0); this isactive during the time when the processor initially shifts out three hundred 0 bits on the LED serial interface.

The LED processor has 256 bytes of program RAM and 256 bytes of data RAM. The host is free to read or write either ofthese RAMs at any time. The host processor should disable the LED processor while any changes are made, then re-enablethe LED processor when all changes are finished.

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Figure 11: LED Processor Host Interface

PROCESSOR ARCHITECTURE

The LED processor is an 8-bit processor in all regards: the registers are 8 bits wide, as are the memory, the PC (programcounter), and all addresses. The program space and data space are separate, and each is 256 bytes deep. Thus, althoughthe LED processor can read and write any byte of the data RAM, the program RAM can be modified only by the hostinterface.

PROGRAM SPACE

The LED processor has 256 bytes of program RAM. The LED processor can only fetch instructions from this RAM; it cannotread nor modify the program state in any way. Only the host interface is capable of modifying the program RAM.

There are only two special addresses in the program RAM: 0x00 and 0xFE. At each LED refresh period, the processor wakesup and begins executing from address 0x00. The call/return address stack has limited depth. If the processor makes moreCALLs than RETs, the older call addresses fall off the bottom of the stack. If the processor makes more RETs than the depthof the stack, it ends up branching to 0xFE. This should not be used as a feature of the processor; rather, by placing a“JMP 0xFE” instruction at that address, the programmer can catch runaway programs.

0

0x000

baseaddr+

LED_CTRL

0

0x004LED_STATUS

789

00x800

Program RAM

7

0x8040x000x01

0xBFC0xFE0xFF

0xC00

Data RAM

0xC040x000x01

0xFFC0xFE0xFF

0xFF8

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DATA SPACE

The LED processor has 256 bytes of data RAM. Any byte of data RAM can be read or written by the LED processor and bythe host interface. The data space has some locations that have designated uses. Table 475 lists these addresses.Architecturally, there is space for 32 ports, and only 28 ports (ports 0 to 27) are used.

As Table 476 shows, the status bits for a given port are packed into two bytes. These bytes are refreshed at the LED refreshrate immediately before the LED processor starts running. Table 476 shows what each bit of the two bytes of a given portrepresent.

On the HiGig+ port, the LED bits for Collision, Speed, Duplex, and Flow Control are fixed due to the nature of the high-speedlinks. RX, TX, and Link Status are dynamic values derived from the MAC_XGXS_Stat register. Link Enable is derived fromthe MAC_CTRL.RxEn bit, which is set by software.

Table 475: Designated DMA RAM Locations

Address Range Use

0x00–0x01 Status bits for port 0


… …


0x40–0x5F LED scan chain assembly area

0x60–0xFF Undesignated

Table 476: Per-Port Status Bits

Bit Meaning Status = 0 Status = 1

0 RX No frames received Frames received

1 TX No frames transmitted Frames transmitted

2 Collision No collisions (valid in half-duplex) Collisions have occurred (valid in half-duplex)

[4:3] Speed 00 = 10 Mbps01 = 100 Mbps10 = 1000 Mbps

00 = 10 Mbps01 = 100 Mbps10 = 1000 Mbps

5 Duplex Half-duplex (for 10 Mbps or 100 Mbps) Full-duplex

6 Flow Control Not valid Not valid

7 Link Up Not valid (handled by software) Not valid (handled by software)

8 Link Enabled Link disabled Link enabled

9–13 Unused – –

14 False Always 0 –

15 True Always 1 –

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REGISTER SET

The processor has two registers, the A and B registers, which are completely symmetric in their use. These are what most8b processors call the accumulator registers. They are frequently the source or destination operand of instructions. They areuseful in keeping the program size small in that they can be encoded more compactly than a general data address. The Aand B registers can also be used as memory indexing registers, depending on the address mode used by an instruction.

The processor maintains two status bits: the C bit and the Z bit. The C, or carry flag is set when an ALU operation results inALU overflow. The Z flag is set when the result of some ALU computation has a result of 0x00. Each instruction, documentedlater, specifies whether it affects the C and Z flags.

Finally, there is a four-deep, one-bit wide T stack. This Boolean stack can be used to efficiently build up the serial LED datastream. It is explained in more detail in the descriptions of the instruction set and instructions.

ADDRESS MODES

The processor supports a few addressing modes. Due to a lack of instruction bits in which to encode addressing modes (aproblem with all 8b processors), not all instructions allow all addressing modes. In Table 477, the same nomenclature as theassembler us used to indicate the address mode.

See Table 478 for examples that help illustrate these modes.

Table 477: Address Modes

Address Mode Nomenclature Examples The instruction refers to:

Register AB

The contents of the A or B register

Immediate 3

0 × 21label+ (3 << 2) + 1

An immediate 8b constant value

Indirect (A)

(B)

The data RAM location pointed to by the contents of the A or B

Absolute (3)(0 × 21)(label)

((3 << 2) + 1)

The data RAM location pointed to by the immediate 8b constant value

Table 478: Address Mode Examples

Example Explanation

LD A, B The contents of the B register are copied to the A register.

LD A, 3 The immediate value 3 is copied to the A register.

LD B, (0 x 21) Data RAM location 0 × 21 is copied to the B register.

LD (0 x 21), B Data RAM location 0 × 21 is written with the value of the B register.

LD A, (phase) The symbolic label “phase” represents an 8b constant that selects which data RAM location supplies the new value of the A register.

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SUBROUTINES

Unlike a real microprocessor, the LED processor does not maintain a call/return stack in data memory. Instead, a two-deepreturn address stack is kept in registers.

Every time a CALL is made, the address of the next consecutive instruction is pushed on this return address stack, and theprogram execution continues with the immediate address supplied by the instruction. When the new address is pushed onthe stack, the oldest entry on the stack disappears. No exception hardware detects when more than two CALLs are madewithout a corresponding RET.

When a RET instruction is later executed, the top return address is popped off the stack and becomes the new PC (programcounter). The bottom return address value is loaded with 0xFE. The intent is that this minor feature allows a programmer toset a trap at 0xFE to catch programming errors where too many RET instructions were performed.

INSTRUCTION SET

The instruction set provides the usual set of arithmetic, logical, bit twiddling, and branching constructs. In addition, a handfulof specialized instructions and the T stack can be used to efficiently access the port status bits and to build the serial LEDbit string in memory.

All instructions are either 1 or 2 bytes long. All instructions take six CORECLK cycles to execute, even if the instruction is2 bytes or even if the instruction has to access data memory twice for that instruction. The instruction set is symmetric withrespect to the A and B registers. Immediates are symmetric with A and B as long as it makes sense (that is, an immediatecannot be a destination). Any instruction that accepts one of A or B or # accepts the other modes as well (as long as theencoding results in fewer than three bytes).

Table 481 on page 425 and Table 482 on page 426 supply enough information for any programmer familiar with typicalassembly language to figure out the function of the typical instructions. Looking at the examples later in the document willalso help clarify their use.

However, the LED-specific operations need further explanation. Here too, examining the example code presented later willhelp. Almost all of these instructions involve the Boolean T stack. This stack is 1 bit wide and 4 words deep. The instructionsbelow supply a simple way to extract status bits, combine them, and pack them into bytes ready to shift out the LED serialport. Only the SEND operation is essential; all the other instructions are merely convenient.

LD (A), 077 The data RAM location indexed by the contents of register A is overwritten with the 8b octal constant 077 (63 decimal).

JMP 0x30 The program continues fetching instructions from address 0x30.

Note: Any expression that begins with an opening parenthesis is interpreted as being an absolute or indirectaddress mode. Immediate constant expressions that must be parenthesized can start with a unary + or someother idempotent operation to skirt the issue.

Table 478: Address Mode Examples (Cont.)

Example Explanation

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PORT and PUSHST Instructions

The first 64 bytes of the data RAM are subdivided into 32 pairs of bytes. Each pair of bytes is automatically loaded with themost recent status gathered from each of the Ethernet ports.

PORT takes one argument, which specifies which of the 32 logical Ethernet ports is to be inspected. Although there arelogically 32 ports, the StrataXGS device only scans ports 0 to 25; the status bytes for ports 26–31 are undefined. Thisinstruction itself does nothing, but the value supplied is retained and used by the PUSHST instruction.

PUSHST takes one argument; the four least significant bits of the argument specify which of the 16 bits of the two port statusbytes is to be extracted. The extracted bit is then pushed on the top of the T stack.

For example, the sequence:

PORT 3PUSHST 2

causes bit 2 of data RAM location 0x06 to be tested and pushed on the T stack. Although this example uses a constant tospecify which port to test, most programs would probably use a variable to set the port and increment this variable as partof a loop.

It is quite possible to access a given bit of a given port via the more common LD and TST instructions. PORT and PUSHSTjust make it a lot easier. The above sequence could have been coded as:

LD A,3 ; or whatever port specifier you wantADD A,A ; double it—two status bytes per portTST (A),2 ; extract bit 2 of data RAM location APUSH CY ; save the bit on the T stack

PUSH Instruction

This instruction takes one argument. The least significant bit of the argument is extracted and pushed on the T stack. As aspecial case, the C (carry) flag can be pushed on the T stack with the instruction

PUSH CY

POP Instruction

This instruction removes the top entry of the T stack and copies it into the C (carry) flag. It can be used for further conditionaltests, or it can be useful for simply removing the top of the stack.

For instance, to duplicate the top of stack, the following code sequence can be used:

POPPUSH CYPUSH CY

TAND, TOR, TXOR, TINV Instructions

TAND, TOR, and TXOR instructions remove the top two entries from the T stack, perform the specified Boolean operationon the two bits, then push the resulting bit back on the stack.

The TINV instruction simply complements the value on the top of the T stack.

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All of these instructions are useful for combining status bits to achieve compound status indications. For instance, if an LEDis supposed to go active whenever a port has received or transmitted packets, the following code sequence will do the job:

PUSHSTRX ; extract RX bit from current portPUSHSTTX ; extract TX bit from current portTOR ; replace those two bits with logical OR

PACK Instruction

Unlike the previous instructions concerned with extracting bits, this operation builds the output bit string that drives the serialLED port. Recall that when the processor finishes, hardware serializes the bit stream starting at bit 0 of location 0x40 in thedata RAM and clocks it out on the serial LED interface port.

Every time the hardware begins an LED refresh cycle, just before it wakes up the processor, a buried state associated withthis instruction is initialized to point to bit 0 of byte 0x40 in the data RAM.

Every time a PACK instruction is issued, the top of the T stack is popped off and stored to the bit location indicated by theburied state; the buried state is then updated to point to the next bit, taking care of byte boundary crossings as required.

Note that the buried bit pointer state is inaccessible. This means that programs that use this instruction must build the bitstring in the exact order that it appears on the serial LED line.

It is possible to entirely ignore this instruction; the hardware simply shifts out whatever bits it finds, starting at location 0x40.This instruction could be roughly mimicked by the following few generic instructions:

(at reset)

LD A,0x40LD (packbyte),ASUB A,ALD (packbit),A

(then at each place where PACK would have been used)

LD A,(packbyte) ; get byte pointerLD B,(packbit) ; get bit pointerPOP ; extract top of T stack into C flagBIT (A),B ; copy C flag into specified bitINC B ; point at next bitAND B,7 ; mod 8JNZ UPDPTRINC (packbyte) ; bump the byte pointer

UPDPTR:LD (packbit),B

SEND Instruction

The SEND instruction takes one argument, which specifies how many bits there are in the LED scan chain. A value of 0x00means 0 bits, not 256 bits. This is the only LED-specific instruction that can’t be emulated through other means.

When this instruction is performed, the processor halts until the next LED refresh cycle. Hardware then extracts bits startingat bit 0 of data RAM location 0x40 and shifts them out the LED serial port. Since the maximum length LED chain is 255 bits,this requires 32 bytes: RAM 0x40 to 0x5F. However, if the LED scan chain is shorter, the bytes at the end of this range canbe safely used for any purpose the programmer wants.

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JT and JNT Instructions

JT and JNT test the top of the T stack.

OPCODE MAPS

The following two tables, Table 479 and Table 480, show all valid opcodes. Empty entries in the tables are illegal opcodesand should not be used. Executing such opcodes results in undefined behavior. All opcodes that contain either “#” or “(#)”as an argument require two bytes; all other instructions are encoded in one byte.

The following four instructions, shaded in Table 479 and Table 480, are logically meaningful, but are not permitted becausethey would require two immediate values, resulting in a three-byte long instruction:

• BIT (#),#

• LD (#),#

• LD (#),(#)

• TST (#),#

The mnemonic convention is that if there are two operands for an instruction, the destination is on the left. For example:

ADD A,B

means to add registers A and B together, placing the results into register A.

Table 479: Opcodes 0x00 to 0x7F

MS NibbleLS Nibble

0 1 2 3 4 5 6 7

0 LD A, A LD A, B LD A, # – LD A, (A) LD A, (B) LD A, (#) CLC

1 LD B, A LD B, B LD B, # – LD B, (A) LD B, (B) LD B, (#) STC

2 PUSH A PUSH B PUSH # – PUSH (A) PUSH (B) PUSH (#) PUSH CY

3 PUSHST A PUSHST B PUSHST # – – – – CMC

4 LD (A), A LD (A), B LD (A), # – LD (A), (A) LD (A), (B) LD (A), (#) –

5 LD (B), A LD (B), B LD (B), # – LD (B), (A) LD (B), (B) LD (B), (#) RET

6 LD (#), A LD (#), B LD (#), # – LD (#), (A) LD (#), (B) LD (#), (#) CALL #

7 JZ # JC # JT # – JNZ # JNC # JNT # JMP #

8 INC A INC B – – INC (A) INC (B) INC (#) PACK

9 DEC A DEC B – – DEC (A) DEC (B) DEC (#) POP

A XOR A, A XOR A, B XOR A, # – XOR A, (A) XOR A, (B) XOR A, (#) TXOR

B OR A, A OR A, B OR A, # – OR A, (A) OR A, (B) OR A, (#) TOR

C AND A, A AND A, B AND A, # – AND A, (A) AND A, (B) AND A, (#) TAND

D CMP A, A CMP A, B CMP A, # – CMP A, (A) CMP A, (B) CMP A, (#) TINV

E SUB A, A SUB A, B SUB A, # – SUB A, (A) SUB A, (B) SUB A, (#) –

F ADD A, A ADD A, B ADD A, # – ADD A, (A) ADD A, (B) ADD A, (#) –

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Table 481 is an alphabetic listing of the instructions and their encoding. It includes the affected flags and offers a briefinstruction description. To understand the field encoding used in Table 481, refer to Table 482.

Table 480: Opcodes 0x80 to 0xFF

MS NibbleLS Nibble

8 9 A B C D E F

0 TST A, A TST A, B TST A, # – BIT A, A BIT A, B BIT A, # –

1 TST B, A TST B, B TST B, # – BIT B, A BIT B, B BIT B, # –

2 PORT A PORT B PORT # – PORT (A) PORT (B) PORT (#) –

3 SEND A SEND B SEND # – SEND (A) SEND (B) SEND (#) –

4 TST (A), A TST (A), B TST (A), # – BIT (A), A BIT (A), B BIT (A), # –

5 TST (B), A TST (B), B TST (B), # – BIT (B), A BIT (B), B BIT (B), # –

6 TST (#), A TST (#), B TST (#), # – BIT (#), A BIT (#), B BIT (#), # –

7 – – – – – – – –

8 ROL A ROL B – – ROL (A) ROL (B) ROL (#) –

9 ROR A ROR B – – ROR (A) ROR (B) ROR (#) –

A XOR B, A XOR B, B XOR B, # – XOR B, (A) XOR B, (B) XOR B, (#) –

B OR B, A OR B, B OR B, # – OR B, (A) OR B, (B) OR B, (#) –

C AND B, A AND B, B AND B, # – AND B, (A) AND B, (B) AND B, (#) –

D CMP B, A CMP B, B CMP B, # – CMP B, (A) CMP B, (B) CMP B, (#) –

E SUB B, A SUB B, B SUB B, # – SUB B, (A) SUB B, (B) SUB B, (#) –

F ADD B, A ADD B, B ADD B, # – ADD B, (A) ADD B, (B) ADD B, (#) –

Table 481: Instruction Opcode Encoding

Encoding Op Dst Src Flags Explanation

Typical µP Data Operations

0ddd0sss LD DDD SSS – DDD ← SSS

1111dsss ADD D SSS CY,Z D ← D + SSS

1110dsss SUB D SSS CY,Z D ← D – SSS

1101dsss CMP D SSS CY,Z Null ← D – SSS (only flags affected)

1100dsss AND D SSS Z D ← D & SSS

1011dsss OR D SSS Z D ← D | SSS

1010dsss XOR D SSS Z D ← D ^ SSS

10000ddd INC DDD – CY,Z DDD ← DDD + 1

10010ddd DEC DDD – CY,Z DDD ← DDD – 1

10001ddd ROL DDD – CY,Z DDD ← {DDD[6:0], DDD[7]}; CY ← DDD[7]

10011ddd ROR DDD – CY,Z DDD ← {DDD[0], DDD[7:1]}; CY ← DDD[0]

0ddd11ss BIT DDD SS Z Set bit SS[2:0] of DDD with value of CY

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0ddd10ss TST DDD SS CY Set CY with bit SS[2:0] of DDD

00000111 CLC – – CY CY ← 0

00010111 STC – – CY CY ← 1

00110111 CMC – – CY CY ← !CY

Branching Operations

01110ccc J{CCC} # – – If CCC, PC ← #

01110111 JMP # – – PC ← #

01100111 CALL # – – RET ← PC+2, PC ← #

01010111 RET # – – PC ← RET

LED-Specific Operations

00101sss PORT – SSS – Set PORT addressing state with SSS

001100ss PUSHST – SS – Push state bit MEM[R_PORT,SS[3]] bit SS[2:0]

00100sss PUSH – SSS – Push LSB of SSS onto state stack;SSS==7 means push CY bit

10010111 POP – – CY CY ← top of state stack; pop stack

11000111 TAND – – – ANDs top two bits of T stackBoolean stack manipulation

10110111 TOR – – – ORs top two bits of T stack

10100111 TXOR – – – XORs top two bits of T stack

11010111 TINV – – – Inverts top bit of T stack

10000111 PACK – – – Pops top of stack to output buffer

00111sss SEND – SSS – Shift out SSS bits on LED port and halt

Table 482: Instruction Field Encoding

Field Key 0 1 2 3 4 5 6 7

SSS A B # – (A) (B) (#) –

SS A B # – – – – –

DDD A B – – (A) (B) (#) –

D A B – – – – – –

CCC Z C T – NZ NC NT –

Table 481: Instruction Opcode Encoding (Cont.)

Encoding Op Dst Src Flags Explanation

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LED PROCESSOR TOOLS

The tools described below are supplied with the Broadcom SDK.

ASSEMBLER

A simple assembler, ledasm, has been written to help generate the binary to be loaded into the program RAM. Because theprograms are rather small and simple, the assembler does not support advanced features of typical macro assemblers. Ifmacro capabilities are wanted, use cpp, m4, or a similar program to get that capability. The ledasm assembler does notsupport linking.

The ledasm assembler does support a few niceties. Comments begin with a semicolon. Symbolic labels are supported, upto 31 characters. Constant expressions can be formed using a number of operators, following the precedence rules of theC language.

The input to the assembler is a simple ASCII text file. The assembler produces two output files: a listing file, and a binaryhex file. The hex file consists of 16 lines of 16 bytes, where each byte is encoded as a pair of uppercase ASCII hex digits,with a space before hex pair.

DISASSEMBLER

The hex files produced by the ledasm, or any hex file in the same format, can be disassembled with ledasm. In and of itself,the program probably does not have tremendous utility. However, the disassembler was written in two pieces: a standaloneone-instruction disassembler that can be used as part of other tools, and a driver program that reads the hex file and callsthe one-line disassembler for each instruction.

SIMULATOR

A simple simulation environment can read ledasm hex files and either run through or single-step through the instructionstream, allowing the LED programs to be debugged before entering into a system environment. There are commands toinspect memory, load memory from a file, turn tracing on and off, disassemble a range of addresses, single-step, continue,reset, and run.

EXAMPLE PROGRAMS

Example programs are provided with the Broadcom SDK software.

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Document 56500-PR100-R


16215 Alton ParkwayP.O. Box 57013

Irvine, CA 92619-7013Phone: 949-450-8700

Fax: 949-450-8710

Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation

does not assume any liability arising out of the application or use of this information, nor the application or use of any product orcircuit described herein, neither does it convey any license under its patent rights nor the rights of others.

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