Session 2532

Pros and Cons of replacing discrete logic with programmable logicin introductory digital logic courses.

Kevin Nickels

Trinity University

Abstract

Digital circuit constructionwith small-scaleintegrated(SSI) andmedium-scaleintegrated(MSI)logic haslong beena cornerstoneof introductorydigital logic designlaboratories.Recently, in-structorshavebegunreplacingtheseprojectswith designsusingcomplex programmablelogic suchasprogrammablearraylogic (PLA) chipsandfield programmablegatearrays(FPGAs).

This paperinvestigatesthe trendof replacingthe “traditional” SSI/MSI breadboardeddigitallogic designprojectswith designprojectsutilizing morecomplex programmableintegratedcir-cuits.Withouta doubt,eachstylehasits own strengthsandweaknesses.

Utilizing complex programmableintegratedcircuits (ICs) suchas PLAs and FPGAs,moreinterestingandinvolvedprojectscanbeimplemented.Modernprogrammingtoolsallow thespec-ification of quitecomplex circuitsfrom agraphicalschematicor proceduralhardwaredescription.Thesespecificationscanbedownloadedinto theIC, whichthenfunctionsasspecified.Sincemuchof thedesignis in theprogrammingof theIC, very involvedprojectscanbeimplementedwithoutsignificantlyincreasingthewiring complexity of theproject.Studentsdon’t spendhourstrying tofind anupside-down IC or a brokenconnection,andcanconcentrateon digital design.

Thedesigncomplexity andinnovationin theseprojectsis unarguablyincreasedoverSSI/MSIprojects,but this doesnot comewithout a pedagogiccost. Someof the argumentsfor having alaboratorycoursein thefirst placeareto appealto thesensorlearningstyle,to exposethestudentsto more“hands-on”andlesstheoreticalprojects,andto introducethepracticalaspectsof designingandimplementingdigital circuits.Theseobjectivesmaynotbemetaswell whenmoving from theSSI/MSIprojectsto moresoftware-orientedprojects.

Bothstylesof digital designprojectshavepedagogicstrengthsandappealto particularlearningstyles. It is importantto studythecourseobjectivesandthestudentmix whendecidingto moveprojectsfrom the traditionalstyle of physicallyconstructingcircuits from SSI andMSI compo-nentsto anew styleof simulatingandprogrammingcomplex chipsasameansof verifying digitallogic designs.By doing this, we cancombinethe two methodologiesto arrive at a coursethatappealsto a broadrangeof students,providesthe“hands-on”experiencesomestudentsneed,andutilizes moderntechnologiesto increasethe innovation,designcomplexity, andinterestvalueofimplementedprojects.

1 Introduction

Theconstructionof combinationalandsequentialdigital logic circuits from discretecomponents,usuallyutilizing TTL (TransistorTransistorLogic) DIP (Dual In-Line Packaging)chips,will befamiliar to anyonewhohasseenundergraduateelectricalandcomputerengineeringlabsin thepastfew decades.In this typeof lab,adesiredbehavior is oftengivenin termsof aproblemdescription

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with input/outputspecifications.The theoreticaldesignis completed,andtheresultmappedinto7400serieschips. The final designis thenconstructedon a breadboard,andverified by usingswitchesandsignalgeneratorasinputsandLEDs(Light Emitting Diodes)asoutputs.

TTL SSI (small scaleintegration)packagescontainfewer than10 gates,andtypically imple-mentsimplecombinationalcircuitssuchasAND, OR,andNOT gates,or simplesequentialcircuitssuchasD or JK flop-flops.TTL MSI (mediumscaleintegration)packagescontain10to 100gates,andimplementmorecomplex circuitssuchassmalladders,decoders,andcounters.

As complex programmablelogic deviceshave becomemoreavailableandaffordable,manyschoolsareincorporatingtheminto their undergraduatelaboratorycurriculum.2,4,7 In somecases,they arecompletelyreplacingthediscreteTTL DIP implementationsdescribedabove.

ProgrammableLogic Arrays(PLAs)aresinglechippackages(availablein DIP format)thatim-plementanarrayof logic: theinputscanbeANDed togetherin any combination,andtheproducttermsgeneratedcanbeORedtogetherto arriveatany SOP(Sumof Products)Booleanexpressionwith theavailablenumberof input terms.5 Theprogrammermayberequiredto computetheinter-connections,or softwaredistributedby thechip manufacturermaycomputethe interconnectionsfrom Booleanexpressionsgivenby theuser.

Field ProgrammableGate Arrays (FPGAs) are much more complex programmablechips.Thereareseveralarchitecturesfor FPGAsavailable: two populararchitectureswill bedescribedhere. TheXilinx chipsutilize an “island-type”architecture,wherelogic functionsarebrokenupinto small islandsof 4-6 termarbitraryfunctions,andconnectionsbetweentheseislandsarecom-puted.Figure1(a) illustratesthebasicstructureof theXilinx FPGA.Altera’s architecturetiesthechip inputsandoutputsmorecloselyto thelogic blocks,asshown in Figure1(b). Thisarchitectureplacesthelogic blocksaroundonecentral,highly connectedroutingarray.

Block (CLB)Logic

Configurable

I/O Block

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Block (CLB)Logic

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Block (CLB)Logic

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I/O Pins

(LAB)

BlockArrayLogic Logic

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(LAB)

LogicArrayBlock

(LAB)(LAB)

BlockArrayLogic

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BlockArrayLogic Logic

ArrayBlock

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InterconnectionProgrammable

Array

(PIA)

(a) Xilinx 6 (b) Altera5

Figure1: Field-ProgrammableGateArray Structure

Segmentinga digital designinto islandsof appropriatesizeandcomplexity for the chip androutingtheconnectionsbetweenthemwithin theconnectivity constraintsof thechipiscertainlynotsomethingthata usercanbeexpectedto do. Manufacturersprovide standalonetoolsor interfacesto popularCAD (computeraideddrafting)packagesto allow usersto input thedesign,graphically

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or in a hardwaredescriptionlanguage.Thesetools thenautomaticallysegmentthedesign,routetheconnectionsbetweenthesegments,andallocatechip resourcesfor thedesign.Theuserthendownloadsthedesignfrom thedesignworkstationto thechip.

Manufacturersprovide developmentsboardsfor studentsanddesignersthat containa powersupply, someswitchesfor input andLEDs for output,a FPGA,andconnectionsfor downloadingdesignsfrom aworkstationall ononeboard.TheswitchesandLEDsareoftenhardwiredto FPGAinput/outputpins,andthepinoutsaregiven.

2 ExampleLaboratoryProject

In thispopularproject,thestudentis askedto designandimplementasimpletraffic light controller.It is assumedthat therearetwo setsof lights: onefor the east-westroadandonefor the north-southroad.Thestreetlightscycle in afixedpatternof 45secondsgreen,3 secondsyellow, and48secondsred.A designrequirementis thatalight mustalwayscyclethroughyellow beforechangingfrom greento red. It is assumedthatan 0.33Hz clock anda 45 secondtimer areavailable(Thetimer is referredto assignal

�����below). Extensionsto this basicscenarioincludetraffic sensors

to detectwaiting traffic and emergency sensorsto detectoncomingemergency vehiclesand asquickly aspossible(allowing for therequiredyellow) give theappropriatestreetagreenlight.

2.1 Design

Thedigital logic designportionof this laboratoryconsistsof threesteps:thestatetransitiondia-gram,thepresent-state/next-state(PSNS)table,andthenext-state/outputequations.Theproblemstatementis analyzed,andit is foundthatfour statessuffice for thebasicscenario.A statetransi-tion diagramandPSNStablearederived.FromthePSNStable,Karnaughmapsfor thenext-stateequationsandoutputequationscanbecreated.TheKarnaughmapsyeild minimal Booleanequa-tionsfor thesefunctions,asfollows:

���� ������� � � ���� ��� ���� ����� � ���� ��� � �� � � ����� ��� ��� � � ����� ��� �� � ����� � ����� ��� � �

Theseequationscompletethetheoreticaldesignof thetraffic light controller.

2.2 ConstructionComparison

TheTTL DIP implementationof this controllerinvolvesfinding 7400serieschipsthat implementeachcomponentin the schematic,andconnectingthemasshown in Figure2(a). Additionally,powerandgroundconnectionsfor eachTTL chip arerequired.

This implementationrequireswiring 5 separateDIPson a breadboard,connecting6 LEDs tomonitor theoutputsof thedesign,a clock to drive thesequentialcircuit, anda resetswitch. Thisinvolvesapproximately35 separatewires,not including power andgroundconnectionsfor eachchip.

TheFPGAimplementationinvolvesdescribingthecircuit in aformatthatthemanufacturercanaccept.Thegraphicalinput to Altera’s MAXPLUS-II softwareis shown in Figure2(b). Input andoutputpins that correspondto pins thatareaccessibleon theFPGAdevelopmentkit arechosen,andthedesignis downloadedto theFPGA.

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(a) TTL Implementation

(b) FPGAImplementation

Figure2: AlternateImplementationsof Traffic Light Controller

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This implementationmay requirewiring 6 LEDs to specifiedoutputpins of the FPGA, if adevelopmentkit is involvedthatdoesnot provide hardwiredLEDs. Similarly, a resetswitchandclock mayneedto beattachedto theFPGA.No otherwiring is required.

3 DebuggingComparison

Commondesignerrorsincludeproblemswith readingthePSNStable,with theKarnaughmaps,andwith translatingthe Booleanequationsinto a gate-level schematic.Errors in this stagewillcauseproblemswith all implementationsof thedesign.

Commonimplementationerrorsin theTTL implementationinvolveplacingchipsin thebread-boardbackwards,notconnectingpowerandgroundwires,wiring to thecorrectpin of anincorrectchip,andmissedconnections.Occasionally, wiresthatarebrokeninsidetheinsulationandfaultychipscomplicatethis (althoughnotasoftenasthestudentswill claim).

Debuggingtheseerrorsusuallyinvolvesputtingthemachineinto aknown state,lookingat thenext-stateequationsto determinethedesirednext state,connectinga logic probe(or LED) to theinputof thestateflip-flops,andmoving theprobebackwardin thenext-statelogic to determinethelocationof the incorrectlogic signal. This is repeateduntil themachinemakesthedesiredsetofstatetransitions.Outputdebuggingis similar, with theprobetracingtheoutputlogic.

Oncethedesignis completelyprobedin a givenstate,theerrorcanbefixedby replacingthefaulty chip or wire. A fully labelledschematicwith pin assignmentsis invaluablein debuggingthesecircuits.

Commonimplementationerrorsin the FPGA implementationinvolve assigningoutputsto apin otherthanthe onewired (by the useror the developmentsystemmanufacturer)to the LED,incorrectgraphicalentryof theschematic,andmany othersoftwaretool problemssuchascompi-lationproblems,incorrectlibrary references,or operatingsystemproblems.

Debuggingtheseerrorsusuallyconsistsof a seriesof compileandteststeps,resemblingthecompilationof a programmingproject. The only signalvaluesavailable for debuggingareanythat have beenpre-assigned(the designatedoutputs,plus any predefinedprobes). The probingprocessdescribedabove can be repeated,but only with a recompilefor eachmovementof theprobe. Simulationalleviatesmany of theseproblemsby allowing the user to debug the logicbeforedownloadingthecircuit to theFPGA.A fully debuggedcircuit usuallyonly hasinput/outputassignmentproblems.

4 PedagogicComparison

Now that the implementationandcommonerrorsof a projectusingthesetwo technologieshavebeendiscussed,wemoveonto adiscussionof theimpactof theseissuesontheprojectimplement-ed,andwhatthestudentslearnby completingtheseprojects.

The TTL implementationof a designis the closestin feel to a “direct” implementationof agate-level design.Thecorrespondencebetweenthelogic design,thegate-level schematic,andtheTTL schematicis easilyseen.Theeffect on thedigital signalsof eachtypeof gateis alsoeasytosee,asthesignalspropagateacrossthebreadboard.For studentsof the “sensor”learningstyle,3

this typeof implementationoffers an opportunityto touchchipsthat they canassociatewith theabstractconceptof a gateor flip-flop.

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However, theTTL implementationis alsothemostproneto wiring error. As all theconnectionsbetweengatesaremadeonthebreadboard,therearemany opportunitiesfor amiswireor omission.Oncebreadboardshave beenusedfor a few years,they developsomelooseconnections,so thata circuit maywork at times,andnot work at othertimes. This implementationis by far themoretime consumingof the two implementationsdiscussedhereto construct. Without closeattentionto wire routing,evenamoderatelycomplex TTL-baseddesignbeginsto resembleabirdsnest.Forthis reason,circuitswith a chip countof approximately7 arethemostcomplex theauthorwouldrecommendfor asingleafternoonintroductorylab.

Theseerrorscontributeto problemsin learningwhenthestudentsspendaninordinateamountof time working with, and solving, problemsthat have little to do with the courseobjectives.Worseyet theseproblemsmayonly have to do with laboratoryhardware,andmaynot generalizeto thepracticalproblemsencounteredprototypingcircuitsin practice.Many studentsspendhourscheckingandrecheckingtheir PSNSequationsonly to find that they have benta pin underthepackagewheninsertingit into thebreadboard.Certainly, this is not thetypeof lessonthestudentsneedto learnasa resultof laboratorywork.

Thegraphicalimplementationof a designbeginsto resembleasoftwareprogrammingor sim-ulationproject.If agoodsimulatoris available,thebulk of theimplementationtime takesplaceinfront of a computerin a testandcompilecycle. Oncethedesignis simulatedto work correctly, itis downloadedto theFPGAand(barringany input/outputassignmentproblems)is shown to work.The illustrationof a working circuit is ananti-climaxto many studentsworking on FPGA-baseddesigns:few new insightsaregainedby thefinal step. If theavailablesimulatoris not adequate,studentsoftenroutelogic probesfrom differentplacesin thecircuit to a few outputpinsdedicatedfor the debuggingprocess.Eachtime theseprobesneedto be moved,a compileanddownloadcycle is required. The cycle time for an incrementalchangeis much longer for a FPGA-basedimplementationthanfor theequivalentTTL-basedimplementation.

Theerrorsintroducedin this implementationtendto bedifferentfrom thoseencounteredin theTTL-basedimplementation.Miswires aremoreeasilyspotted,andwire tanglesareavoidedbyshortcutsin the softwaresuchasnamedsignals(signalsthat aretaggedwith the samenameareconsideredto be connectedto oneanother, regardlessof their routing in theschematic.)Finally,a hierarchicalstructureis available,wherea small circuit is testedanddebugged,thenusedin alarger circuit. This modulardesignallows the constructionof muchmorecomplex circuits thanarepossiblewith SSIandMSI basedlogic. Horning4 givesexampleprojectscontainingup to 72statesthathavebeenimplementedusingFPGAswith Altera’s designtools.

Theproblemsencounteredin a typical laboratoryalsodo not necessarilycontributeto desiredlearninggoals.Proficiency with acomputersimulatorandschematiceditorrequiresaconsiderableamountof time andeffort. Althoughbotharegettingbetterastime progresses,Operatingsystemandsoftwaretool problemsmaydominatetheexperiencefor a student,contributing little to theirunderstandingof theunderlyingdigital designtasks.

In an introductorycourse,theseproblemsmay precludethe exclusive useof programmablelogic devicesin thelaboratory. Many of theseargumentsholdevenwhenthesedevicesareusedinadvancedcoursessuchasthosedescribedby ChrenandZomberg,1 but areovercomeby thenatureof thecourseandtheprerequisiterequirementfor anintroductorylogic designcourse.

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5 Discussion

While thereis muchto begainedby usingcomplex programmablelogic in introductorydigital de-signlaboratories,it shouldbeimplementedwith caution.Theuseof this technologywill allow anincreasein thedesigncomplexity while allowing adecreasein theamountof timespentdebuggingwiring andotherhardwareimplementationproblems.

However, thereare someseriousdrawbacksto using thesetechnologies,particularly in anintroductorylaboratory. Studentsstudyingsequentialandcombinationallogic for the first timeoften have problems“seeing” how the designwill translateinto input/outputbehavior. Studentsoperatingin the “sensor” learningstyle will have moredifficulty graspingthe effect of variouschangesin logic designs.Thetotal amountof time spentdebuggingdoesnot seemto change,butthe typesof activities the studentsengagein changesfrom finding miswiresandproblemswithchipplacementto amorecomputer-basedapproachof simulationandre-compilation.

Bibliography

1. W. A. ChrenandB. G. Zomberg. Programmablelogic coursedevelopmentin anengineeringcurriculum. In Proceedings American Society for Engineering Education Annual Conference,pages1154–1158,1993.

2. R. Coowar. Designingwith field programmablegatearrays.In Proceedings American Societyfor Engineering Education Annual Conference, pages853–859,1995.

3. R. M. FelderandL. K. Silverman. Learningandteachingstylesin engineering.Journal ofEngineering Education, 77(2),February1988.

4. D. W. Horning.Integrationof digital designtoolsinto adigital designsequence.In ProceedingsAmerican Society for Engineering Education Annual Conference, pages1104–1108,1993.

5. R. Katz. Contemporary Logic Design. Benjamin/Cummings,California,1994.

6. M. M. ManoandC. R. Kime. Logic and Computer Design Fundamentals. Prentice-Hall,NewJersey, 2ndedition,1997.

7. A. K. Ojha. Implementationof anundergraduatelaboratoryonprogrammablelogic devices.InProceedings American Society for Engineering Education Annual Conference, pages846–852,1995.

KEVIN M. NICKELSKevin Nickels is anAssistantProfessorof EngineeringScienceat Trinity University. He receivedtheB.S.degreeinComputerandElectricalEngineeringfrom PurdueUniversity in 1993,andreceivedtheM.S. degreein 1996andthedoctorof philosophydegreein 1998in ElectricalEngineeringfrom TheUniversityof Illinois at Urbana-Champaign.He is currently working in the areasof computervision, patternrecognition,androbotics. His e-mail addressisknickels@engr.trinity.edu

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