Protection of hybrid transformers in the distribution grid

J. Burkard, J. Biela Power Electronic Systems Laboratory, ETH Zürich

Physikstrasse 3, 8092 Zürich, Switzerland

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Protection of Hybrid Transformers in the

Distribution Grid

J. Burkard and J. Biela

Laboratory for High Power Electronic Systems

ETH Zurich, Physikstrasse 3, CH-8092 Zurich, Switzerland

Email: burkard@hpe.ee.ethz.ch

Abstract—Due to the increasing integration of renewable energysources and power electronic loads into the distribution grid, adeterioration of the grid power quality is expected. Consistingof a low frequency transformer and a fractionally rated powerelectronic converter, the hybrid transformer can be applied toensure a high power quality by controlling voltage, current,active and reactive power dynamically. For the application ingrids with conventional grid protection infrastructure, hybridtransformers have to withstand considerable overvoltage and-current stresses during voltage surges or grid short circuits.Since the semiconductors are less robust than low frequencytransformers with respect to these stresses, the effects of possiblefault scenarios and a protection concept are studied in this paper.

I. INTRODUCTION

In the future grid, an increasing penetration of distributedgenerators and power electronic converters with high dynamicsare expected. Fast grid voltage variations due to the fluc-tuating generation power of renewable energy sources area consequence, especially in the low voltage (LV) distribu-tion grid. Hybrid transformers (HT) combine a conventionallow frequency transformer (LFT) with a fractionally ratedpower electronic converter and are a promising solutions toensure high grid power quality. With the ability of the powerelectronic converter to control voltage, active and reactivepower, to filter harmonics and to balance the load currents,HTs feature enhanced controllability in comparison to LFTsequipped with tap changers. Since the major part of the poweris transferred through the LFT, the HT concept utilizes thehigh efficiency and low cost of LFTs. Besides distributiongrids, further possible applications of HTs are transmission,industry and railway grids. A detailed comparison of HTsand alternative solutions like tap changing and solid statetransformers (SST) has been performed in [1]. In Fig. 1 theconsidered HT topology for the connection of the mediumvoltage (MV) and LV distribution grids is depicted. ConverterA© of the back to back converter is series connected to the LVwinding, whereas converter B© is connected to an auxiliarywinding of the LFT. With this arrangement, the injection ofactive and reactive currents and voltages is possible. In the LVdistribution grid, an accessible neutral conductor is requiredwhich is provided by an actively balanced split DC-link. Thespecifications of the considered 400 kVA, 20 kV-400 V HT aregiven in Tab. I. A 3D rendering of a possible attachment ofthe converter to the LFT is shown in Fig. 2.

Due to external faults like short circuits and lightning tran-sients, the operation of power electronic converters in the grid

AC

DC

DC

AC

LV gridMV

grid

LFT

N

Converter

Vser

B A

Fig. 1: Three-phase HT as presented in [1]. Converter A© is series connectedto the LV winding, converter B© is connected to an auxiliary winding. The MVwinding is delta connected, whereas a neutral conductor with earth connectionis present on the LV side.

1.3 m0.7 m

1.2 m

Fig. 2: 3D rendering of a possible attachment of the back to back converterto the LFT including the protection concept as described in section IV.

presents a challenge. In contrast to the LFT, semiconductorsemployed in such converters have a very limited overvoltageand only a very short term overcurrent capability. However, thegradual transition towards a smarter grid requires novel assetslike HTs, SSTs and FACTSs to comply with the existing gridprotection technology, which is adapted to robust overheadlines, cables and LFTs. Considerable voltage and currentstresses necessitate the development of a protection conceptfor the HT which is presented in this paper.

Although SSTs and FACTS devices are widely discussed inliterature, only few publications investigate the implicationsof the protection requirements on the design. The authors of[2], [3] and [4] present measures to protect the semiconduc-tors of SSTs from overvoltages and overcurrents. In [5] theprotection of series injection converters as present in unifiedpower flow controllers and HTs (cf. Fig. 1) is addressed. For

TABLE I: Specifications of the investigated 400kVA, 20kV-400V HT.

Parameter Value

Sn 400kVAVMV, VLV 20kVRMS, 400VRMS, line to lineControllability ±10% of nominal V (LV side), P and QSconv, Vser 40kVA, 23VTopology 2-level voltage source inverters, back to backDC-link 70V, 5mF, actively balanced split DC-link

the HT, the connection of the power electronic converter tothe LFT prevents the application of the published protectionconcepts. A detailed investigation of the effects of differentfault scenarios taking into account the transformer parasiticsand the grid characteristics is performed in this paper, which isstructured as follows. In Section II, an overview of possiblefaults is given and the protection requirements for the LFTand the HT are derived. Simulation models for voltage surgesand grid short circuits are developed in Section III based onwhich the protection concept is developed in Section IV. Theimpact of the protection concept on the system performanceis discussed in Section V.

II. FAULTS AND PROTECTION REQUIREMENTS IN

DISTRIBUTION GRIDS

A. Possible Grid Faults

A variety of fault scenarios is possible for converters interfacedwith the grid. In general, they can be classified into internalfaults, which occur within the converter (e.g. semiconductor orcontrol system failures) and external faults, which occur in thegrid and impose stresses on the converter. This paper focusseson external faults, which can be further divided into scenarioswhere primarily overvoltages or -currents reach critical values,cf. Fig. 3. However, it has to be noted that overvoltages alsoexcite overcurrents and vice versa, which can be harmful forthe converter. Transient overvoltages with very high amplitudescan be caused by lightning and switching surges and havetypical durations between a few tens of microseconds and sev-eral milliseconds. In contrast to that, temporary line frequencyovervoltages can last for up to seconds and are mainly causedby earth faults.

The selectivity of the grid protection limits the adverse impactof the fault to the smallest possible grid region by discon-necting the fault as far downstream as possible. In the LVgrid this selectivity is achieved by applying circuit breakers orfuses with decreasing tripping currents and times. To ensure areliable fault detection and disconnection, the transformer hasto provide considerable short circuit currents for up to severalseconds with the existing grid protection infrastructure.

B. Protection Requirements for Hybrid Transformers

For a reliable operation in the energy grid, the HT has towithstand the same overvoltage and overcurrent stresses asa LFT. The protection requirements for the different faultsdepicted in Fig. 3 are deduced in the following and summarizedin Tab. II. The four critical fault scenarios requiring protectionmeasures are denoted with F1-F4 throughout this paper. The

External faultOvervoltage Overcurrent

Lightning surge

Temporary(ms...s)

MV overhead line(induced or direct)

Transient(μs...ms)

Overload

Switching surge

Short circuit(LV side)

LV cable(induced)

- earth 3 Earth fault

Fig. 3: Classification of external faults in the grid based on the root cause.Overvoltages can be separated into temporary and transient faults whereasovercurrent faults are mainly temporary due to the relatively long clearingtimes of the fuses and circuit breakers. The identified critical faults arehighlighted.

standard IEC 60076 is applied where possible since it definesrequirements for power transformers [6]. The limits stated inTab. II apply for a HT interfacing the 20 kV MV and the400 V LV grid. It is assumed that the LFT of the HT fulfillsall relevant standards. Depending on the installation location,additional provisions like MV surge arrestors may be necessaryto protect the LFT. This is common practise and is thus notcovered in this paper.

LV short circuit (F1): In the LV grid, phase to phase,phase to ground and three-phase short circuits can occur.A short circuit between one phase and ground close to theterminals of the transformer results in the highest currents.The standard IEC 60076-5 defines the ability to withstandshort circuit currents for power transformers [6]. Accordingto this standard, the same requirements apply to transformersequipped with tap changers so that the limits given by IEC60076-5 are applied for the HT. The maximum peak valueof the asymmetric short circuit current Isc,max =

√2 ·k · Isc,RMS

can be calculated from the RMS value of the symmetric shortcircuit current Isc,RMS =

Inzsc

. The factor k = f (XscRsc

) is a functionof the transformer short circuit reactance and the resistanceand is given in IEC 60076-5. Assuming a relative shortcircuit impedance of zsc,MV−LV = 4% between the MV and LVtransformer terminals and a short circuit impedance fraction ofXscRsc

= 3.3, the HT has to conduct a maximum asymmetric short

circuit current of Isc,max = 28.28kA. According to IEC 60076-5 the transformer has to withstand the symmetric short circuitcurrent of Isc,RMS = 14.5kA for a duration of 2 s, cf. Tab. II.

MV short circuit: For radial LV distribution grids, only theinstalled generation power from distributed sources connectedto this part of the LV grid feeds current into the MV grid shortcircuit. The current stress for the HT is thus lower than for aLV grid short circuit.

Temporarily increased VMV (F2): Although a maximumRMS phase to phase operating voltage of VMV,max = 1.2 ·VMV

is defined as normal operation and not as a fault according toIEC 60038, this deviation from the ideal grid voltage has tobe considered in the converter design [7], cf. Tab. II.

MV earth fault: Single-phase line to earth faults are commonin the MV grid and cause a temporary rise of the line to groundvoltages by a factor of up to

√3. Due to the galvanic isolation

of the LFT, this overvoltage is not transferred to the converterso that no additional protection requirements have to be takeninto account.

TABLE II: Protection requirements for a 400kVA, 20kV-400V HT.

Disturbance Protection Requirement

F1 - LV short circuit (1-Φ) Isc,max = 28.3kA, Isc,RMS = 14.5kA (2s)F2 - Increased VMV VMV,max = 24kVF3 - MV lightning surge 1.2/50 μs, 125kV, CMF4 - MV switching surge 250/2500 μs, 70.71kV, DM

MV lightning surge (F3): The standard IEC 60076-3 defines a1.2/50 μs voltage surge with a peak value of 125 kV for testingthe insulation of LFTs [6]. This fast voltage transient representsa lightning surge. The testing procedure described in IEC60076-3 requires the voltage pulse to be applied separately toeach winding terminal under test, whereas the other terminalsare connected to ground. Since the propagation of the voltagesurge to the converter is of decisive importance, the standardcannot be applied directly. As discussed in [8], lightning strikespredominantly induce common mode (CM) voltage surges indistribution lines. As a consequence, the 1.2/50 μs, 125 kVvoltage surge defined in IEC 60076-3 is applied to the shortcircuited MV transformer terminals with respect to ground tostudy the effect of lightning strikes on the HT, cf. Tab. II.

MV switching surge (F4): For grid voltages Vm < 72.5kV, thestandard IEC 60076-3 does not define swichting surge test volt-ages since lightning surges are assumed to be more cirtical withrespect to the transformer insulation. However, the long fronttime and differential mode (DM) voltage component of switch-ing surges impose particular stress on the converter as will bediscussed in section IV-D. A 250/2500 μs switching surge asdefined in [9] with a peak value of 2.5 ·√2 ·Vn = 70.71kVis applied between two terminals of the MV winding in thisinvestigation, cf. Tab. II. The study performed in [10] presentsrecords of even higher switching surge phase to phase voltagesfor certain grid configurations. Even for the protection ofconventional grid assets, these scenarios require modificationsof the grid setup or additional protection devices in the MVgrid, which is not within the scope of this paper.

LV side voltage surges: In contrast to voltage surges on theMV side, voltage surges on the LV side are less frequent andof lower amplitude. For this aspect, the protection of the HT issimilar to the protection required for standard grid connectedconverters and can be realized for example with a spark gapbased surge arrester. Thus, the effects of LV side voltage surgesare not investigated in this paper.

Furthermore, IEC 60076-3 specifies line frequency test volt-ages of 50 kV and 3 kV for the MV and LV winding, re-spectively, to be applied successively between all windingterminals and ground for 60 s. Such high overvoltages are notexpected to occur in the distribution grid but focus on theinsulation design. Thus, these test voltages are not consideredas protection requirements for the HT.

III. DEVELOPMENT OF SIMULATION MODELS

To study the effects of the described fault scenarios on theconverter and to verify the effectiveness of the protectionconcepts presented in Section IV, simulation models have beendeveloped, which are described in the following.

A. LV Short Circuit (F1)

η For determining the implications of grid short circuits, theequivalent circuit of Fig. 4 is applied. Besides the converter A©and its filter elements, the short circuit impedance ZSC,MV−LV

of the transformer as given in Tab. III has to be taken intoaccount. The inductance of the wiring between converter andbypass as well as between bypass and transformer are eachconsidered by LWA

2 . Due to the high apparent short circuitpower in the MV grid, its grid impedance does not influencethe short circuit current significantly [6]. As a worst casescenario, the short circuit is considered to occur on the LVside close to the transformer terminals. The effects of grid shortcircuits are investigated at full load of the HT. In the back toback system, converter B© regulates the DC-link voltage VDC toits nominal value by controlling the current. Hence, converterB© is modeled as a controlled current source as shown in Fig. 4.If a fault is detected and all semiconductor switches are turnedoff, the filter inductors of both converter sides discharge intothe DC-link. To take the DC-link voltage rise due to the energystored in the filter inductances of converter B© into account,an energy equivalent inductance is placed in the DC-link. Ina three-phase system, the total energy stored in the DM filterinductances LFB,DM and the connection wires LWB is given by(1) if the ripple of the current is neglected.

WL,B =3

4· (LF,B +LWB) · I2

conv,B

=1

2· (LF,B +LWB) ·

(Pout

η ·VMV· NMV

NAux

)2

(1)

The peak line current of converter B© Iconv,B can be calculatedfrom the converter output power Pout, the back to back con-verter efficiency η, the line to line voltage of the MV grid VMV

and the transformer turns ratio NMVNAux

. Similarly, the energy inthe equivalent inductance WL,DC and the inductance value LDC

can be calculated with (2) and (3), respectively, if the sameefficiency for converter A© and B© is assumed.

WL,DC =1

2 ·η ·LDC ·(

Pout

VDC

)2

(2)

LDC =(LF,B +LWB)

η·(

VDC

VMV· NMV

NAux

)2

(3)

Except for symmetrical three-phase short circuits, a neutralcurrent is excited during the fault. The balancing circuit of thesplit DC-link has to be included into the model to study theimbalance of the DC-link capacitor voltages.

B. MV Surges (F3 & F4)

Especially in case of overvoltage transients, the parasiticelements of the transformer have to be taken into accountsince they significantly influence the overvoltage stress of theback to back converter. Therefore, a high frequency model ofthe LFT is included in the simulation model to determine theconverter voltages for voltage surges transferred from the MVgrid. Although some publications focus on the propagation ofvoltage surges from the MV to the LV grid, the applied modelsare mainly based on measured frequency responses [11]. Byconsidering the capacitive and inductive couplings of each turn,

Zsc,MV-LV

Converter A Bypass

MV grid

LFA,CM

CFA,DM

CFA,CM

LFA,DM

CDC

LWA

LN

VDC control

VDC

LDC 2LWA2

Converter B

LFT

Fig. 4: Simulation model used to determine the effects of LV side short circuits. Besides the LFT and converter A© including its filter elements, the actively splitDC-link is included in the model. A simplified representation of converter B© consists of a controlled current source and an equivalent inductance LDC. For theconverter protection, a bypass switch has to be connected in parallel to converter A©.

MV

LV

Aux

LV1

LV2

MV2

MV1

Aux1

Aux2

Fig. 5: Single-phase high frequency transformer equivalent circuit with lowfrequency elements, coupling capacitances and the definition of the terminaldesignations.

the exact voltage distribution across the winding can be deter-mined which is especially useful for the design of transformers[12]. For the investigations regarding the converter protection,only the voltage between the transformer terminals and groundare of interest since the LFT is assumed to be designedproperly. As a consequence, only the couplings between theseterminals are considered. In [13] the capacitive high frequencycouplings of a two winding transformer are represented by sixindependent capacitances between each winding terminal (6-Cmodel) which can be determined by measurements or FEMsimulations. In the following investigation, this approach isextended to a three-winding single-phase representation of theLFT, cf. Fig. 5. Although this approach does not reproduceall resonance frequencies of the transformer, it is sufficientlyaccurate to determine the worst case voltage surge transferredthrough the high frequency coupling. A similar approach isapplied in [14] where the low frequency equivalent circuit isextended with four parasitic capacitances, which are calculatedform the winding geometry.

If n is the number of winding terminals, there are n2+n2 inde-

pendent coupling capacitances between the winding terminalsand ground. As can be seen in Fig. 5, for the single-phaserepresentation of a three winding transformer n= 6 applies and21 capacitances can be identified. As depicted in Fig. 7, a 2Drepresentation of the winding geometry is used to determinethe coupling capacitances in COMSOL. Due to the smallthickness of the concentric LV and auxiliary foil windings,they are each modeled by two cylinders at the inner andouter diameter of the respective winding where the terminalsLV1/2 and Aux1/2 are connected to. The terminals of the disc-type MV winding MV1/2 are connected on the top and thebottom of the winding. As depicted in Fig. 7, a linear voltagedistribution across the MV winding is assumed. This results in

a)

b)

Core

MV LV Aux

Core

AuxLVMV

Fig. 6: a) Winding arrangement of the con-sidered LFT. b) Due to the shielding effectof the LV winding, there is only a negligibledirect coupling between the MV and auxiliarywinding.

z

r

MV1

MV2

Core

TankLV1

LV2

Aux2Aux1

Fig. 7: 2D FEM model of atransformer phase. A linearpotential distribution acrossthe MV winding is assumed.

an overestimation of the parasitic capacitances and thus of thevoltage transferred to the converter compared to a non-linear(e.g. exponential) voltage distribution.

Both the transformer tank and the core are on ground potential.For determining the capacitances, 21 independent simulationshave to be performed whereby always different combinationsof terminals are excited by a test voltage. By integratingthe simulated energy density and identifying the relevantcapacitances for the considered case, all capacitances can becalculated. Due to the shielding effect of the windings, mostof the capacitances can be neglected, cf. Fig. 6 b). As aresult, there is no direct coupling between the MV and theauxiliary winding. The dominant parasitic capacitors are givenin Tab. III.

To study the effect of CM and DM voltage surges, thepresented single-phase transformer model is extended to athree-phase model. Therefore, identical parasitic coupling ca-pacitances for all phases and negligible couplings betweendifferent phases are assumed. Besides the transformer, theconverter B© including its CM and DM filter elements andthe split DC-link capacitors is included in the model as shownin Fig. 8. Due to the short duration of the voltage surges,converter A© does not have a significant influence on the riseof the DC-link voltage during a voltage surge. Similar to the

TABLE III: Parameters for the model of the 400kVA, 20kV-400V LFT. Inthe lower part, the dominant capacitances are given. Their indices denote theterminals the capacitors are connected to.

Parameter Value

Winding losses (MV, LV, Aux) 2800 W, 1500 W, 500 W (full load)Core losses 600 WNumber of turns cf. Tab. VShort circuit imp. MV-LV zSC,MV−LV = 4%Short circuit imp. MV-Aux zSC,MV−Aux = 6.5%

Short circuit imp. ratio XscRsc

|MV−LV = 3.3, XscRsc

|MV−Aux = 1.2

CMV1−LV1, CMV1−GND 330 pF, 200 pFCMV2−LV1, CMV2−GND, 330 pF, 200 pFCLV1−LV2 200 pFCLV2−Aux1 3570 pFCAux1−Aux2, CAux2−GND 430 pF, 850 pF

HF transformer model

Voltage surge

Converter B

LFB,DM

CFB,DM

CDCLWB

Fig. 8: Model used to determine the propagation of CM and DM voltagesurges from the MV side to the back to back converter.

insulation tests of the LFT, the HT is at no load when the CMand DM voltage surges are applied and only the body diodesof the MOSFETs conduct current.

IV. PROTECTION CONCEPT FOR HYBRID TRANSFORMERS

With the models presented in the previous section, the effectsof the critical scenarios F1 - F4 as summarized in Tab. II areevaluated and adequate protection concepts are developed.

A. LV short circuit (F1)

A single-phase to ground short circuit close to the transformerterminals excites the highest currents. With a power factor ofthe LV load of cosφ ≈ 1, the maximum peak short circuitcurrent occurs for a fault at the zero crossing of the phaseto ground voltage. Due to the high current amplitude and thedefined fault duration of 2s, a significant overrating of theconverter would be required if no protection concept is applied.To prevent excessive inductor and semiconductor currents, theMOSFETs have to be turned off. A fault situation is detected ifan overcurrent of 120% of the maximum inductor current or asignificant CM component in the output voltage is detected. Inaddition to the time between the occurrence and the detectionof the fault, a measurement delay td,meas = 20μs, and a timedelay required for processing the fault in the control systemtd,proc = 20μs are considered. In Fig. 9, the simulated phasecurrent and the DC-link voltage of the converter are depictedfor the worst case short circuit current for different protectionconcepts. Without further protection devices, the DC-linkvoltage rises considerably. The application of DC-link varistorswith high energy absorption capabilities limits the voltage rise,

-20

0

20

0 10 20 30 40 50 600

400

800

DC-link varistors

LV short circuit (F1)

Without protection

Bypass switch

DC-linkvaristors

Without protection

Bypass switch

I phas

e in

kA

t in ms

V DC

in V

Fig. 9: Simulated phase current and DC-link voltage for a single-phase toground short circuit for different protection concepts.

however, the fault current is reduced significantly. With theprotection infrastructure present in today’s grid, this cannot betolerated since the reliable fault detection and disconnectionby fuses or circuit breakers is impaired. For the investigatedHT, a bypass switch with a closing time of tbypass ≤ 200μsis required to provide an alternative path for the short circuitcurrent and to limit the voltages of the split DC-link capacitorsto acceptable values.

Conventional mechanical circuit breakers have closing timesof more than 10 ms to establish a reliable current path, whichis longer than the rise time to the first peak of the short circuitcurrent [15]. Readily available mechanical switches used forultra-fast earthing achieve closing times of less than 4ms butcan only be actuated once [16]. Ultra fast mechanical switchesbased on Thomson coil actuators (TCAs) have recently gainedattention for applications in HVDC breakers. Although TCAsfor low voltages have not been investigated in literature yet,published designs for MV switches suggest that closing timesbelow 2ms are achievable [17], [18]. To comply with therequired closing time of tbypass ≤ 200μs, thyristors have to beapplied. In the following, a bypass switch with thyristors ratedfor the full fault current and a hybrid solution with thyristors oflower current rating in combination with a TCA are designedand compared.

1) Design of a Thyristor Bypass Switch: The thyristor bypassconsists of two antiparallel devices per phase, where eachthyristor has to conduct an average current of

Isc =

√2 Isc,RMS

π= 6.53kA.

For this current rating, press pack thyristors with double sidedcooling have to be applied. As can be seen in Fig. 10, theplates required to clamp the devices with the defined mountingforce and for the electrical connection are used as thermalcapacitances Cth,h. By taking the transient thermal impedanceof the thyristor Zth,thy into account, the thermal equivalentcircuit of Fig. 11 is obtained for one thyristor according tothe procedure presented in [19]. Besides the conduction lossesof the thyristors Pthy transferred from the thyristors to thealuminum plates, also the self heating of the plates due to thecurrent flow is considered by Pplate. The internal thermal ca-pacitances of the semiconductor device cause a delay betweenPthy and the heat flowing from the thyristor case to the heatsink, which is taken into account by a low pass filter (LPF).

2·Cth,h

NPthy

Pthy

Cth,h

Cth,h

Fig. 10: Thyristors and clamp-ing plates for one phase of thebypass switch. An equal heatflow through the anode andcathode contacts is assumed.

Fig. 11: Transient thermal equivalent circuitfor one thyristor of the bypass switch. Thecoupled approach presented in [19] allows tocombine the data sheet Zth parameters of thethyristor with an external thermal interfacematerial and heat sink.

For this bypass switch, 800 V thyristors with an average on-state current of IT(AV) = 6.82kA are chosen (Poseico AT908).The designed bypass switch without gate drivers is shown inFig. 12 (a) and has a volume of 10 l. Maximum junction andplate temperature rises of ΔTj,max = 50K and ΔTc,max = 10K,respectively, were verified for this design by a transient thermalsimulation of the LV short circuit. The characteristics of thissolution are listed in Tab. IV.

2) Design of a Hybrid Bypass Switch: In contrast to thepreviously discussed solution, the hybrid bypass utilizes thehigh pulse current capabilities of the thyristor in combinationwith an ultra-fast mechanical switch based on a TCA. Untilthe mechanical switch establishes a current path, the thyristorsconduct the fault current, cf. Fig. 13. To drive the TCA,an energized capacitor bank is discharged into a concentriccoil by triggering a thyristor. The resulting current pulseinduces eddy currents and thus repulsive forces in a metal disk,which is arranged in close proximity to the coil. To preventthe electrolytic capacitors from negative voltages, a diode isemployed. A detailed description of the working principle andthe modeling of TCAs can be found in [17], [18] and is thusomitted here. For the TCA and the required capacitor bank, adesign similar to the one presented in [20] and a worst caseclosing time of tclose = 2ms are considered as listed in Tab. IV.

The maximum integral of the squared surge current∫i2dt

∣∣thy,max of the thyristor is defined for a sinusoidal grid

frequency half-wave. Before this limit is exceeded, the currenthas to commutate to the mechanical switch to avoid thedestruction of the thyristor. For sinusoidal half-wave currentpulses shorter than 10ms, the allowable

∫i2dt decreases.

Considering a pulse duration of 2 ms, the allowable integralof the squared current reduces to kpulse = 45% of the datasheet value for typical power thyristors [21]. A short circuitoccurring at the peak of the phase to ground grid voltageleads to the largest rate of current rise if the load powerfactor cosφ ≈ 1. Representing the highest current stress for thethyristors of the hybrid switch, this condition is considered forthe design. By assuming that current pulses of non-sinusoidalshape but with equal

∫i2dt cause a similar heating of the device

and taking a margin m = 0.8 into account, (4) is deduced forthe selection of the thyristors. The applied inequality for theshort circuit current is a worst case approximation for a short

TABLE IV: Parameters of the thyristor and hybrid bypass switch.

Thyristor Bypass Hybrid Bypass

Thyristors 6×800V,6.82kA 3×400V,250A, 2 per module(Poseico AT908) (Vishay VSKT250)

Package Press packs, clamped Modules, screwedMech. switch - • TCA similar to [20], tclose = 2ms

• Cap. bank: 400V,8×3.8mF(TDK B43415)

• Thyr. & diode: 400 V, 250 A(Vishay VSKH250)

Boxed volume 10 l 6.4 l

circuit occuring at the grid current maximum I = zsc · Isc.

∫i2dt

∣∣thy,max >

2I2sc,RMS

m · kpulse·∫ tclose

0(sin(ωt)+ zsc)

2 dt = 344kA2s

(4)

For the thyristors of the hybrid bypass switch, 400 V deviceswith a rated mean on-state current of IT(AV) = 250A and∫

i2dt∣∣thy,max = 361kA2s (Vishay VSKT250) are chosen. A

similar device is also chosen for the thyristor and the dioderequired for the TCA drive (Vishay VSKH250). A 3D render-ing of the hybrid solution with the parameters given in Tab. IVis shown in Fig. 12 (b) and features a volume of 6.4 l.

3) Comparison of Bypass Switches: To provide an alternativecurrent path within tbypass ≤ 200μs, thyristors have to beapplied for both solutions. In contrast to semiconductors, theoperating temperature of the mechanical switch is less criticalso that very high current densities and a compact design arepossible. As can be seen from Tab. IV, the application of ahybrid bypass switch entails the potential to reduce the volumeof the switch by almost 4 l. However, some practical aspectsof TCAs still need further investigation. This includes thedeceleration of the actuator and the development of a bistablelatching mechanism ensuring that the switch remains in its onor off position.

4) Short Circuit Fault Sequence: The voltage and currentwaveforms presented in Fig. 13 are used to demonstrate howthe HT detects a phase to ground short circuit and returns tonormal operation after the fault has been cleared externally.In stage 1©, the converter operates at full load and injects aseries voltage of Vser = 23V. At the zero crossing of the phaseto ground voltage, a short circuit occurs which is detected0.65 ms later due to a significant common mode componentin the output voltage Vser. After the converter is turned offwith a time delay of td,meas + td,proc = 40μs, the thyristors ofthe hybrid bypass switch turn on and the converter currentsIL,FA decay to zero. Closing the bypass switch excites anoscillation between the CM filter capacitor CFA,CM and the

wire inductance LWA2 , cf. Fig. 4. This inductance reduces the

occuring capacitor currents. The CM capacitor has to withstanda voltage of 250 V and a rate of voltage change of dv

dt ≥ 25 Vμs

in this design. The phase current Iph rises significantly in stage2© and the current in the bypass switch Ibyp commutates to theultra-fast mechanical switch after it has established a currentpath within 2 ms. Converter B© controls the DC-link voltageto the nominal value. At the end of this stage, the short circuit

(b)320 mm

190 mm

105 mm

TCA Capacitor bank

Bypass thyristors

TC thyristor + diode

L1N N

N

L2 L3

(a)

490 mm

113 mm

Bypass thyristors

N-connection

N

N

L1

180 mmPhase connection

N

N

L2 N

N

L3

Fig. 12: CAD rendering and dimensions of the developed bypass switches. (a): Thyristor bypass employing 800 V, 6.82 kA devices, (b) hybrid bypass switchemploying 400 V, 250 A devices and a TCA.

I ph [k

A]

-200

20

I L,FA

[kA

]

-101

I byp [

kA]

-200

20

V ser [

V]

-500

50

t in ms0 40 80 100

V dc [V

]

050

100

4321 1

Thyristor

20

Mech. switch

Detection

Fig. 13: Procedure for detecting a short circuit, closing of the hybrid bypassswitch and returning to the normal operation of the converter. A single-phaseshort circuit at the transformer terminals is considered as a worst case scenario.

is cleared by external grid protection devices like fuses orcircuit breakers and the phase current decreases to its nominalvalues in stage 3©. If the sum of the phase currents flowingthrough the bypass does not exceed the overcurrent limit forone grid frequency period, the bypass switch is opened and theconverter returns to normal operation in stage 4© by rampingup the output voltage Vser. In addition to the boost inductorcurrent IL,FA measurement, which is anyway required for thecontrol, a measurement of Ibypass is needed, for which a shuntresistor or a hall effect sensor could be applied.

B. Temporarily increased VMV (F2)

Since a temporary voltage increase in the MV grid of 20%is defined as normal operation, the converter has to continueits operation under such a condition. In order not to impairthe semiconductor reliability, the DC-link voltage must notbe increased above its normal value temporarily during suchvoltage fluctations. If the DC-link voltage is designed tooptimally suit the output voltage of converter A©, the requiredsemiconductor breakdown voltage Vbr can be calculated. Foran actively balanced split DC-link and a series voltage of upto 10% of the LV grid line to neutral voltage VLV√

3= 230VRMS

(cf. Tab. I), the semiconductor breakdown voltage has to fulfill(5).

Vbr ≥ 2√

2√3

· 10%VLV

k= 108.87V. (5)

The factor k = VDCVbr

≈ 0.6 takes the margin between the DC-

link voltage and the semiconductor breakdown voltage intoaccount. The maximum allowable turns ratio NMV

NAuxcan now be

calculated for a given DC-link voltage to ensure the operationif the MV grid voltage is increased to VMV,max.

NAux

NMV≤ kVbr√

2VMV,max

. (6)

As will be discussed in section IV-D, both the turns ratio NMVNAux

and the semiconductor breakdown voltage have an impact onthe required protection measures against slow transient voltagesurges as caused by switching actions in the MV grid. Based on(6), different design alternatives are investigated and comparedin section IV-D.

C. MV Lightning Surges (F3)

Due to the delta connected MV windings, the magneticcoupling of CM pulses to the auxiliary and LV side isnegligible. The parasitic transformer capacitances provide acoupling between the MV, LV and auxiliary windings andground for the high frequency components of the considered1.2/50 μs lightning surge. Based on the general model for thepropagation of voltage pulses shown in Fig. 8, the CM modelof Fig. 14 is derived by only taking the dominant capacitancesinto account, cf. Tab. III. For a CM pulse, the terminals MV1/2and Aux1/2 are effectively short circuited and the couplingcapacitances of the three transformer phases are connectedin parallel. Without protection measures, an oscillating CMvoltage VFB,CM of several tens of kV is excited between theauxiliary winding terminals Aux1/2 and ground.

Due to the short pulse duration and the filter inductor LFB,DM,the resulting DC-link voltage rise is not critical. A reductionof the voltage stress is possible by applying varistors betweenthe auxiliary winding terminals and ground. Varistors rated for50 VRMS (TDK S20K50) limit the CM voltage VFB,CM to 120 Vwhereas the rise of the DC-link voltage is negligible.

D. MV Switching Surges (F4)

In comparison to the fast transient lightning surge, voltagesurges caused by switching actions in the MV grid typically

VDC

CDC

VFB,CM CDC

Vsurge

3LWB

3LFB,DM

3 (CMV1-LV1+CMV2-LV1)

LV1LV2

Aux1/2

MV1/23 CLV1-LV2

3 CLV2-Aux1

3 CAux2-GND

HF transformer model (CM)

Fig. 14: CM equivalent circuit to evaluate the voltage stress of a CM voltagesurge. Input varistors are applied to protect converter B©. The transformerterminals are denoted according to Fig. 5.

2·LFB,DM

CFB,DM

2·LWB

CDC2

2VDC

IL,FB

Vsurge

Aux1

Aux2

LF transformer model (DM)NMV:NAux

Zsc,MV-AuxMV1

MV2

Fig. 15: Equivalent circuit for the propagation of slow DM voltage transientsto converter B© through magnetic coupling. DC-link varistors are applied tolimit the rise of the DC-link voltage and DM filter inductances LFB,DM limitthe inrush current.

exhibit longer time constants. The considered 250/2500 μs,70.71kV switching pulse is mainly transferred to the auxiliaryside via the magnetic coupling whereas the influence of theparasitic capacitances is negligible. Also DM voltage pulseswith shorter rise and fall times will be excited in the grid.However, long DM pulses as the considered 250/2500 μspulse represent the worst case since the energy transferredto converter B© is higher for longer pulses. As for the CMvoltage surge, the equivalent circuit shown in Fig. 15 can bederived for long DM pulses based on the general model (cf.Fig. 8). Only the low frequency elements of the transformermodel (cf. Tab. III), the wiring inductance LWB and the DMfilter elements LFB,DM and CFB,DM are considered. With thefilter structure shown in Fig. 8, the DM element are connectedin series for a DM pulse. As mentioned in section III-B, onlythe body diodes of converter B© conduct current in this case.To limit the rise of the DC-link voltage, varistors are placed inparallel to the DC-link capacitor. In contrast to the lightningsurge, the ratio between the nominal line to line voltage andthe amplitude of the switching surge is low. As a consequence,varistors applied across the MV or auxiliary winding terminalsin a delta connection do not significantly clamp the transferredvoltage pulse and are thus not sufficiently effective to reducethe DC-link voltage rise.

The voltage and current stress from a switching surge aremainly influenced by the four parameters described in thefollowing.

Turns ratio NMVNAux

: With an increasing turns ratio NMVNAux

, thevoltage pulse transferred to the auxiliary winding terminalsdecreases. On the one hand, an increase of the turns ratioreduces the resulting DC-link voltage rise and the inrushcurrent through the filter inductances. On the other hand, therated current and thus the conduction losses of the converterB© and its filter inductances increase in normal operation.

DM filter inductance LFB,DM: Besides the transformer shortcircuit impedance Zsc,MV−Aux and the inductance of the con-necting cables LWB, the DM filter inductance LFB,DM limitsthe maximum occurring inrush current. Saturation of the filterinductances has to be avoided by applying larger inductancevalues or air core inductors. The DM filter capacitor CFB,DM

has only a minor influence on the maximum DC-link voltagerise and inrush currents.

Maximum allowable DC-link voltage VDC,max: To increasethe maximum allowable DC-link voltage, semiconductors withan increased breakdown voltage are required. A lower turnsratio NMV

NAuxand thus a lower rated current of converter B© are

possible if the nominal DC-link voltage is increased. How-ever, the on-state resistance Rds,on of the MOSFETs increasessignificantly.

DC-link capacitance CDC: A reduction of the DC-link capac-itance CDC decreases the inrush current the filter inductanceshave to withstand. However, a minimum capacitance is re-quired for a stable operation of the back to back system. Thislower limit is defined by the control dynamics and is chosen inthis design. For higher DC-link voltages, a lower capacitanceis possible if an equal stored energy is regarded.

For the design of the protection concept, the best compromisebetween increased losses and system volume has to be found.Therefore, the three possible designs given in Tab. V arediscussed and compared based on a pareto optimization. Fromdesign I to III, the turns ratio NMV

NAuxdecreases resulting in

lower currents and thus lower conduction losses of converter B©Iconv,B. However, with decreasing turns ratio, the inrush currentincreases which necessitates larger inductances to preventsaturation of the inductor core. Except for design variantIII, 120 V MOSFETs (Inf. IPP041N12N3) can be applied.According to (6), the low turns ratio of design III requiresan increased DC-link voltage VDC = 90V and hence 150 VMOSFETs (Inf. IPP075N15N3). These system designs take ahybrid bypass switch (cf. section IV-A2) as well as DC-linkand lightning surge protection varistors into account. To showthe influence of the protection concept on the system powerdensity and efficiency, the optimal design of an unprotectedsystem is also given. For each design, the number of parallelMOSFETs for both converters A© and B© is determined asa compromise between an increased component count anddecreased semiconductor losses.

Since dedicated high energy varistors are not available for therequired low clamping voltages, a parallel connection of pre-selected standard varistors with a maximum clamping voltagederivation of ±5% is considered. The selected varistors TDKS20K50 and TDK S20K60 feature a DC operation voltage of65 V and 85 V, respectively. Due to the soft transition of thevaristor form the high to the low impedance state, it is ensuredthat even a varistor with 95% of the rated clamping voltageis not thermally destroyed in normal operation. In order notto exceed the maximum energy dissipation and current duringthe clamping, 20 varistors are connected in parallel.

The DM filter inductors of converter B© LFB,DM have tobe sufficiently large to limit the inrush current. If the filter

TABLE V: Parameters of possible system designs to comply with the protection requirements of faults F1-F4. The turns ratioNMVNAux

decreases from design I to

III resulting in lower nominal currents of converter B© Iconv,B. At the same time, larger inductances have to be applied to prevent inductor saturation caused byexcessive inrush currents. The converter power density and efficiency are determined by pareto optimizations.

Design without protection Design I Design II Design III

NMV, NLV, NAux 2510, 29, 6 2300, 27, 4 2050, 24, 4 2385, 28, 6# par. MOSFETs A©, B© 12, 12 (120 V Inf.) 12, 16 (120 V Inf.) 12, 14 (120 V Inf.) 16, 14 (150 V Inf.)VDC, CDC 70 V, 5 mF 70 V, 5 mF 70 V, 5 mF 90 V, 3 mFVaristors - 20×65VDC ±5% 20×65VDC ±5% 20×85VDC ±5%CFBDM type 63 VDC, MKT (TDK B32526) 63 VDC, MKT (TDK B32526) 63 VDC, MKT (TDK B32526) 100 VDC, MKT (TDK B32526)min. LFBDM, type 0 μH, METGLAS core 3 μH, METGLAS core 8 μH, METGLAS core 0 μH, air core

Iconv,B 719 A 988 A 881 A 683 A

Power density 2.8 kWl 1.85 kW

l 1.7 kWl 1.62 kW

lEfficiency 95.5% 95% 95.5% 94.2%

0 1 2 3 42

6

10

14

0 5 10 15 20Îinrush / Îconv,B fsw in kHz

(a) (b)

Saturation limit

Design IIDesign I

Design IIIDesign IIDesign I

Design III

Inrush limited

Ripple limited

L FB,D

M in

μH

min LFB,DM

Fig. 16: (a) Required filter inductance LFB,DM to limit the inrush current for thedesigns I to III. (b) LFB,DM is determined by the maximum of the inductancevalues to limit the current ripple (here 8%) and the inrush currents. For higherfsw, the inductance is defined by the allowable inrush current and thus remainsconstant over fsw.

inductor is designed to operate at a maximum core excita-tion of 80% of the saturation flux density Bsat = 1.4T witha current ripple of 8%, the core saturates at a current ofIsat = 1.35 · Iconv,B. From the simulated peak inrush currentsIinrush, the minimum filter inductance to prevent core saturationcan be determined as shown in Fig. 16 (a). A further constraintfor the minimum inductance is the limitation of the switchingfrequency current ripple. Consequently, the maximum of theinductance values to limit both the current ripple and the inrushcurrent has to be applied for the filter design in the paretooptimization. As shown in Fig. 16 (b) the required inductanceis inversely proportional to the switching frequency fsw up toa frequency where the limitation of the inrush current definesthe inductance. In design III, air core inductors are chosen dueto the high inrush current. The semiconductors, however, haveto withstand overcurrents of up to 5 · Iconv,B for a few ms inthis design.

For the optimization, the procedure presented in [1] is ex-tended by also taking volume and losses of the CM filter ofconverter A© as well as the inductances of the connecting wiresLWA = LWB = 1μH into account. The resulting pareto curvesfor the case without a protection concept and the three designvariants are shown in Fig. 17, while the full load efficiencyand the converter power density including protection devicesare given in Tab. V. The power densities are calculated fromthe sum of the component volumes. Based on experience, theboxed volume of the converter is assumed to be approximately50% higher than the summed volumes. Despite the higher

1 2 3Power density in kW / l

93

94

95

96

Effic

ienc

y in

%

Without protection

Design I

Design II

Design III

Fig. 17: Pareto fronts with regard to converter full load efficiency and powerdensity of the three alternatives defined in Tab. V. Design I and a switchingfrequency of 16 kHz are chosen as the best compromise between high powerdensity and high efficiency.

nominal currents Iconv,B, design I features the lowest increaseof losses and volume compared to the case without protectionand is thus the preferred alternative for the considered 20 kV-400 V HT. As can be seen in Fig. 17, both the efficiencyand the power density of the converter designed accordingto alternative III are comparatively small mainly due to theapplication of air core inductances. To realize the necessaryfilter inductance value, the component volume and thus themean length of one winding turn entails significant windinglosses.

V. DISCUSSION OF THE PROTECTION CONCEPT

In section IV, measures are investigated which protectthe converter of the HT against the effects of ligthning andswitching surges as well as LV side short circuits. Furthermore,the design implications of a temporarily increased MV gridvoltage are presented. The presence of the LFT in the HTconcept reduces the voltage and current stresses of theconverter. Varistors placed between the auxiliary windingterminals and ground and in the DC-link are required to avoidexcessive overvoltages during MV lightning and switchingsurges. A thyristor or a hybrid bypass switch has to providean alternative current path within tbypass ≤ 200μs after a gridshort circuit occured. In comparison to the design withoutprotection, the converter efficiency is reduced from 95.5% to95% which can be attributed to the reduction of the turns

Transformer

Converter

Losses

Cond.losses A

Switch. losses A

Filter ind. losses

Converter

Hybrid Transformer

Transformer

Converter

Volume

DM filter ind.

DM filter cap.

Cooling system

Semicond.

DC- link

Switch. losses B

Cond.losses B

Protection (Bypass)

CM filter

Fig. 18: Volume (boxed) and loss distribution of the converter and the HTsystem including the protection concept. With respect to HT system includingthe LFT, the additional volume and losses of the converter protection conceptare relatively small.

ratio NMVNAux

. The converter power density reduces from 2.80 kWl

to 1.85 kWl if a hybrid bypass, and to 1.59 kW

l if a thyristorbypass is applied. The pie charts in Fig. 18 present the volumeand loss distribution of the converter and the HT systemincluding the protection concept. The bypass switch and theDM filter inductances account for half the converter volume.Even with the increased number of parallel switches ofconverter B©, its semiconductor losses are considerably higherthan those of converter A© because of the higher rated current.Due to the fractional rating of the power electronics converter,the additional losses and volume of the protection concept areof minor significance for the total HT system performance.Taking into account a LFT with a full load efficiency of98.65%, the HT full load efficiency reduces from 98.23% to98.15% by applying the protection concept. The decrease inpower density of the HT is negligible due to the significantLFT volume of more than 1000 l. However, especially thecost of the bypass switch has to be considered. The CADrendering in Fig. 2 illustrates the volume contributions ofthe LFT and the converter to the HT system including theprotection concept.

VI. CONCLUSION

Since the transformation towards a smarter grid will begradual, the hybrid transformer has to withstand overvolt-age and -current stresses, which are defined by the existinggrid protection infrastructure. The implications of possibleexternal faults in the LV and MV grid on the design andthe performance of the HT are investigated in this paper.Temporary and transient overvoltages on the MV side as wellas LV grid short circuits close to the transformer terminals areidentified to be the most critical fault scenarios. Simulationmodels are presented for these faults and protection conceptsare developed. The application of a protection concept lowersthe converter efficiency from 95.5% to 95% and the powerdensity by 0.95 kW

l for the investigated 40 kVA converter. Theperformance of the HT system is not significantly deteriorateddue to the fractional rating of the converter. Hence, the HT isa promising solution to enhance the grid power quality evenwith conventional grid protection infrastructure.

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