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Pulse Width Modulation

Pulse width modulation (PWM) is a powerful technique for controlling analog circuitswith a microprocessor's digital outputs. PWM is employed in a wide variety of

applications, ranging from measurement and communications to power control and

conversion.

Analogue circuits

An analogue signal has a continuously varying value, with infinite resolution in both timeand magnitude. A nine-volt battery is an example of an analog device, in that its output

voltage is not precisely 9V, changes over time, and can take any real-numbered value.

Analogue signals are distinguishable from digital signals because the latter always take

values only from a finite set of predetermined possibilities, such as the set {0V, 5V}.

Analogue voltages and currents can be used to control things directly, like the volume of

a car radio. In a simple analogue radio, a knob is connected to a variable resistor. As youturn the knob, the resistance goes up or down. As that happens, the current flowingthrough the resistor increases or decreases. This changes the amount of current driving

the speakers, thus increasing or decreasing the volume. An analogue circuit is one, like

the radio, whose output is linearly proportional to its input.

Digital control

By controlling analogue circuits digitally, system costs and power consumption can be

drastically reduced.

In a nutshell, PWM is a way of digitally encoding analogue signal levels. Through theuse of high-resolution counters, the duty cycle of a square wave is modulated to encode aspecific analogue signal level. The PWM signal is still digital because, at any given

instant of time, the full DC supply is either fully on or fully off. The voltage or current

source is supplied to the analog load by means of a repeating series of on and off pulses.

The on-time is the time during which the DC supply is applied to the load, and the off-

time is the period during which that supply is switched off.

Figure 1 shows three different PWM signals. Figure 1a shows a PWM output at a 10%

duty cycle. That is, the signal is on for 10% of the period and off the other 90%. Figures1b and 1c show PWM outputs at 50% and 90% duty cycles, respectively. These three

PWM outputs encode three different analogue signal values, at 10%, 50%, and 90% ofthe full strength. If, for example, the supply is 9V and the duty cycle is 10%, a 0.9V

analogue signal results.

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Figure 1: PWM signals of varying duty cycles

Figure 2 shows a simple circuit that could be driven using PWM. In the figure, a 9Vbattery powers an incandescent lightbulb. If we closed the switch connecting the battery

and lamp for 50ms, the bulb would receive 9V during that interval. If we then opened theswitch for the next 50ms, the bulb would receive 0V. If we repeat this cycle 10 times a

second, the bulb will be lit as though it were connected to a 4.5V battery (50% of 9V).

We say that the duty cycle is 50% and the modulating frequency is 10Hz.

Figure 2: A simple circuit

The AVR atmega16 supports pulse width modulation (PWM) on all three timer counters.

Initially we will use the 8 bit timer 0 to implement this function. The AVR supportsnormal PWM or so called fast PWM. Normal PWM involves starting a counter which

counts up to its maximum value and then reverses, counts back to zero and then repeats.

This can be visualised as a sawtooth waveformas shown in Figure 3. In order to create

output pulses whose mark:space ratio changes the output compare register (Ref) is loadedwith a value so that when the count reaches that value the Output is reversed.

Figure 3

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As the value ofRefreduces so the width of the pulses increase and as Refincrease then

the width of the pulses will decrease. In the atmega16 Ref = OCR0 and the output is

OC0 which is bit 3 on PORTB.

Section from mega16 datasheetThe phase correct PWM mode (WGM01:0 =1) provides a high resolution phase correctPWM waveform generation option. The phase correct PWM mode is based on adualslopeoperation. The counter counts repeatedly from BOTTOM to MAX and then fromMAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0)is cleared on the compare match between TCNT0 and OCR0 while upcounting, and seton the compare match while downcounting. In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation frequencythan single slope operation. However, due to the symmetric feature of the dual-slopePWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phasecorrect PWM mode the counter is incremented until the counter value matches MAX.When the counter reaches MAX, it changes the count direction. The TCNT0 value willbe equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 33. The TCNT0 value is in the timing diagram shown asa histogram for illustrating the dual-slope operation. The diagram includes non-invertedand inverted PWM outputs. The small horizontal line marks on the TCNT0 slopesrepresentcompare matches between OCR0 and TCNT0.

This technique is effectively digital to analogue conversion.

Fast Pulse Width Mode

Figure. 4: Fast Pulse Width Mode

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Section from mega16 datasheetThe fast Pulse Width Modulation or fast PWM mode provides a high frequencyPWM waveform generation option. The fast PWM differs from the other PWMoption by its single-slope operation. The counter counts from BOTTOM to MAX thenrestarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare

(OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOTTOM.In inverting Compare Output mode, the output is set on compare match andcleared at BOTTOM. Due to the single-slope operation, the operating frequency of thefast PWM mode can be twice as high as the phase correct PWM mode that use dualslopeoperation. This high frequency makes the fast PWM mode well suited for powerregulation, rectification, and DAC applications. High frequency allows physically smallsized external components (coils, capacitors), and therefore reduces total system cost.In fast PWM mode, the counter is incremented until the counter value matches the MAXvalue. The counter is then cleared at the following timer clock cycle. The timing diagramfor the fast PWM mode is shown in Figure 32. The TCNT0 value is in the timing diagramshown as a histogram for illustrating the single-slope operation. The diagram includesnon-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0slopes represent compare matches between OCR0 and TCNT0.

#i ncl ude #i ncl ude #i ncl ude

#def i ne PWM_sel ect ( ( ~( i np( PI NA) ) & 3) )

mai n( ){

unsi gned i nt ol dt ogs;

out p(0x??, DDRA) ;out p(0x??, DDRB) ;out p(0x??, PORTA) ;out p( 0x??, TCCR0) ;out p(0x??, OCR0) ;

whi l e ( 1){

i f ( PWM_sel ect ! = ( ol dt ogs) ){

ol dtogs = PWM_sel ect ;ol dt ogs = ol dt ogs;swi t ch ( ol dt ogs)

{case 0:

out p(0x??, OCR0) ;break;

case 1:out p(0x??, OCR0) ;break;

case 2:out p(0x??, OCR0) ;

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break;case 3:

out p( 0x??, OCR0) ; ;

}}

}}

Type in the above program and insert the correct values for the registers. Enter

comments where relevant and save in your area.

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