quad 2-to-1 and quad 4-to-1 multiplexers discussion d2.4 example 7
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Quad 2-to-1 and Quad 4-to-1 Multiplexers
Discussion D2.4
Example 7
Quad 2-to-1 Multiplexer
Quad
2-to-1
MUX
a(3:0)
b(3:0)
y(3:0)
s
s y
0 a
1 b
2 x 1MUX
a(0)
b(0)
y(0)
s
0
1
2 x 1MUX
s
0
1
2 x 1MUX
s
0
1
2 x 1MUX
s
0
1
s
y(1)
y(2)
y(3)
a(1)
a(2)
a(3)
b(2)
b(3)
b(1)
Quad 2-to-1 Multiplexer
y <= ~s*a + s*b;
Quad
2-to-1
MUX
a(3:0)
b(3:0)
y(3:0)
s
s y
0 a
1 b
2 x 1MUX
a(0)
b(0)
y(0)
s
0
1
2 x 1MUX
s
0
1
2 x 1MUX
s
0
1
2 x 1MUX
s
0
1
s
y(1)
y(2)
y(3)
a(1)
a(2)
a(3)
b(2)
b(3)
b(1)
may only AND bits of a STD_LOGIC_VECTOR of equal length.
sel: STD_LOGIC_VECTOR(3 downto 0);
sel <= s & s & s & s;
y <= (not sel and a) or (sel and b);
2 x 1MUX
a(0)
b(0)
y(0)
s
0
1
2 x 1MUX
s
0
1
2 x 1MUX
s
0
1
2 x 1MUX
s
0
1
s
y(1)
y(2)
y(3)
a(1)
a(2)
a(3)
b(2)
b(3)
b(1)
-- Example 7a: Quad 2-to-1 MUX using logic equationslibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux24a is
port( s : in STD_LOGIC; a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0)
);end mux24a;architecture mux24a of mux24a is signal sel: STD_LOGIC_VECTOR(3 downto 0);begin
sel <= s & s & s & s;y <= (not sel and a) or (sel and b);
end mux24a;
-- Example 7b: Quad 2-to-1 MUX using if statementlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux24b is
port( s : in STD_LOGIC; a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0)
);end mux24b;
architecture mux24b of mux24b is begin
process(a, b, s) begin if s = '0' then y <= a; else y <= b; end if; end process;end mux24b;
Aldec Active-HDL Simulation
A Quad 4-to-1 MUX
Quad
4-to-1
MUX
a(3:0)
b(3:0)y(3:0)
s(1:0)
s y
00011011
c(3:0)
d(3:0)
abcd
-- Example 7c: Quad 4-to-1 MUX using with..select..whenlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux44 is
port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); c : in STD_LOGIC_VECTOR(3 downto 0); d : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0)
);end mux44;architecture mux44 of mux44 isbegin
with s select y <= a when "00",
b when "01",c when "10",d when others;
end mux44;
Note selected signal assignment statement
Quad
4-to-1
MUX
a(3:0)
b(3:0)y(3:0)
s(1:0)
s y
00011011
c(3:0)
d(3:0)
abcd
Aldec Active-HDL Simulation