radiation effects in the readout chip for the atlas sct

2888 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 6, DECEMBER 2002

Radiation Effects in the Readout Chip for the ATLASSemiconductor Tracker

Igor Mandic, representing the ATLAS SCT collaboration

Abstract—The ABCD3TA readout chip for silicon strip detec-tors of the ATLAS SemiConductor Tracker (SCT) is described. Itis the final design of the single chip implementation of the binaryreadout architecture. The chip is manufactured in the DMILL ra-diation-hardened BiCMOS process. Summary of results of irradi-ations of ABCD3TA chips with up to 100 kGy and 2 1014 n cm2

(1-MeV neutron NIEL equivalent) done with various sources isgiven in this paper. Measurements of single event effects with high-energy proton and pion beams are also reported. The tests provedthat the chips are sufficiently radiation hard for application in theATLAS SCT.

Index Terms—ABCD3TA readout chip, LHC experiment, siliconstrip detector, radiation effects.

I. INTRODUCTION

T HE ATLAS experiment at the Large Hadron Collider(LHC) at CERN will use silicon strip detectors as a part

of the charged particle tracking system. The SemiConductorTracker (SCT) [1] will consist of 4088 modules with about6 000 000 readout channels. It will comprise a central barrelwith four cylinders and two end-caps with nine disks each.Track point measurement resolution will be 23m per sensingplane. Such a position resolution can be achieved with binaryreadout architecture in which signals from strips are amplifiedand compared to a threshold giving only hit or no hit informa-tion. The main advantage of the binary scheme is a significantreduction of data to be read out, leading to less stringentrequirements for the data transmission system.

ABCD3TA [2], [3] is the final design of the single chipimplementation of the binary readout architecture. It comprisesfront-end circuitry employing a bipolar transistor in the inputstage, discriminators, binary pipeline, derandomizing buffer,data compression logic, and the readout control. There are128 readout channels on a 6.68.4 mm die, which containsabout 30 000 bipolar and 200 000 CMOS devices. The chip ismanufactured in the DMILL [4] radiation-hardened BiCMOSprocess.

The detector together with its readout electronics will belocated close to the interaction point and so exposed to highlevels of radiation. The highest accumulated radiation levelsexpected in the ATLAS SCT after 10 years of operationwill be 100 kGy of total ionizing dose and 210 n cmof 1-MeV neutrons NIEL equivalent (in the rest of the textfluence expressed in ncm will always mean 1-MeV neutrons

Manuscript received; July 16, 2002, revised August 23, 2002.The author is with the Jozef Stefan Institute, Ljubljana, Slovenia (e-mail:

[email protected]).Digital Object Identifier 10.1109/TNS.2002.805412

NIEL equivalent), causing displacement damage. High-energyparticles present in the LHC radiation field will also causesingle event effects (SEE) in the readout chips. These extremeradiation levels exceed the upper limits specified by the DMILLprocess (100 kGy and 110 n cm ). In addition, if one takesinto account very stringent requirements regarding the noise,speed, and power consumption of the chip, it becomes obviousthat radiation effects, although limited, cannot be ignored.

Therefore, to validate the design of the chips with respect toradiation hardness, an extensive irradiation program has beenperformed in which about 300 chips have been irradiated withvarious sources. In this paper, we present a summary of resultsof these irradiations.

II. ABCD3TA DESIGN OVERVIEW

The ABCD3TA is the final version of the SCT readout chip.A minor correction of the ABCD3T design was implementedin the step between ABCD3T and ABCD3TA versions. The de-sign of the ABCD3T chip has been described in greater detail inearlier publications [2], [3]. Here, we give only a brief reminderof ABCD3TA architecture and main specifications of the chip.

The block diagram of the chip is shown in Fig. 1. Signals fromdetector strips are first passed to the bipolar front-end wherethe preamplifier-shaper circuits, optimized for 15–20 pF stripcapacitance and up to 2A strip leakage current, provide sig-nals with peaking time of 25 ns. The output of the preampli-fier-shaper circuit is passed to the discriminator. The discrim-inator threshold is controlled via three digital-to-analog con-verters (DACs). A common threshold for all 128 channels isset by an 8-bit DAC. In addition, an individual threshold cor-rection for each channel using a 4-bit DAC has been imple-mented. The range of the threshold correction is set by a 2-bitDAC, again common for all channels. This control ensures thatchannel-to-channel variation of 1-fC threshold within one chipis below 4%. To meet the timing requirements, time-walk mustbe less than 16 ns for input charges between 1 and 10 fC, anddouble pulse resolution must be better than 50 ns.

The binary data from the discriminator output are latchedinto the input register every 25 ns, synchronized with the bunchcrossing frequency of the LHC, and from there clocked into a132-cell pipeline. In the pipeline, the data are stored for 3.3s,while the decision of the ATLAS trigger system is being made.If the trigger signal is received, the data are transferred from thepipeline into an eight-events deep derandomizing buffer fromwhere they are read out via a token ring, allowing the read outof six chips on one optical fiber. Trigger signals, commands, and40-MHz clock for 12 chips on one module are received via oneoptical link.

0018-9499/02$17.00 © 2002 IEEE

MANDIC : RADIATION EFFECTS IN THE READOUT CHIP FOR THE ATLAS SEMICONDUCTOR TRACKER 2889

Fig. 1. Block diagram of the ABCD3TA chip.

The chip also contains circuitry for internal generation of cal-ibration pulses. The amplitude of the pulse within a 16-fC rangeis set by an 8-bit DAC.

The chip uses two power supply voltages: 3.5 V for the ana-logue part and 4.0 V for the digital part. Total power consump-tion is 3.2 mW/channel for typical operating conditions.

III. I RRADIATION TESTS

The design of the ABCD3TA chip is realized in BiCMOStechnology, and so both displacement damage and ionizationeffects have to be considered. Presence of high-energy particlesin the LHC radiation field also requires measurements of singleevent effects.

In the ABCD3TA design, there are some particularly criticalissues that are influenced by radiation: noise of the front-end,matching in the front end circuit, in particular the offset spreadof the discriminator, and the speed of the digital CMOS part.Given the limitations of the SCT cooling system, imposed by re-strictions on the amount of material introduced into the detector,the increase in power consumption, which is a consequence ofirradiation should also be addressed.

Irradiations were done using different facilities:

• 24-GeV proton beam and X-ray facility at CERN [5];• 200-MeV pion beam at PSI, Villigen, Switzerland [6];• neutrons from TRIGA reactor in Ljubljana, Slovenia [7];• Co source at different sites in California, USA [8].

Chips irradiated with charged particles and neutrons weremounted on hybrids and were biased, configured, and clockedduring irradiation. Analogue parameters were extracted from

threshold scans for given input signals delivered from internalcalibration circuitry. In a threshold scan, channel efficiency ismeasured as a function of threshold setting. An S-curve (i.e.,Gaussian error function) is fitted to measured data. Sigma ofthe Gaussian, which gives the output noise, and 50% efficiencypoint yielding the output amplitude of the analogue stage, areextracted from the fit. The gain of a channel is measured throughrepeated threshold scans at different input charges.

Irradiations with 24-GeV proton beam at CERN PS were per-formed in conditions most similar to those expected in the ex-periment. The radiation environment provided by the PS beamis close to what is expected in the ATLAS experiment, and itallows for testing the components with respect to total ionizingdose, bulk damage, and single event effects. Therefore, PS fa-cility was used as the standard irradiation test bed for SCT elec-tronics. Irradiations at other facilities were done as cross checksof results of PS irradiations.

During proton irradiation hybrids were kept inside a cold boxflushed with nitrogen at a temperature of about 2C, which willalso be the operating temperature of the chips in the ATLASexperiment. The proton beam with a spot of 12 cm wasscanned across the hybrid. Chips received the total fluenceof 3 10 p cm during a period of about 10 days. Thedisplacement damage of this proton fluence is equivalent to1.8 10 n cm [9]. The total ionization dose delivered withthis proton fluence is 100 kGy.

Hybrids were irradiated with neutrons by inserting them intothe reactor core through an irradiation tube. The neutron en-ergy spectrum in the irradiation tube spans from thermal ener-gies to about 10 MeV [7]. From the measured flux, the NIEL


equivalent flux of 1-MeV neutrons was determined using theneutron damage function for silicon from [10]. The fluence of2 10 n cm (in 1-MeV neutrons) was delivered to the chipsin 440 s. During this time, chips received also about the samefluence of thermal neutrons and about 4 kGy of ionization dosefrom gamma background. Temperature of the chips during irra-diation was about 30C.

In the pion beam at PSI, the hybrid was not irradiated uni-formly because of the beam area constraints. The chips receivedfluences between 110 cm and 2 10 cm duringfive days of irradiation. Temperature of the chips during mea-surements was about 40C.

X-ray irradiation was performed for single chips mounted ondedicated test boards. Chips were biased and clocked duringirradiation. The main goal of these irradiations was the studyof the effects of total ionizing dose on the digital part of theABCD3TA design.

With Co sources, the ionizing dose effects at low dose ratesin the DMILL bipolar transistors were studied.

A. Noise

The front-end circuit of the ABCD3TA chip is built as a tran-simpedance amplifier using a bipolar input transistor. One ofthe noise sources is the shot noise of the base current in thistransistor, which is increased by the degradation of the currentgain factor . In bipolar transistors, is degraded by the ion-ization effects as well as by the displacement damage. Duringthe lifetime of the ATLAS experiment, is expected to degradeby a factor of about 4, and so the circuitry design has to be in-sensitive to the variation of . Therefore, there are two 5-bitDACs implemented in the chip by which collector current inthe input transistor and DC bias current of the following stagesof the front-end can be adjusted [11].

The evolution of noise with fluence measured during protonand reactor neutron irradiation is shown in Figs. 2 and 3, re-spectively. The noise is expressed as the number of electronsof equivalent noise charge (ENC). This is the input charge thatwould cause voltage at the amplifier’s output, which is equalto the noise measured from the sigma of the Gaussian obtainedfrom the threshold scan. Noise expressed in electrons can becompared to the charge generated by a minimum ionizing par-ticle crossing the detector. In an SCT detector, a minimum ion-izing particle will generate signal equivalent to about 23 000electrons.

The noise shown in Figs. 2 and 3 was measured with open in-puts so that the capacitance at the preamplifier input can be ne-glected. In an SCT module, i.e., with strips connected to inputs,the total noise will be dominated by the contribution due to thestrip capacitance. The noise of an SCT barrel module is about1400 electrons before irradiation, and it rises to about 2100 elec-trons after 3 10 p cm [12]. This increase is caused by theincrease of noise in readout chips as well as by the increase ofinterstrip capacitance and leakage current in strip detectors. Onecan see a slightly larger noise increase at the same NIEL fluence(note that the proton fluence should be multiplied by 0.6 to getthe fluence in units of 1-MeV neutrons) in chips irradiated withneutrons as compared to protons. This effect was seen also inother irradiation tests of SCT readout chips [2], including the

Fig. 2. Evolution of noise with fluence of 24-GeV protons for six chipsirradiated on a hybrid. Noise is expressed in the number of electrons of ENC.

Fig. 3. Evolution of noise with fluence of reactor neutrons (in 1-MeV neutronsNIEL equivalent) for six chips irradiated on a hybrid. Noise is expressed in thenumber of electrons of ENC.

irradiations of basic DMILL bipolar test structures. The resultsof the pion irradiation, for what concerns noise, were closelysimilar to those obtained with protons.

Assuming that the shaping function of the overall front-endcircuit can be approximated by a - filter with a peakingtime of 25 ns, the measured increase in noise level is compatiblewith degradation by a factor of 4 or more [2].

Comparing the results of irradiations with neutrons andcharged hadrons, it can be concluded that the major contribu-tion to the degradation of comes from displacement damage.However, ionizing dose rates to which SCT electronics will beexposed in the ATLAS experiment will be much lower thanthose experienced in the proton or pion irradiation experiments.Because degradation of could be worse at low dose rateirradiation, a dedicated experiment was performed to study thelow dose rate effects in the DMILL technology. The irradiationof bipolar transistors with different dose rates was performedwith a Co source. The degradation of the current gain factorfor DMILL bipolar transistors irradiated to 10 kGy at differentdose rates is shown in Fig. 4. Fig. 5 shows degradation ofversus total dose measured for irradiations at different doserates and temperatures. The measurements do not indicate any


Fig. 4. Degradation of current gain factor� for DMILL bipolar transistorirradiated to 10 kGy at different dose rates. The vertical line shows the expecteddose rate in the ATLAS experiment (0.05 rad/s).

Fig. 5. Degradation of� vs. total dose for irradiations at different dose ratesand temperatures.

significant low dose rate effect in the degradation of currentgain factor [8].

B. Threshold Spread

In the binary readout scheme, precise control overchannel-to-channel threshold matching is one of the mostcritical issues. The effective threshold of the discriminatoris determined by the offset of the discriminator and by thegain of the amplifying stages preceding the discriminator. Thepreamplifier stage has to be implemented in a single-endedconfiguration, and the gain of the circuit is sensitive tovariation of resistors, which are used in the feedback loops.Channel-to-channel matching of the gain is limited by thematching of resistors across the whole chip. On the other hand,the discriminator circuit is based on a fully differential structureso that the offset of the discriminator is determined by the localmatching of resistors and transistors.

In the earlier phases of ABCD3TA development, a commonthreshold setting for all 128 channels was foreseen. In such a de-sign, matching of parameters of the front-end is crucial. Tests on

Fig. 6. Evolution of threshold spread at 1-fC input charge with fluence ofreactor neutrons for six chips on a hybrid. Thresholds were not trimmed forthis measurement.

Fig. 7. RMS of trimmed thresholds measured at 1-fC input charge for 12 chipson a hybrid before and after irradiation with reactor neutrons to 2�10 n=cm .

the chip prototypes showed that matching of the resistors is thelimiting factor for the offset spread in the discriminator and thatresistor matching degrades significantly after irradiation withneutrons, protons, or pions [11].

In order to guarantee the required threshold spread, individualthreshold correction with 4-bit resolution for each channel wasimplemented in the ABCD3TA design. Four ranges of the cor-rection, common for all channels, can be selected with the max-imum range being 240 mV. This means that after irradiation,the peak-to-peak threshold spread must be less than 240 mV,which translates into an RMS value for the thresholds of lessthan 70 mV, assuming a flat distribution.

Fig. 6 shows the evolution of the untrimmed threshold spreadwith received neutron fluence. Threshold is defined here as the50% efficiency point at 1-fC input charge. In Fig. 7, one cansee the spread of trimmed thresholds before and after irradia-tion for 12 chips on a hybrid. The threshold spread after trim-ming is negligible when compared to the noise of the module,both before and after irradiation. Similar values of spread weremeasured also after proton and pion irradiation, proving the suc-cessful performance of trimming circuitry.


Fig. 8. Evolution of the maximum clock frequency after X-ray irradiation and annealing.

Fig. 9. Excess current immediately after X-ray irradiation to 100 kGy for chips from various production lots.

C. Speed of Digital CMOS Blocks

The ABCD3TA chip is required to work at a clock frequencyof 40 MHz for any set of corner parameters, including thechanges after irradiation to 100 kGy. In addition, the ABCD3TAchip is designed for a digital power supply of 4 V, which isbelow the nominal supply voltage of 5 V specified by theDMILL technology. In order to cover possible variations of theprocess parameters, temperature, supply voltage, and post-ir-radiation changes, the digital part of the chip was designed towork at least at a clock frequency of 80 MHz at 4 V beforeirradiation.

A major total dose effect in the digital part of the ABCD3TAchip is degradation of the maximum speed at the nominal supplyvoltage. Typical degradation of the maximum clock frequencyvs. total ionizing dose after x-ray irradiation is shown in Fig. 8.Because the test was done after a high dose rate irradiation, thestandard high-temperature annealing was performed in order tosimulate irradiation with a low dose rate. After the full dose of100 kGy and high-temperature annealing, the maximum clockfrequency is 52 MHz at nominal supply voltage of 4 V still com-fortably exceeding the required 40 MHz [3].

D. Power Consumption

After delivering ionizing dose to the chips, an increase ofcurrent consumption in the digital part of the chips was ob-served. This current increase was identified as the leakage cur-rent between MOS transistors. The excess current does not in-fluence the digital performance of the chips. However, the powerconsumption must comply with the limitations imposed by thepower distribution and cooling systems of the SCT.

Large lot-to-lot variations of the current increase were ob-served. Fig. 9 shows the excess current, defined as the differencebetween currents after and before irradiation, measured imme-diately after 100-kGy X-ray irradiation for chips from differentlots. Irradiation was done at dose rate of 36.6 krad/min and attemperature of 30-40C. In Fig. 10, the time dependence of theexcess current during and after X-ray irradiation is shown [13].One can see in Fig. 10 that the excess current anneals after irra-diation. But the measurement in Fig. 10 was done at 30-40C,whereas the operating temperature of the chips in ATLAS willbe about 0C, and therefore, annealing will be slower. Mea-surements of current annealing for chips kept at 0C after ir-radiation at PS, measurements of correlation between current


Fig. 10. Time evolution of the excess current during and after X-ray irradiationto 100 kGy at 30 to 40C.

increase after PS, and X-ray irradiations as well as irradiationof chips at lower dose rate allowed to determine an upper limitfor the acceptable current increase measured immediately afterhigh-dose-rate X-ray irradiation to be used for screening pur-pose. It should be noted that all measurements performed onchips produced up to now showed that the current increase willbe manageable in the ATLAS experiment. But given the largelot-to-lot variation of the excess current, a protection againstthe risk of a process change, which might make the current in-crease much worse, is needed. For this purpose, X-ray irradia-tions to 100 kGy at high dose rate will be done for chips sampledfrom each lot to screen for lots with excessive current increase.Based on measurements of chip-to-chip variation of current in-crease within one lot, it was decided that one chip per lot willbe irradiated.

E. Single Event Effects

The SCT readout chips in the experiment will be ex-posed mainly to high-energy particles. A maximum of3 10 hadronscm with energy greater than 20 MeV willcross the ABCD3TA chips during their lifetime. Study of thesensitivity of the chips to SEE is therefore equally importantas the cumulative effects.

There are two major types of digital blocks in the ABCD3TAchip, which may be affected by SEE: the pipeline and the staticregisters, which contain information about chip configurationand settings of operating points. A bit flip in the pipeline causesa single data error and does not require intervention. The rate ofsuch events has to be compared to the noise from the front end.Errors in the static register may lead to changes in operatingmode and will require reloading of the chip configuration.

Sensitivity to the SEE has been tested in the 24-GeV protonbeam at the CERN PS and the 200-MeV pion beam at the PSI.The results of measurements at the PS are consistent with PSImeasurements. This is expected because the cross section forSEE is expected to saturate well below 200 MeV [14].

It was measured that at these beam energies, the cross sectionfor a bit flip in the pipeline is 1 10 cm . Static register cellsare more robust with cross section for a bit flip of 310 cm .

During 10 years of LHC operation, the machine will berunning at high luminosity for about one-third of the time,

Fig. 11. Efficiency as a function of discriminator threshold for nonirradiatedand irradiated modules.

i.e., about 10 s. To estimate the worst-case SEE rate, it canbe taken that maximum of 310 fast particlescm willcross the chips during this time giving the maximum flux of3 10 particles cm s .

With 132 bits per channel in the pipeline, one expects an SEErate of 10-11 per bunch collision (every 25 ns) per channel. Thisnumber is negligible compared to the expected noise occupancyof 1 10 .

Similar consideration for static cells gives the SEE rate of9 10 bit-flips s per cell. With 10 critical bits per chip andsix chips daisy chained for one link and 96 links per off-detectorreadout crate, the expected SEE rate is 510 crate s. Suchan error rate can easily be handled by reloading chip configura-tions in regular intervals from the readout crates.

No destructive single event effects were observed.

F. Irradiation of Complete Modules

Several complete SCT modules, i.e., readout electronics to-gether with detectors have been irradiated with 310 p cmat the PS. Irradiated modules were tested in the beam, wherethey were used for measuring tracks of charged particles, thus,giving the most relevant test of their performance after irradia-tion [8], [15]. The parameters describing module quality, whichare to the largest extent related to radiation effects, are noise oc-cupancy and efficiency. The requirements are noise occupancyless than 5 10 and 98% efficiency at 1-fC threshold. Noiseoccupancy is equal to the probability that hit on a strip is causedby noise. The limit on noise occupancy ensures that the noisehit rate does not affect the data transmission rate or track recon-struction.

In Fig. 11 efficiency and in Fig. 12 noise occupancy measuredin the beam test as a function of threshold can be seen for non-irradiated and irradiated barrel modules. Noise occupancy forirradiated module is on the edge of requirement. But becauseefficiency higher than required is measured at thresholds above1 fC, a margin to the noise occupancy requirement can be madeby running at thresholds slightly above 1 fC.


Fig. 12. Noise occupancy as a function of threshold for nonirradiated (emptymarkers) and irradiated (full markers) barrel modules measured in the test-beam.

IV. SUMMARY

Irradiation tests preformed with ABCD3TA chips showedthat this design, realized in the DMILL technology, meets allthe requirements for the ATLAS-SCT readout electronics.

During irradiation tests, more than 200 chips were irradi-ated to required fluence using various sources of radiation. Sub-stantial degradations of device parameters caused by radiationwere measured. Displacement damage resulted indegrada-tion in the bipolar input transistor and in degradation of resistormatching. Degradation of speed of digital CMOS blocks, in-creased power consumption in the digital part and to some ex-tent degradation in the input transistor were caused by totalionization dose. Bit flips in memory cells were observed whenthe chips were exposed to high-energy hadron beams.

Despite the extreme radiation levels and large shifts of deviceparameters, the chips were fully functional and performed withrequired quality after irradiation. Complete SCT modules, irra-diated to nominal fluence, were successfully tested in the beam.

ABCD3TA was therefore chosen as the final version of thereadout chip for ATLAS SCT. Mass production of chips hasstarted at Atmel. About 60 000 good chips must be produced,of which 50 000 will be assembled into SCT modules.

A wafer screening system has been developed for die qual-ification [16]. After wafer screening, several QA proceduresfor chips will be done at different stages of module building.Quality control will include also irradiation of chips with neu-trons in the reactor in Ljubljana [7] to monitor the extent of dis-placement damage on a lot-by-lot basis. X-ray irradiations ofchips from each lot will be done by the vendor to certify thateach lot meets post-irradiation device parameter specifications

and does not exceed leakage current limits. A sampling of chipswill be irradiated with X-rays at CERN as a cross-check of thetotal dose certification.

ACKNOWLEDGMENT

The author would like to thank W. Dabrowski from FPNT,UMM, Krakow, Poland, and A. Grillo from SCIPP, Universityof California Santa Cruz, for invaluable help during preparationof the paper. Thanks go also to L. Eklund from Uppsala Univer-sity, Sweden, M. Ullan from Instituto de Microelectronica deBarcelona, Spain, and J. Kaplon from CERN, Geneva, Switzer-land, for contributing graphs for the paper.

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radiation effects in the readout chip for the atlas sct

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