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Radiation Tolerant Intelligent Memory Stack RTIMS Flash- Radiation Hardened Design

3DSS24G08VS3626

Doc. N°:3DFP-0626-4 /47 This document is 3D PLUS property, it cannot be used by or communicated to third parties without written authorization

1 FEATURES

• Single 3.3V Power Supply

• Up to 24 Gb of Space qualified NAND

Flash Memory

- 8 Gb with TMR memory protection

- 16 Gb with EDAC memory protection

- 24 Gb with no additional memory

protection

• Memory Organization: 4,096 Blocks of 4,

8 or 12 Mb

• SLC memory technology

• 100 Kcycles Program/Erase endurance

• 10 years data retention

• Standard 8-bit NAND Flash Interface

• Access Time:

- Write mode at 99 Mbits/s

- Read mode at 287 Mbits/s

• Special functionalities:

- Error free guaranteed sector 0 for

Boot data storage

- Continuous logic sectors - Embedded

Bad blocks management

- Embedded dynamic wear leveling

function

- Embedded format, sector logic generation

commands for initialization

• Serial Port Interface for RTIMS flash

configuration, command and telemetry

• Operating Temperature Range:

-40°C/+105°C

• Storage Temperature Range: -55°C/ +150°C

• Radiation Tolerance:

- TID: > 50 krad(Si)

- High Current SEFI Immune by design

- SEU Immune by design

- SEL Immune

• ITAR Free

• Package: SOP 38 package (30 I/OS + Power

lines)

• Dimensions (Lxlxh): 31 x 28 x 11.2 mm

• Mass: 16 gr.

2 GENERAL DESCRIPTION

The NAND Flash Radiation Tolerant and Intelligent Memory Stack (RTIMS FLASH) is a User’s

Friendly, Plug-and-Play and Radiation Protected high density NAND Flash Memory. It provides a very

high density, radiation hardened by design and non-volatile memory module suitable for all space

applications such as commercial or scientific geo-stationary missions, earth observation, navigation,

manned space vehicles and deep space scientific exploration.

The Intelligent Memory Module embeds a very high density of non-volatile NAND Flash memory and

one Intelligent Flash Memory Controller (FMC). The FMC provides the module with a full protection

against the radiation effects such as SEL, SEFI and SEU.

Also, it offers continuous logic sectors (no bad blocks) and high added value functionalities such as

wear leveling, memory self-test, internal registers for telemetry information. The RTIMS FLASH is fully

configurable thanks to H/W configuration pins and a powerful User Interface Port.

Thanks to its standard NAND FLASH interface, the RTIMS FLASH can be easily connected to any

existing µprocessor and FPGA with an embedded NAND Flash interface. Its embedded high level

functions also allow using it as a standalone small local data recorder.

Operational temperature range is -40°C/+105°C.


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TABLE OF CONTENTS

1 Features........................................................................................................................................... 1

2 General description ......................................................................................................................... 1

3 Bloc diagram .................................................................................................................................... 7

4 Absolute maximum ratings .............................................................................................................. 7

5 Recommended operating conditions ............................................................................................... 8

6 Pin definition & assignments ........................................................................................................... 9

7 Application modes ......................................................................................................................... 11

8 SEE protection modes ................................................................................................................... 11

9 FLASH Command definitions ........................................................................................................ 13

9.1 READ Operations .................................................................................................................... 14

9.1.1 PAGE READ 00h-30h ................................................................................................... 14

9.1.2 RANDOM DATA READ 05h-E0h .................................................................................. 15

9.1.3 READ ID 90h ................................................................................................................. 16

9.1.4 READ STATUS 70h ...................................................................................................... 16

9.2 PROGRAM Operations ........................................................................................................... 17

9.2.1 PROGRAM PAGE 80h-10h ........................................................................................... 17

9.2.2 RANDOM DATA INPUT 85h ......................................................................................... 19

9.3 BLOCK ERASE Operation ...................................................................................................... 19

9.4 RESET Operation ................................................................................................................... 20

9.5 WRITE PROTECT Operation ................................................................................................. 21

10 RTIMS FLASH Services definitions ............................................................................................ 22

10.1 Hardware Reset ................................................................................................................... 22

10.2 Format ................................................................................................................................. 22

10.3 Add a Bad Block .................................................................................................................. 22

10.4 Internal Self-Test ................................................................................................................. 23

11 Error management ...................................................................................................................... 23

11.1 High current SEFI event ...................................................................................................... 23

11.2 Procedure to add a bad block in “Stand-alone” mode ......................................................... 24

11.3 Procedure to add a bad block in “telemetry” mode ............................................................. 24

12 Interfaces .................................................................................................................................... 24


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12.1 FLASH interface .................................................................................................................. 24

12.2 Configuration interface ........................................................................................................ 25

12.2.1 Wired configuration interface ......................................................................................... 25

12.2.2 SPI configuration interface ............................................................................................ 27

13 Detailed description of registers ................................................................................................. 30

13.1 Main registers ...................................................................................................................... 31

13.2 FLASH registers .................................................................................................................. 33

13.3 SPI registers ........................................................................................................................ 38

13.4 MRAM registers ................................................................................................................... 38

14 DC and AC characteristics ......................................................................................................... 39

14.1 DC characteristics ............................................................................................................... 39

14.2 VCC power cycling .............................................................................................................. 39

14.3 Miscellaneous timing diagrams ........................................................................................... 40

14.4 FLASH interface Timing diagrams ...................................................................................... 40

14.5 SPI timing diagrams ............................................................................................................ 43

15 Module mechanical drawing ....................................................................................................... 45

16 Part number / Order information ................................................................................................. 46

17 Revision History .......................................................................................................................... 47


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TABLE OF FIGURES

Figure 1: RTIMS FLASH overview .......................................................................................................... 7

Figure 2: Pin assignment for the SOP-38 ................................................................................................ 9

Figure 3: Array organization .................................................................................................................. 13

Figure 4: PAGE READ operation .......................................................................................................... 15

Figure 5: RANDOM DATA READ operation .......................................................................................... 16

Figure 6: READ ID operation ................................................................................................................. 16

Figure 7: READ STATUS operation ...................................................................................................... 17

Figure 8: PROGRAM and READ STATUS operation ........................................................................... 19

Figure 9: RANDOM DATA INPUT operation ......................................................................................... 19

Figure 10: BLOCK ERASE operation .................................................................................................... 20

Figure 11: RESET operation ................................................................................................................. 21

Figure 12: Operation enable .................................................................................................................. 21

Figure 13: Operation disable ................................................................................................................. 22

Figure 14: Connection between RTIMS FLASH and a µController ....................................................... 27

Figure 15: Connection of RTIMS FLASH interrupts in Stand-Alone ..................................................... 27

Figure 16: SPI configuration .................................................................................................................. 28

Figure 17: SPI slaves’ connection ......................................................................................................... 29

Figure 18: VCC power cycling ................................................................................................................. 40

Figure 19: Hardware reset timings ........................................................................................................ 40

Figure 20: Command latch cycle ........................................................................................................... 42

Figure 21: Address latch cycle .............................................................................................................. 42

Figure 22: Serial data read .................................................................................................................... 43

Figure 23: SPI timings with CPOL=CPHA=0 ......................................................................................... 44

Figure 24: SPI timings with CPOL=CPHA=1 ......................................................................................... 44

Figure 25: 38 pin SOP package ............................................................................................................ 45


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TABLE OF TABLES

Table 1: Absolute maximum ratings ........................................................................................................ 7

Table 2: Recommended operating conditions ......................................................................................... 8

Table 3: RTIMS FLASH pinout .............................................................................................................. 10

Table 4 : RTIMS FLASH memory configuration .................................................................................... 12

Table 5: Command set .......................................................................................................................... 13

Table 6: Array addressing ..................................................................................................................... 14

Table 7: Status Register Bit Definition ................................................................................................... 17

Table 8: FLASH interface pinout ........................................................................................................... 25

Table 9: Wired configuration interface ................................................................................................... 26

Table 10: SPI configuration interface .................................................................................................... 27

Table 11: SPI command word ............................................................................................................... 28

Table 12: SPI write register ................................................................................................................... 29

Table 13: SPI read register.................................................................................................................... 30

Table 14: RTIMS FLASH internal registers addresses ......................................................................... 31

Table 15: Version_Sts ........................................................................................................................... 31

Table 16: Conf_Reg register ................................................................................................................. 32

Table 17: Cmd_sts register ................................................................................................................... 32

Table 18: Cmd_ctl register .................................................................................................................... 32

Table 19: EDACErr_Sts register ........................................................................................................... 33

Table 20: EDACErr_Ctl register ............................................................................................................ 33

Table 21: Read_ID_Reg0 ...................................................................................................................... 33

Table 22: Read_ID_Reg1 ...................................................................................................................... 33

Table 23: Read_ID_Reg2 ...................................................................................................................... 34

Table 24: Read_ID_Reg3 ...................................................................................................................... 34

Table 25: Read_ID_Reg4 ...................................................................................................................... 34

Table 26: ECC_Cnt_Reg0 ..................................................................................................................... 34

Table 27: ECC_Cnt_Reg1 ..................................................................................................................... 35

Table 28: BlockErr_Sts0 and BlockErr_Sts1 registers .......................................................................... 35

Table 29: LBErr_Sts0 and LBErr_Sts1 registers ................................................................................... 35

Table 30: BadBlockErr_Sts register ...................................................................................................... 35


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Table 31: BadBlockErr_Ctl register ....................................................................................................... 36

Table 32: FLASHErr_Sts register .......................................................................................................... 36

Table 33: FLASHErr_Ctl register ........................................................................................................... 37

Table 34: FLASH_Sts ............................................................................................................................ 37

Table 35: SPIErr_Sts register ................................................................................................................ 38

Table 36: SPIErr_Ctl register................................................................................................................. 38

Table 37: MRAMErr_Sts register .......................................................................................................... 38

Table 38: MRAMErr_Ctl register ........................................................................................................... 38

Table 39: DC characteristics ................................................................................................................. 39

Table 40: Hardware reset characteristics .............................................................................................. 40

Table 41: PROGRAM/ERASE characteristics....................................................................................... 40

Table 42: Command, address and data input ....................................................................................... 41

Table 43: AC characteristics: Normal Operation ................................................................................... 41

Table 44: AC characteristics: SPI interface ........................................................................................... 43


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3 BLOC DIAGRAM

An overview of the RTIMS FLASH is given in Figure 1.

RTIMS FLASH

Flash Memory

Controller

FLASH0 FLASH1 FLASH2

Analogic

Rst_N

Oscillator

CE_N

CLE

ALE

WE_N

RE_N

IO(7:0)

WP_N

R_B

ITACK_SPICLK

BBACK_SPICS_N

IT0_SPIMOSI

IT1_SPIMISO

IT2

Non

volatile

memory

MEM_AR(1:0)

WL_EN

AD(4:0)

SPI_EN

Vcc x 4

GND x 4

VFlash

91155

Figure 1: RTIMS FLASH overview

4 ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are described in Table 1.

Parameter/Condition Symbol Min Max Unit

Junction Temperature TJ - +150 °C

Maximum Body Temperature

(short exposure only)

Tmax - +215 °C

Storage temperature Tstg -55 +150 °C

Supply voltage relative to VSS VCC 0 5 V

IO voltage relative to power

supply

VIO -0.5 VCC+0.5 V

Power dissipation PDmax - 3 W

Table 1: Absolute maximum ratings


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Note 1: Permanent module damage, including package and Die, may occur if Absolute maximum ratings are exceeded.

Operating Temperature Range may be increased to +125°C during dynamic Burn-in and Life test. Functional operation should

be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time

could affect device reliability.

5 RECOMMENDED OPERATING CONDITIONS

Functional operations outside of the recommended conditions explained in Table 2 are not

guaranteed.

Parameter/Condition Symbol Min Typ Max Unit

Operating temperature TA -40 - +105 °C

Operating supply voltage VCC 3.0 3.3 3.6 V

Ground supply voltage VSS 0 0 0 V

Input High Voltage VIH 2.0 - - V

Input Low Voltage VIL - - 0.8 V

Thermal resistivity (Note 1) RTH(J-C) - - 3 °C/W

Thermal resistivity without

underfill (Note 2)

RTH(J-A) - - 19.5 °C/W

Thermal resistivity with underfill

(Notes 2 et 3)

RTH(J-A) - - 6.5 °C/W

Table 2: Recommended operating conditions

Note 1:

In RTH(J-C) (Thermal resistance Junction to Case), Case is defined as the temperature at the module lateral sides, Junction is

defined as the Junction Temperature of the top die in the stack.

Note 2:

In RTH(J-A) (Thermal resistance Junction to Ambient), Ambient is defined as the temperature at the bottom of the leads in

contact with the board.

Note 3 (Module underfill requirements):

The RTIMS FLASH module shall be under filled on a minimum area of 400 mm² in order to ensure its performances at the

following temperature ranges:

• I (-40°C/+85°C)

• S (-40°C/+105°C)

The underfill material thermal conductivity must be higher or equal to 1.44 W/mK (Emerson & Cuming Eccobond 285 for

example)


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6 PIN DEFINITION & ASSIGNMENTS

RTIMS FLASH has the pinout described in Figure 2 and Table 3.

Figure 2: Pin assignment for the SOP-38

Signal name Direction Comments

User FLASH interface

R_B Output/High-Z(1)

Ready/Busy: An open-drain, active-LOW output, that uses an external pull-up resistor. R_B is used to indicate when the chip is processing a PROGRAM or ERASE operation. It is also used during READ operations to indicate when data is being transferred from the array into the serial data register. When these operations have completed, R_B returns to the High-Z state.

CE_N Input Chip Enable, active low

CLE Input Command Latch Enable

ALE Input Address Latch Enable

WE_N Input Write Enable, active low

RE_N Input Read Enable, active low

IO(7:0) I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/Os are inputs.

WP_N Input Write protect: Protects against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when WP_N is LOW.


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Signal name Direction Comments

Configuration interface (Wired or SPI)

ITACK_SPICLK Input Wired: Acknowledge interrupt SPI: SPI clock

BBACK_SPICS_N Input Wired: Accept the new bad block SPI: SPI Chip Select

IT0_SPIMOSI I/O Wired: Memory full interrupt, active high SPI: Data from Master to Slave

IT1_SPIMISO Output/High-Z

(1)(2)

Wired: Bad block detected interrupt, active high SPI: Data from Slave to Master

IT2_IT Output Wired: Counter overflow interrupt, active high SPI: Global interrupt, active high

Miscellaneous

RST_N Input Hardware reset, active low

MEM_AR(1:0) Input These 2 configuration input pins are used to select one of the 3 modes available: b00: Triple redundancy, 8Gb b01: Hamming code, 16Gb b1x: Full memory, 24Gb These modes are described in paragraph 4.

WL_EN Input 0: Wear Leveling disabled 1: Dynamic Wear Leveling enabled

AD(4:0) Input Component address, used for SPI

SPI_EN Input This input configuration pin is used to select one of the 2 user configuration interfaces available: 0: Wired configuration interface is enabled (stand-alone mode) 1: SPI interface is enabled (telemetry mode) These modes are described in 12.2.

VCC Supply Power Supply.

GND Supply Ground connection.

Table 3: RTIMS FLASH pinout

Note 1: High-Z is for High impedance output.

Note 2: To allow several SPI slaves connected to one master using the same Chip Select signal (SPICS_N), SPIMISO output is

High Z when not reading.


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7 APPLICATION MODES

RTIMS FLASH provides 2 operating modes, the “stand alone” (Wired) mode and the “telemetry” (SPI)

mode.

In the “Stand Alone” mode, RTIMS FLASH acts like a standard NAND FLASH memory, with benefits.

Without any intervention from the user, RTIMS FLASH handles automatic bad block management,

wear leveling, and data encoding (see paragraph 8).

RTIMS FLASH can automatically add a new Bad Block on reception of a “Program/Erase failed” flag

from the FLASH memory array. If the Wear Leveling configuration is selected (see WL_EN input pin in

Table 3), RTIMS FLASH implements counters for each block, and automatically selects the logical

block to use for a user program operation.

In the “telemetry” mode, a serial configuration interface can be used by user to start additional

services (see chapter 10 for detailed definition of services), to read internal information, as the number

of detected bad blocks, the number of program/erase cycles in a block, the number of remaining free

blocks …

The operating mode can be selected by setting the SPI_EN input configuration pin as described in

paragraph 12.2. In both modes, the power sequence described in paragraph 14.2 should be applied.

8 SEE PROTECTION MODES

RTIMS FLASH implements 3 types of SEE protection configuration, as described in Table 4.

Depending on the selected configuration, the size of the page and the size of the word have different

values as described in Figure 3. Anyway, the number of pages in the block and the number of blocks

are constant for the 3 configurations.

In “Stand-alone” mode, the SEE protection configuration is selected using the 2 dedicated input pins,

MEM_AR(1:0), as described in Table 3.

In “telemetry” mode, the SEE protection configuration can be selected using the 2 dedicated pins

MEM_AR(1:0) as described in Table 3, or by writing the RTIMS FLASH configuration register through

the SPI interface as described in Table 16.


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Memory Array

Configuration

TMR EDAC None

Component Size 8 Gb 16 Gb 24 Gb

Block size

(without spare area)

2 Mb 4 Mb 6 Mb

Word Size 8 bits 16 bits 24 bits

Page size

(without spare area)

4 KWords

Spare area size 128 Words

Page Number 64

Block number 3968Note 1

Table 4 : RTIMS FLASH memory configuration

Note 1: Total number of physical blocks is 4096, but 128 are reserved for internal bad block management

Depending of the requested configuration, RTIMS FLASH is able to prevent from the following

radiation effects:

Protection

Mode

SEL HC SEFI SEFI SEU MBU

None Y Y N N N

EDAC Y Y N Y Y(1)

TMR Y Y Y(2)

Y Y

(1) Non Correctable MBU rate: 5.85E-27 per bit per year – Worst case calculation ISS Orbit

(51.5°, 400km)

(2) Non Correctable SEFI rate: 1.0E-1 per RTIMS per year – Worst case calculation ISS

Orbit (51.5°, 400km)

The protection mode can be selected by MEM_AR(1:0) input pins (Table 3) or by configuration

register, as described in Table 16.


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Figure 3: Array organization

Note 1: If MEM_AR=0, 1 word is 8 bits width.

If MEM_AR=1, 1 word is 16 bits width.

If MEM_AR=2, 1 word is 24 bits width.

Note 2: The spare area of the 3968 valid blocks does not contain any specific information. It can be used by user as a normal

area.

9 FLASH COMMAND DEFINITIONS

RTIMS FLASH accepts the set of commands described in Table 5.

Command Name Command

Cycle 1

Number of

Address

Cycles

Data Cycles

Required

Command

Cycle 2

Valid during

Busy

Page Read 00h 5 No 30h No

Random Data

Read

05h 2 No E0h No

Read ID 90h 1 No - No

Read Status 70h - No - Yes

Program Page 80h 5 Yes 10h No

Random Data Input 85h 2 Yes - No

Block Erase 60h 3 No D0h No

Reset FFh - No - Yes

Table 5: Command set

Depending on the command, the number of address cycles requested is different. Table 6

summarizes the address mapping of the RTIMS FLASH through the standard interface.


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Address Cycle IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

1 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

2 0 0 0 CA12 CA11 CA10 CA9 CA8

3 BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

4 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

5 0 0 0 0 0 0 BA17 BA16

Table 6: Array addressing

Note: If CA12 is “1,” then CA[11:7] must be “0”.

If MEM_AR=0, CA shall be given in Bytes.

If MEM_AR=1, CA shall be given in 16bit-words.


9.1 READ OPERATIONS

9.1.1 PAGE READ 00h-30h

To enter READ mode while in operation, write the 00h command to the command register, then write

5 ADDRESS cycles, and conclude with the 30h command.

To determine the progress of the data transfer from the NAND Flash array to the data register (tR),

monitor the R_B signal or, alternatively, issue a READ STATUS (70h) command. If the READ

STATUS command is used to monitor the data transfer, the user must reissue the READ (00h)

command to receive data output from the data register. After the READ command has been reissued,

pulsing the RE_N line will result in outputting data, starting from the initial column address.

A serial page read sequence outputs a complete page of data. After 30h is written, the page data is

transferred to the data register, and R_B goes LOW during the transfer.

When the transfer to the data register is complete, R_B returns HIGH. At this point, data can be read

from the device. Starting from the initial column address and going to the end of the page, read the

data by repeatedly pulsing RE_N at the maximum tRC rate (see Figure 4).


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Figure 4: PAGE READ operation

If a READ timeout occurs, RTIMS FLASH automatically:

o asserts the IT1 interruption (Stand-alone mode) or the IT interruption (Telemetry

mode);

o updates the TIMEOUT bit of the BadBlockErr_Sts register (only in Telemetry mode);

o updates the BlockErr_Sts0 and BlockErr_Sts1 registers(only in Telemetry mode);

o updates the LBErr_Sts0 and LBErr_Sts1 registers(only in Telemetry mode);

Note: If block read has failed, it is user responsibility to declare the physical block failed in SST, RTIMS FLASH does not do

anything. The provided “Add a bad block” service can be used.

9.1.2 RANDOM DATA READ 05h-E0h

The RANDOM DATA READ command enables the user to specify a new column address so the data

at single or multiple addresses can be read. The random read mode is enabled after a normal PAGE

READ (00h-30h) sequence.

Random data can be output after the initial page read by writing an 05h-E0h command sequence

along with the new column address (2 cycles).

The RANDOM DATA READ command can be issued without limit within the page.

Only data on the current page can be read. Pulsing the RE_N pin outputs data sequentially (see

Figure 5).

If MEM_AR=0, CA shall be given in Bytes.




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Figure 5: RANDOM DATA READ operation

9.1.3 READ ID 90h

Writing 90h to the command register puts the device into the read ID mode. The command register

stays in this mode until the next command cycle is issued (see Figure 6).

When receiving the “Read ID” command, RTIMS FLASH outputs the 5 FMC registers,

READ_ID_Reg0 to Read_ID_Reg4. See Table 21 to Table 25 for detailed information.

Figure 6: READ ID operation

9.1.4 READ STATUS 70h

The RTIMS FLASH device has an 8-bit status register the software can read during device operation.

Table 7 and Table 34 describe the status register.

After a READ STATUS command, all READ cycles will be from the status register until a new

command is issued. Changes in the status register will be seen on I/O[7:0] as long as CE_N and

RE_N are LOW; it is not necessary to start a new READ STATUS cycle to see these changes.

While monitoring the status register to determine when the tR (transfer from NAND Flash array to data

register) is complete, the user must reissue the READ (00h) command to make the change from


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status to read mode. After the READ command has been reissued, pulsing the RE_N line will result in

outputting data.

When receiving the “Read Status” command, RTIMS FLASH outputs the internal FLASH_Sts register.

Status Bit Program

Page

Page Read Block Erase Definition

0 Pass/Fail - Pass/Fail 0 = Successful

PROGRAM/ERASE

1 = Error in PROGRAM/ERASE

1 - - - 0

2 - - - 0

3 - - - 0

4 - - - 0

5 Ready/Busy Ready/Busy Ready/Busy 0 = Busy

1 = Ready

6 Ready/Busy Ready/Busy Ready/Busy 0 = Busy

1 = Ready

7 Write Protect Write Protect Write Protect 0 = Protected

1 = Not protected

Table 7: Status Register Bit Definition

Figure 7: READ STATUS operation

9.2 PROGRAM OPERATIONS

9.2.1 PROGRAM PAGE 80h-10h

RTIMS FLASH devices are inherently page-programmed devices.

RTIMS FLASH devices also support partial-page programming operations. This means that any single

bit can only be programmed one time before an erase is required; however, the page can be

partitioned such that a maximum of four programming operations are supported before an erase is

required.


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PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command into the

command register, followed by 5 ADDRESS cycles, then the data. Serial data is loaded on

consecutive WE_N cycles starting at the given address. The PROGRAM (10h) command is written

after the data input is complete. The control logic automatically executes the proper algorithm and

controls all the necessary timing to program and verify the operation. Write verification only detects

“1s” that are not successfully written to “0s.”

R_B goes LOW for the duration of array programming time, tPROG. The READ STATUS (70h)

command and the RESET (FFh) command are the only commands valid during the programming

operation. Bit 6 of the status register will reflect the state of R_B. When the device reaches ready,

read bit 0 of the status register to determine if the program operation passed or failed (see Figure 8).

The command register stays in read status register mode until another valid command is written to it.

The logical block becomes “Used” in the LSTATE field of the LST. The physical blocks become “Used”

in the PSTATE field of the three SST.

The write counter for the logical block is increased, only if targeted page is #0.

If Wear Leveling is enabled (WL_EN field is 1), RTIMS FLASH creates the entry in FDT associated to

the file with the first logical block of the linked block list (the one which has the lowest write block

number in LST), and updates the FFS.

Note: LST entry has already been created, during GENLST service.

If a timeout occurs during FLASH program, the following operations are automatically performed by

RTIMS FLASH:

• update the TIMEOUT bit of the BadBlockErr_Sts register;

• update the BlockErr_Sts0 and BlockErr_Sts1 registers;

• update the LBErr_Sts0 and LBErr_Sts1 registers;

• Reset the 3 FLASH components;

Note: If Page program has failed, it is user responsibility to declare the block failed in SST, RTIMS FLASH does not do anything.

The provided “Add a bad block” service can be used.


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Figure 8: PROGRAM and READ STATUS operation

9.2.2 RANDOM DATA INPUT 85h

After the initial data set is input, additional data can be written to a new column address with the

RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any

number of times in the same page prior to issuing the PAGE WRITE (10h) command. See Figure 9 for

the proper command sequence.

Figure 9: RANDOM DATA INPUT operation

9.3 BLOCK ERASE OPERATION

Erasing occurs at the block level. The RTIMS FLASH device has 4,096 erase blocks, organized into

64 pages per block. The BLOCK ERASE command operates on one block at a time (see Figure 10).

Three cycles of addresses BA[18:6] and PA[5:0] are required. Although page addresses PA[5:0] are

loaded, they are a “Don’t Care” and are ignored for BLOCK ERASE operations.

See Table 6 for addressing details.

The actual command sequence is a two-step process. The ERASE SETUP (60h) command is first

written to the command register. Then 3 cycles of addresses are written to the device. Next, the

ERASE CONFIRM (D0h) command is written to the command register. At the rising edge of WE_N,

R_B goes LOW and the control logic automatically controls the timing and erase-verify operations.

R_B stays LOW for the entire tBERS erase time.


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The READ STATUS (70h) command can be used to check the status of the BLOCK ERASE

operation. When bit 6 = 1, the ERASE operation is complete. Bit 0 indicates a pass/fail condition

where 0 = pass (see Figure 10).

The logical block becomes free in the LSTATE field of the LST. The 3 physical blocks become free in

the STATE field of the three SST.

RTIMS FLASH increases the number of free blocks.

Note: This operation takes about 1 ms, but it is masked time because of FLASH erase time tBERS worst case, which is 2 ms.

If a timeout occurs during FLASH ERASE operation, the following operations are automatically

performed by RTIMS FLASH:

• update the TIMEOUT bit of the BadBlockErr_Sts register;

• update the BlockErr_Sts0 and BlockErr_Sts1 registers;

• update the LBErr_Sts0 and LBErr_Sts1 registers;

• Reset the 3 FLASH components;

Note: If BLOCK ERASE has failed, it is user responsibility to declare the block failed in SST, RTIMS FLASH does not do

anything. The provided “Add a bad block” service can be used.

I/Ox 0x60 Address input (3 cycles) 0xD0 0x70 Status

I/O0=0: Erase successful

I/O0=1: Erase error

R_B

tBERS

ALE

WE_N

CLE

RE_N

Figure 10: BLOCK ERASE operation

9.4 RESET OPERATION

The RESET command is used to abort the command sequence in progress. READ, PROGRAM, and

ERASE commands can be aborted while the device is in the busy state. The contents of the memory

location being programmed or the block being erased are no longer valid. The data may be partially

erased or programmed, and is invalid. The command register is cleared and is ready for the next

command. The data register and cache register contents are marked invalid.


3DSS24G08VS3626


The status register contains the value E0h when WP_N is HIGH; otherwise it is written with a 60h

value. R_B goes LOW for tRST after the RESET command is written to the command register.

Figure 11: RESET operation

9.5 WRITE PROTECT OPERATION

It is possible to enable and disable PROGRAM and ERASE commands using the WP_N pin. Figure

12 and Figure 13 illustrate the setup time (tWW) required from WP_N toggling until a PROGRAM or

ERASE command is latched into the command register. After command cycle 1 is latched, the WP_N

pin must not be toggled until the command is complete and the device is ready (status register bit 5 is

“1”).

Figure 12: Operation enable


3DSS24G08VS3626


Figure 13: Operation disable

10 RTIMS FLASH SERVICES DEFINITIONS

10.1 HARDWARE RESET

RTIMS FLASH receives an asynchronous hardware reset input, RST_N, active low. This reset is used

to reset the whole RTIMS FLASH, including the FLASH memory array. When leaving the reset,

RTIMS FLASH automatically updates the internal configuration register by reading the 3 input

configuration pins, MEM_AR(1:0) and WL_EN.

After tON, RTIMS FLASH drives the R_B output to High Z (Ready state), to inform user that RTIMS

FLASH is ready for normal operation.

Please note that this Hardware Rest is different with the Flash Reset commend descripted in Chapter

9.4.

10.2 FORMAT

The purpose of this operation is to erase all the physical and valid blocks. This operation formats the

whole memory array.

The service starts when the FORMAT field in Cmd_ctl register is set.

The service ends when:

• the FORMAT_ON field of Cmd_Sts register goes back to 0;

• the R_B output goes back to High impedance;

• the R_B field of FLASH_Sts goes back to 1.

FLASH interface remains Busy during the whole service. The format service is tF.

10.3 ADD A BAD BLOCK

The purpose of this service is to automatically add a bad block into the internal block management

system. The physical invalid block is selected:

• by user, when writing LBErr_Sts0, LBErr_Sts1, BlockErr_Sts0 and BlockErr_Sts1 registers

(only available if SPI_EN input pin is 1);


3DSS24G08VS3626


• automatically when detecting an error.

The service starts when:

• BBACK_SPICS_N input pin is high and SPI_EN = 0;

• The ADDBB field in Cmd_ctl register is set and SPI_EN = 1.

The service ends when:

• the ADDBB_ON field of Cmd_Sts register goes back to 0;

• the R_B output goes back to High impedance;

• the R_B field of FLASH_Sts goes back to 1.

FLASH interface remains Busy during the whole service. RTIMS FLASH automatically replaces the

invalid block with a physical spare block (number 3968 to 4095). If no spare is available, asserts the

FULLMEM bit of the FLASHErr_Sts.

The “Add Bad Block” service operation time is tADDBB.

10.4 INTERNAL SELF-TEST

The purpose of this operation is to find new bad blocks into memory array. This operation erases the

whole memory array, takes about 30 min, and updates the SST.

Self-Test operation can be started only with SPI, i.e. SPI_EN input is high.

Upon writing on ST field in Cmd_ctl register, RTIMS FLASH sets the R_B output to 0 during the Self-

Test operation.

At the end of the Self-Test, RTIMS FLASH sets the R_B output back to High Z.

If the Self-Test is interrupted before the end (RTIMS FLASH power-off), the Format or the Self-Test

service must be run before any other operation.

The “Internal Self-Test” service operation time is tIST.

11 ERROR MANAGEMENT

11.1 HIGH CURRENT SEFI EVENT

When a High Current SEFI occurs on RTIMS FLASH, a normal mode is automatically retrieved, the

HCSEFI field of FLASHErr_Sts is asserted, and the output interrupt is asserted.

If a Program or ERASE command was in progress, the status may be “Operation Failed”. In this case,

the PROGRAM or ERASE command should be resent to the RTIMS FLASH.

Note: If the last received FLASH command is 0x00 or 0x30, the read data may be invalid.

When receiving a Program or an Erase command with WP_N low, RTIMS FLASH asserts the WP field

of FLASHErr_Sts register. The FLASH data will not be corrupted.


3DSS24G08VS3626


11.2 PROCEDURE TO ADD A BAD BLOCK IN “STAND-ALONE” MODE

This procedure may be used in the following cases:

• IT1 interruption asserted, meaning that an “Operation Failed” or a “Timeout” has been

detected on the block by RTIMS FLASH;

• IT2 interruption asserted, meaning that data errors have been detected during the last read

operation.

Steps to execute:

• Assert the ITACK input signal to acknowledge for the interruption;

• Assert the BBACK signal to start the “Add a bad-block” internal service.

11.3 PROCEDURE TO ADD A BAD BLOCK IN “TELEMETRY” MODE

This procedure may be used in the following cases:

• Several correctable errors detected during PAGE READ command;

• Operation timeout detected by RTIMS FLASH (field TIMEOUT of BadBlockErr_Sts register is

asserted);

• Operation failed detected by RTIMS FLASH (field OP_FAILED of BadBlockErr_Sts register is

asserted).

Steps to execute:

• Step 1: Identify the physical block in error by reading the BlockErr_Sts0 and BlockErr_Sts1

registers;

• Step 2: Start the “Add Bad block” service.

12 INTERFACES

12.1 FLASH INTERFACE

RTIMS FLASH implements a FLASH interface, with signals described in Table 8.

RTIMS FLASH drives R_B output low or HighZ, to allow multiple RTIMS FLASH modules tied

together.


3DSS24G08VS3626


Pin name Direction Comments

R_B O/z 0: Busy

HighZ: Ready

CE_N I Chip Enable, active low

CLE I Command Latch Enable

ALE I Address Latch Enable

WE_N I Write Enable, active low

RE_N I Read Enable, active low

IO(7:0) I/O Command/Address/Data bus

WP_N I Write protect, active low

Table 8: FLASH interface pinout

RTIMS FLASH implements an EDAC code into the 3 FLASH components, to correct SEU.

RTIMS FLASH implements 2 codes, depending on the MEM_AR(1:0) configuration input value:

• MEM_AR(1:0) = 1: Hamming code

RTIMS FLASH implements 8 check bits for 16 data bits, to prevent SEU and MBU.

• MEM_AR(1:0) = 0: TMR code

RTIMS FLASH implements 16 check bits for 8 data bits. Data correction is performed with an

independent majority voter for each data bit.

• MEM_AR(1:0) = 2 or MEM_AR(1:0) = 3: No code implemented.

RTIMS FLASH implements the FLASHMode_Reg register. When set, put the 3 FLASH components in

idle mode.

12.2 CONFIGURATION INTERFACE

RTIMS FLASH implements 2 multiplexed configuration interfaces, depending on SPI_EN input pin

value:

• SPI_EN = 0: Wired configuration interface;

• SPI_EN=1: SPI interface.

12.2.1 Wired configuration interface

RTIMS FLASH implements inputs/outputs described in Table 9, for the wired configuration interface.


3DSS24G08VS3626


Pin Name Signal Name Input / Output Comments

IT0_SPIMOSI IT0 O Memory Full Interruption

IT1_SPIMISO IT1 O Bad Block detected

IT2_IT IT2 O Internal counters overflowed or

components FLASH have different Read

ID

ITACK_SPICLK ITACK I Interrupt acknowledge

BBACK_SPICS_N BBACK I Accept the last detected bad block by

starting the “Add a bad block” service

Table 9: Wired configuration interface

The 3 RTIMS FLASH interrupts electrical level active HIGH. They are cleared when ITACK input is

asserted.

RTIMS FLASH asserts IT0 output interrupt if at least 1 of these RTIMS FLASH internal registers is

asserted:

1. FIFO_UND field of FLASHErr_Sts register;

2. FIFO_OVF field of FLASHErr_Sts register;

3. WP field of FLASHErr_Sts register;

4. FILE_ERR field of FLASHErr_Sts register;

5. FULLMEM field of FLASHErr_Sts register.


asserted:

1. TIMEOUT field of BadBlockErr_Sts register;

2. OP_FAILED field of BadBlockErr_Sts register.


asserted:

1. ERRCNT_OVF field of FLASHErr_Sts register;

2. READ_ID field of FLASHErr_Sts register;

3. HCSEFI field of FLASHErr_Sts register;

4. READ_ERR field of MRAMErr_Sts register;

5. WRITE_ERR field of MRAMErr_Sts register;

6. PER_DT field of SPIErr_Sts register;

7. PER_CMD field of SPIErr_Sts register.

Figure 14 and Figure 15 describe 2 examples of connection for the 3 interruptions and the 2

acknowledges, with and without a microcontroller.


3DSS24G08VS3626


µController RTIMS FLASH

IT0

IT1

IT2

ITACK

BBACK

Figure 14: Connection between RTIMS FLASH and a µController

RTIMS FLASH

IT0

IT1

IT2

ITACK

BBACKVCC R

Figure 15: Connection of RTIMS FLASH interrupts in Stand-Alone

12.2.2 SPI configuration interface

RTIMS FLASH implements an SPI interface, with the signals described in Table 10.

RTIMS FLASH is compliant with SPICLK frequency range from 1 MHz to 8 MHz.

RTIMS FLASH samples data bit on SPICLK rising edge, and generates data bit on SPICLK falling

edge, i.e. RTIMS FLASH is compatible either with CPOL=0 and CPHA=0, or CPOL=1 and CPHA=1.

SPI configurations are described in Figure 16.

Serial data Bytes are sent MSB first to RTIMS FLASH.

RTIMS FLASH sends read data Bytes MSB first.

Pin Name Signal Name Input / Output Comments

ITACK_SPICLK SPICLK I SPI clock

BBACK_SPICS_N SPICS_N I SPI Chip Select

IT0_SPIMOSI SPIMOSI I Data from Master to Slave

IT1_SPIMISO SPIMISO O/Z (Note 1) Data from Slave to Master

IT2_IT IT O Global interruption

Table 10: SPI configuration interface

Note: To allow several SPI slaves connected to the same master using the same read data line (SPIMISO), SPIMISO output is

High Z when not reading.


3DSS24G08VS3626


SPICS_N

SPICLK

(CPOL=0)

SPIMOSI

SPIMISO

(CPHA=0)

SPICLK

(CPOL=1)

Z D7 D6 PB Z

SPIMOSI

SPIMISO

(CPHA=1)Z D7 D6 PB Z

D0

D0

Figure 16: SPI configuration

SPI access begins with an 8-bit command word, with an added odd parity bit, like described in Table

11.

7 6 5 4 3 2 1 0

1 R/W Reserved AD(4:0) P

Table 11: SPI command word

• R/W: Read/Write

o 0: Write

o 1: Read

• AD: Component Address. Using this field allows SPI master to control up to 32 slaves with

only 1 SPI interface, like described in Figure 17.

• P: Odd parity bit

After a Read (register or data) has been performed, RTIMS FLASH outputs a serial bit low on

SPIMISO line before High impedance, to avoid unknown state on SPIMISO line.

Note: A pull down resistor has to be connected on SPIMISO line at board level.


3DSS24G08VS3626


Figure 17: SPI slaves’ connection

12.2.2.1 Write register

In case of Write register, RTIMS FLASH receives the address and the data Byte directly following the

command Byte, like described in Table 12.

RTIMS FLASH writes the correct data Byte in the register.

7 6 5 4 3 2 1 0 PB

RCV Byte 0 1 0 0 AD(4:0) -

RCV Byte 1 REG_AD(7:0) -

RCV Byte 2 DATA(7:0) -

Table 12: SPI write register

12.2.2.2 Read register

In case of Read register, RTIMS FLASH receives the address directly following the command Byte,

like described in Table 13.

RTIMS FLASH reads the correct data Byte from the register.

RTIMS FLASH sends the status Byte, equal to the received command Byte, directly followed by the

Data Byte.


3DSS24G08VS3626


7 6 5 4 3 2 1 0 PB

RCV Byte 0 1 1 0 AD(4:0) -

RCV Byte 1 REG_AD(7:0) -

SENT Byte 0 1 1 0 AD(4:0) -

SENT Byte 1 DATA(7:0) -

Table 13: SPI read register

12.2.2.3 SPI Error management

RTIMS FLASH asserts IT output interrupt if at least 1 of these registers is asserted:

1. FIFO_UND field of FLASHErr_Sts register;

2. FIFO_OVF field of FLASHErr_Sts register;

3. WP field of FLASHErr_Sts register;

4. FILE_ERR field of FLASHErr_Sts register;

5. FULLMEM field of FLASHErr_Sts register;

6. TIMEOUT field of BadBlockErr_Sts register;

7. OP_FAILED field of BadBlockErr_Sts register;

8. ERRCNT_OVF field of FLASHErr_Sts register;

9. READ_ID field of FLASHErr_Sts register;

10. HCSEFI field of FLASHErr_Sts register;

11. READ_ERR field of MRAMErr_Sts register;

12. WRITE_ERR field of MRAMErr_Sts register;

13. PER_DT field of SPIErr_Sts register;

14. PER_CMD field of SPIErr_Sts register.

If a command word with parity error is received, RTIMS FLASH ignores the command and asserts the

PER_CMD bit of the SPIErr_Sts register.

If a data word with parity error is received, RTIMS FLASH writes the data word in memory as expected

and asserts the PER_DT bit of the SPIErr_Sts register.

13 DETAILED DESCRIPTION OF REGISTERS

RTIMS FLASH implements the registers described in Table 14. These registers are available through

“SPI write register” and “SPI read register” commands


3DSS24G08VS3626


Register name Address (Byte)

Version_Sts 0x00

Conf_Reg 0x01

Cmd_sts 0x02

Cmd_ctl 0x03

EDACErr_Sts 0x04

EDACErr_Ctl 0x05

EDACConf_Reg 0x06

FLASHErr_Sts 0x40

FLASHErr_Ctl 0x41

Read_ID_Reg0 0x42

Read_ID_Reg1 0x43

Read_ID_Reg2 0x44

Read_ID_Reg3 0x45

Read_ID_Reg4 0x46

BlockErr_Sts0 0x47

BlockErr_Sts1 0x48

BadBlockErr_Sts 0x49

BadBlockErr_Ctl 0x4A

ECC_Cnt_Reg0 0x4B

ECC_Cnt_Reg1 0x4C

FLASHMode_Reg 0x4D

LBErr_Sts0 0x4E

LBErr_Sts1 0x4F

FLASH_Sts 0x50

SPIErr_Sts 0x80

SPIErr_Ctl 0x81

MRAMErr_Sts 0xC0

MRAMErr_Ctl 0xC1

Table 14: RTIMS FLASH internal registers addresses

RTIMS FLASH implements the internal registers like described in the Table 15 to Table 38.

13.1 MAIN REGISTERS

Bits Field Name Comments R/W Reset value

7-0 VERSION Version of the RTIMS FLASH internal ASIC R 0x36

Table 15: Version_Sts


3DSS24G08VS3626



7 WL_EN 0: Wear Leveling disabled

1: Dynamic Wear Leveling enabled

This field reflects the value of WL_EN input

pin after reset, but can be updated.

R/W -

6-5 MEM_AR b00: Triple redundancy, 8 Gb;

b01: Hamming code, 16 Gb;

b10: No redundancy, 24 Gb.

This field reflects the value of

MEM_AR(1:0) input pins after reset, but

can be updated.

R/W -

4-0 AD Component address.

This field reflects the value of AD input pins.

R -

Table 16: Conf_Reg register


7-5 Reserved R 0

4 ST_ON Internal Self-Test in progress R 0

3 ADDBB_ON Adding the Bad Block described in

BlockErr_Sts0 and BlockErr_Sts1 registers

in progress.

R 0

2 FORMAT_ON Memory Format in progress R 0

1 GENLST_ON New LST generation in progress R 0

0 Reserved R 0

Table 17: Cmd_sts register


7-5 Reserved R 0

4 ST 0: No effect 1: Start internal Self-Test

W -

3 ADDBB 0: No effect 1: Start adding the Bad Block described in BlockErr_Sts0 and BlockErr_Sts1 registers into SST

W -

2 FORMAT 0: No effect 1: Start memory format

W -

1 GENLST 0: No effect 1: Start the new LST generation

W -

0 Reserved W -

Table 18: Cmd_ctl register


3DSS24G08VS3626



7-3 Reserved R 0

2 ERR_OUT 0: No error

1: EDAC error detected in output FIFO

R 0

1 ERR_INT 0: No error

1: EDAC error detected in internal FIFO

R 0

0 ERR_IN 0: No error

1: EDAC error detected in input FIFO

R 0

Table 19: EDACErr_Sts register


7-3 Reserved R 0

2 ACK_ERR_OUT 0: No effect

1: Clears the ERR_OUT field of the

EDACErr_Sts register

W -

1 ACK_ERR_INT 0: No effect

1: Clears the ERR_INT field of the


W -

0 ACK_ERR_IN 0: No effect

1: Clears the ERR_IN field of the


W -

Table 20: EDACErr_Ctl register

13.2 FLASH REGISTERS


7-0 M_ID Manufacturer ID R 0x01

Table 21: Read_ID_Reg0


7-0 D_ID Device ID R 0x3D



3DSS24G08VS3626



7 CP Cache programming

0: Not supported

1: Supported

R 0

6 INT_OP Interleaved operations between multiple die

on the same CE_N

0: Not supported

1: Supported

R 0

5-4 NPP Number of simultaneously programmed

pages

R b01

3-2 CT Cell Type R 0

1-0 NDIE Number of Die per CE R 0



7;3 S_ACC Serial access

b10: 25 ns min

R -

6 ORG Organization

0: x8

R -

5-4 B_SIZE Block size, without spare

b10: 256 KWords

R -

2 SP_SIZE Spare area size

1: 128 Words

R -

1-0 P_SIZE Page size

b10: 4 KWords

R -



7 Reserved R -

6-4 PL_SIZE Plane size

b110: 4 GWords

R -

3-2 NB_PLANES Planes per CE_N

b01: 2

b10: 4

R -

1-0 Reserved R -



7-0 ECC0 MSB Byte of ECC counter R/W 0

Table 26: ECC_Cnt_Reg0


3DSS24G08VS3626



7-0 ECC1 LSB Byte of ECC counter R/W 0

Table 27: ECC_Cnt_Reg1


15 PB_VALID 0: Content of these registers is not valid

1: Content of these registers is valid

R

(Note1)

0

14 Reserved R 0

13-12 FLASH_ID Number of the FLASH component in error.

Updated on the 1st error reported in

BadBlockErr_Sts register.

R

(Note1)

0

11-0 PB Number of the physical block in error.



R

(Note1)

0

Table 28: BlockErr_Sts0 and BlockErr_Sts1 registers


15 LB_VALID 0: Content of these registers is not valid

1: Content of these registers is valid

R

(Note1)

0

14-12 Reserved R 0

11-0 LB Number of the logical block in error.



R

(Note1)

0

Table 29: LBErr_Sts0 and LBErr_Sts1 registers

Note1: These registers are reset using BadBlockErr_Ctl register if SPI is available (SPI_EN=1), else they are reset automatically

at the end of the “Add a Bad Block” service.


7-2 Reserved R 0

1 TIMEOUT Timeout detected on Program, Erase or

Read.

R 0

0 OP_FAILED Program or Erase failed detected. R 0

Table 30: BadBlockErr_Sts register


3DSS24G08VS3626



7-2 Reserved R 0

1 ACK_TIMEOUT 0: No effect

1: Clear the field TIMEOUT in the


Clear the BlockErr_Sts0, BlockErr_Sts1,

LBErr_Sts0 and LBErr_Sts1 registers

W -

0 ACK_OP_FAILED 0: No effect

1: Clear the field OP_FAILED in the


Clear the BlockErr_Sts0, BlockErr_Sts1,

LBErr_Sts0 and LBErr_Sts1 registers

W -

Table 31: BadBlockErr_Ctl register


7 HCSEFI A High Current SEFI has been detected,

FLASH components have been reset.

R 0

6 FILE_ERR An erase or a Read is requested in a non-

existing file (only when WL_EN=1).

R 0

5 WP A program or erase operation has been

requested, with WP_N input pin low.

R 0

4 FULLMEM Memory is full, occurs when a write is

requested without any logical block

available, or during GenLST if Wear

Leveling is deactivated.

R 0

3 ERRCNT_OVF Corrigible error counter overflows R 0

2 READ_ID Different Read ID have been found on the 3

FLASH components.

R 0

1 FIFO_UND Underflow in the output FIFO, used during

read operation.

R 0

0 FIFO_OVF Overflow in the input FIFO, used during

program operation.

R 0

Table 32: FLASHErr_Sts register


3DSS24G08VS3626



7 ACK_HCSEFI 0: No effect

1: Clear the HCSEFI field in the

Err_Sts register

W -

6 ACK_FILE_ERR 0: No effect

1: Clear the FILE_ERR field in the

Err_Sts register

W -

5 ACK_WP 0: No effect

1: Clear the WP field in the Err_Sts

register

W -

4 ACK_FULLMEM 0: No effect

1: Clear the field FULLMEM in the

Err_Sts register

W -

3 ACK_ERRCNT_OVF 0: No effect

1: Clear the ERRCNT_OVF field in the

Err_Sts register

W -

2 ACK_READ_ID 0: No effect

1: Clear the READ_ID field in the

Err_Sts register

W -

1 ACK_FIFO_UND 0: No effect

1: Clear the FIFO_UND field in the

Err_Sts register

W -

0 ACK_FIFO_OVF 0: No effect

1: Clear the FIFO_OVF field in the

Err_Sts register

W -

Table 33: FLASHErr_Ctl register


7 WP Write Protect

0: protected

1: Not protected

R -

6 R_B Ready/Busy R -

5 R_B Ready/Busy R -

4-1 Reserved R 0

0 P_F This field is relevant only after a program or

an erase operation.

0: Successful program/erase

1: Error in program/erase

R 0

Table 34: FLASH_Sts


3DSS24G08VS3626


13.3 SPI REGISTERS


7-2 Reserved R 0

1 PER_DT 0: No error

1: Parity error detected in a received data

R 0

0 PER_CMD 0: No error

1: Parity error detected in a received

command.

R 0

Table 35: SPIErr_Sts register


7-2 Reserved R 0

1 ACK_PER_DT 0: No effect

1: Clear the PER_DT field in the

SPIErr_Sts register

W -

0 ACK_PER_CMD 0: No effect

1: Clear the PER_CMD field in the

SPIErr_Sts register

W -

Table 36: SPIErr_Ctl register

13.4 MRAM REGISTERS


7-2 Reserved R 0

1 READ_ERR 0: No error

1: Data error detected when reading

MRAM.

R 0

0 WRITE_ERR 0: No error

1: Data error detected when writing MRAM.

R 0

Table 37: MRAMErr_Sts register


7-2 Reserved R 0

1 ACK_READ_ERR 0: No effect

1: Clear the READ_ERR field in the

MRAMErr_Sts register

W -

0 ACK_WRITE_ERR 0: No effect

1: Clear the WRITE_ERR field in the

MRAMErr_Sts register

W -

Table 38: MRAMErr_Ctl register


3DSS24G08VS3626


14 DC AND AC CHARACTERISTICS

14.1 DC CHARACTERISTICS

PARAMETERS Symbol TEST CONDITIONS MODULE

Min Max

Standby Current ISB #CE = VIH,

WP = 0V to VCC - 580 mA

Operating Current

(Any Mode )

ICC #CE = VIL, IOUT = 0 mA,

tRC = 25 ns - 650 mA

Input Leakage

Current Low

ILIL VDD = 3.6V, VIN = 0V -20µA 20µA

Input Leakage

Current High

ILIH VDD = 3.6V, VIN = 3.6V -20µA 20µA

Output Leakage

Current Low(1)

ILOL VDD = 3.6V, VOUT = 0V

CE_N = 3.6V

RST_N = 3.6V

SPI_EN = 3.6V

BBACK_SPICS_N = 3.6V

-20µA 20µA

Output Leakage

Current High(1)

ILOH VDD = 3.6V, VOUT = 3.6V

CE_N = 3.6V

RST_N = 3.6V

SPI_EN = 3.6V

BBACK_SPICS_N = 3.6V

-20µA 20µA

Low Level Output

Voltage

VOL VDD = 3.0V, IOL = 2.1mA - 0.4V

High Level Output

Voltage

VOH VDD = 3.0V, IOH = -0.4mA 2.4V -

Table 39: DC characteristics

Note 1: IT2_IT output is not tested for ILOL and ILOH.

14.2 VCC POWER CYCLING

RTIMS FLASH is designed to prevent data corruption during power transitions. VCC is internally

monitored. When VCC goes below approximately 3.0V, PROGRAM and ERASE functions are disabled

by the FMC.


3DSS24G08VS3626


Figure 18: VCC power cycling

14.3 MISCELLANEOUS TIMING DIAGRAMS

Parameter Symbol Min Max Unit

Reset LOW to Busy delay tOFF - 50 ns

Reset HIGH to Ready delay tON - 1 ms

RST_N input pin pulse width tHRST 100 - ns

Table 40: Hardware reset characteristics

Figure 19: Hardware reset timings

14.4 FLASH INTERFACE TIMING DIAGRAMS

Parameter Symbol Min Typ Max Unit

Number of partial page programs NOP - - 4 cycles

BLOCK ERASE operation time tBERS 100 ns 1.5 2 (Note 1)

ms

PAGE PROGRAM operation time tPROG 100 ns 220 700 (Note 2)

us

“Format” service operation time tF - - 12 s

“Add Bad Block” service

operation time

tADDBB - - 30 us

“Internal Self-Test” service

operation time

tIST - 5 30 min

Table 41: PROGRAM/ERASE characteristics

Note 1: When a timeout occurs during a page program, tBERS can be up to 2010 us.


3DSS24G08VS3626


Note 2: When a timeout occurs during a page program, tPROG can be up to 710 us.


ALE to data start tADL 70 - ns

ALE hold time tALH 5 - ns

ALE setup time tALS 10 - ns

CE_N hold time tCH 5 - ns

CLE hold time tCLH 5 - ns

CLE setup time tCLS 10 - ns

CE_N setup time tCS 15 - ns

Data hold time tDH 5 - ns

Data setup time tDS 10 - ns

WRITE cycle time tWC 25 - ns

WE_N pulse width HIGH tWH 10 - ns

WE_N pulse width tWP 12 - ns

WP_N setup time tWW 30 - ns

Table 42: Command, address and data input


ALE to RE_N delay tAR 10 - ns

CE_N access time tCEA - 25 ns

CE_N High to output High-Z tCHZ - 31 ns

CLE to RE_N delay tCLR 10 - ns

CE_N HIGH to output hold tCOH 9 - ns

Output High-Z to RE_N LOW tIR 0 - ns

Data transfer from Flash

array to data register

tR 0.1 25 (Note 1)

us

READ cycle time tRC 25 - ns

RE_N access time tREA - 20 ns

RE_N HIGH hold time tREH 10 - ns

RE_N HIGH to output hold tRHOH 18 - ns

RE_N HIGH to WE_N LOW tRHW 100 - ns

RE_N HIGH to output High-Z tRHZ - 100 ns

RE_N LOW to output hold tRLOH 5 - ns

RE_N pulse width tRP 12 - ns

Ready to RE_N low tRR 20 - ns

Reset time

(READ/PROGRAM/ERASE)

tRST - 5/10/500 us

WE_N HIGH to busy tWB - 100 ns

WE_N HIGH to RE_N LOW tWHR 60 - ns

Table 43: AC characteristics: Normal Operation

Note 1: When a timeout occurs during a page read, tR can be up to 38 us.


3DSS24G08VS3626


Figure 20: Command latch cycle

Figure 21: Address latch cycle


3DSS24G08VS3626


Figure 22: Serial data read

14.5 SPI TIMING DIAGRAMS


Input clock period tC 125 - ns

Input clock High tCH 60 - ns

Input clock Low tCL 60 - ns

Data setup time tDS 5 - ns

Data hold time tDH 20 - ns

CLK to SPIMISO propagation

delay

tPD 20 70 ns

CS_N setup time tCSS 20 - ns

CS_N high pulse width tCSW 20 - ns

CLK fall to CS_N fall setup tCSH0 20 - ns

CLK fall to CS_N rise hold

time

tCSH1 20 - ns

CS_N rise to clock rise setup tCS1 20 - ns

Table 44: AC characteristics: SPI interface


3DSS24G08VS3626


Figure 23: SPI timings with CPOL=CPHA=0

Figure 24: SPI timings with CPOL=CPHA=1


3DSS24G08VS3626


15 MODULE MECHANICAL DRAWING

Figure 25: 38 pin SOP package


3DSS24G08VS3626


16 PART NUMBER / ORDER INFORMATION

3DSS24G08VS3626-XX

Temperature Range Quality Grade (Screening Level)

C : 0°C /+70°C B : Industrial

I : -40°C / + 85°C S : Space

S : -40°C / +105°C

Available Part Numbers:

Part Number Temperature range Quality Grade

3DSS24G08VS3626-IB -40°C / + 85°C Industrial

3DSS24G08VS3626-IS -40°C / + 85°C Space

3DSS24G08VS3626-SS -40°C / +105°C Space

Main Sales Office

FRANCE 3D PLUS

408, rue Hélène Boucher ZI.

78532 BUC Cedex

Tel : 33 (0)1 30 83 26 50 Fax : 33 (0)1 39 56 25 89 Web : www.3d-plus.com

e-mail : [email protected]

USA

3D PLUS U.S.A, Inc 6633 Eldorado Parcway

Suite 420

Mckinney, TX 75070

Tel : (214) 733-8505 Fax : (214) 733-8506 e-mail : [email protected]


3DSS24G08VS3626


17 REVISION HISTORY

Rev. 4, December 2015

• Add VIO maximum ratings to Table 1

• Paragraph 9.2: Remove the restriction for Random page address programming

• Add paragraph 14.3 with timings tHRST, tOFF and tON

• Add tPROG and tBERS minimum timings to Table 41

• Add tF, tADDBB and tIST timings in Table 41

• Add tR minimum timing to Table 43

Rev. 3, August 2015

• Remove the Preliminary mention in the footer of the document

• Add Figure 3: Array organization

• Table 17 and Table 18: Remove the “Fetch Failing Block” service

• Table 40:

o Update tPROG to 700 us instead of 600 us

o Add Note 1 and Note 2

• Table 42: Add Note 1 regarding tR timing

Rev. 2, January 2015

• Paragraph 1:

o Update picture on page 1

o Define operating temperature range to -40°C to +105°C

o Temperature storage is -55°C/+150°C

• Paragraph 4: Update PDmax and VCC

• Paragraph 5:

o Add RTH(J-C) and RTH(J-A)

o Add note “Module underfill requirements”

o Minimum operating voltage set to 3V

• Paragraph 14.1: Update ISB and ICC parameters

• Paragraph 14.1: Add test conditions for ILOL and ILOH

• Paragraph 14.4: Update tPD timing

• Add paragraph 17: Revision History

Rev. 1, September 2014

• Initial release

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