rc messages

Message Reference for Encounter RTL Compiler Product Version 12.2 May 2013

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Message Reference for Encounter RTL Compiler1Info Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5List of Info Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51List of Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161List of Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

ContentsMay 2013 3 Product Version 12.2 2003-2013 Cadence Design Systems, Inc. All rights reserved.

Message Reference for Encounter RTL Compiler

May 2013 5 Product Version 12.2 2003-2013 Cadence Design Systems, Inc. All rights reserved.

1Info Messages

Message Reference for Encounter RTL CompilerInfo Messages


List of Info Messages

Message-ID Title Help

ATTR-101 Setting attribute.

ATTR-102 Resetting attribute.

CDFG-5 Error encountered during high level optimization.

The optimization can be turned off by setting the hdl-architecture's (module's) attribute to false before elaboration.

CDFG-6 Error encountered during high level optimization.

The optimization can be turned off by setting the tcl variable to 0 before elaboration.

CDFG-22 Unresolved instance '%s'.

CDFG-23 Wrote CDFG.

CDFG-250 Processing multi-dimensional arrays.

CDFG-286 Reference to global signal in subprogram.

CDFG-295 Applying architecture pragma. Error during elaboration.

CDFG-300 Checking HDL design.

CDFG-301 No HDL designs to process. The 'read_hdl' command creates an HDL design for every Verilog module and every VHDL architecture. HDL designs are automatically deleted when you use the 'elaborate' or the 'read_netlist' command. Use 'find / -hdl_arch *' to list all available HDL designs.

CDFG-302 HDL design is up to date.

CDFG-303 Processing HDL design.

CDFG-305 Deleting HDL design.

CDFG-308 Processing HDL design from subprogram.

CDFG-309 Processing HDL design from operator.

CDFG-325 Problem in processing of input RTL. Error in processing of HDL during elaboration. Possibly due to combinational loops, or unsynthesizable constructs.

CDFG-327 Processing ChipWare component.

CDFG-328 Processing module from operator.

CDFG-340 Building parameterized design.

CDFG-345 Ignored range specification for parameter. In Verilog-1995 a range given in a parameter declaration is ignored. To make use of the parameter range, read the design with 'read_hdl -v2001' or 'read_hdl -sv'.

CDFG-359 Building ChipWare component.



CDFG-361 Signal is not referenced within the process or block, but is in the sensitivity list.

Asynchronous logic, such as a latch or combinational logic, is inferred for this process or block. Signals that are not referenced can be removed from the sensitivity list. If the intent is to infer a flip-flop, ensure that the process or block is sensitive to the signal edge by adding 'posedge' or 'negedge' for Verilog designs or 'event' for VHDL designs.

CDFG-362 Assuming that the full range of indexed or sliced sensitivity signal is in the sensitivity list.

CDFG-363 Ignored invalid sensitivity signal in the sensitivity list.

CDFG-365 Clock signal is not used as a clock in this process or block.

CDFG-372 Bitwidth mismatch in assignment.

CDFG-373 Sign mismatch in assignment.

CDFG-425 Instantiated design.

CDFG-426 Searching for library cell.

CDFG-427 Linking module.

CDFG-458 Inferred leading 0/1 detector from a 'for loop' statement.

For example, a 'for loop' statement of the form:reg [width-1:0] array;for (i = 0; i < width; i = i + 1)

if (array[i])count = i;

is recognized as a leading-1 detector. Other coding styles, including loops with disable statements, can be recognized. See 'HDL Modeling in Encounter RTL Compiler' for more information.

CDFG-459 Detected an RTL macro for the 'for loop' statement. Replacing it with an equivalent internal representation.

RTL macro replacement can result in improved QOR.

CDFG-470 Constant conditional expression.




CDFG-478 Converting if statement to equivalent case statement.

An if statement is internally converted to an equivalent case statement if:1. Each condition compares the same expression against a constant value2. Conditions may be OR'd together3. There are at least two branches in the if statement containing the above types of conditionsThis transformation converts an if statement, which is by default considered to have priority logic, to a case statement, which has simpler parallel logic.

CDFG-479 Constant relational expression. A relational expression can evaluate to a constant when a variable is compared to a value which is outside the bounds of the variable.

CDFG-500 Unused module input port. The value of the input port is not used within the design.

CDFG-501 Unused module inout port. The value of the inout port is not used within the design.

CDFG-505 Assignment to supply0/supply1.

CDFG-509 Preserving unused register. A flip-flop or latch that was inferred for an unused signal or variable is being preserved. Better area results are possible if the 'hdl_preserve_unused_registers' attribute is set to 'false'.

CDFG-511 An 'X' or 'Z' value propagated to a conditional statement can cause a simulation mismatch between the original and the synthesized designs.

Verify that 'X' and 'Z' assignments in the HDL are as intended. If the HDL source line given for this assignment is not accurate, search backwards in the file for an explicit 'X' or 'Z' assignment that may have been propagated to the given location.

CDFG-512 HDL design already elaborated.

CDFG-555 Linking parameterized module by name.

CDFG-560 Implementation selected for component instance.

CDFG-565 Linking to ChipWare library component instead of user module.

CDFG-738 Common subexpression eliminated.

CDFG-739 Common subexpression kept.

CDFG-740 Constant propagating graph.

CDFG-741 Tree height reduction on graph.




CDFG-742 Common subexpression elimination.

CDFG-743 Balancing Boolean functions.

CDFG-744 Constant indexed array optimizing.

CDFG-747 Balancing arithmetic functions.

CDFG-749 Arithmetic nodes found outside datapath partitions after initial partitioning. This may be due to incomplete graph cleanup. Creating partitions for these nodes.

CDFG-750 Created sum-of-products hierarchy.

CDFG-752 Enabling partial SOP-logic extraction.

CDFG-753 Transformed priority-encoded case to casex.

CDFG-754 Transformed if-else-if to priority-encoded case.

CDFG-755 Combined sum-of-products logic.

CDFG-757 Performing xz propagation on HDL design. Use 'set_attribute hdl_xz_propagation false /' to disable xz propagation (which has no effect on QOR).

CDFG-758 Detected an RTL macro. Replacing it with an equivalent internal representation.


CDFG-759 Detected an RTL macro for the conditional logic. Replacing it with an equivalent internal representation.


CDFG-768 Simplified the variable part select operation.

CDFG-771 Replaced logic with a constant value.

CDFG-772 Removed unused code identified during constant propagation.

CDFG-800 Statistics for case statements.

CDFG-815 Redundant conditional branches removed. There were some redundant branches as part of a conditional if-else-if or case statement which are removed.

CDFG-820 DesignWare instantiations are mapped to feature compatible ChipWare components, ChipWare components should be independently verified to meet design requirements.

Support for third-party components like DesignWare is provided for compatibility purposes. All supported third-party components are mapped to ChipWare components proprietary to Cadence. While the features and functions are compatible they cannot be guaranteed to be exactly implementation equivalent. It is your responsibility to verify if the specific Cadence implementation matches your requirements.




CDFG2G-110 Finished processing module. The processing of the referenced module is complete.

CDFG2G-210 Sum-of-products logic.

CDFG2G-616 Latch inferred. Use 'set_attribute hdl_error_on_latch true' to issue an error when a latch is inferred. Use 'set_attribute hdl_latch_keep_feedback true' to infer combinational logic rather than a latch when a variable is explicitly assigned to itself.

CDFG2G-624 Detected a RTL Macro Function represented as constant conditional logic.

CG-103 Created discrete clock-gating module. Two discrete clock-gating modules are created: one for the positive-edge triggered registers and one for the negative-edge triggered registers. The names of the clock-gating modules are based on the name of the design.

CG-210 Failed to insert observability logic. Use 'set_attr lp_clock_gating_add_obs_port true /designs/' to select clock-gating logic with observability logic. Insert clock-gating logic starting either from RTL or a netlist. Rerun the 'clock_gating insert_obs' command to insert observability logic.

CG-211 Skipped insertion of observability logic.

CG-214 No value was specified for the '-max_cg' option. The '-max_cg' option of the 'clock_gating insert_obs' command specifies the maximum number of clock-gating cells that can be observed per observability flip-flop. You can specify a number between 1 and 32.

CG-400 Removed a clock-gating instance.

CG-430 Retained a clock-gating instance.

CG-700 Could not insert dummy clock-gating logic. Set the lp_clock_gating_exclude attribute to false on the flop to insert dummy clock-gating logic.

CHECK_CWD-104 The permutable_group for the hdl_operator defined is set.

CHECK_CWD-121 Same pin of the component used in pin_association formula is associated with many pins of the operator.

CHECK_CWD-126 The hdl_operator output pin is associated with any output pin of the component.

CHECK_CWD-131 Bit_width attribute for the input pin is not set to empty.

CHLNK-201 Performing change_link. The instance would be linked to a new libcell or subdesign.




CHLNK-203 The instance of a non-uniquified module is being changed.

The same change will be copied to all the modules when the module is uniquified.

CHNM-102 Changed names successfully.

CPF-392 Overwrote one of the operating voltages in library set.

The specified library set had no library whose operating voltage corresponded to the voltage specified with the '-voltage' option of the 'create_nominal_condition' command. The 'read_cpf' command chose the operating voltage closest to the voltage specified in the CPF file and replaced it with that voltage.

CPF_ISO-109 No driver pin found in pin list given with '-enable_driver'. Selecting one of drivers of specified pins.

CPF_ISO-112 Isolation rule applied.

CPF_ISO-113 Port cloning turned off. Set variable ::lp_dont_clone_ports_for_insertion to 1 to turn this behavior ON.

CPF_ISO-117 Multiple isolation rules specified on a pin in cpf file.

CPF_ISO-201 Completed isolation cell insertion.

CPF_ISO-202 Completed level shifter insertion.

CPF_ISO-203 Isolation cell inserted.

CPF_ISO-204 Enabled level shifter inserted.

CPF_ISO-205 Level shifter inserted.

CPF_ISO-214 Global inversion not done.

CPF_ISO-215 Local inversion not done.

CPF_ISO-217 Global inversion done.

CPF_ISO-218 Local inversion done.

CPF_ISO-220 Skipping isolation / level shifter insertion.

CPF_ISO-221 Skipping isolation / level shifter insertion.

CPF_ISO-225 Optimization of isolation cell instances done.

CPF_ISO-226 Optimization of level shifter instances done.

CPF_ISO-227 Found an enabled level shifter as an appropriate isolation cell for insertion.

CPF_ISO-228 Global inversion not done on isolation control signal.

CPF_ISO-229 Local inversion not done on isolation control signal.




CPF_ISO-230 Global inversion done on isolation control signal.

CPF_ISO-231 Local inversion done on isolation control signal.

CPF_ISO-232 Multi driven pin is found. This pin will be skipped from low power cell insertion.

CPF_ISO-301 Completed assigning secondary domain to low power instances.

CPF_ISO-302 Secondary domain is assigned to the low power instance.

CPF_ISO-802 Rule removed from splitted port.

CPF_ISO-803 Buffer cannot be inserted for constant. LS/ISO insertion requires buffers to be inserted at constants.

CPF_ISO-804 Hierarchical instance not a valid hierarchical buffer instance.

CPF_ISO-805 No buffers found in library domain. LS/ISO might not be inserted at constants in this library domain.

CPF_ISO-806 Multiple level shifter rules applied on pin.

CPF_ISO-807 Multiple isolation rules applied on pin.

CPF_ISO-808 Duplicate isolation rules specified in cpf-file. Rule with higher sequence value will win.

CPF_ISO-809 Multiple isolation rules specified for same crossing in cpf-file.

This rule will win, since it is either more towards load or it is a more specific rule.

CPF_ISO-812 Port cloning performed.

CPF_ISO-820 Isolation cell import completed.

CPF_ISO-821 Level shifter import completed.

CPF_ISO-822 Instance imported as isolation cell.

CPF_ISO-823 Instance imported as level shifter cell.

CPF_ISO-901 ICG swapped with ICG-Retention.

CPF_ISO-904 ICG swapped with ICG-Isolation.

CPF_ISO-910 Uniquifying the multiple instantiated subdesign to prepare for pin/port cloning.

CPF_ISO-912 Uniquifying the multiple instantiated subdesign to prepare for LS/ISO insertion.

For inserting LS/ISO in hierarchy given with '-within_hierarchy', uniquifying the subdesign.

CPF_ISO-914 Timing exception is present on LS/ISO cell data pin driver path.

LS/ISO cells may not be merged due to this reason.

CPF_LS-809 Level shifter rule applied.

CPF_LS-810 Port cloning turned off. Set variable ::lp_dont_clone_ports_for_insertion to 1 to turn this behavior ON.




CPF_LS-814 Multiple level shifter rules specified on a pin in cpf file.

CPF_LS-816 Duplicate level shifter rules specified in cpf-file. Rule with higher sequence value will win.

CPF_LS-817 Multiple level shifter rules specified for same crossing in cpf-file.

This rule will win, since it is either more towards load or it is a more specific rule.

CTP-2 A clock source lies in the fan-out of another source.

CTP-9 A clock source is associated by more than one clock.

CTP-14 A reconvergent path exists, and all fan-out flops are common to all branches.

Clock skew estimates will be correct.

CTSTCH-2 Found unsupported keyword while parsing CTSTCH file.

The unsupported keyword will be ignored.

CWD-11 Library already exists.

CWD-19 An implementation was inferred.

CWD-21 Skipping an invalid binding for a subprogram call.

CWD-26 The output pin is unused.

CWD-29 The netlist for implementation was already built. The netlist for the implementation was previously built from its synthesis model for the specified set of parameter values.

CWD-36 Sorted the set of valid implementations for synthetic operator.

CWD-37 Actual speed grade differs from the expected speed grade.

CWD-46 Multiple components found with the same name.

DATABASE-100 Writing the database to a default file name. For a different name, specify a file name with -to_file option.

DATABASE-101 Reading the netlist of the given name. Use this name to refer to the design.

DATABASE-102 Deleting the existing design of this name. If an existing design is not to be overwritten, rename it prior to reading a database.

DATABASE-105 The database was successfully written. The database is now saved to the file.

DATABASE-111 While writing the database, attribute 'write_db_unresolved' to a subdesign was encountered.

Only parts of the design and no data besides the netlist will be written.

DATABASE-112 Ignoring file/row/column information. File/row/column is included in the database. Since root attribute 'hdl_track_filename_row_col' is set to 'false' it will not be restored.




DATABASE-113 While writing the database, certain data cannot be saved.

Avoid creating objects that cannot be saved and restored.

DATABASE-120 Current directory restored.

DEX-401 Removing existing exploration power domain. The existing exploration power domain was removed as another exploration power domain with same name was requested to be created.

DEX-402 Removing existing exploration run. The existing exploration run was removed as another exploration run with same name was requested to be created.

DEX-403 No reports to show. Add reports before querying for report.

DFM-201 No systematic probability defined. There is no defined systematic probability in the coefficient file.

DFT_GL-102 Skip the 'pll' clock related checks. In order to run 'pll' clock related checks specify the 'pll' instances.

DFT-100 Added DFT object.DFT-101 Moved/renamed DFT object.DFT-102 Removed DFT object.DFT-103 Changed attribute value. DFT changed some user-definable attribute.

DFT-118 Would remove DFT object.DFT-130 Created DFT port. A port for DFT purposes was created.

DFT-140 Identified pad hookup pin. A primary input/output port was specified as the driver/load of a DFT object; the tool determined the port to be connected to a pad and reported the hookup pin on the pad's core side.

DFT-151 Added scan chain.

DFT-163 Marking instance as dft_abstract_dont_scan as an abstract segment is being defined on it.

This is done to prevent flops (if present) within the instance from being scan synthesized.

DFT-164 Unmarking instance as dft_abstract_dont_scan as all abstract segments defined on it have been deleted.

This is done to allow flops (if present) within the instance to be scan synthesized.

DFT-182 No internal registers with fixed value outputs were found.

Ensure that the STIL file used by the 'identify_test_mode_registers' command has been updated with the required test-mode initialization sequence.




DFT-185 Did not find any shift-register segment in the design.

Shift registers are searched along the functional path. A shift register is considered a valid scan segment if the set, reset, and preset pins of all its flops are held at their inactive value and the enable pin is held to its active value. Ensure that test mode signals are specified for the synchronous pins of the flops in the shift register. Additionally, ensure that the '-min_length' and '-max_length' options have proper values, and that the design is not already scan-connected.

DFT-186 Identified a shift-register scan segment.

DFT-187 Would identify a shift-register scan segment.

DFT-220 Cannot unmap instance.

DFT-275 Propagating DFT constants. Will propagate the DFT constants and try to determine the hookup pin again.

DFT-276 Test clock defined during DFT constant propagation.

A test clock is auto-defined when the signal controls the enable port of a latch that is fed by a constant. To prevent auto-identification, define this port as a test signal before running this command OR set the design level attribute 'dft_identify_top_level_test_clocks' to false. The later will prevent any test_clock identification and so may not be the best choice.

DFT-303 Auto detection of Async control signal.

DFT-306 Rerun check_dft_rules. An operation has occurred that may cause previous Test Design Rule Check (TDRC) data to be invalidated. Examples of such operations are netlist changes, modification of test clocks or signals, etc. Rerun check_dft_rules.

DFT-501 Terminal lockup not needed. The terminal lockup element is not needed because the last element in the chain already is a lockup element, probably because the tail segment in the chain is a skew-safe segment.

DFT-502 Terminal lockup not needed for the current scan style.

Terminal lockup elements serve no purpose for the current scan style.

DFT-550 Scan mapping summary. A short summary of what happened during scan mapping.

DFT-564 Updated the scan chain.

DFT-569 Associating wrapper segment to port.

DFT-650 Identified test clock for dedicated wrapper cell. A test clock has been identified from the fanin/fanout analysis of the port.




DFT-653 Excluding port from wrapper cell insertion. Excluding this port from wrapper cell insertion, since user has specified to exclude it or it is a combinational feedthrough path and user has specified option '-exclude_comb_feedthrough_paths'.

DFT-715 Lockup element insertion is unnecessary for analyzed chain.

Insertion of lockup elements is unnecessary when (1)The the analyzed scan chain has no test clock domain transitions (2)It already has lockup elements inserted where the test clock domain transitions occur or (3)The scan style is not 'muxed_scan'.

DFT_GL-103 Skip the 'pll' reset pin related checks. In order to run the 'pll' reset pin related checks specify the 'pll' reset pin.

DFT_GUIDELINE-407 Test clock signal propagates to primary output port.

The endpoint of test signal is a primary output port, which may be effected during functional examination and not get the expected value .

DFT_GUIDELINE-408 Async clear and preset pins are driven by same source point.

As async clear and preset pins are driven by same source point, the output of flop became irregular if both the pins are active at same time.

DFT_GUIDELINE-409 The data pin of flop is driven by constant. Failure detection rate decreases as data pin of flop is tied to a constant ,so ensure that a constant should not propagate to data pin of flop..

DFT_GUIDELINE-410 Blackbox connected to the data pin. Detection of failure cannot be performed, as the data pin is driven by blackbox and failure detection rate decreases.

ECCD-414 Completed CCD execution. CCD ran successfully without any errors.

ELAB-1 Elaborating Design.

ELAB-2 Elaborating Subdesign.

ELAB-3 Done Elaborating Design.

ELAB-4 Error in Elaborating Design.

ELABUTL-128 Undriven module output port.

ELABUTL-129 Unconnected instance input port detected.

ELABUTL-130 Undriven signal detected.

ELABUTL-131 Undriven module input port.

ELABUTL-132 Unused instance port.

ENC-8 Encounter executable found. The specified Encounter executable will be used for the Encounter batch jobs.




ENC-13 The design has been changed by Encounter. The design was changed during QoS prediction. This may include netlist structural changes.

ENC-17 The following license was used for the Encounter session.

The specified license was used for the Encounter session. Use the enc_license_flag attribute to specify a particular license.

ENC-18 The following executable version was used for the Encounter session.

The specified Encounter version was used for the Encounter batch job.

ENC-21 An Encounter license will be checked out. A license will be checked out for the Encounter batch job. The license will be checked in when the job is finished.

ENC_MSV-301 Design has no library or power domains. No power domains will be created for Encounter.

GB-1 Doing context sensitive CSA optimization.

GB-2 Generating Booth encoder for Product-Of-Sum form.

GB-3 Doing super operator transformations.

GB-4 Doing conservative CSA transformations.

GB-6 A datapath component has been ungrouped.

GLO-12 Replacing a flip-flop with a logic constant 0. This optimization was enabled by the root attribute 'optimize_constant_0_flops'.

GLO-13 Replacing a flip-flop with a logic constant 1. This optimization was enabled by the root attribute 'optimize_constant_1_flops'.

GLO-14 Replacing a latch with a logic constant 0. This optimization was enabled by the root attribute 'optimize_constant_latches'.

GLO-15 Replacing a latch with a logic constant 1. This optimization was enabled by the root attribute 'optimize_constant_latches'.

GLO-16 Deleting a transparent latch. This optimization replaces a latch with a feedthrough.

GLO-17 Replacing a blocking latch with a logic constant 0.

The value used to replace the latch can be set by the root attribute 'optimize_seq_x_to'.

GLO-18 Replacing a blocking latch with a logic constant 1.

The value used to replace the latch can be set by the root attribute 'optimize_seq_x_to'.

GLO-19 Replacing a blocking latch with a dont care. The value used to replace the latch can be set by the root attribute 'optimize_seq_x_to'.

GLO-20 Replacing a blocking flip-flop with a dont care. The value used to replace the flop can be set by the root attribute 'optimize_seq_x_to'.

GLO-21 Replacing a blocking flip-flop with a logic constant 0.

The value used to replace the flop can be set by the root attribute 'optimize_seq_x_to'.




GLO-22 Replacing a blocking flip-flop with a logic constant 1.


GLO-23 Replacing a dont care flip-flop with a dont care. The value used to replace the flop can be set by the root attribute 'optimize_seq_x_to'.

GLO-24 Replacing a dont care flip-flop with a logic constant 0.


GLO-25 Replacing a dont care flip-flop with a logic constant 1.


GLO-30 Replaced instances of avoided library cells. To disable this replacement, set the 'preserve' attribute on the affected instance(s) or the instances' library cell, or remove the 'avoid' attribute on the instances' library cell.

GLO-31 Replaced instance of avoided library cell. To prevent this replacement, set the 'preserve' attribute to 'true' on the affected instance(s) or its library cell, or set the 'avoid' attribute to 'false' on the library cell of the instance.

GLO-32 Deleting instances not driving any primary outputs.

Optimizations such as constant propagation or redundancy removal could change the connections so an instance does not drive any primary outputs anymore. To see the list of deleted instances, set the 'information_level' attribute to 2 or above.

GLO-33 Found floating hierarchical output. To see the list of floating hierarchical instances, set the 'information_level' attribute to 2 or above.

GLO-40 Combinational hierarchical blocks with identical inputs have been merged.

This optimization usually reduces design area. To prevent merging of combinational hierarchical blocks, set the 'merge_combinational_hier_instances' root attribute to 'false' or the 'merge_combinational_hier_instance' instance attribute to 'false'.

GLO-41 Sequential hierarchical blocks with identical inputs have been merged.

This can be turned off with 'set cse_sequential_hier_instances 0'.

GLO-42 Equivalent sequential instances have been merged.

To prevent merging of sequential instances, set the 'optimize_merge_flops' and 'optimize_merge_latches' root attributes to 'false' or the 'optimize_merge_seq' instance attribute to 'false'.

GLO-43 Invert equivalent sequential instances have been merged.

To prevent merging of sequential instances, set the 'optimize_merge_flops' and 'optimize_merge_latches' root attributes to 'false' or the 'optimize_merge_seq' instance attribute to 'false'.




GLO-45 Replacing the synchronous part of an always feeding back flip-flop with a logic constant.

The value used to replace the flop can be set by the root attribute 'optimize_seq_x_to'. The assigned constant might also conflict with the simulation and/or verification setup.

GLO-51 Hierarchical instance automatically ungrouped. Hierarchical instances can be automatically ungrouped to allow for better area or timing optimization. You can control auto ungrouping using the root-level attribute 'auto_ungroup'. You can skip individual instances or modules using the attribute 'ungroup_ok'.

GSC-1 No pins specified.

GSC-2 No pins with general stitching code attributes found.

Found no pin with gsc_pin_function attributes.

HF-113 DEF file is not created for ILM. A floorplan is not read. So DEF file is not written for ILM. Load the floorplan using 'read_def'.

HF-114 File is not found for ILM. Check the path and filename again and check if the file exists.

HPT-78 Freeing module.

HPT-79 Undumping module.

INCRSYN-1 Preparing incremental synthesis.

INCRSYN-12 Finished creating incremental synthesis cache data.

ISO-102 Isolation rule defined.

ISO-103 Empty rule created. No valid pin(s)/port(s) for isolation rule definition available.

ISO-116 Could not define isolation rule.

ISO-117 No driver pin found in pin list given with '-enable_driver'. Selecting one of drivers of specified pins.

ISO-200 Completed isolation cell insertion.

ISO-208 Isolation cell not inserted. Isolation cells are inserted between two power domains, if one of them is OFF in at least one power mode.

ISO-214 Isolation cell inserted.

ISO-216 No cell found that is an isolation cell and level shifter.

The tool will try to synthesize the required isolation logic using available cells. Depending on whether it finds suitable cells, the tool may or may not insert isolation logic.

ISO-301 Could not use the library cell as isolation cell. Data pin of the cell is inverted.




ISO-403 Removed isolation logic.

ISO-501 Isolation cell inserted at dft port.

ISO-602 Found isolation cells inserted by other tools.

ISO-603 Isolation cell import completed.

ISO-604 Could not import as isolation cell.

ISO-605 Uniquifying the multiple instantiated subdesign to prepare for isolation cell import.

ISO-606 Hierarchical instance imported as isolation cell.

ISO-607 Subdesign imported as isolation cell module.

ISO-611 Skipping the current hierarchy from importing. Try using 'ui_respects_preserve' to false.

ISO-612 Uniquifying the multiple instantiated subdesign to prepare for isolation cell import.

LBR-1 Multiple objects with same name in library. The new object will overwrite the original one.LBR-3 Appending library. Appending libraries will overwrite some of the

characteristics of the library.

LBR-27 Replacing timing arc(s).LBR-30 Promoting a setup arc to recovery. Setup arcs to asynchronous input pins are not

supported.

LBR-31 Promoting a hold arc to removal. Hold arcs to asynchronous input pins are not supported.

LBR-40 An unsupported construct was detected in this library.

Check to see if this construct is really needed for synthesis. Many liberty constructs are not actually required.

LBR-41 An output library pin lacks a function attribute. If the remainder of this library cell's semantic checks are successful, it will be considered as a timing-model (because one of its outputs does not have a valid function.

LBR-42 Could not parse a library pin's function statement.

Check the pin's function statement in the library source.

LBR-46 Unsupported bus_type declaration. Attribute values should be integer.

LBR-47 Unsupported bus_type declaration. Non-bool value for bus_type attribute 'downto'.

Attribute value should be either 'true' or 'false'.

LBR-48 Unsupported bus_type declaration. 'bus_type' attribute 'bus_width' is less than 1.

LBR-49 Unsupported bus_type declaration.

LBR-54 Library has missing unit. Current library has missing unit.




LBR-70 Automatically disabling a borrow arc in a flip-flop.

The library cell was described as a flip-flop yet this timing arc appears to be intended for time-borrowing. Time borrowing is not supported in flip-flops.

LBR-71 Automatically disabling an unsupported borrow arc.

The library cell appears to be a latch, yet an arc was found between the D and Q pins that was not described as combinational. Only combinational arcs may be used for time-borrowing.

LBR-72 Detected an unsupported timing arc type. Refer to 'Supported Liberty timing_type Values' in 'Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler' for more information.

LBR-74 Disabling a setup/recovery arc. Setup/recovery arcs to output pins are not supported.

LBR-77 Automatically disabling a scan-only combinational arc.

The library cell is sequential and it has a combinational arc involving at least one pin that is only used in scan mode. You can enable such arcs by setting root-level attribute "ignore_scan_combinational_arcs" to false, but that will deem the cell unusable.

LBR-83 Found 'statetable' group in cell. Currently, state tables are only supported for scan cells for the clocked LSSD scan style and for clock-gating cells whose Liberty attribute 'clock_gating_integrated_cell' is set to 'generic'.

LBR-109 Set default library domain.

LBR-114 Overwrite previously defined pin function with user function.

LBR-118 Inverting the sense of a setup arc to be consistent with the launching clock edge.

In a flip-flop, the setup and clock -> q arcs must refer to the same clock edge. In a latch, they must refer to opposite clock edges. The technology library has an inconsistency in this respect.

LBR-119 Use model will change in future release. Operating condition is set before libraries were loaded. Future releases will require you to specify an object instead of a string. Consequently, you will only be able to set this attribute after you load libraries.

LBR-120 Removing libraries.

LBR-122 Automatically disabling an inconsistent clock edge arc.

The library description of this flip-flop or latch specified multiple clock edge arcs that are sensitive to different clock edges. A flip-flop or latch may only be sensitive to one clock edge.




LBR-123 Automatically disabling an unsupported timing arc.

The timing arc connects two pins that are already connected by a clock edge arc. Clock edge arcs cannot be mixed with non-clock-edge arcs in a flip-flop or latch.

LBR-149 Replaced unresolved instances with mapped instances.

The subdesigns with the same name as the library cells that were missing in the old library domain were removed.

LBR-155 Mismatch in unateness between 'timing_sense' attribute and the function.

The 'timing_sense' attribute will be respected.

LBR-160 Library-cells are not swappable. Check the number of input, output, and internal pins of the two library cells as well as the functions of the output pins.

LBR-161 Setting the maximum print count of this message to 10 if information_level is less than 9.

LBR-162 Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed.

Setting the 'timing_sense' to non_unate.

LBR-170 Ignoring specified timing sense. Timing sense should never be set with 'rising_edge' or 'falling_edge' timing type.

LBR-202 Invalid level shifter / isolation cell.

LBR-204 Undefined 'mode_definition' group.

LBR-209 Removed the existing level shifter group.

LBR-218 Level shifter cell is set to be avoided. To use the level shifter cell, the avoid attribute must be set to false.

LBR-409 Found conflicting clock polarity information. The tool derives the clock polarity from the sequential timing arcs specified through the Liberty 'timing_type' attribute. For the positive-edge triggered cells a positive value is expected for the 'clocked_on' or 'enable' attribute while an inverted value is expected for the negative-edge triggered sequential cells.

LBR-412 Created nominal operating condition. The nominal operating condition represents either the nominal PVT values if specified in the library source, or the default PVT values (1.0, 1.0, 1.0).

LBR-415 Found unusable library cells. For more information, refer to 'Cells Identified as Unusable' in the RC User Guide. The number of unusable cells that is listed depends on the setting of the 'information_level' root attribute. If set to a value less than 6, the list is limited to 10 unusable cells. If set to a value equal to or higher than 6, all unusable cells are listed.

LEX-3 Illegal size specification.




LIC-1 Limited access feature. Final production licensing of this limited access feature has not been determined and is subject to change. Usage and support of this limited access feature are subject to prior agreement with Cadence. In addition, Cadence assumes you understand the feature limitations and expected results. Contact your Cadence representative if you have any questions.

LIC-2 Beta feature. Final production licensing of this beta feature has not been determined and is subject to change. Usage and support of this beta feature are subject to prior agreement with Cadence. In addition, Cadence assumes you understand the feature limitations and expected results. Contact your Cadence representative if you have any questions.

LIC-10 License checkout request.

LIC-11 Preventing license checkout.

LS-100 Removed level shifter.

LS-106 Ignored instance for level shifter removal. The instance is neither a hierarchical level shifter instance nor its parent.

LS-110 Removed invalid level shifter hierarchy.

LS-201 Skipped level shifter insertion. Define level shifter cells between these domains. To define level shifters, use 'define_level_shifter_group' in non-CPF flow or 'define_level_shifter_cell' in CPF flow.

LS-207 Completed level shifter insertion.

LS-209 Ignore level shifter insertion from a library domain to another library domain with lower or same operating voltage.

LS-210 Uniquifying the multiple instantiated subdesign to prepare for level shifter insertion.

LS-220 Could not insert level shifter.

LS-221 Pin/Port has multiple domain load. Extra ports might be created for level shifter insertion.

LS-222 Insert level shifter using CPF specifications.

LS-223 No CPF commands for level shifter insertion can be found.

LS-233 One or more pin/port loads' power domain does not match with the power domain given with -to_power_domain option.

For more information on -from_power_domain option, consult 'level_shifter insert' in user guide.




LS-234 One or more pin/port drivers' power domain does not match with the power domain given with -from_power_domain option.

For more information on -from_power_domain option, consult 'level_shifter insert' in user guide.

LS-300 Merging level shifters.

LS-301 Newly merged level shifters.

LS-302 Merging level shifters from.

LS-303 Level shifters before merging.

LS-304 Level shifters after merging.

LS-501 Removing level shifter instance.

LS-502 Inserting level shifter instance.

LS-602 Found level shifters inserted by other tools.

LS-603 Level shifter import completed.

LS-604 Could not import level shifter.

LS-605 Uniquifying the multiple instantiated subdesign to prepare for level shifter import.

LS-606 Hierarchical instance imported as level shifter.

LS-607 Subdesign imported as level shifter module.

MAP-4 Non-standard use of global mapping. The results from the non-standard flow are not necessarily better or worse, but could just be different from the standard flow.

MAP-6 Unable to unmap a sequential cell with exceptions/attributes on the input pins.

MAP-7 Removing exceptions from a sequential cell while unmap.

MAP-9 Could not find pin or port.

MAP-10 You can reproduce this netlist by setting attribute 'stop_at_iopt_state' to the appropriate iopt state as follow:

MAP-15 Sequential phase inversion. This optimization was enabled by 'lbr_seq_in_out_phase_opto' root attribute.

MAP-24 Rerun of check_dft_rules may be needed. Multibit mapping has changed the previous Test Design Rule Check (TDRC) data as it ran check_dft_rules with default options.

MAP-25 Discrepancy between the mapper-timer and ian-timer has been detected.

This is a development only check and can be disabled by setting fatal_on_constraint_checking to '0'.




MAP-26 Cannot split the multibit cell. A multibit cell mapped to regular multibit library cell and having proper 1-bit replacement available in library can only be split.

MAP-29 Sequential phase inversion. This optimization was enabled by 'lbr_async_clr_pre_seq_interchangable' root attribute.

MAP-30 Attribute map_enhanced_parallelization is enabled.

MAP-127 Enabling some advanced optimizations in incremental optimization.

Enabling this attribute can potentially improve Qor and increase runtime.

MAP-128 Enabling some advanced optimizations in global mapping.

Enabling this attribute can potentially improve Qor and increase runtime.

MAP-130 Enabling TNS optimization for Parallel Incremental Optimization.

Parallel Incremental Optimization is executed in TNS mode to ensure consistency of QOR. Any comparison to single thread Incremental Optimization should be done in TNS mode only.

MAP-133 The create_timing_budgets command was successful.

Timing Budget Created.

MBIST-1 No memory cells to BIST. No target memory cells or instances provided in the configuration file.

MBIST-2 Module location is used multiple times. Module location for the target BIST engine is used multiple times and has multiple instances. All instances will be modified to insert the BIST engine. Verify that the indicated number of instances of a module agree with the expected value.

MBIST-3 Module location has a single instance. Module location for the target BIST engine has a single instance. Instance will be modified to insert the BIST engine.

MBIST-4 No JTAG attention pin found. No BIST engine inserted, thus no JTAG attention pin associated with the memory BIST engine found. Verify no BIST engines are to be inserted.

MBIST-5 No TDO pin found. No memory BIST engine inserted, thus no TDO pin associated with the memory BIST engine's scan chain found. Ensure no BIST engines are to be inserted.

MBIST-6 No TDI pin found. No memory BIST engine inserted, thus no TDI pin associated with the memory BIST engine's scan chain found. Ensure no BIST engines are to be inserted.

MBIST-7 System clock source net is found in module. Clock source net is used as a clock input to the associated target group's BIST engine(s).




MBIST-9 The synthesis phase of the processing completed.

Check the log file to verify no rules or assumptions are violated.

MBIST-10 Completed writing output netlist file. Check for any preceding Warning messages to ensure the file's format and contents are as intended.

MBIST-11 No functional net is connected to pin. Ensure no functional net is assumed to be connected.

MBIST-12 Input pin on memory instance is left unconnected.

Ensure the pin is required to be left unconnected.

MBIST-13 Input bus on memory instance is left unconnected.

Ensure the bus is required to be left unconnected.

MBIST-14 Writing output netlist of test macro to file.

MBIST-15 Deleting unconnected ports on program generated module.

MBIST-16 Synthesis/Timing completed successfully for module.

MBIST-17 Synthesis ran successfully for module.

MBIST-18 Directory was not found, creating directory.

MBIST-19 Checking the existence of file.

MBIST-20 Embedded test macro targeted to run at specified frequency.

MBIST-21 Memory Target and BIST Engine Summary.

MBIST-22 Memory Cell and Initial MBIST Status.

MBIST-23 Started MBIST insertion.

MBIST-24 MBIST inserted successfully.

MBIST-25 Started checking MBIST rules.

MBIST-26 Finished checking MBIST rules.

MBIST-27 Generation of the configuration file template completed.

Check for any preceding Warning messages to ensure the file's format and contents are as intended.

MBIST-28 Bitmap MBISTREAD TDR segment summary table.

MBIST-29 All the traversals will be done in a specific 'dft_configuration_mode'.

Verify that the attributes of this mode are correct.

MBIST-30 Interface files location used for checking MBIST rules is specified below.

Make sure that the interface files directory being used is correct.

MBIST-31 Memory cell pin usage status.

MBIST-32 MBIST area overhead summary table.




MBIST-33 MBIST area comparison table.

MBIST-34 No clock gating macros found in the design. Make sure that the clock gating logic exist in the design and re-run.

MBIST-35 Clock gating macros are replaced with clock gating integrated cell.

MBIST-36 MBIST scheduling summary table.

MBIST-37 MBIST scheduling summary table, power and test-time.

MBIST-38 Interface files location used for optimizing MBIST schedule is specified below.

Make sure that the interface files directory being used is correct.

MBIST-39 MBIST grouping summary table.

MBIST-40 MBIST grouping summary table, area and wire-length.

MBIST-53 Redundant interface files specified. No response required.

MBIST-54 Created temporary directory. No response required.

MBIST-55 The format of the input netlist file is assumed. Ensure the assumed HDL format is as expected.

MBIST-57 Black-box instance found. This instance will be ignored from the analysis.

MBIST-58 File with the same name already used. Generated file will have different name.

No response required.

MBIST-59 Gathering required information for the memory. No response required.

MBIST-61 Write enable pin will be treated as write enable mask for BIST purpose.

In case write enable mask pin is not present on a memory then the write enable pin is treated as write enable mask for BIST purpose. No action is required.

MBIST-93 Pin of a memory cell is tied to logic. Ensure the pin is tied to a required value.

MBIST-96 This is an informational message. For faster resolution of the issue, provide this information.

MESG-7 Message severity has been changed from default value.

MM_FE-50 No output directory has been specified. Creating the output directory using the design name appended with '_RC_FE_MM_PATH'.

MM_FE-51 FE path has been created.

MM_FE-53 File has been generated.

MM_FE-66 Not a Multi-Mode design. Default corner and mode will be created.

MSV_FE-50 FE path has been created.

MSV_FE-51 Identify the library domain for design top.




MSV_FE-52 No FE file name specified.

MSV_FE-54 All the files are created successfully.

MSV_FE-55 This library domain is for level shifter.

MSV_FE-56 No hierarchical instances found for library domain.

MSV_FE-57 No output directory has been specified. Creating the output directory using the design name appended with '_RC_FE_MSV_PATH'.

MSV_FE-59 Start to generating file.

MSV_FE-60 File has been generated.

MTDCL-12 An inverter and a 2-input gate found in library set.

MTDCL-14 Processing the instances on clock-path.

MTDCL-15 Preserved instance is skipped for replacement/remapping.

MTDCL-18 Ignoring clock for dedicated cell library mapping. The clock should have a valid library set defined in clock_library_cells attribute and a source pin/port to track clock-path.

MTDCL-19 Preview mode is enabled. No changes will be done to the design.

Keep information_level above 0 to get info about all the changes.

MTDCL-20 Library cell of instances on clock-path will be changed.

MTDCL-29 Successfully finished remapping the instances on clock-path.

MTDCL-30 Preview of remapping based clock-path optimization feature is not supported.

PA-6 Removed switching activities from nets driven by clock source.

Removed switching activities (user-asserted or computed) from all nets driven by this clock source, because the switching activities of a clock net are derived from the new (or latest) clock definition.

PA-7 Resetting power analysis results. All computed switching activities are removed.

PA-8 Set the toggle rate for the clock net to '0/ns'. The toggle rate is the number of toggles within a clock period. When the clock period is very large, the toggle rate is rounded to '0/ns'. To achieve better accuracy for power analysis, define the clock with a meaningful value for the period.




PA-10 Ignored clock redefinition for power analysis. A clock redefinition is ignored for power analysis when its associated clock net has user-asserted switching activity information. To apply the redefined clock for power analysis, remove the user-asserted switching activity information from the clock net, redefine the clock and then perform power analysis.

PA-18 Skipped building RTL power model for nonexistent instance.

Skipped modeling the hierarchical instance as it is dangle and has been removed during netlist clean-up.

PA-21 Ignoring this scope as it is outside the hierarchy which can be monitored.

If '-module' option is used in 'read_vcd', you can monitor scopes only which lie under the specified hierarchy.

PA-30 A power loop has been found. The power loop has been disabled for power analysis. This has no QoR impact.

PHYS-52 Physical information has been annotated. The physical information for the design has been prepared and annotated.

PHYS-53 Existing placement will be used. The current instance placement will be used for QoS prediction.

PHYS-63 Replay file created. The replay file contains a list of subcommands run by Encounter interface commands.

PHYS-90 Generating design database. The database contains all the files required to restore the design in the specified application.

PHYS-127 Macro with non-zero origin.

PHYS-129 Via with no resistance will have a value of '0.0' assigned.

PHYS-145 Inconsistent pin direction prevents conversion to pgpin.

Although the pin is considered a power or ground pin in LEF, to be converted to pgpin, the direction of the pin must be consistent in both lib and LEF libraries.

PHYS-146 Pin complexity prevents conversion to pgpin. Although the pin is considered a power or ground pin in LEF, it cannot be converted to pgpin because it either has timing arcs, is a bus or bundle member, is a retention pin, or has a function defined for an output pin in the lib.

PHYS-153 Creating toplevel port.

PHYS-154 Creating physical pin.

PHYS-160 Creating derived placement blockages for pre-routes.

PHYS-173 Reading hierarchical DEF for subdesign.

PHYS-174 Creating fence for hierarchical DEF.




PHYS-180 Placement blockage created for hierarchical DEF.

PHYS-181 Full preserve set on instance. This message has a default max print count of '10', which can be changed by setting the 'max_print' attribute.

PHYS-182 Cover component present.

PHYS-184 Incremental mode found existing component.

PHYS-185 Incremental mode found existing pin.

PHYS-186 Full preserve set on net. This message has a default max print count of '10', which can be changed by setting the 'max_print' attribute.

PHYS-188 Preserve with sizing allowed set on instance.

PHYS-215 Power switch cell present.

PHYS-216 Skipping GCELLGRID statement.

PHYS-218 Connecting power switch cell nets.

PHYS-223 Placed component changed to fixed. Placed components with libcell not class CORE are changed to fixed.

PHYS-230 Creating physical power domain.

PHYS-358 Unconnected port found. A port with no net connected has been found. The net name is assumed to be the same as the port name.

PHYS-362 SPECIALNETS section skipped during write_def.

SPECIALNETS section is skipped during write_def if input DEF is read using the -no_specialnets option or the attribute phys_ignore_special_nets is set to true.

PHYS-364 NETS section skipped during write_def. NETS section is skipped during write_def if input DEF is read using the -no_nets option or the attribute phys_ignore_nets is set to true.

PHYS-383 Loading library and cap-tables according to the worst_corner specified by the user.

Loading library and cap-tables according to the worst_corner specified by the user as opposed to loading library and cap-tables from config file.

PHYS-398 Restoration Complete. Finished Restoration.

PHYS-399 Found cap-table file. Found cap-table file in view definition.

PHYS-400 View definition file does not exist in encounter db.

View definition does not exist in the encounter database.

PHYS-401 Mode file not present. Mode file is not present in encounter db, mode information will not be passed on to FE.

PHYS-402 Loaded config file. Successfully loaded config file into RC.




PHYS-403 Checking for avoided libcells in netlist. Checking for avoided libcells in netlist.

PHYS-404 No avoided libcells present in netlist. There are no libcells in the netlist which have avoid=true.

PHYS-405 Avoided libcells present in netlist. There are libcells in the netlist which have avoid=true.

PHYS-406 Skipping virtual clock. Skipping virtual clock for preserving clock-source pin.

PHYS-407 Done preserving clock network/pins. Finished preserving all the clock-pins, except virtual clocks.

PHYS-408 Done preserving sdc-gates. Finished preserving all the gates that appear in the sdc.

PHYS-410 Using user specified DEF file. The DEF file specified by the user will take precedence over the one present in the database.

PHYS-414 No timing_derate information found in view definition file for specified worst-corner.

Derate information could not be found the worst-corner in the view definition file.

PHYS-419 Using constraint files specified in view definition file.

The constraint files corresponding to the specified analysis view will be used.

PHYS-420 The original location attributes have been populated.

The original location attributes have been populated.

PHYS-421 Location statistics. Printing instance location related statistics.

PHYS-422 Highlight statistics. Printing movement highlight statistics.

PHYS-423 No design loaded, cannot compute row height. Since there was no design loaded, row height could not be computed.

PHYS-424 Multiple designs loaded, cannot compute row height.

Since there is more than one design loaded, row height could not be computed.

PHYS-425 Could not compute row height. Row height could not be computed from the row attribute.

PHYS-431 Using delay-corner corresponding to specified analysis mode.

The delay-corner corresponding to specified analysis mode will be used.

PHYS-432 Timing derate sdc file found. The timing derate sdc file was found in the saved database.

PHYS-434 Timing derate sdc file not found. The timing derate sdc file was not found in the saved database.

PHYS-435 Operating condition was not set. The operating condition was not set because of the above reasons.

PHYS-437 Found operating conditions in view definition file. Found the above operating conditions corresponding to the specified corner.




PHYS-438 Could not find operating conditions in the view definition file.

Could not find the operating conditions corresponding to the specified corner for the above reasons.

PHYS-439 Set the operating conditions from the view definition file.

Operating conditions set according the view definition file.

PHYS-440 The design being restored is a CPF design. The design being restored is a CPF design.

PHYS-444 Found QRC tech file. Found QRC tech file in view definition.

PHYS-604 It is recommended to provide average RC file from encounter.

The Average RC file is not provided using option "-average_rc_file". Already available per unit capacitance and resistance information is being used.

PLC-1 Placement Information.

PMBIST-16 Synthesis/Timing completed successfully for module.

PMBIST-17 Synthesis ran successfully for module.

PMBIST-18 Directory was not found, creating directory. Creating the specified directory for storing the generated output.

PMBIST-20 Embedded test macro targeted to run at specified frequency.

PMBIST-21 Memory Target and programmable MBIST Engine Summary.

PMBIST-23 Started programmable MBIST insertion.

PMBIST-24 Programmable MBIST inserted successfully.

PMBIST-27 Generation of the configuration file template completed.

Check for any preceding warning messages to ensure the file's format and contents are as intended.

PMBIST-28 Generation of the view file template completed. Check for any preceding warning/error messages to ensure the file's format and contents are as intended.

PMBIST-29 All the traversals will be done in a specific 'dft_configuration_mode'.

Verify that the attributes of this mode are correct.

PMBIST-30 No test signals present. All the traversals will be done in the functional mode.

Verify that the mode is correct.

PMBIST-31 Memory cell pin usage status.

PMBIST-32 PMBIST area overhead summary table.

PMBIST-33 PMBIST area comparison table.

PMBIST-41 Summary table for 'read_memory_view'.

PMBIST-42 Summary table for 'algorithm constraints'.




PMBIST-43 Freeing existing interface files in memory.

PMBIST-53 Redundant interface files specified. No response required.

PMBIST-54 Created temporary directory. No response required.

PMBIST-55 The format of the input netlist file is assumed. Ensure the assumed HDL format is as expected.

PMBIST-57 Black-box instance found. This instance will be ignored from the analysis.

PMBIST-58 File with the same name already used. Generated file will have different name.

No response required.

PMBIST-59 Gathering required information for the memory. No response required.

PMBIST-61 Write enable pin will be treated as write enable mask for BIST purpose.

In case write enable mask pin is not present on a memory then the write enable pin is treated as write enable mask for BIST purpose. No action is required.

PMBIST-93 Pin of a memory cell is tied to logic. Ensure the pin is tied to a required value.

PMBIST-96 This is an informational message. For faster resolution of the issue, provide this information.

POPT-10 Cannot find requested type of clock-gating integrated cell.

POPT-11 Found user created clock-gating module.

POPT-12 Could not find any user created clock-gating module.

Looking for Integrated clock-gating cell in library.

POPT-13 User defined clock-gating module is not complete.

Make sure the module has all ports defined according to the manual.

POPT-17 The user specified clock-gating integrated cell will override the 'lp_clock_gating_control_point' and 'lp_clock_gating_style' settings.

POPT-22 Ignore the setting for automatically generating test control port for clock-gating because the user specified test signal exists.

POPT-25 CG instance drives dft_dont_scan flops.

POPT-27 Ignore the flip-flop for clock gating because its synchronous pin is always enabled.

POPT-28 Ignore the flip-flop for clock gating because it has multiple synchronous inputs.

POPT-29 Driver of the scan enable pin does not match the scan signal defined by lp_clock_gating_test_signal attribute. Treat the scan pin as a regular synchronous enable signal for clock gating insertion purpose.

POPT-30 MUX is deleted after clock gating logic inserted.




POPT-34 Could not include pin in clock-gating enable logic.

Make sure the instance or module in which the pin resides is not preserved.

POPT-35 Could not insert clock-gating for flip-flop. Make sure the logic which enables the feedback loop is not preserved.

POPT-50 Could not declone clock-gating instances. Reset the 'lp_clock_gating_max_flops' attribute to a bigger number and re-run the command.

POPT-51 Could not declone clock-gating instances. The design should have 2 or more clock-gating instances for decloning.

POPT-52 Clock-gating instance will not be considered for declone.

Make sure the 'preserve' attribute is set to 'false' on the clock-gating instance.

POPT-53 Clock-gating instance cannot be considered for decloning.

Make sure the logic gates inside the clock-gating module either have the correct library cell attribute to be identified as clock-gating logic, or implement a correct clock-gating function.

POPT-61 Splitted the enable function of a clock-gating instance.

The complex enable function of a clock-gating instance is decomposed into multiple smaller enable function and the original clock-gating instance is converted into a set of multi-stage clock-gating instances.

POPT-62 Merged the enable functions of two clock-gating instances.

The enable function of a root level clock-gating instance is merged with the enable function of a leaf level clock gating instance. The original multi-stage clock gating is converted into a regular clock gating.

POPT-63 Clock-gating instance cannot be considered for splitting.

Make sure the clock gating instance, the nets connected to the clock pin and enable pin of the clock gating logic and the driving logic for the enable pin are not preserved.



A clock-gating instance is splittable only if its enable logic is driven by a single output combinational gate.

POPT-66 Clock-gating instance is not splittable. The enable logic of the clock gating instance cannot be decomposed.

POPT-67 Clock-gating instance cannot be considered for joining.

Make sure the clock gating instance and the nets connected to the clock pin and enable pin of the clock gating logic are not preserved.




POPT-68 Clock-gating instance cannot be considered for joining.

A clock-gating instance with synchronous set logic cannot be considered for joining because there is no way to create the new enable logic without change the logic inside the clock gating hierarchy. A clock-gating whose enable pin is multiply driven is also ignored for joining.

POPT-69 Clock-gating instances cannot be considered for joining.

Only those clock-gating instances, which have the same test pin drivers and lp_clock_gating_test_signal settings, can be considered for joining.

POPT-71 The clock gating instance is violating the 'lp_clock_gating_min_flops' constraint.

Either the 'lp_clock_gating_min_flops' constraint value was changed or the driven flops were optimized. If the clock gating instance is not preserved it might be removed.

POPT-83 Inserted a shared clock-gating instance. Shared clock-gating logic is inserted for enable function shared by clock-gating logic in the design.

POPT-92 A potential clock gating enable was not considered due to the presence of timing exceptions.

Clock gating timing exception awareness can be disabled with the 'lp_clock_gating_exceptions_aware' attribute.

POPT-96 One or more cost groups were automatically created for clock gate enable paths.

This feature can be disabled by setting the attribute lp_clock_gating_auto_cost_grouping false.

POPT-201 Signal width is too small. Signals of bitwidth lesser than 8 are not considered for Operand Isolation.

POPT-204 Nothing to do in Operand Isolation.

POPT-205 Candidates found for Operand Isolation.

POPT-207 Committing Operand Isolation instance.

POPT-208 Decommitting (deleting) operand isolation instance.

POPT-500 Make sure 'max_leakage_power' is set to enable leakage power optimization.

Set 'max_leakage_power' before optimization.

POPT-510 Could not connect a power gating pin of a state retention instance.

Specify an appropriate driver in state retention rule in CPF file to make connections.

POPT-511 No usable cells in the libraries loaded has the 'power_gating_cell' attribute setting.

Load a library which has 'power_gating_cell' attribute as 'true' on cells which are intended to be used as state retention cells.

POPT-513 Could not find an always on buffer in the library to feed the driver for this instance.

Load a proper library which contains always on buffer cells or set the 'is_always_on' attribute on buffer cells for them to get selected.

POPT-514 Cannot find a matching state retention cell for the flip-flop.

Provide a complete state retention library with a matching flip-flop for each regular flip-flop.




POPT-515 Preserve the instance of the power gating pin driver.

POPT-525 Cannot detect a single state retention cell which can be used for mapping.

Provide a proper state retention library with cells usable as state retention cells.

POPT-536 Library pin phase mismatch detected while swapping to an state retention cell.

Ensure that library cells with similar pin phases are used for swapping state retention flops.

POPT-539 Could not find an always on inverter in the library to feed the driver for this instance.

Load a proper library which contains always on inverter cells or set the 'is_always_on' attribute on inverter cells for them to get selected.

POPT-541 No state retention cell with a matching functional class as that of the flip-flop being replaced was found.

Both the normal and state retention cells should have a common functional class for the state retention cell to be considered as a candidate for replacing the normal flip-flop.

POPT-542 The state retention library cell is not suitable to replace the current library cell attached to the flip-flop.

The state retention library cell must have been provided either with the 'lp_map_to_srpg_cells' attribute or the 'state_retention define_map' command. Provide a proper state retention library cell for effective replacement of the cell attached to the flip-flop.

POPT-543 The state retention library cell does not have an input pin corresponding to the normal library cell it is trying to replace.

The state retention cell which has an equal number of input pins as that of the normal flip-flop will be used for replacement. Provide a state retention cell with equal number of input pins as that of the normal flip-flop.

POPT-544 The state retention library cell does not have an output pin corresponding to the normal library cell it is trying to replace.

The state retention cell which has an equal number of output pins as that of the normal flip-flop will be used for replacement. Provide a state retention cell with equal number of output pins as that of the normal flip-flop.

POPT-557 The '-vcd_module' option has not been specified with the 'read_vcd' command.

The first scope encountered in the VCD file has been selected for processing. This may result in lesser coverage if the selected scope does not match up to the design hierarchy to be annotated. To get better coverage, provide the VCD scope name with the '-vcd_module' option.

POPT-558 The object could not be found under the specified hierarchy.

This happens if the hierarchy specified with the '-vcd_module' option lies more than one level below the top level hierarchy or the hierarchy specified with the '-module' option. Adjust the specifications for the '-vcd_module' and the '-module' options to avoid this scenario.




POPT-559 Multiple objects were found under the specified hierarchy.

This happens if the hierarchy specified with the '-vcd_module' option is not unique under the top level hierarchy or the hierarchy specified with the '-module' option. Adjust the specifications for the '-vcd_module' and the '-module' options to avoid this scenario.

POPT-560 The name of the generated SST2 database will have the VCD filename as its prefix as the '-write_sst2' option has not been specified.

You have specified either the '-activity_profile' or the '-dynamic' option. To automatically load the SST2 database in the waveform viewer, you need to provide the '-simvision' option. To have your own named SST2 database, you need to use the '-write_sst2' option.

POPT-600 Could not dedicate subdesign of instance. Make sure the subdesign is not preserved.

PTAM-1 Performing setup for insert_dft ptam. Creating temporary work area, and synthesizing modules that will be used internally during insertion.

PTAM-2 Collecting isolation rule information.

PTAM-3 No isolation rules found.

PTAM-4 Collecting information about the lp_srpg_pg enable signals.

The lp_srpg_pg_driver attributes on the sequential instances in the design are used to gather information about the lp_srpg_pg enable signals.

PTAM-5 No sequential elements found in the design.

PTAM-6 Collecting information about all of the power domains.

PTAM-7 No power domains found.

PTAM-8 Shutoff signal not found for power domain.

PTAM-9 Power Mode / Power Domain Summary.

PTAM-10 Verifying the pin connections. Ensuring that pins specified on the command line are accessible for connections.

PTAM-11 Pin not specified. A pin was not specified on the command line, using default pin name.

PTAM-12 Marking required pins with general stitching code attributes.

PTAM-13 Identifying logical controls. Logical controls required to control each power_control signal are identified.

PTAM-14 Multiple enable signals found for power domain. Logic consisting of OR gates will be created for these enable signals.

PTAM-15 Inserting the test power control blocks. Inserting test power control blocks for the power switch enable signals.

PTAM-16 Mux inserted for power domain.




PTAM-17 Block ptam_shift_logic_pse_block inserted for power domain.

PTAM-18 Applying general stitching code attributes for ptam_shift_logic_pse blocks.

PTAM-19 Inserting the test power control blocks. Inserting test power control blocks for the isolation control enable signals.

PTAM-20 Multiple enable signals found for isolation rule. Logic consisting of AND gates will be created for these enable signals.

PTAM-21 Block ptam_logic_pse_block inserted for isolation rule.

PTAM-22 Inserting the test power control blocks. Inserting test power control blocks for the lp_srpg_pg driver signals.

PTAM-23 Multiple enable signals found for lp_srpg_pg driver.

Logic consisting of AND gates will be created for these enable signals.

PTAM-24 Block ptam_shift_logic_pc_block inserted for lp_srpg_pg driver.

PTAM-25 Creating test mode files. Using write_atpg -cadence to generate the base assign file. Additional power test access method flags are appended to this file.

PTAM-26 Creating assign file for power mode.

PTAM-27 Command insert_dft ptam started.

PTAM-28 Creating sequence file for power mode.

PTAM-29 Power Domain / Shutoff Signal Summary.

PTAM-30 Isolation Rule Summary.

PTAM-31 Block lp_srpg_pg Summary.

PTAM-32 No I/O cell present for port. Connections will made directory to the port.

PTAM-33 I/O cell found for port. Connections will be made to the pad pin.

PTAM-34 Port found for pin. The specified pin was traced to the port. This port will be used in the generated sequence file.

PTAM-35 JTAG module found.

PTAM-36 Single enable signal found for power domain.

PTAM-37 Location for power mode shutoff signal found. The location for the power mode shutoff signal for the power domain has been determined.

PTAM-38 Location for isolation control enable signal determined.

PTAM-39 Single power domain found for isolation rule.

PTAM-40 Location for lp_srpg_pg driver signal determined.




PTAM-41 Single power domain found for lp_srpg_pg driver.

PTAM-42 Directory created.

PTAM-43 Reading Verilog file.

PTAM-44 Elaborating entity.

PTAM-45 Synthesizing design.

PTAM-46 Executing general stitching code. The general stitching code will use the following general stitching code attributes to make the connections for the various power control logic: gsc_pin_function, gsc_pin_type, gsc_pin_polarity.

PTAM-47 Tracing JTAG pin on JTAG module. Traced pin on the JTAG module back to a port.

PTAM-48 Control block summary. Position 0 is closest to final output.

PTAM-49 Insertion of power test access method logic complete.

PTAM-50 Preview of power test access method logic complete. No modifications have been made to the netlist.

PTAM-51 Insertion of power test access method logic did not complete successfully.

PTAM-52 Updated the length of the instruction.

PTAM-53 No power modes found.

RETIME-112 Retiming timing-critical design for area. Use min_delay option to retime for improved delay.

RETIME-113 Retimed asynchronous reset behavior could not be preserved without negatively impacting timing.

Inserting gates for explicit reset and redoing retiming. Disable with retime_fallback_to_explicit_reset root-level attribute.

RETIME-114 Retiming cannot be done on preserved designs/subdesigns.

Change the preserve setting if the design/subdesign should be retimed.

RETIME-501 Categorized flops into classes. Only flops in the same class can merge during a retiming move.

RETIME-601 Unable to perform incremental retiming due to following reason.

Refer to RC documentation for further details.

RETIME-701 Retiming modules are combinational connected. This might limit parallel processing.

RETIME-702 Retiming modules are combinational connected through as cycle.

This might limit parallel processing.




RMSENA-10 Inserted synchronous enable has flops in its transitive fanout.

Valid inserted synchronous enable signal should be an output pin of a hierarchical instance, should not be driven by constant, should not be unconnected and should have at least one flop in its transitive fanout.

RMSENA-11 Removed inserted synchronous enable. Inserted synchronous enable is removed because it was found to be timing critical.

RMSENA-12 Removed inserted synchronous enable. Inserted synchronous enable is removed because the command 'remove_inserted_sync_enable_logic' was issued with '-all' option.

RMSENA-13 Could not find any inserted synchronous enable in the design.

Load a design with inserted synchronous enable.

RMSENA-14 Could not find a valid inserted synchronous enable in the design.

Valid inserted synchronous enable signal should be an output pin of a hierarchical instance, should not be driven by constant, should not be unconnected and should have at least one flop in its transitive fanout.

RMSENA-15 Found valid inserted synchronous enables. Valid inserted synchronous enable signal should be an output pin of a hierarchical instance, should not be driven by constant, should not be unconnected and should have at least one flop in its transitive fanout.

RMSENA-16 Could not find any timing critical inserted synchronous enable in the design.

Timing is either met for all inserted synchronous enables or no timing constraints are set for the design.

RMSENA-17 Found critical inserted synchronous enables. Critical synchronous enables have negative slack.

RPT-7 Time taken to report power.

RPT-11 Detected inconsistency between voltage of library and voltage from nominal_condition in CPF.

The voltage specified in the library of power domain does not match with the voltage specified in CPF file. Using the voltage specified in library.

RPT-22 Nothing to report. There is no more help available in this message. If the help in this message was insufficient, contact customer support with this message ID.

RPT-34 HDL cross referencing is not enabled. Set the 'hdl_track_filename_row_col' root attribute to 'true' before 'elaborate' to enable HDL cross referencing. HDL cross referencing is supported until 'synthesize -to_generic'.

RPT-42 No power mode specified. The design has power modes and 'report power' is used without '-power_mode' option. Without the option '-power_mode', power is reported for the current state the design is in.




RTLOPT-10 Performing RTL speculation.

RTLOPT-15 Performing RTL shannon expansion.

RTLOPT-16 Performing pre-map downsize.

RTLOPT-17 Performing conservative CSA.

RTLOPT-20 Done carrysave optimization.

RTLOPT-21 Found netlist enhancement opportunities for better CSA.

RTLOPT-22 Found carry save over truncation-extension.

RTLOPT-29 Tried to perform RTL resource sharing; but finally rejected.

RTLOPT-30 Performing RTL resource sharing.

RTLOPT-40 Applied datapath macro transformation.

RTLOPT-42 Exploring sop box alternatives.

SDC-300 Entering sdc_shell. All sdc commands will work without the dc:: prefix inside sdc_shell. Type 'exit' to leave the shell.

SDC-301 Leaving sdc_shell. Type sdc_shell to use it again.

ST-110 Connection established with super-threading server.

RC is entering super-threading mode and has established a connection with a CPU server process. This is enabled by the root attributes 'super_thread_servers' or 'auto_super_thread'.

ST-112 A super-threading server has been shut down normally.

A super-threaded optimization is complete and a CPU server was successfully shut down.

ST-120 Attempting to launch a super-threading server. RC is entering super-threading mode and is launching a CPU server process. This is enabled by the root attribute 'super_thread_servers' or 'auto_super_thread'.

ST-121 Automatically enabling super-threading. RC is entering super-threading mode because it is running on a multi-processor machine. Two super-thread servers will be running on 'localhost' and no super-thread licenses will be checked out. This is enabled by the root attribute 'auto_super_thread'.

ST-1

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