Gloss ary

AAccept operation. Operation on a mailbox that is similar to the pend operation, except

that if no clata are available, the task retums immediately from the call with a condition

code rather than susPending.

Access time. The interval between when data are requested from the memory cell and

when they are actually available.

Accumulator. An anonymous register used in certain computer instructions.

Activity packet. A special token passed between the processors in a dataflow

architecture. Each token contains an opcode, operand count, operands, and a list of

destination addresses for the result of the computation.

Actual parameter. The named variable passed to a procedure or subroutine.

Address bus. The collection of wires needed to access individual memory addresses'

Alpha testing. A type ofvalidation consisting ofinternal distribution and exercise ofthe

software.

ALU. See arithmetic logic unit'

Anatog-to-digital conversion. The process of converting continuous (analog; signals

into discrete (digital) ones.

Anonymous variable. A hidden variable created by the compiler to facilitate call-by-

value parameter passing.

Application programs" Programs users write to solve specific problems.

Arithmetic logic unit. The CPU intemal device that performs arithmetic and logical

operations.

Assemblers. Software that translates assembly language to machine code.

Assembly language. The set of symbolic equivalents to the macroinstruction set.

327

328

Associative memory.contents.

Asynchronous event.

Atomic instruction.

I Glossary

Memory organized so that it can be searched according to its

An event that is not synchronous.

An instruction that cannot be intenupted.

BBackground. Non-interrupt driven processes in foreground/background systems.

BAM. See binary angular measurement.

Banker's algorithm. A technique sometimes used to prevent deadlock situations.

Bathtub curve. A graph describing the phenomenon that in hardware components most

errors occur either very early or very late in the life of the component. Some believe

that it is applicable to software.

Belady's Anomaly. The observation that in the FIFO page replacement rule, increasing

the number of pages in memory may not reduce the number of page faults.

Beta testing. A type of system test where preliminary versions of validated software are

distributed to friendly customers who test the software under actual use.

Binary angular measurement. An n-bit scaled number where the least significant bit

is 2"- ' .180.

Binary semaphore. A semaphore that can take on one of two values.

Binary tree. A collection of n nodes, one of which is a special one called the root. The

remaining n - 1 nodes form at most two subtrees.

Black box testing. A testing methodology where only the inputs and outputs of the unit

are considered. How the outputs are generated inside the unit is ignored.

Blocked. The condition experienced by tasks that are waiting for the occurrence of an

event.

Broadcast communication. In statecharts, a technique that allows for transitions to

occur in more than one orthogonal system simultaneously.

Buffer. A temporary data storage area used to interface between, for example, a fa^st

device and a slower process servicing that device.

Burn-in testing. Testing that seeks to flush out those failures that appear early in the life

of the part and thus improve the reliability of the delivered product.

Burst period. The time over which data are being passed into a buffer.

Bus arbitration. The process of ensuring that only one device at a time can place data

on the bus.

Bus contention. Condition in which two or more devices attempt to gain control of the

main memory bus simultaneously. - --

Bus cycle. Memory fetch.

Bus grant. A signal provided by the DMA controller to a device indicating that it has

exclusive rights to the bus.

Bus time-out. A condition whereby a device making a DMA request does not receive

a bus grant before some specified time.

Busy wait. In polled loop systems, the process of testing the flag without success.

I Glossary 329

CCall-by-address. See call-by-reference.

Call-by-reference. The process in which the address of the parameter is passed by thecalling routine to the called procedure so that it can be altered there.

Call-by-value. Parameter passing method in which the value of the actual paramerer inthe subroutine or function call is copied into the procedure's formal parameter.

Calling trees. See structure chart.CASE. Computer-aded software engineering.Catastrophic error. An error that renders the svstem useless.CCR See condition code register.

Cellular automata. A computational paradigm for an efficient description of SIMDmassively parallel systems.

Chain reaction. In statecharts, a group of sequential events where the nth event istriggered by the (n - l)th event.

Checkpoints. 'Code

that outputs intermediate results to allow an external Drocess tomonitor the efficacy of the process in questron-

Checksum. A simple binary addition of all program code memory locations used roverify the contents.

Circular queu€. See ring buffer.

CISC. See complex instruction set computer.

Class definitions. Object declarations along with the methods associated with thern.Clear box testing. See white box testing.

Code inspection. See group walkthrough.

Collision. Condition in which a device already has control of the bus and anotherobtains access. Also, simultaneous use of a critical resource.

C-ompaction. The process of compressing fragmented memory so that it is no lon-eerfragmented. Also called coalescing.

Compiler. Software rhat translares high-order language programs into assembll, codeComplex instruction set computers. Architectures characterized bv a larse. micrr.-

coded instruetion set with numerous addressing modes.Composition. An operation applied to a reliability matrix that determines the marin-iuir

reliability between processors.

Compute-bound. Computations in which the number of operations is laree in ;,r:---parison to the number of I/O instructions.

Condition code register. Intemal CPU register used to implemenr a .Lrr.,i::1.-:.;.transfer.

Conditional transfer. A change of the program counter based on the resuk .ri : !3>:Content.addressable memory. See associatrve memory.context. The minimum information that is needed in order to sa'e a curienrlr .\e.-urrns

task so that it can be resumed.

Context switching. The process of saving and restorine suft-rcient information for areal-time task so that it can be resumed after beins intem-rpred.

330 I Glossary

Continguous firle allocation. The process of forcing all allocated file sectors to follow

one another on the disk.

iontinuous random variable. A random variable with a continuous sample space.

Control flow diagram. A real-time extension to dataflow diagrams that shows the flow

of control signals through the system.

Control specifications. In dataflow diagrams, a finite state automaton in diagrammatic

and tabular representation.

Control unit. CPU internal device that synchronizes the fetch-execute cycle.

Cooperative multitasking system. A scheme in which two or more processes are

divided into states or phases, determined by a finite state automaton. Calls to a central

dispatcher are made after each phase is complete.

Coprocessor. A second specialized CPU used to extend the macroinstruction set.

Coroutine system. See cooperative multitasking system.

Correlated data. See time-relative data.

Counting semaphore. A semaphore that can take on two or more values.

CPU. Central processing unit.

CRC. See cyclic redundancY code.

Critical region. Code that interacts with a serially reusable resource.

CU. See control unit.

Cycle stealing. A situation in which DMA access precludes the CPU from accessing the

bus.

Cyclic redundancy code. A method for checking ROM memory that is superior to

checksum. See Chapter 11.

Cycling. The process whereby all tasks are being appropriately scheduled (although no

actual processing is occurring).

cyciomatic complexity. A measure of a system reliability devised by McCabe.

DDaemon. A device server that does not run explicitly but rather lies dormant waiting for

some condition(s) to occur.

Dangerous allocation. Any memory allocation that can preplude system determi-

nrsm.

Data bus. Bus used to carry data between the various components in the system.

Dataflow architectures. A multiprocessing system that uses a large number of speciai

processors, and computation is performed by passing activiti packs between them.

Dataflow diagrams. A structured analysis tool for modeling software systems.

Dead code. See unreachable code.

Deadlock. A catastrophic situation that can arise when tasks are cornpeting for the sarne

set of two or more serially reusable resources.

Deadly embrace. See deadlock.

Death spiral. Stack overflow caused by repeated spurious interrupts.

Decode. The process of isolating the opcodeTield of a macroinstruction and determin-:ne

the address in micromemory of the programming corresponding to it'

I Glossary 33r

Defect. The preferred term for an error in requirement, design, or code. See also fault,

failure.

Demand page system. Technique where program segments are permitted to be loaded

in noncontiguous memory as they are requested in fixed-size chunks.

Density. In computer memory, the number of bits per unit area.

De-referencing. The process in which the actual locations of the parameters that are

passed using call-by-value are determined'

Derivative of f at x. Represents the slope of the function / at point x.

Deterministic system. A system where for each possible state. and each Set of inputs,

a unique set of outputs and next state of the system can be determined.

Digital-to-analog conversion. The process of converting discrete (digital) signals into

continuous (analog) ones.

Direct memory access. A scheme in which access to the computer's memory is

afforded to other devices in the system without the intervcntion of the CPU'

Direct mode instruction. Instruction in which the operand is the data contained at the

address specified in the address field of the instruction.

Discrete random variable. A random variable drawn from a discrete sample space.

Discrete signals. Logic lines used to control devices.

Dispatcher. The part of the kernel that performs the necessary bookkeeping to start 3

task.

Distributed real.time systems. A collection of interconnected self-contained pro-

cessofs.

DMA. See direct memory access.

DMA controller. Device that performs bus arbitration.

Dormant state. ln the task-control block model, a state that is best described as a TCB

belonging to a task that is unavailable to the operating system.

Double-buffering. A technique using two buffers where one is tllled while the data ir

the other is being used.

DRAM. Dynamic random access memory.

Drive line. In core memory, a wire used to induce a magnetic field in a toroid-shrpe;

magnet. The orientation of the field represents either a 1 or a 0'

Dynamic memory. Memory that uses a capacitor to store logic 1s and 0s. and thet ::-.:

be refreshed periodically to restore the charge lost due to capacitive discharse

Dynamic priority system. A system in which the priorities of tasks ca: ;:i:::

Contrast with fixed priority system'

EEffort. One of Halstead's metrics (see Chapter 11)'

Embedded system. Software used to conffol speci.alized harClare .l';;:.:: :: ---e

computer system.

EncapSulation. A condition that arises when a class of objecis ;n.j ilre rrFEri'.- I --: '-i:l

can be performed on are isolated in both access and implementation'

332 I Glossary

Event. Any occurrence that results in a change in the state of a system.

Event determinism. When the next states and outputs of the system are known for eachset of inputs that trigger events.

Event flag. Synchronization mechanism provided by certain languages.

Exception. Error or other special condition that arises during program execution.

Exception handler. Code used to process exceptlons.

Execute. Process of sequencing througli the steps in micromemory corresponding to aparticular macroinstruction.

Executing state. In the task-control block model, a task that is currently running.

Exccutive. See kernel.

Extennal fragmentation. When main memory becomes checkered with unused butavailable partitions, as in Figure 8.-5.

FFailed system. A system thai cannot satisfy one or more of the requirements listed in the

formal system specification.

Failure. A fault that causes the software system to fail to meet one of its requirements.See also defect.

Failure function. A function describing the probability that a system fails at time r.

Fault. The appearance of a defect during the operation of a software system;synonymous with error or bug. See also failure.

Fault tolerance. The ability of the system to continue to function in the presence ofhardware or software failures.

Fetch. The process of retrieving a macroinstruction from main memory and placing itin the instruction register.

Fetch-execute cycle. The process of continuously fetching and executing macroinstruc-tions from main memory.

File fragmentation. Analogous to memory fragmentation but occurring within files,with the same associated problems.

Finite state automaton. A mathematical technique used to represent systems with finiteinput and output spaces. Also known as a finite state machine.

Firing. In Petri nets or in certain multiprocessor architectures, when a process block orprocess performs its prescribed function.

Firm real-time system. A system with hard deadlines where some lowmissing a deadline can be tolerated.

Fixed priority system. A system in which the taskContrast with dynamic priority system.

Fixed-rate system. A system in which intemrpts occui

Flip-flop. A bistable logic device.

Flow chart. Graphical algorithm representation.

Flush. In pipelined architectures, the act of emptyingoccurs.

of

priorities cannot be changed.

only at fixed rates.

the pipeline when branching

I Glossary 333

Foreground. A collection of interrupt driven or real-time processes.

Formal parameter. The dummy variable used in the description of a procedure orsubroutine.

FSA. See finite state automaton.

FSM. See finite state automaton.

Function points. A widely used metric set in nonembedded environments; they formthe basis of many commercial software analysis packages. Function points measure thenumber of interfaces between modules and subsystems in programs or systems.

Functional requirements. Those system features that can be directly tested brexecuting the program.

GGarbage. Memory that has been allocated but is no longer being used by a task (that is.

the task has "lost track of it").

General register. CPU intemal memory that is addressable in the address field ofcertain macroinstructtons.

General semaphore. See counting semaphore.

General polynomial. The modulo-2 divisor of the message polynomial in CRC.

Granularity. See scale factor.

Group walkthrough. A kind of white box testing in which a number of persons inspectthe code line-by-line with the unit author.

H 1

-Hamming code. A coding technique used to detect and correct errors in computermemory.

Hard error. Physical damage to memory cell.

Hard real-time system. Systems where failure to meet response time constraints leadsto system failure.

Hybrid system. A system in which interrupts occur both at fixed frequencies andsporadically.

Hypercube processor. A processor configuration that is similar to the linear arrar'processor except that each processor element communicates data along a number ofother higher dimensional pathways.

IICE. See in-circuit emulation.

Immediate mode instruction. An instruction in which the operand is an intege:

Implied mode instruction. An instruction involving one or more specitk nnern\a{-\locations or registers that are implicitly defined in the operation pert-urrri trtinstruction.

Incidence matrix. A realiability matrix in which the enries are eitlrer I or 0.

334 I Glossary

In-circuit emulation. A device that uses special hardware in conjunction with softwareto emulate the target CPU for debugging purposes.

Indirect mode instruction. Instruction where the operand field is a memory locationcontaining the address of the address of the operand.

Induction variable. A variable in a loop that is incremented or decremented by someconstant.

Information hiding. The process of isolating highly changeable sections of code.

Inheritance. In object-oriented programming, inheritance allows the programmer todefine new objects in terms of other objects that inherit their characteristics.

In-line patch. A patch that fits into the memory space allocated to the code to bechanged.

Input space. The set of all possible input combinations to a system.

Instruction register. CPU intemal register that holds the instruction pointed to by thecontents of the program counter.

Integration. The process of uniting modules from different sources to form the overallsystem.

Internal fragmentation. Condition that occurs in fixed-partition schemes when, forexample, a process requires I kilobyte of memory, while the only 2-kilobyte partitionsare available.

Interrupt. A hardware signal that initiates an event.

Interrupt handler. Special code used to respond to intemrpts. Also called an interruptservice routine.

Interrupt-handler location. Memory location containing the starting address of aninterrupt-handler routine. The program counter is automatically loaded with its addresswhen an interrupt occurs.

Interrupt latency. The delay between when an intemrpt occurs and when the CPUbegins reacting to it.

Interrupt register. Register containing a bit map of all pending (latched) interrupts.

Interrupt return location. Memory location where the contents of the program counteris saved when an intemrpt is processed by the CPU.

Interrupt vector. Register that contains the identity of the highest-priority intemrptrequest.

Intrinsic function. A macro where the actual function call is replaced by in-linecode.

JJackson Chart. A form of structure chart that provides for conditional branchins.

KKalrnan filter. A mathematical construct used to combine measurements of the same

quantity from different sources.

Kernel. The smallest portion of the operating system that provides for task scheduling,dispatching, and intertask communication.

335I Glossary

Kernel preemption. A method used in real-time UNIX that provides preemptlon polnts

in cails to kemel functions to allow them to be intemrpted'

Key. In a mailbox, the data that are passed as a flag used to protect a critical region'

LLeaf. Any node in a tree with no subtrees'

Least recently used rule. The best nonpredictive page replacement algorithm'

Leveling. [n dataflow diagrams. the process of redrawing a diagram at a finer level of

detail.

Linear array processor. A processor organized so that multiple instructions of the same

type can be executed in Parallel'

L inker .Sof twarethatpreparesre locatableobjectcodeforexecut ton '

Little,s law. Rule trom queuing theory stating that the average number of customers in

aqueu ingSys tem,N" ' , i sequa l t o theave ragean i va l ra teo f thecus tomers to tha tsystem, ru,, times the average time spent in that system' ta"'

Live variable. A variable that can be used subsequently in the program'

Livelock. Another term for process starvatron'

Load module. Code that can be readily loaded into the machine'

Locality-of-ret'erence. The notion that if you examine a list of recently executed

progiu* instructions on a logic analyzer, you will see that most of the instructions are

iocalized to within a small number of instructtons'

Lock-up. When a system enters in which it is rendered ineffective'

L o o k - u p t a b l e . A n i n t e g e r a r i t h m e t i c t e c h n i q u e t h a t u s e s t a b l e s a n d r e l i e s o nmathematical definition of the derivative to compute functions quickly'

Loop invariant optimization. The process of placing computations outside a loop that

do not need to be performed within the loop'

Loose l ycoup ledsys tem.Asys temtha tcan runono the rha rdwarew i th the rewr i t eo fcertain modul:s

LRU. See least recenty used rule'

MMachine code. Binary instructions that affect specific computer operations' Also called

machine language.

Macrocode. See macroinstruction'

Macroinstruction. Binary program code stored in the main memory of the computer'

Also called macrocode.

Mailbox, An intertask communication device consi,sting of a memory locatlon in'J 'i A r-

operations-post and pend-that can be performed on it'

Main memory. Memory that is directly addressable by the CPU'

Major cycle. The largest sequence of repeating processes in c1'ciic or pencrltc i\ ilsl'l'ls

MAR. See memory address register'

Mask register. A register that contains a bit map either enabling or di'abling sFecric

intemrPts.

336I Glossary

Master processor. The on-line processor in a master/slave configuration'

MDR. See memorY data register.

Memory address register (or MAR). Register that holds the address of the memory

location to be acted on.

Memory data register (or MDR). Register that holds the data to be written to or that

is read fiom the memory location held in the MAR'

Memory-loading. The percentage of usable memory that is being used'

Memory locking. In a real-time system, the process of locking all or certain parts of a

process lnro memory to reduce fhe <lverhead involved in paging, and thus make the

execution times more predictable.

Mesh processor. A processor configuration that is similar to the linear array processor

"^a"pt that each processor element also communicates data north and south'

Message exchange' See mailbox.

Message polynomial. Used in CRC (see Chapter 11)'

Methods. In object-oriented systems, functions that can be performed on objects.

MFT. Multiprogramming with a fixed number of tasks'

Microcode. A sequence of binary instructions corresponding to a particular macro-

instruction. Also called microinstructions'

Microcontroller. A computer system that is programmable via microcode.

Microinstructions. See microcode.

Micro-kerne| .Anano-kemel thata lsoprovidesfor taskschedul ing.

Micromemory. cPU intemal memory that holds the binary codes corresponding to

macroinstructions.

Microprogram. Sequence of microcode stored in micromemory'

Minor cycle. A sequence of repeating processes in cyclic or periodic systems'

Mixed listing. A printout that combines the high-order language instruction with the

equivalent assembly language code'

Mixed system. A system in which interrupts occur

sporadically"

both at fixed frequencies and

Multimedia computing. Computing that involves computer systems

resolution graphics, CD-ROM drives, mice, high-performance sound

multitasking operating systems that support these devices'

Mul t ip |exer .Adeviceusedtoroutemul t ip le l inesontofewer l ines.

Multiprocessing operating system. An operating system in which more than one

processor is available to provide for simultaneity; contrast with multitasking operating

sysrcm.

Multitasking operating system. An operating system that provides sufficient function-

ality to aiow multiple programs to run on a single processor so that the illusion of

simultaneity is created; contrast with multiprocessing operating system.

Mutex. A common name for a semaphore variable'

MUX. See multiPlexer'

MVT. Muftiprogramming with a variable number of tasks'

with high-cards, and

I Glossary 337

NNano-kernel. Code that provides simple thread-of-execution (same as "flow-of-

control") management; essentially provides only one of the three services provided bya kernel-that is, it provides for task dispatching.

Nonfunctional requirements. System requirements that cannot be tested easily byprogram executron.

Nonvolatile menory. Memory whose contents are preserved upon removing povl'er.

Non-von Neumann architecture. An architecture that does not use the stored program,serial fetch-execute cycle.

No-op. A macroinstruction that does not change the state of the computer.

NP-complete problem, A decision problem that is a seemingly intractable problem forwhich the only known solutions are exponential functions of the problem size; comparewith NP-hard.

NP-hard. A decision problem that is similar to an NP-complete problem (except that forthe NP-hard problem not even an exponential time solution can be found).

nth Order reliability matrix. The composition of a reliability matrix with itself (n - l)trmes.

N-version programming. A technique used to reduce the likelihood of system lock-up

by using redundant processors, each running software that has been coded to the same

specifications by different teams.

Nucleus. See kernel.

oObject code. A specific collection of machine instructions.

Object-oriented language. A language that provides constructs that encourage a high

degree of information hiding and data abstraction.

Opcode. Starting address of the microcode program stored in micromemory.

Operating system. A unique collection of systems programs.

Organic system. A system that is not embedded.

Orthogonal process. In statecharts, the combined functionalit.v of t set of orrhogonalprocesses.

Orthogonal product. In statecharts. a process that depicts concrurent processes that r'Jn

in isolation.

Ostrich algorithm. A technique that advises that the problem of deadlock be ignored.

This solution is viable only in noncritical s\stems.

Output space. The set of all possible output combilations ior a s)'stem'

Overlay. Dependent code and data sections used in overlaf i,ng.

Overlaying. A technique that allows a srngle program to be larger than the allowable

user space.

Oversized patch. A patch that requires more memor)- than is curendy occupied by the

code to be replaced.

I Glossary

PPage. Fixed-size chunk used in demand-paged systems.

Page fault. An exception that occurs when a memory reference is made to a locationwithin a page not loaded in marn memory.

Page-frame. See page.

Page stealing. When a page is to be loaded into main memory, and no free pages arefound, then a page frame must be written out or swapped to disk to make room.

Page table. A collection of pointers to pages used to allow noncontiguous allocation ofpage frames in demand paging.

Parnas partitioning. See information hiding.

Partial order relation. In process scheduling, an indicator that any process can callitself (reflexivity); if process A calls process B, then the reverse is not possible(antisymmetry), and if process A calls process B and process B calls process C, thenprocess A can call process C (transitivity).

Patching. The process of correcting errors in the code directly on the target machine.

PC. See program counter.

PDL. See program design language.

Peephole optimization. An optimization technique where a small window of assemblylangage or machine code is compared against known pattems that yield optimizationopportunltles.

Pend operation. Operation of removing data from a mailbox. If data are not available,the process performing the pend suspects itself until the data become available.

Petri net. A mathematical/pictorial system description technique.

Phase-driven code. See state-driven code.

Ping-pongbuffering. Seedouble-buffering.

Pipeline. An intertask communication mechanism provided in UNIX.

Pipelining. A technique used to speed processor execution that relies on the fact thatfetching the instruction is only one part of the fetch-execute cycle, and that it canoverlap with different parts of the fetch-execute cycle for other instructions.

Polled loop system. A real-time system in which a single and repetitive test instructionis used to test a flag that indicates that some event has occurred.

Polymorphism. In object-oriented programming, polymorphism allows the pro-grarnmer to create a single function that operates on different objects depending on thetype of object involved.

Post operation. Operation that places data in a mailbox.

Power bus. The collection of wires used to distribute Dower to the various componentsof the computer system.

Pragma. In certain programming languages, a pseudo-op that allows assembly code tobe placed in-line with the high-order language code.

Preempt. A condition that occurs when a higher-priority task interrupts a lower-prioritytask.

Preemptive priority system. A system that uses preemption schemes instead of round-robin or first-come/first-serve scheduling.

.."-:--:<]

338

I Glossary

Primary memory. See main memory.

Priority ceiling protocol. A method used in interrupt driven systems to avoid priority

inversion; dictates that a task blocking a higher priority task inherits the higher priority

for the duration of that task.

Priority inversion. A condition that occurs because a noncritical task with a high

execution rate will have a higher priority than a critical task with a low execution

rate.

Process blocks. Subsysterrs used to calculate the overall system reliability.

Processing elements. The individual processors in a multiprocessing system such as a

systolic or wavefiont architecture.

Program counter. The CPU internal register that holds the address of the next

instruction to be executed.

Program design language. A type of abstract high-order language used in sYstem

specification.

Propagation delay. The contribution to interrupt latency due to limitation in switching

speeds of digital devices and in the transit time of electrons across wires.

Prototype. A mock-up of a software system often used during the design phase.

Pseudocode. A type of program design language.

RRaise. Mechanism used to initiate a software interrupt in certain languages such as C.

RAM scrubbing. A technique used in memory configurations that include error

detection and correction chips. The technique, which reduces the chance of multiple bit

errors occuring, is needed because in some configurations memory effors are corrected

on the bus and not in mernory itself. The corrected memory data then need to be written

back to rnemory.

Random variable. A function mapping elements of the sample space into a real

number.

Rate-monotonic system. A fixed-rate, preemptive, prioritized real-time system shere

the priorities are assigned so that the higher the execution frequency, the higher the

priority.

Reactive system. A system that has some ongoing interaction with its enrironment.

Read/write line. Logic line that is set to logic 0 during memory- u'rite and to logr. I

during memory read.

Ready state. In the task-control block model, the state of those thsks that are r:::i :.-

run, but not running.

Real-time system. A system that must satisf;- explicit tbcundea' :eirrcrit ll=.1

constraints or it will fail.

Recovery block. Section of code that terminate. in che.-\pr.int. lf the l ire:r:. -

processing can resume at the beginning of a recoren bir-t-k.

Recursion. A method uhereby a procedure can be self-relerenti ir i. ihat ls. l[ !-all in\\-hi-(call) itself.

339

340 I Glossary

Reduced instruction set cornputer. Architecture usually characterized by a smallinstruction set with limited addressing modes and hard-wired (as opposed tomicrocoded) instructlons.

Reduction in strength. Optimization technique that uses the fastest macroinstructionpossible to accomplish a given calculation.

Re-entrant procedure. A procedure that can be used by several concurrently runningtasks in a multitasking system.

Register direct mode instruction. Instruction in which the operand field is areglster.

Register indirect mode instruction. Instruction in which the operand address is kept ina register named in the operand field of the instruction.

Regression testing. A test methodology used to validate updated softu,are against anold set of test cases that have already been passed.

Reliability matrix. In a multiprocessing system, a matrix that denotes the reliability ofthe connections between processors.

Response time. The time between the presentation of a set of inputs to a softwaresystem and the appearance of all the associated outputs.

Reverse Polish notation. The result of building a binary parse tree with operands at theleaves and operations at the roots, and then traversing it in post-order fashion.

Ring buffer. A first-in/first-out list in which simultaneous input and output to the list isachieved by keeping head and tail pointers. Data are loaded at the tail and read fromthe head.

RISC. See reduced instruction set computer.

Root. In overlaying memory management, the portion of memory containing theoverlay manager and code common to all overlay segments, such as math libraries.

Round-robin system. A system in which several processes are executed sequentially tocompletion, often in conjunction with a cyclic executive.

Round-robin system with time-slicing. A system in which each executable task isassigned a fixed time quantum called a time slice in which to execute. A clock is usedto initate an interrupt at a rate corresponding to the time slice.

SSample space. The set of outcomes to some experiment.

Sampling rate. The rate at which an analog signal is converted to digital form.

Scale factor. A technique used to simulate floating point operations by assigning animplicit noninteger value to the least significant bit of an integer.

sccs. Source code control system for management of system code; typical for UNIXoperating systems.

Schedualability analysis. The compile time prediction of execution time per-formance.

Scheduler. The part of the kernel that determines which task will run.

Scratch pad memory. CPU intemal memory used for intermediate results.

311I Glossary

Screen signature. The CRC of a screen memory'

Secondarymemory.Memorythatischaracterizedbylong-termstoragedevicesSuchaStapes, disks, and cards'

Se l f -mod i f y i ngcode 'Code tha tcanac tua l l ychange i t se l f ; f o rexamp le 'by tak ingadvantage of tn" tu",iiat the opcodes of certain initructions may differ by only one

bit.

Semaphore. A special variable type used for protectrng critical regions'

Semaphore primitives' The two operations that can be performed on a semaphor'

namelY, wait and signal'

Semidetached system' See loosely coupled system'

Sensel ine. lncorememoryawirethat isusedto. . read' ' thememory.Dependingontheorientation of the magnetrc field in the core, a pulse is or is not generated in the sense

line.

Serialty reusable resource. A resource that can only be used by one task at a time and

that must be used to comPletion'

Server .Aprocessusedtomanagemul t ip lerequeststoaser ia l lyreusableresource.

SEU. See single event upset'

Signal. Exception-handling mechanism provided by certain languages' such as C'

S igna lope ra t i on .op " ,u t i - ononasemaphore tha tessen t i a l l y re leases the resou rce

Protected bY the semaPhore'

Single.eventupset .Al terat ionofmemorycontentsduetochargedpart ic lespresent lnJpu"", ot in the presence of a nuclear event'

S|aveprocessor .Theof f - l ine,processor inamaster /s laveconf igurat ion.

Soft eiror. Repairable alteration of the contents of memory'

Sof t real - t imesystem.Asysteminwhichperformancersdegradedbynotdestroyedblfailure to meet response time constrarnts'

Software. A collection of macroinstructlons'

Sof twarere l iab i l i ty .Theprobabi l i ty thatasof twaresystemwi l lnot fa i lbeforesometime t.

Spatiat fault tolerance' Methods involving redundant hardware or software'

Speculat iveexecut ion. Inmul t iprocessingsystems,asi tuat ionthat invol r 'eseni . ] ]eprocessor optimislcailv and predictively executing code in the next process birrrr' :>

longasthereisnodepend"ncyinthatprocessblockoncodethatcouidberu: i l - : . i . - :other Processors'

Spin lock. Another name for the wait semaphore operatlon'

Sporadic system. A system with all interrupts occulrlng sporadicarir'

Sporadic task. A task driven by an interrupt that occurs apen'rir'i'i

S p u r i o u s i n t e r r u p t s . E x t r a n e o u s a n d u n w a n t e d i n t e m l p t s i h " : , : , : ' . ' ] : : . . ] . . . _ . , : -loading.

SRAM. Static random-access memory'

Stack. A first-inAast-out data structure'

S tackmach ines .Compu te ra rch i t ec tu re inuh i chL te lns t . ' ; - - - : : i 3 r= ;en : i r 3 . JJ , i . : :intemal memory store called a stack' and an accurtuial"t

342 I Glossary

Starvation. A condition that occurs when a task is not being serviced frequently

enough.

State-driven code. Program code based on a finite state automaton.

Static memory. Memory that does not rely on capacitive charge to store binary data.

Statistically based testing. Technique that uses an underlying probability distribution

function for each system input to generate random test cases.

Status register. A register involved in interupt processing that contains the value of the

lowest interrupt that will presently be honored.

Stress testing. A type of testing wherein the system is subjected to a large disturbance

in the inputs (for example, a large burst of interupts), foilowed by smaller disturbances

spread out over a longer period of time.

Structure chart. Graphical design tool used to partition system functionality.

Suspended state. In the task-control block model, those tasks that are waiting on a

particular resource, and thus are not ready. Also called the blocked state.

Swapping. The simplest scheme that allows the operating system to aliocate main

memory to two processes simultaneously.

Switch bounce. The physical phenomenon that an eiectricai signal cannot instanfa-

neously change from its logical false condition.

Synchronous data. See time-relative data.

Synchronous event. Event that occurs at predictable times in the flow-of-control.

Syndrome bits. The extra bits needed to implement a Hamming code.

System. An entity that when presented with a set of inputs produces

outputs.

System programs. Software used to manage the resources of the computer.

System unification. A process consisting of linking together the testing software

modules in an orderly fashron.

Systotic processors. Multiprocessing architecture that consists of a large number of

uniform processors connected in an array topology.

TTask-control block. A collection of data associated with a task including

process code (or a pointer to it), and other infonnation.

TCB. See task control block.

Telepresence. A form of virtual reality in which a human operator can remotely control

robots or other devices as if the operator were physically present.

Temporal determinism. A condition that occurs when the response time for each set of

outputs is known in a deterministic system.

Temporal fault tolerance. Techniques that allow for tolerating missed deadlines.

Test-and-set instruction. A macroinstruction that can atomically test and then set a

panicular memory address to some value.

Test probe. A checkpoint used only during testing'

Test suite. A collection of test cases.

I Glossary 343

Thrashing. Very high paging activity.

Throughput. A measure of the number of macroinstructions per second that can beprocessed based on some predetermined instruction mix.

Time-loading. The percentage of "useful" processing the computer is doing. Alsoknown as the utilization factor.

Time overloaded. A system that is l00olo or more time-loaded.

Time-relative data. A iollection of data that must be time correlated,

Time-slice. A fixed time quantum used to limit execution time in round-robinsystems.

Transceivers. A transmitheceive hybrid device.

Tiansputer. A fully self-sufficient, multiple instruction set, von Neumann processor,designed to be connected to other transputers.

Trap. Internal interrupt caused by the execution of a certain instruction.

Tri-state. A high-impedance state that, in effect, disconnects a device from the bus.

UUnit. A software module.

Unreachable code. Code that can never be reached in the normal flow-of-control.

User space. Memory not required by the operating system.

Utilization facator. See time-loadine.

vVector processor. See linear iuray processor.

Version control software. A system that manages the access to the various componentsof the system from the software library.

Volatile memory. Memory in which the contents will be lost if power is removed.

von Neumann bottleneck. A situation in which the serial fetch and execution ofinstructions limits overall execution speed.

wWait and hold condition. The situation in which a task acquires a resource and then

does not relinquish it until it can acquire another resource.

Wait operation. Operation on a semaphore that essentially locks the resource protectedby the semaphore, or prevents the requesting task from proceeding if the resource isalready locked.

Wait state. Clock cycle used to synchronize macroinsEuction execution with the accesstime of memory.

Watchdog timer. A device that must be reset periodically or a discrete signal isissued.

I Glossary

Wavefront processor. A multiprocessing architecture that consists of an array of

identical processors, each with its own local memory and connected in a nearest-

neighbor topology.

White box testing. Logic-driven testing-designed to exercise all paths in the module.

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lndex

A0-address architecture, 25 -3 I

1-address architecture, 3 1-3

2-address architecture, 33-5

3-address architecture, 35

O-address machine, instruction set' 26

l-address machine, instruction set, 32

2-address machine' instruction set' 34

3-address machine, instruction set' 36

0-address machine, Programmlng'28-3r

Absract data tYPing' 68-71

Accumulator, 22

Activity Packets,292Ada, 17, 60, 61, 63, 65, 66, 11'

80-1, 150, 182,324

Ada-95, 8r-2, 324' 325

Ada++, 70

Address bus, 2

Addressing modes, 21-5

ALGOL-60, 63, 66

ALGOL-W 63

Alpha testing, 267

Analog+o-digital (A/D) circuitry, 53

ANSI-C, 78, 181

Aiplication Programs, 7

Adthmetic logic unit (ALU)' 4

Arithmetic oPerations, 27

Assemblers, 8

AssemblY languages, 21,82-3' lI2'

324

Asynchronous events, 12

Automatic teller machine, 118-20

BBackground, 156

Background Processing, 157-8

Banker's algorithm, 185-6

BASIC, 17, 60,63,65, '13, '74 ' 197

Bathtub curve, 257

Beta testing, 267

BinarY angular measurement

(BAM), t?1-?

Binary ree, definition, 28

Bit failures, 277

Black box testing, 264-5

Blocked tasks, 181

BRANCH instructions, 38

Broadcast communication, 133' 135

Buffer size calculation, 245-8

maximum, 248

M[\4/1 queue' 251

variable, 246-8

Buffering data,170-2

Buffering sYstem' 245

Bugs, 255-6

Built-in-software test (BIST), 271

Built-in{est software (BITS)' 271'

2'16

Burn-in testing, 267

Burst petiod, 245,248

Bursting of events, 146

Bursts of data,245-6

Bus, 2arbitration, 50

contention, 50

cycles,21-2grant signal' 50

interface unit (BIU), 318

time-out signal, 51

transfer mechanisms, 2-3

Byzantine Generals' Problem' 286

cC language, l'1, 60, 61, 65, 66"13'

75 -8 ,83 , 324 ,326

disadvantages, 78

excePtion handling, 77-8

special variable tYPes, 75-6

C++ language, 70,78, 324' 326

Caches,227Call-by-address, 61-2

Call-bY-name, 63

Call-bY-reference, 6 1-2

Call-bY-value' 61-2

Call-bY-value-result- 63

Calling trees, 113-i4

CASE (comPuter-aided software

engineering), 1 10

Central processing unit (CPU), 2,

20-roPeration, 4-7

structure, 4

tesrifig, 27 l-2

throughput, 13

Chain reaction, i35

CheckPoints, 269-70

Checksum, 272

CICS (Customer Information

Control SYStem), 148

Circular queue (ring buffer), 171

CISC (comPlex instruction sdt

comPuters) architecture' 4 1-3

Class definitions' 70

Cleanroom testing, 268

cMS-2, l7

Code generation, 83-4

Code insPections, 266

COHESION environment, 95

Col l is ion,50' 175

COM variables, 63

COMMON variables, 63

Compaction' 200

Compare instructions, 35-8

Compiler optimization techmques'

224-i2

combination effects' 233-4

common subexPresston

elimination, 225

constant folding, 226

constant ProPagation' 229

cross jumP eliminadon' Ii:-l

dead-store eliminanon' ll9

dead-vanable ellmlnarex'- l-tr'

fl ow-of-codlFoi r'OtrruDi:-ir- -li

intrinsic runcc:'is- lit

lmP Lr':uc-.-r :--::-rroY- ll-

ItF: L\:r-.$l: "ft-f'Ii^'tl-

l-:

.rtr: -;:::f-::g- ]i -

.:":6 -:--:r-;g- i-{--

-t<-s

356

Compiler optimization techniques

\cont.)reduction in strength, 225

removal of dead or unreachable

code,22'7-8short-circuiting Boolean code, 230

speculative execulion, 234

use of arithmetic identities, 225

use of registers and caches,22'7

Compilers, 8, 83-4Complex systems, 315-16

multimedia, 323Computer architecturc, 2

Computer architectules,multiprocessing systems,

282-3Computer hardware, 19-58

history, 17prototypes/simulators, 307

Computer hardware/softwareintegration, 301-13

Condition code registers (CCRs), 37

Conditional branching, 114

Conditional transfer, 37

Context, 150

Context-saving rule, 151

Context swirching, 150-l

Contiguous file allocation, 204

Continuous probability distribution.

242

Continuous random variable, 242

Continuous real-valued function,

222-3

Control flow diagram, 124

Control specifications, 124

contrbl unit (cU), 4

Cooperative multitasking systems,

148-50Coprocessors, 40-l

Core memory, 44

Coroutines, 148-50, 157

response time, 208

Counting semaphores, 178-9

Critical regions, 175

Cross jump elimination, 231-2

CSML,60Customers, 248

Cycle stealing, 46

Cyclic executive system, 149

Cycl ic redundancy code (CRC), 272-4

Cycling, 307eychmatic c-or[plexiry, 260

DDaemons, 175Data bus, 2

Data flow architectures, 292-4

Data flow diagrams, 120-4,133,286,294

conventions, 121

DeMarco's rules for, i21

for navigation system, 122

for nuclear plant, 123

Hatley and Pribhai's extensions,1 a A

Data flow processors, systemspecification, 293-4

Data Item Descriptions (DIDs),

99-100Data strobe (DST), 2-3

Data transfer timing diagram, 3

Databasesapplications, 3 17-19

construction,3l7-18design,317

Deadlock, 183-5avoidance, 185-6

conditions necessary for, 183-4

detection of, 185-7

recovery 186-7

Death spiral, 277

DEBUG, 228Debuggers, 307Defects, 255-6Dernand paging, 201-3DeMarco's rules for data flow

diagrams, 121

Descrete random variable, 243-4

Design, 109-40

Detailed design document, 9l

Determinism, l2-13

Digital-to-analog (D/A) circuitry, 53

Direct memory access (DMA),

50-1,218,27',7acknowledge signal (DMACK),

50controller, 50-l

memory, 235request signal (DMARQ, 50

transfer timing diagram, 51

Direct mode instructions, 22

Disable priority interrupt (DPI),

38-9Discrete random variable, 241

Discrite signal, 3

Dispatcher, 142,149

Distributed systems, 283-91

reliability in, 286-91

DOD-STD-2I674 (ME-STD-

2167A),99-rc4Double buffering, 170

Double indirect mode addressing,

24-5

Index

DRAGOON,70Dynamic allocation, 65Dynamic-priority systems, 154

EElectropically erasable

programmable read-onlymemory (EEPROM),47-8

Embedded data processor (EDP),

3 1 8Embedded distribution systems, 283

Embedded systems, 10

Enable priority interrupt (EPI),

38-9Enumerated types, 69

Erlang's loss formula, 253-4

ESTEREL, 60Euclid, 326Even parity checker, ll7

Event determinism, 12

Event flags, 181-3

Event signals, 181-3Events, 12, 144

bursting of, 146

Exception handling, 68

C language, 77-8Executive, 143Exponential distribution, 242, 243

Extemal fragmentation memory,

199

FFailed system, definition, 9

Failure function, 257

Failures, 255-6FALSE state, 3Fault tolerance, 269

Faults, 255-6Fetch-execute cycle, 5

Fiber Distributed Data Interface(FDDr), 318

File fragmentation, 204Finite state automata (FSA), 117,

t33-4,146-:7Finitq state machines (FSMs), 117First-in/first-out (FIFO), 202Fixed-priority systems, 153-4Fixed-rate systems, 150Flash memory, 48Flip-flop, zt4-5Floating point instructions, 39, 214,

215Flow-of-control optimization, 228Flowcharts, ll2-13, ll4Foreground, 156

Index

Foreground,ibackground systems,l 56-60

initialization, 158major drawback, 160real-time operation, 158-9response times, 160

Formal program proving, 266-1FORTRAN, 16, 1'7 . 60, 61, 63_6,

t3-5. 112, 197, 211, 324Freedom space station, 318Function points, 263Fusible-link ROMs, 46Fusible links, 46-7

GGarbage collection, 204Gaussian (or normal) distribtion, 242Gaussian probability function, 243General registers, 4Generator poly nomial, 27 2Global variables, 63-4

reuse, 238GOTO statemenr, 112, 113Granularity, 220-1Graphical techniques, design

precautions, l38Group walkthrou ghs, 266

HHalstead's metrics, 261-3Hamming code error detection and

cotection,274Hard, enor,2'72Harells statecharts, 136-7Heisenberg uncertainty pnnciple,

307,310-12Hybrid systems, 150, 156

I

IEEE 830-1993, 104rEEE 1003 1-1990, 164-5IEEE standards, 106If-then structure, 147Image processin g, 319-24Immediate mode instructions, 22Implied mode instructions, 22Incidence matrix,287In-circuit emulation (ICE), 305-6In-circuit emulator block diagram, 308Indexed loop construct, 132-3Indirect memory instructions, 23Induction v ariable, 22'7Inertial measurement unit (IMU), 10Information hiding, 7lInheritance, 70

Input/output (I/O)

inteirupt driven, 48, 52memory-mapped, 49-50, 235me thods , 2 ,3 ,48 -52perfcrrmance, 239programmed, 48-9

Input space, 8Inputs, 8Instruction counting. 213-16Instruction execution time

simulators, 217- l l iInstruction register, 4Integrat ion,30lInternal fragmentation memory, 199Interpolation, geometric

interprctation, 222-3Interpreter, 74Irrterrupt, definition, 6Interrupt controllers, 54-5Interrupt disabling, 211Interrupt driven I/O, 48, 52Interrupt driven systems, 150-6Interrupt handlers, 6, 182, 191, 195Interrupt handling, 5J, 311

timing sequence, 55Intenupt latency, 21O-12

low priority interrupts highpriority,212

Interrupt register 6Interrupt retum location, 6Interrupt systems, 144-6

response 1ime, 209Intenupt vector, 6Intertask communication, 169-88Intrinsic functions, 226ISO Standard 9000, 103-4

J

Jackson chart, 113Java language, 326JOVIAL, 17Jump instructions, 35-8

conditional and unconditional, 37-8"Jump-to-self instruction, 150Jump unconditional absolute (JUA),

38

KKalman filter, 269Kemels

build or buy?, 164definitions, 142-3design strategies, 141-67hierarchy. 143role of. 142

357

LLanguage features, 59-85

comparison of, 74see also specific languap,es and

specific language featuresLeast recently used (LRU) method

202Level ing, l2 lLinkers, 8Little's law, 253L i ve lock ,183LOAD instruction, 25, 28, 63Load module, 302Local area networks (LANs), 43,

3 1 5Locality-of-reference method,

203*4Locks up,271Logic analyzer, 213, 304-5Longmp,77Look-up tables,222-4Loop induction elimination, 227Loop invariant optimization, 226Loop jamming, 231Loop unrolling, 230-lLoosely coupled system, 10LSB (least significant bir,220

M

McCabe's metric, 260Machine language, 20, 83Macrocode, 5Macroinstruction execution times,

211Macroinstructions, 5Mailboxes, 173-5

and semaphores, 177implementation, 173-4queues, 174-5

Major cycles, 155-6Mask registeq 6Mathematical specification, 1 1 l-12Matrix multiplication, 65Maximum stack size, 193Mealy FSA, 117-18Memory, 2, 43-8

analysis of requirements i3-1--dangerous allocation- i !-rDMA,235dynamic al localr . - r .

' i i i - - : . l

extemal frasm3n-'rror-- ^,

fragmei--:::::. l-'il|]le;nal lnlSneri::]:.. -+.icckine. l0-rmanasement schernes- l-1-nonvolatile. 43

358

Memory (cont )primary or main, 3program arca,236RAM area, 236secondary, 3stack area, 236static schemes, 205rcsiLn|,272volatile, 43

Memory address register (MAR), 4Memory data register (MDR), 4Memory-loading, 201, 312

rcducing,237-8variable selection-23r

Memory-loading f actot, 236-:7Memory management, 189-205Memory management model, 196Memory map,234-5Memory-mapped l/o, 49 -50, 235Message exchanges, 173Message polynomia| 2'1 2Methods, 70MFT (multiprogramming with a

fixed number of tasks),198-200

Microcode, 5Microcontroller, 20Microinstructions, 5Micro-kemal, 143Micromemory,4Microprogram, 5Mil-Std-15538 bus standard, 52-3Mil-Std-21 67A (DOD-STD-21674'),

99-100MIMD archiiecture, 283Minor cycles, 155-6MISD architecture, 282Mismatched COMMON overlays,

64Missed intemrpts, 27 6-7Mixed listing, 214MMll queae,249-52

buffer size calculation, 251real-time systems, 252

Modeling techniques, advantagesand disadvantages, 138

Modula-2, l '7 , 63, 65, 66,71,79-80, 150, 183

Modularity, 7l-3MODULE,71 ,79Moore finite state automaton, 117MSB (most significant bit),22A-1MULT1,65MULr2, 65Multi Bus tr, 318Multimedia architecture, 323Multimedia systems, 321-4

Multimeters, 304Multiple stack anangements, 193Multiplexer, 52Multiplexer/demul tiplexer (MDM)

u n i t s , 3 1 8Multiprocessing systems, 2, 124,

129, r7 5, 260, 281-99, 3t5classification of computer

architectures, 282-3Multiprogramming, 129Multitasking systems, 79, 124, 146,

169, r',]5.260Mutex, 177MUX transceivers, 52-3MVT (multiprogramming with a

variable number of tasks),200-1

N

Nano-kemel, 143Natural languages, 110-11Nearest neighbor topolo1y, 294Network interface unit (NIU), 318No-op (no-operation), 5Non-von Nuemann multiprocessing

architectures, 21, 291-8NP-complete problems, 218-19NP-hard problem, 219N-version programming, 271

oObject-oriented programming, 70Occam, 60Occam-2,325Odd parity checker, 118Opcode (operation code), 5Operating system, 8, 143Operational concept document, 89Optimization

basic theory,223-32peephole,225techryqaes,224-32

Orbital replaceable units (ORU),3 1 8

Qrganic distributed processingsystem, 283

Organic systems, l0Orthogonal states,284Orthogonality, 134OS/2 Presentation Manager, 148Oscilloscope, 304Ostrich algorithm, 186Output space, 80utputs, 8Overlaying, 198

Index

PPackage, 7 l-2Page faul t ,201Page frames, 201Page stealing, 201Page table, 201Parallel subsystems, equivalent

reliability, 258Parameter passing, 60-73Pamas partitioninE, 92-4, ll0, 265Partial transition table, 120Pascal , 17, 60, 6I , 65, 66, '13,

78-9, 83Patching, 308, 309-10PEARL,326Peephole optimization, 225Petri nets, 124-9

examples, 129firing, 125flowchart analogs,127systolic array, 296-7

Phase-driven code, 146-8, l5'7, 208Ping-pong buffering, 170Pipelining, 39-40Poisson process, 244, 252Polled loop systems, 144

response time, 146,208with inrerrupts, 144-6

Polymorphism, 70POP instruction, 27POSIX standard, 164-5, 318Power bus, 2keemption, 212Preemptive priority systems, 153-5Priority ceiling protocol (PCP), 155Priority inversion, 155Probability density function, 242Probability distribution function,

241-3,248Probe effect, 311Process, 142Process blocks, 258hocessing elements, 294Program counter (PC), 4Program design languages (PDLs),

I l 5 -16Programmable logic arrays (PLAs),

46hogrammable read-only memories

(PROMs),46-7

Programmed I/O,48-9Programming languages, 324-6Project Whirlwind, 316-17Propagation delays, 211Pseudocode, 1 15-16PUSH instruction, 28-PUSH operation, 27

Index

oQueues, mailboxes, i74-5Queuing models, 241-54Queuing system, components, 249Queuing theory,248-52

buffer calculations, 25 1service and production rates,

250-7

R

Raise operation, 181Random-access memory (RAM), 43

corraplion,2T2dynamic (DRAM),43

scrubbing, 157 -8, 274-5static (SRAM), 43testing,274-6

Randomvariable, 241Rate-monotonic analysis (RMA),

155Rate-monotonic systems, 154Reactive systems, 10Read-only mernory (ROM), 43

conuption,272

testing,272-4Read/write line, 3Real-time computing, 16Real-time languages. See Language

features and under specificlanguages

Real-time systems, 1applications,3l5-26basic cpncepts, 1-18definition, 9design issues, 14examples, 14-16full-featured, 160-3history, 16-17Mlivl/l queue, 252significant development events, 16use of term, 10-11

Recovery blocks, 270Recursion, 64-5Re-entrant procedures, 65Register direct mode instnrctions,

24Register indirect instructions, 24Registers, 227Regression testing, 267Reliability, 256-63

characterizations, 256in distributed systems, 286-91

Reliability functions, 256-8Reliability manix;.287 -9

hiiher-order, 290-1maximum,29l

second-order, 289third-order, 290

Resource allocation, 185Resource sharing, 175Resource table, 174Response time,9,207

calculation, 208-10coroutines, 208interrupt systems, 209modelling, 252phase-driven code, 208polled loops, 208reducing, 219-34

Restore routine, 191-2Retum from interrupt (RI), 38RETURN instruction, 38Retum location, 38Reverse Polish notation, 28Ring buffers, 171-2RISC (reduced instruction set

computer) architectures, 4 1-3,282,315

Round-robin systems, 152Run-time ring buffer, 193Run-time stack, 190

S

SABRE, 16Sample space, 241Sampling rate, 53Save routine, 191-2Scale factor, 220Scaled arithmetic, 220-lSchedualability analysis, 84Scheduler, 142Scheduling, NP-complete, 2 1 8-l 9Scratch pad memory, 4Screen signature, 274Second-order reliability matrix, 289Self-modifying code, 238Semaphores, 175-80

and mailboxes, 177counting, 178-9primitives, 176problems with, 179

Semiconductor memory. 44-6Semidetached system, 10Sense line, 44Serially reusable resources, 175Series subsystems, equivalent

reliability, 259Servers, 172,248Setjmp, 77Signal library function call. 182Signal operation. 176SIMD architectures, 282

359

Single-event upset (SEU), 158protection mechanisms, 277-8

Single-processing system, 2Slowest cycle computation, 220Smalltalk, 70Soft enor, 272Software

concepts, 7-8design, i10Heisenberg uncertainty principle,

3 1 1history, 17reliability, 256-63

definition, 256simulators, 306test ing,311-12watchdog timers, 56, I57,276,

2',77Software Design Descriptions

(SDDs), 104Software life cycle, 87-107

concept phase, 89design phase, 91-4functional requirements, 90maintenance phase, 96nonfunctional requirements, 90-lnontemporal transitions, 96-8Pamas partitioning, 92-4phases, activities and byproducts,

88-96programming phase, 94-5requirements phase, 89-91rules for requirements and design

documents, 91standards, 99-107test phase, 95-6version control software, 94

Space station, Freedom, 318SPARC (Special Application of

RISC) series, 42Spatial fault tolerance, 269Specification, 109-40

mathematical, 111-12Speculative execution, 234Spin lock, 177Spiral software model, 98sPool-, 175Sporadic systems. 150Sporadic tasks, 150Spurious interrups. 276-lStack, 38

architecture. 15area. 136managemen.- 190--molel . i51operations. 21overf los.277

360

Standards, software develoPment'

99-r07Starvation, 154, 183

State counters, 149

State-driven code, 146-9

Statecharts, 133-8, 284

depth, 134

orthogonality, 134

Statistiqally based testing, 267-8

Status register, 6

sToRE, 25, 63Stress, tesring, 269

Strong typing,66

Structure chans, 113-14

Structured Analysis, 110, 120

SUBROUTINE, 65, 73

Subroutine instructions, 35-8

Subsystems, reliabilities, 259

Swapping, 198

Switch bounce, 1zl4

Synchronous events, 12

Syndrome, 274

System, definition, 8

System bus, 2

System concePts, 8-9

System integration

backoff method, 308-9

establishing a baseline, 307-8

goals, 302-3

methodology, 307-10

System-level testing, 267

Systern performance analysis, 207-23

System programs, 7

System reliability, 258-63

System specification, 284-6

data flow processors, 293-4

for wavefront Processors, 298

System test suite, 267

System unifrcation, 302

System validation, 303

Systolic anay

for convolution, 295

in nearest neighbor toPologY' 295

peti net,296-:1

Systolic process ots, 29 4-7

. Systolic systems, specification, 297

Tfable-driven code, 148

Task, 142

Task-control block (TCB), 161-3

model, 161, 190, l96J

state transitions, 162

task management, 163

task states, 161

Task resource request table, 173-4

Task synchronization, 169-88

Temporal determinism, 13

Temporal fault tolerance, 269

Test-and-set instruction, 1 80

Test instructions, 37

Tesr log, 303Test probe, 269-?0

Test tools, 303-7

Testing, 263-9

black box, 264-5

cleanroom, 268

cPu,27r-2goal of,263

memory,272planning, 263-9

RAM, 274-6

ROM,272-4sof tware,311-12statistically based, 267-8

stress, 269

systemJevel, 267

unit level, 264-:7

white box, 265-6

Thrashing, 201

Threat-management systems, 154

Time-loading, 2O7 , 312

and its measuremettt, 212-18

deterministic Performance, 218

instruction counting, 2 13-1 6

instruction execution time

simulators, 217-18

logic analYzer,2l3pictorial representation, 2 16-17

definition, 13

reducing, 219-34

Time-overloaded sYstem, 13, 250

Time-relative buffering, 170-1

Time slice, 152

Timing code, 305

Timing instructions, 304-5

Transceiver, 52

Transitibn Table, 118

Transputen, 298

Traps,7, 182

Tri-state condition, 50

Index

TRUE state, 2

Type definition, 69

Typing, 66-8

UUltraviolet read-onlY memory

(uvRoM),47UNIT, 73Universal asynchronous relaY

terminal (UART), 52

uNrx, 143, 3r8,324User space, 198

Utilization factor, definition, 13

VVersion control software, 94

Virtual reality (VR) systems, 320-l

VLSL292,295Von Neumann bottleneck, 39

Von Neumann computer

architectures, 20, j9, 282

WWait and hold condition, 185

Wait operation, 176

Wamier-Orr notation, 129-33

examples, tr31-2

Watchdog timer (WDT), 56, 157,

276,2"t7

Waterfall, 88

Wavefront processors, 297-8

system specification for, 298

Weak typing, 66-8

Weibull distribu tion, 243

Weibull probabilitY densitY

-. funcrtion, 243

Whirlwinil computer, 316-17

White box, testing, 265-6

Wide area networks (WANs), 315

Working sets, 203-4

World Wide Web, 113, 133

zZ notation, 110