reality statistical characterization of a high-k metal gate 32nm arm926 core under process...
TRANSCRIPT
REALITY
STATISTICAL CHARACTERIZATION OF A HIGH-K METAL GATE 32NM ARM926 CORE UNDER PROCESS VARIABILITY IMPACT
Paul ZuberPetr DobrovolnyMiguel Miranda
Imec, Process Technologies Unit, Design & Technology Enablement Group, INSITEKapeldreef 75, B-3001 Leuven, Belgium
Selma LaabidiVirgile JaverliacYves Laplanche
ARM, Physical IP Division (PIPD), R&D
group60 Rue des Berges, F-38000 Grenoble,
France
MEMORIES AND SSTA
Local (Intra-die) Critical Path Delay Breakdown in ARM 92614% of clock period margin for intra-die variability:
2Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
MEMORIES AND SSTA
Local (Intra-die) Critical Path Delay Breakdown in ARM 926
SRAM
14% of clock period margin for intra-die variability:
2Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
MEMORIES AND SSTA
SRAM variability dominates total intra-die variation by 75%
Yet, no approach can give a SSTA view on memories. ▸ In this work, we quantify that memory contribution on an ARM926 core
Local (Intra-die) Critical Path Delay Breakdown in ARM 926
SRAM
14% of clock period margin for intra-die variability:
2Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
MOTIVATION / OBJECTIVES
Challenge:▸ Today’s deep submicron technologies suffer from
variability▸ High-k / Metal Gate promising technology solution
Problem:▸ Assessment of process variability on product level difficult▸ Memories play important role▸ Commercial solutions to capture memory variability
incomplete => Incomplete SSTA analysis
Objectives:▸ Correctly characterize memory’s statistical contribution▸ Quantify variability’s impact of an ARM core timing
including all 20+ memories
3Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
MOTIVATION / OBJECTIVES
Challenge:▸ Today’s deep submicron technologies suffer from
variability▸ High-k / Metal Gate promising technology solution
Problem:▸ Assessment of process variability on product level is
difficult▸ Memories play important role▸ Commercial solutions to capture memory variability are
incomplete → Incomplete SSTA analysis
Objectives:▸ Correctly characterize memory’s statistical contribution▸ Quantify variability’s impact of an ARM core timing
including all 20+ memories
3Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
MOTIVATION / OBJECTIVES
Challenge:▸ Today’s deep submicron technologies suffer from
variability▸ High-k / Metal Gate promising technology solution
Problem:▸ Assessment of process variability on product level is
difficult▸ Memories play important role▸ Commercial solutions to capture memory variability are
incomplete → Incomplete SSTA analysis
Objectives:▸ Correctly characterize memory’s statistical contribution▸ Quantify variability’s impact of an ARM core timing
including all 20+ memories
3Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION
4Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION
.lib
4Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION
Use of corners = No benefits of SSTA (as we will see)
Use of corners = No benefits of SSTA (as we will see)
.lib
4Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION
Use of corners = No benefits of SSTA (as we will see)
Use of corners = No benefits of SSTA (as we will see)
Statistical simulation of entire SRAM impossible unless we
have 100 days characterization time
Statistical simulation of entire SRAM impossible unless we
have 100 days characterization time
.lib
4Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
ALTERNATIVES FOR DEALING WITH MEMORY BLOCKS FOR STATISTICAL CORE CHARACTERIZATION
Use of corners = No benefits of SSTA (as we will see)
Use of corners = No benefits of SSTA (as we will see)
Statistical simulation of entire SRAM impossible unless we
have 100 days characterization time
Statistical simulation of entire SRAM impossible unless we
have 100 days characterization time
Considering single memory path as one big gate and run
Statistical Spice .... Danger! = Parallel Paths! & Topology!
Considering single memory path as one big gate and run
Statistical Spice .... Danger! = Parallel Paths! & Topology!
.lib
4Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW
Standard cell netlists
Device variability Single Memory Path Netlist
5Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW
Statistical SRAM
Modeling[DAC10]
Statistical SRAM
Modeling[DAC10]
In-House Stat.
Characterizer
[PATMOS09,DAC11]
In-House Stat.
Characterizer
[PATMOS09,DAC11]
Stat.Hspice, SiSmart/ELC/NCX,...
Single Path Sensitivities (Stat. Hspice)
Calculate Memory-wide Statistics
Standard cell Liberty filesStandard cell Liberty filesStat. Standard cell LibrariesMemory cell Liberty filesMemory cell Liberty filesStatistical SRAM Libraries
Standard cell netlists
Device variability Single Memory Path Netlist
5Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW
Statistical SRAM
Modeling[DAC10]
Statistical SRAM
Modeling[DAC10]
In-House Stat.
Characterizer
[PATMOS09,DAC11]
In-House Stat.
Characterizer
[PATMOS09,DAC11]
New for
Statistical FlowsStat.Hspice,
SiSmart/ELC/NCX,...Single Path Sensitivities (Stat.
Hspice)
Calculate Memory-wide Statistics
Standard cell Liberty filesStandard cell Liberty filesStat. Standard cell LibrariesMemory cell Liberty filesMemory cell Liberty filesStatistical SRAM Libraries
Standard cell netlists
Device variability Single Memory Path Netlist
5Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
DEVICE TO CORE LEVEL FULLY STATISTICAL CHARACTERIZATION FLOW
Statistical SRAM
Modeling[DAC10]
Statistical SRAM
Modeling[DAC10]
In-House “SSTA”
tool[ISQED09]
In-House “SSTA”
tool[ISQED09]
In-House Stat.
Characterizer
[PATMOS09,DAC11]
In-House Stat.
Characterizer
[PATMOS09,DAC11]
New for
Statistical Flows
DigiVAM (Design Compiler / ModelSim)
Stat.Hspice, SiSmart/ELC/NCX,...
Single Path Sensitivities (Stat. Hspice)
Calculate Memory-wide Statistics
Statistical Timing / Power Report
Standard cell Liberty filesStandard cell Liberty filesStat. Standard cell Libraries
Memory cell Liberty filesMemory cell Liberty filesStatistical SRAM Libraries
Standard cell netlists
Device variability Single Memory Path Netlist
ARM gate level netlist
5Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING
Cri
tica
l Path
Dela
y (
mem
ory
&
log
ic)
7Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics)
Inter-die: set final spread of distribution Total: combination of the two (shift and spread)
SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING
Cri
tica
l Path
Dela
y (
mem
ory
&
log
ic)
7Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics)
Inter-die: set final spread of distribution Total: combination of the two (shift and spread)
SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING
Cri
tica
l Path
Dela
y (
mem
ory
&
log
ic)
7Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics)
Inter-die: set final spread of distribution Total: combination of the two (shift and spread)
SUPERPOSITION OF ALL CONDITIONS ALLOWS COMPARISON OF PVT: TIMING
Cri
tica
l Path
Dela
y (
mem
ory
&
log
ic)
7Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
Intra-die: distribution shifts in all corners: memory effects dominate (worst case cell statistics)
Inter-die: set final spread of distribution Total: combination of the two (shift and spread)
BREAKING OUT THE INFLUENCE OF MEMORIES (INTRA-DIE)
8Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
Intra-die: Logic only (TT Corner for SRAM)
No variations (TT Corner for Logic and SRAM)
BREAKING OUT THE INFLUENCE OF MEMORIES (INTRA-DIE)
8Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
Intra-die: Logic only (TT Corner for SRAM)
Intra-die SRAM only (TT Corner for Logic)
No variations (TT Corner for Logic and SRAM)
BREAKING OUT THE INFLUENCE OF MEMORIES (INTRA-DIE)
Intra-die: Logic only (TT Corner for SRAM)
Intra-die SRAM only (TT Corner for Logic)
SRAM and Logic Intra-die (both considered)
No variations (TT Corner for Logic and SRAM)
8Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
BREAKING OUT THE INFLUENCE OF MEMORIES: INTRA-DIE VARIATION
75%
100%
0%
33
8Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
50%
Intra-die: Logic only (TT Corner for SRAM)
Intra-die SRAM only (TT Corner for Logic)
Intra-die: SRAM & Logic
No variations (TT Corner for Logic and SRAM)
BREAKING OUT THE INFLUENCE OF MEMORIES: INTRA-DIE VARIATION
75%
100%
0%
33
8Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
50%
Intra-die: Logic only (TT Corner for SRAM)
Intra-die SRAM only (TT Corner for Logic)
Intra-die: SRAM & Logic
No variations (TT Corner for Logic and SRAM)
SRAM
INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926
Intra-die: SRAM & Logic
33
9Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
No variations (TT Corner for Logic and SRAM)
INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926
Intra-die: SRAM & Logic
33
Inter-die :SRAM and Logic
9Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
No variations (TT Corner for Logic and SRAM)
INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926
Intra-die: SRAM & Logic
Total convolution intra- & inter-die (full core)
33
Inter-die :SRAM and Logic
9Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
No variations (TT Corner for Logic and SRAM)
INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926
Intra-die: SRAM & Logic
Total convolution intra- & inter-die (full core)
33
Inter-die :SRAM and Logic
9Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
No variations (TT Corner for Logic and SRAM)
60%
100%
0%
40%
INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926
Intra-die: SRAM and Logic
Total convolution intra- & inter-die (full core)
33
Inter-die :SRAM and Logic
9Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
No variations (TT Corner for Logic and SRAM)
60%
100%
0%
40%
Intra-die
INTER- AND INTRA- DIE VARIATION COMPONENTS IN ARM926
Intra-die: SRAM and Logic
Total convolution intra- & inter-die (full core)
33
Inter-die :SRAM and Logic
9Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
No variations (TT Corner for Logic and SRAM)
60%
100%
0%
40%
Intra-dieIntra-
dieSRAM
CONCLUSIONS
Variability impact of 32nm HK-MG technology on a ARM926 quantified:
Intra-die: Total:
75% 30%
Risk of under/over- design if margin concluded from SRAM typical/worst case corner only
State-of-art (in-house) statistical memory characterization used for SRAM .lib generation
SRAM
10Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
CONCLUSIONS
Variability impact of 32nm HK-MG technology on a ARM926 quantified:
Intra-die: Total:
75% 30%
Risk of under/over- design if margin concluded from SRAM typical/worst case corner only
State-of-art (in-house) statistical memory characterization used for SRAM .lib generation
SRAMIntra-die
10Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
CONCLUSIONS
Variability impact of 32nm HK-MG technology on a ARM926 quantified:
Intra-die: Total:
75% 30%
Risk of under/over- design if margin concluded from SRAM typical/worst case corner only
State-of-art (in-house) statistical memory characterization used for SRAM .lib generation
SRAMIntra-die
Intra-dieSRAM
10Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
CONCLUSIONS
Variability impact of 32nm HK-MG technology on a ARM926 quantified:
Intra-die: Total:
75% 30%
Risk of under/over- design if margin concluded from SRAM typical/worst case corner only
State-of-art (in-house) statistical memory characterization used for SRAM .lib generation
SRAM
10Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011
Intra-die
Intra-dieSRAM
THANK YOU!
Statistical Characterization of a High-K Metal Gate 32nm ARM926 -- DAC User Track 2011