reconfigurable neuromorphic synapse interconnects with tft · amorphous silicon tft lcd tv –tft...
TRANSCRIPT
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PUBLIC
RECONFIGURABLE NEUROMORPHIC SYNAPSE INTERCONNECTS
WITH TFT
SOEREN STEUDEL, KRIS MYNY, JAN STUIJT AND FRANCKY CATTHOOR
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Every neuron in a
human brain is
connected via its
synapses to 10-
15.000 other
neurons.
Those connections
can be over time
reconfigured
allowing new
connections with
any other neuron.
But only few of the
longer connections
are concurrently
active
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GLOBAL SYNAPSE
In a neuromorphic IC with more then >1000 neurons, where every neuron can
communicate with every neuron, the transistor count of the reconfigurable interconnect (
switches, buffer, repeater) heavily dominates the transistor count, area and power
consumption of the IC.
Scaling in power consumption
Scaling in integration density
Scaling in cost
ObjectiveLarge scale reconfigurable interconnect that allows to connect every neuron with every neuron even across the whole neuromorphic IC but with only limited amount of them concurrently active (as motivated earlier)
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BEOL OF N14 (INTEL)
4
Aspect
ratio
Pitch / Metal Thickness
K. Fischer et al, “Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-
metal capacitors for 14nm high volume manufacturing , Proceeding of IEEE MAM (2015)
For the global interconnect (BEOL > M4 ) the via size dominates the
area consumption of switches and repeaters. Not the FEOL transistor
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3D INTEGRATION
5
3D TSV chip stacking 3D BEOL TFT
Stacking multiple identical chips with TSV Integrate thin film transistors in the BEOL
Pro:
High speed, high performance, relative
mature
Con:
High cost,
integration density/size of TSV?
Pro:
Low cost?, high integration density
Con:
Performance, maturity
Pro:
high performance, high speed
Con:
Integration density? since only few
(2) transistor layer are stacked
Monolithic 3D
Transfer of crystalline Si
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Cu
FEOL
M1
M2
M3
M4
M5
M6
M7
M8
M9 TFT
3D BEOL TFT
Enable in every BEOL
layer a TFT process
module with minimal
additional mask count
(cost) and a critical
dimension that
corresponds to the
existing pitch of the
metalization
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3D BEOL TFTTFT REQUIREMENTS
1. Scalability down to pitch of M3-M4 (L<50nm)
2. Temperature budget of BEOL (380°C)
3. Leakage below low-leakage transistor of advanced nodes (<10pA/um; low
duty cycle in neuromorphic computing static leakage dominates);
4. High uniformity ( amorphous or nano-crystaline)
5. Speed ( stage delay <<1ns for buffering data rates of 100M-1G bit/s )
6. Bias stability / Reliability
7. Complementary ( n and p-type )
8. Mask count ( max 1-2 additional mask per BEOL layer )
9. Maturity of process technology
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THIN FILM TRANSISTOR (1)
Thin film semiconductor
Silicon
Amorphous silicon
Microcrystalline silicon
Polycrystalline silicon
Metaloxide 1D/2D Chalcogenide Organic
e.g. ZnS, CdTe,
CIGS, MoS,
WSe
e.g. ZnO, IGZO
(In2Ga2ZnO7),
ITZO, HfInZnO,
SnO, CuO,
ZnON
e.g. Carbon
nanotube
(CNT),
Graphene
Black
phosphorus
e.g. C60, P3HT,
pentacene
CuPc, DNTT
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THIN FILM TRANSISTOR (2)
TFT Amorphous Si Polysilicon Chalcogenide
(e.g. WSe2)
Metaloxide
(e.g. IGZO)
Organic
(e.g. DNTT)
1D/2D
(CNT, MoS,
Graphene)
Mobility [cm2/Vs] 0.5-1 50-150 140 10-20 0.5-5 >100
Bias stability very poor good n.a. medium medium n.a.
Uniformity good poor n.a. good good n.a.
polarity n n, p n, p n n, p n, p
Ioff [A/um]
@VGS=-10V
10p 10p * Bad, mostly
ambipolar
<<1f <10p Very bad
Maturity Production
display
Production
display
R&D Lab Production
display
R&D; Pilot line R&D Lab
Substrate size max. Gen10 max. Gen6 Flakes of mm2 max. Gen8 max. Gen3.5 Wafer
Deposition
process
PECVD PECVD + anneal
(laser, thermal)
Crystal growth +
transfer
PVD, (solution
coating)
OMBE, solution
coating
CVD, transfer
Process
Temperature [°C]
350 450 Growth > 600C
Transfer = RT
350 150 Growth > 600C
Transfer = RT
Lets look at mature TFT technologies
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AMORPHOUS SILICON TFTLCD TV – TFT IS USED AS A SWITCH IN AN ACTIVE MATRIX
cfr. DowCorning
Gen10
2850 x 3050mm
Latest Generation: Sharp’s Gen10 plant, Sakai City
72,000 substrates per month
Investment:~ $4.25B
• Lithographically patterned amorphous silicon transistor (L=5um, μ~0.5cm2/Vs) behind every pixel
• Backplane has 4-5 mask steps
• N-type only
• Low speed (mobility <1cm2/Vs)
• low bias stability
• high uniformity
• Temperature budget of 350°C
No solution for BEOL too slow
too low bias stability
too high leakage
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LOW-TEMPERATURE POLYSILICON TFT (1)SMART PHONE DISPLAY
Japan Display Inc. SID DIGEST 75, 2014
Complex in-panel digital complementary circuits with TFT
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Nobuo Karaki et al, A Flexible 8-bit Asynchronous Microprocessor Based on Low-Temperature Poly-
Silicon (LTPS) TFT Technology , Digest of SID 2005, pp.1430-1433
LOW-TEMPERATURE POLYSILICON TFT (2)MICROPROCESSOR
Cfr. Epson Seiko
No solution for BEOL too high temperature (>450°C)
high Ioff (grain boundaries)
Low uniformity (micro-crystalline)
High mask count (contact doping)
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METALOXIDETFT
13
MANUFACTURING RAMP UP OF IGZO DISPLAYS SINCE 2014
n-type only
medium speed, medium bias stability
High uniformity, ultralow Ioff
Temperature budget of 350°C
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METALOXIDETFT
< 14
FLEXIBLE AMOLED DISPLAYS @IMEC
with GIP @ SID 2015
on PEN @ IDW 2013
W/L=10/2 um/um
Mobility ~10cm2/Vs
Stage delay <10ns for L=2um
256 TFT across 6” wafer for VDD=5V technology
Uniformity of IGZO TFT(baseline PVD but ALD, CVD, Sol-gel possible)
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METALOXIDETFTRFID CHIPS WITH IGZO TFT @ IMEC
Mo
buffer
Mo
Glass
SiNxSiO2
IGZO
polyimide
0.5
0.4
0.3
0.2
0.1
0.0
Vo
ut
[V]
543210Time [ms]
500
400
300
200
100
0
Da
ta r
ate
[kb
it/s
]
1086420VDD [V]
ISO/IEC 14443
ISO/IEC 15693
Sony Felica
Vbias = 2VDD27ns
stage delay
K. Myny and S.Steudel, ISSCC 2016
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THIN-FILM MICROPROCESSORSMETALOXIDETFT
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METALOXIDETFTIoff of IGZO TFT technology @ imec wide bandgap 3.2eV without minority carriers
10-15
10-14
10-13
10-12
10-11
10-10
10-9
I D
[A
] x
-10 -8 -6 -4 -2 0
VGS [V]
10-15
10-14
10-13
10-12
10-11
10-10
10-9
|ID| [A
]
'ESL DieH'W/L = 60/20 um/umtins = 200 nm
er = 5.6
VDS =0.5V
linear saturation
Zoom in with long integration
and auto range
-10 -5 0 5 10
VGS [V]
10-13
10-11
10-9
10-7
10-5
I DS [
A]
'ESL DieH'W/L = 60/20 um/umtins = 200 nm
er = 5.6
VDS =20V
noise floor ~ 3e-14A
25C 60C 90C 105C
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
I D
[A
] x
-10 -5 0 5 10
VGS [V]
'ESL DieH'W/L = 60/20 um/umtins = 200 nm
er = 5.6
VDS =0.5V
25C 60C 90C 105C
Up to 105°C, the Ioff below 10-14A/um.
For more accurate measurement, TFT
with larger W/L are required.
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METALOXIDETFT
18
LEAKAGE CURRENT OF IGZO TFT
Shunpei Yamazaki, SEL (2015)
Lowest leakage current of any know material system
Matsubayashi et al, “20-nm-node trench-gate-self-aligned crystalline In-Ga-Zn-Oxide FET with high” IEEE IEDM, pp-141-143 (2015)
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METALOXIDE TFTSUB-MICROMETER IGZO TFT ON CMOS
SEL : state recovery SAMSUNG
SAMSUNG
SEL
Toshiba
Renesas
Many companies and R&D center work on metaloxide BEOL TFT for different application
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METALOXIDETFTSCALABILITY OF IGZO TFT
Matsubayashi et al, “20-nm-node trench-gate-self-aligned crystalline In-Ga-Zn-Oxide FET with high” IEEE IEDM, pp-141-143 (2015)
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METALOXIDETFT
21
SPEED OF SCALED IGZO TFT
IGZO has an average mobility ~ 10cm2/Vs. Higher mobility metaloxide
material with mobility >40cm2/Vs have been demonstrated
Matsubayashi et al, “20-nm-node trench-gate-self-aligned crystalline In-Ga-Zn-Oxide FET with high” IEEE IEDM, pp-141-143 (2015)
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METALOXIDETFTVLSI INTEGRATION ON CMOS
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IGZO TFT LOOKS LIKE THE PERFECT BEOL TFT SOLUTION
BUT......
23
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METALOXIDE TFTP-TYPE TFT 60
50
40
30
20
10|ID|1
/2 [A
1/2
] x 1
0-3
-15 -10 -5 0 5 10
VGS [V]
10-11
10
-9 10
-7 10
-5 10
-3
|ID| [A
]
W/L = 1400/5 um/umtins = 100 nm
er = 8
VT = -0.3 V
= 1.93 cm2/(V.s)
-2.0
-1.5
-1.0
-0.5
0.0
I DS [A
] x 1
0-3
-12 -8 -4 0
VDS [V]
SnOx at 350 °C
Lower mobility <5cm2/Vs
High Ioff >1nA/um
Low bias stability
Low maturity
Ab-initio modeling suggest that an
amorphous metaloxideTFT with
better performance is unlikely
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TFT CIRCUIT LOGIC / DEVICE LIMITATION !!
25
Low noise margin / soft yield
Power consumption
Present solution in FPD
Not possible in CMOSNo resistor available
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LIMITATIONS PSEUDO CMOS
26
• 2 different VDD can not be accepted in advanced
logic within a µCore
• Large footprint
• High energy consumption / static leakage
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3D BEOL TFT FOR GLOBAL SYNAPSE
27
METALOXIDE TFT
1. Scalability down to pitch of M3-M4 (L<50nm)
2. Temperature budget of BEOL (380°C)
3. Leakage below low-leakage transistor of advanced nodes (<10pA/um)
4. High uniformity ( amorphous or nano-crystaline)
5. Speed ( stage delay <<1ns for buffering data rates of 1Gbit/s )
6. Bias stability / reliability
7. Complementary / Dual-VT( n and p-type )
8. Cost ( max 1-2 additional mask per BEOL layer )
9. Maturity of process technology on CMOS
Will this approach translate into lower energy
consumption, smaller footprint and lower cost
then conventional FEOL solutions for global
synapse reconfigurable interconnect?
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H2020: NEU-RAM3BEOL TFT TEST CHIP WITH RECONFIGURABLE INTERCONNECT
Clever
Interc
bus
Sensor
NN classifier
Clever
Interc
bus
Clever
Interc
bus
Prototype Cluster interc IC with only BEOL @ IMEC
Neuron Cluster IC
Cluster interc IC
N-bit data bondpads
At IC boundary
Output
Figure 10: conceptual implementation with several neural clusters ICs with central
scalable global synapse communication IC.
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NEURAM3 TEST CHIP
29
CAN YOU MAKE A STABLE SWITCH MATRIX IN N-TYPE ONLY TFT TECHNOLOGY?
Two buffered three-way switch implementation forms
Simple segmented bus networks
Test chip overall schematic (5bit decoder)
Layout (1800 TFT)
• Create standard cell library of BEOL TFT to enable VHDL design environment
• Synthesis layout of simple segmented bus network with decoder
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NEURAM3 TEST CHIP
30
IMPLEMENTATION IN PASSIVATION MODULE
Stable TFT switch matrix with data rate >1Mbit/s @ VDD=3.3V
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CONCLUSION
31
1. BEOL TFT should enable large scale reconfigurable interconnect that allows to connect every neuron with every neuron even across the whole neuromorphic IC but with only limited amount of them concurrently active
2. First BEOL TFT test chip under evaluation with data rate > 1Mbit/s
3. Aggressive technology scaling required to move the BEOL TFT from passivation to M3-M4 level (target L=45nm)