registers and counters chapter 6. digital circuits 2 6.1 registers clocked sequential circuits a...
TRANSCRIPT
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Registers and Counters
Chapter 6
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2Digital Circuits
6.1 Registers
Clocked sequential circuits a group of flip-flops and combinational gates connected to form a feedback path
Flip-flops + Combinational gates(essential) (optional)
Register: a group of flip-flops gates that determine how the information is
transferred into the register Counter:
a register that goes through a predetermined sequence of states
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3Digital Circuits
6-1 Registers
A n-bit register n flip-flops capable of
storing n bits of binary information
4-bit register
Fig. 6.1Four-bit register
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4Digital Circuits
4-bit register with parallel load
load'
load
Fig. 6.2Four-bit register with parallel load
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5Digital Circuits
6-2 Shift Registers
Shift register a register capable of shifting its binary information
in one or both directions Simplest shift register
11
01 1
01
10
1
Fig. 6.3Four-bit shift register
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6Digital Circuits
Serial transfer vs. Parallel transfer Serial transfer
Information is transferred one bit at a time shifts the bits out of the source register into the
destination register Parallel transfer:
All the bits of the register are transferred at the same time
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7Digital Circuits
Example: Serial transfer from reg A to reg B
Fig. 6.4Serial transfer from register A to register B
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8Digital Circuits
Example: Serial transfer from reg A to reg B
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9Digital Circuits
Serial addition using D flip-flops
0101
0011
1
1 0
0
1
1010
?001
1
0
1
0
1
Fig. 6.5Serial adder
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10Digital Circuits
Serial adder using JK flip-flops
JQ = x y
KQ = x y = (x + y)
S = x y Q
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11Digital Circuits
Circuit diagramJQ = x y
KQ = x y = (x + y)
S = x y Q
Ci
Fig. 6.6Second form of serial adder
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12Digital Circuits
Universal Shift Register Unidirectional shift register Bidirectional shift register Universal shift register:
has both direction shifts & parallel load/out capabilities
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13Digital Circuits
Capability of a universal shift register:1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift-right control to enable the shift right operation and the serial input and output lines associated w/ the shift right.
4. A shift-left control to enable the shift left operation and the serial input and output lines associated w/ the shift left.
5. A parallel-load control to enable a parallel transfer and the n parallel input lines associated w/ the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in the presence of the clock.
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14Digital Circuits
Example: 4-bit universal shift register
Fig. 6.7Four-bit universal shift register
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15Digital Circuits
Function table
Clear s1 s0 A3+ A2
+ A1+ A0
+ (operation)
0 × × 0 0 0 0 Clear
1 0 0 A3 A2 A1 A0 No change
1 0 1 sri A3 A2 A1 Shift right
1 1 0 A2 A1 A0 sliShift left
1 1 1 I3 I2 I1 I0 Parallel load
第三版內容,參考用 !
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16Digital Circuits
Function Table
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17Digital Circuits
A1
A2
A0
Fig. 6.7 Four-bit universal shift register (continued)
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18Digital Circuits
6-3 Ripple Counters
Counter: a register that goes through a prescribed
sequence of states upon the application of input pulses
Input pulses: may be clock pulses or
originate from some external source
The sequence of states: may follow the binary number sequence ( Binary
counter) or
any other sequence of states
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19Digital Circuits
Categories of counters1. Ripple counters
The flip-flop output transition serves as a source for triggering other flip-flops
no common clock pulse (not synchronous)
2. Synchronous counters:The CLK inputs of all flip-flops receive a common clock
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20Digital Circuits
Example: 4-bit binary ripple counter Binary count sequence: 4-bit
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21Digital Circuits
10
10
Fig. 6.8 Four-bit binary ripple counter
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22Digital Circuits
BCD ripple counter
Fig. 6.9 State diagram of a decimal BCD counter
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23Digital Circuits
The circuit
Fig. 6.10 BCD ripple counter
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24Digital Circuits
Three-decade BCD counter
Fig. 6.11 Block diagram of a three-decade decimal BCD counter
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25Digital Circuits
6-4 Synchronous Counters
Sync counter A common clock triggers all flip-flops
simultaneously Design procedure
apply the same procedure of sync seq ckts Sync counter is simpler than general sync seq ckts
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26Digital Circuits
4-bit binary counter
C_en A0
C_en A0 A1
C_en A0 A1 A2
Fig. 6.12 Four-bit synchronous binary counter
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27Digital Circuits
4-bit up/down binary counter
up
down
down A'0
down A'0 A'1
down A'0 A'1 A'2
up A0
up A0 A1
Fig. 6.13 Four-bit up-down binary counter
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28Digital Circuits
BCD counters
Simplified functions:
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29Digital Circuits
4-bit binary counter w/ parallel load
Fig. 6.14 Four-bit binary counter with parallel load
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30Digital Circuits
Fig. 6.14 Four-bit binary counter with parallel load (cont.)
async
count load'loadc_en
c_en A0
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31Digital Circuits
Generate any count sequence: E.g.: BCD counter Counter w/ parallel load
Fig. 6.15 Two ways to achieve a BCD counter using a counter with parallel load
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32Digital Circuits
6-5 Other Counters
Counters: can be designed to generate any desired
sequence of states Divide-by-N counter (modulo-N counter)
a counter that goes through a repeated sequence of N states
The sequence may follow the binary count or may be any other arbitrary sequence
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33Digital Circuits
n flip-flops 2n binary states Unused states
states that are not used in specifying the FSM may be treated as don’t-care conditions or
may be assigned specific next states Self-correcting counter
Ensure that when a ckt enter one of its unused states, it eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation.
Analyze the ckt to determine the next state from an
unused state after it is designed
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34Digital Circuits
An example
Two unused states: 011 & 111
The simplified flip-flop input eqs:JA = B, KA = B
JB = C, KB = 1
JC = B, KC = 1
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35Digital Circuits
The logic diagram & state diagram of the ckt
Fig. 6.16 Counter with unsigned states
The simplified flip-flop input eqs:
JA = B, KA = B
JB = C, KB = 1
JC = B, KC = 1
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36Digital Circuits
Ring counter: a circular shift register w/ only one flip-flop being
set at any particular time, all others are cleared
(initial value = 1 0 0 … 0 ) The single bit is shifted from one flip-flop to the
next to produce the sequence of timing signals.
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37Digital Circuits
A 4-bit ring counter
A2 A2 A1 A0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0
Fig. 6.17 Generation of timing signals
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38Digital Circuits
Application of counters Counters may be used to generate timing signals to control
the sequence of operations in a digital system. Approaches for generation of 2n timing signals
1. a shift register w/ 2n flip-flops
2. an n-bit binary counter together w/ an n-to-2n-line decoder
Fig. 6.17 Generation of timing signals
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39Digital Circuits
Fig. 6.17 Generation of timing signals
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40Digital Circuits
Johnson counter
Ring counter vs. Switch-tail ring counter Ring counter
a k-bit ring counter circulates a single bit among the flip-flops to provide k distinguishable states.
Switch-tail ring counter is a circular shift register w/ the complement output of the
last flip-flop connected to the input of the first flip-flop a k-bit switch-tail ring counter will go through a sequence
of 2k distinguishable states. (initial value = 0 0 … 0)
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41Digital Circuits
An example: Switch-tail ring counter
Fig. 6.18 Construction of a Johnson counter
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42Digital Circuits
Johnson counter a k-bit switch-tail ring counter + 2k decoding gates provide outputs for 2k timing signals
E.g.: 4-bit Johnson counter
The decoding follows a regular pattern: 2 inputs per decoding gate
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43Digital Circuits
Disadv. of the switch-tail ring counter if it finds itself in an unused state, it will persist to
circulate in the invalid states and never find its way to a valid state.
One correcting procedure: DC = (A + C) B
Summary: Johnson counters can be constructed for any # of
timing sequences:# of flip-flops = 1/2 (the # of timing signals)# of decoding gates = # of timing signals2-input per gate
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44Digital Circuits
6-6 HDL for Registers and Counters
Shift Register
Statement:A_par <+ {MSB_in, A_par [3: 1]}
specifies a concatenation of serial data input for a right shift operation (MSB_in) with bits A_par[3 : 1] of the output data bus.
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45Digital Circuits
HDL Example 6.1
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46Digital Circuits
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47Digital Circuits
HDL Example 6.2
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48Digital Circuits
HDL Example 6.2 (cont.)
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49Digital Circuits
HDL Example 6.2 (cont.)
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50Digital Circuits
HDL Example 6.2 (cont.)
Synchronous Counter
HDL Example 6.3
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51Digital Circuits
HDL Example 6.3 (cont.)
Ripple Counter HDL Example 6.4
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52Digital Circuits
HDL Example 6.4 (cont.)
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53Digital Circuits
HDL Example 6.4 (cont.)
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54Digital Circuits
Simulation Output of HDL Example 6.4
Fig. 6.19Simulation output of HDL Example 6.4
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55Digital Circuits
Simulation Output of HDL Example 6.4
Fig. 6.19Simulation output of HDL Example 6.4 (cont.)