reliabilityyg challenges in sub 20nm technologiestinv scalinggg challenge tinv scaling severely...

Reliability Challenges in Sub 20nm y gTechnologiesTanya NigamDistinguished Member of Technical Staff

Motivation

Why do we worry about CMOS reliability?

Performance

Reliability Cost

CMOS technologies are designed to maximize performance

Reliability

at reduced cost increasing pressure on reliability

The challenge is finding the optimum trade off to be titi i th k t lcompetitive in the market place

If you are too conservative you leave money on the table !!!

If you are too aggressive you may risk your business !!!

February 21, 2015 2Confidential

y gg y y y

Tinv Scaling Challengeg g

Tinv Scaling severely limited due to BTI for sub 20 nm nodes.

Reliability aware design can alleviate the challenge3

Outline

Introduction Industry overview

Role of Reliability Engineer in Technology Development

Wh t i li d h t i t li What is scaling and what is not scaling…

Basics of FEoL Reliability MechanismsBTI BTI

HCI

TDDBTDDB

Moving beyond 20nm Product level degradation Product level degradation

New Channel materials

2/21/2015 4

The Convergence is HereThe Convergence is Here

Communication NavigationConvergence gof communications,

computing, and consumer technologies

Computing Imaging

Devices are smaller and cheaper th i i d

Entertainment Video

than ever imagined. And now these devices are

connected to the internet and run applications in the cloud.Entertainment Videoapplications in the cloud.

2/21/2015 5

Convergence Powered by Semiconductors

Wireless segment overtakes PCs in 2011g Becoming world’s leading market for semiconductor purchasing by OEMs

Sign of a fundamental shift from PCs to mobile devices

D i b b i l f t h d t bl t Driven by booming sales of smartphones and tablets

800

Unit shipment for PC versus Smartphone + tablets

500

600

700

n m

illio

ns

200

300

400

Uni

t shi

pmen

t in

0

100

200

2008 2009 2010 2011 2012

Source: IHS iSuppli, Mercury Research PC Smartphone + Tablets

2/21/2015 6

Application specific ‘tuned’ Solutions

opop

CPUHIGH HIGH PERFORMANCEPERFORMANCE

> 3GHz

Des

kto

Des

kto

1-3GHz

GamesNetworkingWatts

PERFORMANCEPERFORMANCE

MOBILE MOBILE COMPUTINGCOMPUTING DIGITALDIGITAL

Laptop, Netbooks

DTV

Graphics

U t

Tablets

COMPUTINGCOMPUTING DIGITAL DIGITAL CONSUMERCONSUMER

LOW POWERLOW POWER

Up to 1GHz

STB

Up to ‘00s mW

Feature phones Smartphones

LOW POWERLOW POWER

U t

P fP fMob

ileM

obile

Wireless Connectivity

Up to ‘0s mW

PerformancePerformanceMM

2/21/2015 7

Role of Reliability Engineers in Technology DevelopmentDevelopment

Technology TechnologyTechnology Definition

Technology Development Production

Define Technology Vmax and Tinv Overlay and

V i ti f i CD

Provide Feedback to the development line on scaling

Enable reliability support for over biasing the

Variation of via CDs worst case Min. Insulator spacing. GR must protect Min.

line on scaling trends. Validate the tends

as derived from

gtechnology Support custom

circuits and designGR must protect Min. Ins. at target Vdd+tolerance.

previous technology nodes. Develop new

methodologiesmethodologies which would help technology enablement.

2/21/2015 8

Qualification

Outline




Basics of FEoL Reliability MechanismsBTI BTI

HCI

TDDBTDDB

Moving beyond 20nm Product level degradation Product level degradation


2/21/2015 9

Three Key Technology Enablers

90nm

130nmX

0.6X80nm0.8X 65nm

0.8X45

Strained Si High k / MG Multigate

Die

Are

a 45nm0.6X

32nm0.6X

22

Rel

ativ

e 22nm0.8X

15nm

Lithography Enabled

Materials Enabled• Density

P / P f Materials Enabled

3D enabled

• Power / Performance• Cost • Power / Performance

• Strained Silicon• High K / Metal Gates

L K

• Density• Functionality• Low-K • Functionality• Integration

2/21/2015 10

HKMG in Production

Lessons learnedMaterials integration as important as materials choice g pHKMG is hard – but we have tamed the beast!

2/21/2015 11

3D Devices (FINFET/TRIGATE)

Need for low Vt and betterNeed for low Vt and better subthreshold slope drives 3D Device approach.

MOSFET becomes a resistor for short Channel lengths

d D i t ithand Drain competes with Gate to control the channel barrierbarrier.

Gate can not control the leakage current paths thatleakage current paths that are far from gate irrespective of oxide scaling.

2/21/2015 12

Device Scaling Basics

ScalingWi iV Scaling

Voltage V/

Gate Length L/Gate

Wiring

Wt

V

g

Wire Width W/

tox tox/source drain

Wtox

Diffusion Xd/

Doping Na*XdL

Scaling results in Higher Density Higher Density

Higher Speed

Lower Power

….

2/21/2015 13

Vdd and Thickness Scaling

1.5

1.6

1 2

1.3

1.4

ge (

V)

1

1.1

1.2

Vol

tag

0.8

0.9

0 50 100 150 200

?HK MGSiO2 SiON

Vdd and Tox scaling virtually stopped after 90nm technology.

f

Technology Node (nm)

Below this node the power dissipation and reliability halted further scaling and need for HK- MG became necessary.

Further material changes seem unlikely and we may again face no further u e a e a c a ges see u e y a d e ay aga ace o u eTox scaling driven by reliability unless Vdd scales with FINFETs.

14

Juse targets and implications for EM

Juse targets likely to remain similar to previous node.

Cu Cross-section could scale as much as 50% for tight pitch lower

101

glevels.

This gap must be bridged by Material engineering and more

100

d Ju

se

g gprecise accounting of EM performance; Cu-Alloy seed. (Resistivity hit, 10-1

orm

aliz

ed

y ( yindustry standard, 20 nm option)

Metal Cap. (Manufacturability and TDDB, …)

2

Juse Desired Juse based Cu scalingJuse with EM boost

N

Short line EM boosts.

Vertical current flow rules.

Redundant via array boosts.

10-2

10 20 30 40 50 60 70 80 90Technology Node (nm)

15

Outline




Basics of FEoL Reliability MechanismsTDDB (Ti D d t Di l t i B kd ) TDDB (Time Dependent Dielctric Breakdown)

BTI (Bias Temperature Instability)

HCI (Hot Carrier Injection)HCI (Hot Carrier Injection)

Moving beyond 20nmMoving beyond 20nm Product level degradation


2/21/2015 16

What is reliability?

“Reliability is defined as the probability that a given item will Reliability is defined as the probability that a given item will perform its intended function for a given period of time under a given set of conditions”

The probability is the likelihood that some given event will occur and l b t 0 d 1 i i das a measure a value between 0 and 1 is assigned

The intended function of the item and its use condition areThe intended function of the item and its use condition are specifications which need to be stated

The period of time is often referred as lifetime and depends on the items application

2/21/2015 17

Definition of failure and the various mechanism

“Failure is when the given item lost its ability to perform the Failure is when the given item lost its ability to perform the intended function within previously specified limits”

FEOL related failure mechanism in CMOS devices: Time Dependent Dielectric Breakdown (TDDB), Bias Temperature Instability

(BTI) Hot Carrier Injection (HCI)(BTI), Hot Carrier Injection (HCI)

Mobile Ion Contamination, Plasma-processing Induced Damage (PPID), Random Telegraph Noise (RTN), Electrostatic Discharge (ESD), Latch-up, Soft Error Rate (SER)Soft Error Rate (SER), …

FEOL related failure modes: Gate current increase, Threshold voltage shift, Drain current degradation, …

2/21/2015 18

Typical failure modes for reliability modelingyp y g

Gate current increase caused by dielectric breakdown sudden failure 101

) 2 sudden failure

100

10

curr

ent (

au)

Gate

V

-2-101

N(-

LN(1

-F))

Threshold oltage shift or drain c rrent degradation ca sed

1 10 10010-1

Gat

e c

Stresstime (s)

BD

p-sub

Source Drain

n+

100 101 102 103-4-3LN

TBD (s)

Threshold voltage shift or drain current degradation caused by e.g. BTI or HCI gradual failure

rent

Pre-stress: lin sat

Post-stress:lin sat

Current degradatione.g. NBTI

V

0.1

hift

(V)

Voltage shift

Dra

in c

urr lin sat

Gate

Source Drain

p+

ll 1E-3

0.01

Vol

tage

sh

D

Gate voltagep-sub

n-well 0.01 0.1 1 10 10010001E 3V

Stress time (s)2/21/2015 19

Time Dependent Dielectric Breakdown

What is TDDB?What is TDDB?

TDDB measurement methods

Challenges of detecting breakdownChallenges of detecting breakdown

BD in HK MG

2/21/2015 20

What is dielectric breakdown?

“Dielectric breakdown occurred when the dielectric has lost it i l ti t ”its insulating property”

101

au)

Constant voltage applied to MOS device

102

sta

nt

tag

eo

de BD

100

curr

ent (

a

e-trapping 100

101

Co

ns

Vo

lM

o

BDrren

t (au

) Constant Current Injection

t=0

1 10 10010-1G

ate

Stresstime (s)

e-trapping

BD0 1 2 3 4 5 6 7 8 9 10 11

10-1

10

Cu t 0

Trapping

Loosing insulting property in thick oxide means:

Stresstime (s) Voltage (V)

High current when a voltage source is connected

Small build up of voltage when a current source is connected

2/21/2015 21

Methods to study TDDB

Constant Current Stress (CCS) VI

A.Kerber/McMahon, IRPS 2012 tutorial.

Inject current and measure Voltage as function of time.

Used for thicker oxides (>~5nm) for F-N stress where QBD/TBD

dependend on J and independent of thickness.

Constant Voltage Stress (CVS)

time

V Ig ( ) Apply voltage and measure current as function of time, possibly

interrupt stress to measure current at referencecondition.

Used for thinner dielectrics stressed in DT regime where TBD/QBD d d t lt d thi k

time

depends on gate voltage and thickness.

Exponential Current Ramp Stress (ECRS) Increase injection current on an exponential scale and measure

voltage at each current level.

ln(I)

time

V

Voltage Ramp stress (VRS) Increase stress voltage on a linear scale and measure current at each

voltage, include intermittent current measurement at reference condition.

V ln(I)

ti Gaining in popularity for quick turn feedback on process learning.

For leading-edge technologies two methods, CVS d VRS f d f TDDB d li

Applied Measured

time

CVS and VRS are preferred for TDDB modeling.

222/21/2015

Degradation Modes

1 SILC

2 SBD

1. Trap generation : Vt shifts and SILC2. Formation of local conducting path

3 HBD

via the neutral electron traps leading to Soft Breakdown (SBD)3 Thermal run away leading to Hard3. Thermal run away leading to Hard Breakdown (HBD)

2/21/2015 23

Degradation Mode-SILC

T. Nigam, PhD Thesis 1999

• Signature : Gradual Increase in gate leakage at low voltage/fields• Conduction Mechanism: Trap assisted tunneling via neutral p gelectron traps generated in the bulk of the oxide.•Current voltage relationship: Exponential with a reduced barrier•Impact on Transistor : Gradual shift in Vt, gm etc..Impact on Transistor : Gradual shift in Vt, gm etc..

• Is a reliability challenge for Non-Volatile Memory devices2/21/2015 24

Degradation Mode-SBD

Signature : Sudden Increase in gate leakage at low voltage/fields


• Signature : Sudden Increase in gate leakage at low voltage/fields• Conduction Mechanism: Quantum co-tunneling arising from Coulomb Blockade or Quantum point contact

C l l i hi P l (I V)• Current voltage relationship: Power law (I=V)• Impact on Transistor : Further shift in Vt, gm etc., but transistor still functional

• May or may not be a reliability challenge for CMOS

2/21/2015 25

Degradation Mode-HBD

T Ni PhD Th i 1999

• Signature : Sudden Increase in gate leakage • Conduction Mechanism : Simple resistor


p•Current voltage relationship: Linear dependence (I=a.V)• Impact on Transistor : Transistor no longer functional

• Is a reliability challenge for CMOS• Is a reliability challenge for CMOS

2/21/2015 26

Percolation Theory

Oxide BD occurs when a conducting path is formed

Defect density reaches a critical l Nvalue NBD

NBD : an intrinsic statistical property of the oxideproperty of the oxide

NBD decreases as TOX decreases

P di t d ti i W ib llPredicts reduction in Weibull slope with TOX

Degraeve et al., IEDM, 863, 1995

2/21/2015 27

Time Dependent Dielectric Breakdown

• 2 modes for breakdown distribution2 modes for breakdown distribution• Intrinsic and Extrinsic

• Weibull distribution given by F(t)=1-exp{-(t/t63)}W(t)=Ln(-Ln(1-F))=Ln(t/t63)

2/21/2015 28

Ultra-thin Oxide BreakdownT. Nigam IRPS Tutorial 2006

(Kaczer et al. IEDM, 2004)

• Larger and smaller voltage g gacceleration measured if 1st

SBD not detected properly

2/21/2015 29

SILC in HK : Stress Induced Leakage Current

1E-4

T=125OC

2.2V2.15V 102 g

t s

T = 195 oCVs = 1.6 V 9

1E-6

1E-5

rren

t (A

)

2.15V 2.1V 2.1V 2.05V 2.0V 1.95V

101

10in

crea

sing

s

@ 0

.9 V Slope = 3.1

r, IR

PS 2009

1E-7

1E-6

Sen

se c

u

10-1

100

Slope = 2.9

T = 25 oCVs = 1.8 V

(I-I

0)/I 0

@

E. Cartier

1E-4 0.01 1 100 10000 10000001E-8

Stresstime (s)

linearcomponent

10-2

0.01 0.1 1

a)

Vt-shift (V)

TAT

( )

SILC has emerged as a new concern for HKMG (esp. nFET).

SILC is commonly attributed to Trap assisted Tunneling (TAT)

Vtshift (V)

SILC is commonly attributed to Trap-assisted Tunneling (TAT).

SILC is sensitive to IL thickness and to gate stack processing Less SILC formation for thicker ILLess SILC formation for thicker IL. At long stress times “linear SILC” seen, independent of IL thickness.

Basic TDDB Observations for HK

Significant SILC is measured on NFET during stressLarge number of defects are generated in HK.

In the literature, data is mostly collected on small areasIn the literature, data is mostly collected on small areasThe obtained Weibull slope is limited by the interfacial oxide

Weibull slope increases with area for NMOS and PMOSWeibull slope increases with area for NMOS and PMOSSee Kerber, IRSP 2009

PFET Weibull slope is less than that of NFET PFET Weibull slope is less than that of NFET See Kerber IRPS 2009

V ti l li k ll th t 1000 2 Vertical area scaling works all the way to 1000m2

Any theory proposed must explain all the above observations

3131

Nature of BD Path ChangesMC simulationsAHK=300AIL

Long BD: probability determined only by IL. =0.38x2=0.763-layer HKy

2-layer IL

ln(-ln(1-F))=2

Short BD: probability determined by

ln(-ln(1-F))=0.5

determined by complete stack. =0.38x5~1.9

ln( ln(1 F))= 2

ln(ln(1-F))=-6

ln(-ln(1-F))=-2

32

HK MG NFET Breakdown Challenge

3

3.5

40

45

e

2

2.5

30

35

We

ibu

ll S

lope

VA

E

1

1.5

20

25

10-6 10-5 10-4

For small Ifail larger and smaller voltage acceleration in SILC regime.

For large Ifail we get lower if device suffer HBD and may see an uptake

Ifail (A)

g g yin Weibull if progressive breakdown is observed.

VAE will increase with Ifail.

For intermediate Ifail Weibull slope will decrease and VAE will increase For intermediate Ifail Weibull slope will decrease and VAE will increase.

2/21/2015 33

Figure of merit for dielectric breakdown

3.4

3.6

125OC

data from A. Kerber et al., IRPS, pg. 505, 2009.

2.8

3

3.2

% (

V)

2.4

2.6

V63

%

2

2.2

pFET nFET

S l i b l k d b kd

10-2 10-1 100 101 102 1032

Gate leakage current at 2V (A/cm2)101 102 103 104 105

Strong correlation between gate leakage and breakdown voltage

V63 J d h i f BD fi f itV63 versus Jg a good choice for BD figure of merit

2/21/2015 34

TDDB Take away

TDDB is studied using CVS.TDDB is studied using CVS.

Breakdown in oxides can be either soft leading to local percolation or Hard breakdown.p

Detecting dielectric breakdown is becoming challenging as oxide is scaled.

Presence of SILC in HK MG for NFET devices makes BD detection a challenge.

Introduction of HK MG induced a new mode in breakdown distribution.

Continued scaling of dielectric leads to a reduction in lifetime TDDB.

2/21/2015 35

Bias Temperature Instability

What is BTI?What is BTI?

BTI measurement methods

Recovery in BTIRecovery in BTI

BTI in HK MG

2/21/2015 36

BTI

When the MOSFET device is biased in inversion mode the V

Stress or Sense


biased in inversion mode the device characteristics shift / degrade

Gate

Source Drain

V

en

se

g(stress condition: Vg high, Vd low)

p-sub

p+

n-wellV

Gn

do

r S

e

Magnitude of shift / degradation depends on gate t k ( t i l thi k )

1.4

1.6

1.8

au)

pre stress post stress

stack (material, thickness), voltage, temperature and time.

0.6

0.8

1.0

1.2

n c

urre

nt (

a

0.0 -0.2 -0.4 -0.6 -0.8 -1.00.0

0.2

0.4

VDra

in

G t V lt (V)Gate Voltage (V)

2/21/2015 37

Typical NBTI dataset A Kerber S Krishnan E Cartier IEEE EDL VOL 30 NO 12 pp 1347 1349 2009

From CVS Vt – time tracesvoltage and time evolution

0.1

T=125OCtdelay

=1msfit range

A. Kerber, S. Krishnan, E. Cartier, IEEE EDL, VOL. 30, NO. 12, pp. 1347–1349, 2009.

voltage and time evolution is extracted Note the sub-linear time

0.01 -1.25 V

VT (

V)

Note the sub linear timeand super-linear voltage dependence

1E 3 0 01 0 1 1 10 100 1000 10000

1E-3

-1.5 V -1.75 V -2.0 V -2.25 V -2.5 V

a)

1E-3 0.01 0.1 1 10 100 1000 10000

Time (s)

0 1

0 18

0.20

nt,

n

0.01

0.1

m = 4.16

at 1

s (V

)

0 14

0.16

0.18

me

exp

on

en

1E-3 c)

V

T a

0 10

0.12

0.14

e)

ow

er la

w ti

m

1 1.5 2 2.5 3

Gate Voltage (V)

1 1.5 2 2.5 30.10P

o

Gate Voltage (V)2/21/2015 38

BTI Degradation Metric

BTI degradation is reported either as %Ion or more commonly


BTI degradation is reported either as %Ion or more commonly as a Vt shift.

Id b i t d Id can be approximated as

For negligible gm degradation

)( tgmd VVgI 1 21.4

1.6

1.8Id

(au)

pre stress post stress

For negligible gm degradation

)())((0 tgmttgmdd

VVgVVVgII

0.6

0.8

1.0

1.2

n cu

rren

t

)(0 tgmd VVgI

)(% t

d VV

VI

0 0 -0 2 -0 4 -0 6 -0 8 -1 00.0

0.2

0.4

VDra

in

For Vnom=1V, Vt=0.3

10 V 0 01/0 7 1 4%

)( tg VV 0.0 0.2 0.4 0.6 0.8 1.0

Gate Voltage (V)

10mV 0.01/0.7 = 1.4%

2/21/2015 39

BTI measurement methods

Stress-Measure-Stress (S-M-S)

h ll i t

M D i t l IEDM 2004

challenge is to minimize delay time(intermittent Id-Vg versus spot Id)

M. Denais et al., IEDM, 2004.

On the fly method

challenge is to translate challenge is to translate current degradation to voltage shift (issue of the t0 value)

AC BTI characterization

insufficient by itselfsu c e by sefor comprehending recoverable part of degradation.

2/21/2015 40

BTI Recovers and has Permanent and Recoverable PartsRecoverable Parts

NBTI recovers

002

S. Rangan et al., IEDM 2003al. E

DL

20

g ,

G. C

hen

et

Unavoidable recovery during S-M-S

G

Unavoidable recovery during S-M-S distorts time dependence. When continuous Idlin is measured, time evolution notevolution not a simple power law

At 125C, there is “lock-in” or permanent damage that is not recovered.

2/21/2015 41

BTI recovery extended to s delay times

H. Reisinger et al., IRPS, pg. 448, 2006. Log(t) like recovery observed down to sobserved down to s delay times

log(t) recovery implies log(t) recovery implies equal amount of recovery per decade in y ptime

To accurately determine magnitude of shift, sense delay needs to be

i i i dminimized

2/21/2015 42

Challenges for dynamic BTI assessment

10-1

poly Si / SiON: T=125OC DC: -2VAC: -2V & 0V, 100Hz, 50%

0.08 DC: -2V, t=1000s,


10-2

VT (

V)

0.04

0.06

VT (

V)

10-3 10-2 10-1 100 101 102 10310-3

0 00

0.02

V

Stress time (s) 10-4 10-3 10-2 10-1 100 101 102 1030.00

Relaxation time (s)0.06

0.08

stre

ss

reco

very

1000

s

ower

-On

ift (

V)

100

0s

DC=1ms senseDC Stress=no intermediate senseAC 100H 50%≠DC St (1000 )

0.02

0.04

1000

s s

+ 1

000s

r

1000

s P

o

olta

ge s

hi

AC 100Hz 50%≠DC Stress (1000s)+ Recovery (1000s)D

C

0Hz,

50%

DC

Str

ess

Rec

ove

r y

0.00Vo

Data from GLOBALFOUNDRIES(unpublished)

AC

, 100 D

DC

Str

ess

+

2/21/2015 43

Comparison of BTI in MG/HK toconventional Poly Si / SiON gate stacks

100

1.3nm SiON / poly Si 1.6nm SiON / poly Si (S.Zafar, JAP05)2.5nm HfO / TiN (S.Zafar, VLSI06)

A. Kerber, et al., TED 2008

conventional Poly Si / SiON gate stacks

103

10-1

10

2.2nm

1 7

2.5nm HfO2 / TiN (S.Zafar, VLSI06)

HfO2 / TiN / poly Si

0 s

(V)

2.2nm1

100101102 |V

stress| = 2V @ 125OC:

1.2 nm SiON, 1000 s

2.2 nm HfO2, 10 s

1.7 nm HfO2, 100 sV

/s)

10-2

1.7

Vt)

at 1

0

10-410-310-210-1

Vt)/

dt (

V

3 2 1 0 1 2 310-3ab

s(

V

5 3 1 1 3 510-710-610-510

d(

With introduction of MG/HK into CMOS technologies PBTI has

-3 -2 -1 0 1 2 3

Vg-V

T (V)

10-5 10-3 10-1 101 103 105

Relaxation time (s)

With introduction of MG/HK into CMOS technologies PBTI has emerged as addition reliability challenge

Magnitude of PBTI similar to NBTI for technology relevant gateMagnitude of PBTI similar to NBTI for technology relevant gate stacks2/21/2015 44

NBTI versus PBTI in MG/HK

NBTI:H l t i

S. Pae et al., IRPS, pg. 352, 2008.

Hole trapping

Hole trap generation at and near Si-SiO2 interface in PFET2

Interface trap generation and corresponding mobility degradationdegradation

PBTI: Electron trapping and trap

generation in HfO2 for HKMG NFETNFET

No interface traps, no mobility degradation

2/21/2015 45

Impact of interlayer and high-k layer thickness on VRS PBTI reliability parameteron VRS PBTI reliability parameter

1 85 S. Krishnan et al., IRPS 2011. Increase in interlayer (IL)

1.75

1.80

1.85

H (

V)

y

HfO2 T

P

thickness leads to: Increase in VG to 50mV

Increase in slope (m+n)

1.65

1.70

mV

V

TH

IL T Ph

y Phy Increase in slope (m+n)

substantial improvement in operation lifetime

1 50

1.55

1.60

ConstantIL TG

to

50m

ConstantHfO T

in operation lifetime

Increase in HfO2

5 6 7 81.45

1.50

5 6 7 8

IL TPhyV

G

Slope (m + n)

HfO2 T

Phy

Slope (m + n)

thickness leads to: Decrease in Vg to 50mV

Increase in slope (m+n)Slope (m + n) Slope (m n) Increase in slope (m+n)

fairly constant lifetime at constant operating biasconstant operating bias

2/21/2015 46

Impact of CET scaling on NBTI & PBTI for Gate First and Gate Last processes

E C ti t l (i it d) IEDM 2011Gate Last processes

E. Cartier et al. (invited), IEDM 2011

Poly-Si Cap

Gate First Gate Lasta) b)

Poly-Si Cap

Gate First Gate Lasta) b)

Gate First and Gate Last process follow a

i l BTI CET

y pPC Gap Fill

MGHKIL

y pPC Gap Fill

MGHKIL universal BTI – CET

scaling trend

IL

Si

IL

Si

Exponential xBTI CET relationxBTI – CET relation makes gate stack scaling at constant gVDD very difficult

Take away for BTI

NBTI in SiON, PBTI + NBTI in HKMG.

Both show similar voltage dependence and time evolution g pincluding recovery

NBTI causes gm degradation in addition to Vt shift, PBTI only Vt shift.

Controlling measurement delays is critical for assessing magnitude of BTI and extracting the time evolutionmagnitude of BTI and extracting the time evolution

S li Di l t i thi k l d t i ifi t i iScaling Dieelctric thickness leads to significant increase in BTI.

2/21/2015 48

Hot Carrier Injection

Methods to study HCIMethods to study HCI

Modeling HCI

Challenges with HCIChallenges with HCI

2/21/2015 49

Methods to Study HCI

HCI is always studied with Vd high. V

SMU


HCI is always studied with Vd high.

Vg is a variable which needs explicit modeling for circuit level projection.

Gate

V

g p j

Typically during qualification worst case Vg/Vd ratio is tested. p-sub

Source Drain

n+V

SM

U

Two approaches for testing Constant Voltage Stress (Qualification)

R V lt St (S i /M it i )

Pre-stress characterization Ramp Voltage Stress (Screening/Monitoring)

Recovery is not typically observed in HCI and hence Stress Measure Stress

characterization

StressHCI and hence Stress Measure Stress (SMS) is used. intermittent

characterization

2/21/2015 50

Modeling Idsat degradation

T0 degradation normalization:leading to Saturation Model for

100

T

T. Nigam et al., IRPS, pp. 634, 2009.

leading to Saturation Model for HCI

nttIdId )(10-1

ed %

I DS

AT

1.6V

1 4V

1/B, B=0.01 for saturation at 100%

nd Bt

t

Id

tIdIdI

1~%100

)(%

0

0

10-2

orm

aliz

e 1.4V

1.2V NMOSV =V, %

saturation.10-3

10-1 101 103 105 107 109

N

Stress time (s)

VG

VDS

Dynamic degradation normalization

)(

)(

1

1)(

11% 00

tId

tIdIdIdtIdId

Stress time (s)

)(10

tdId

so 1/Id may be a better metric if Ni degradation1

~itN so 1/Id may be a better metric if Nit degradation dominates

2/21/2015 51

Challenges for HCI modeling as function of LgA K b /M M h IRPS 2012 t t i l

Ea changes from positive to negative


negative

Isub_max increases from Vg<Vd

to V ~VdE. Li et al. IRPS p. 4A.6 1999to Vg Vd

Peak HCI shifts from V <V toPeak HCI shifts from Vg<Vd to Vg~Vd as evident from the channel length dependence of g pIdsat

2/21/2015 52

Challenges with DC to AC Correlation for short channel HCIchannel HCI

Model 1 (see, e.g. McMahon et al. Trans. Nanotech. p. 33 2002)

Model 2 (see, e.g. Rauch IRPS Tutorial 2010)


Multiple carrier bond breaking

Single Electron Energy < Bond Energy hence multiple electrons

)

Local self-heating NBTI

Local self-heating accelerates N/PBTI process causing highEnergy hence multiple electrons

required to break bond.

But

N/PBTI process, causing high apparent degradation

ButBut Excitation time >> switching times.

But Self-heating time >> switching

times.

Quasi-static approximation breaks down. AC ≠ (i t t d) DC(integrated) DC.

All models suggest that DC HCI measurements are not ggmeaningful for AC lifetime prediction

Take away for HCI

Worst case DC hot carrier degradation shifts from Isub max


Worst case DC hot carrier degradation shifts from Isub max to Vg=Vd condition for ~ <200nm devices

BTI contributions are inherently present in advanced technology nodes (poly Si / SiON pFETs and MG/HK n/pFETs) and the separation is not trivial

Device degradation >10% only properly capture with saturation models

All models unable to capture AC to DC translation since quasi t ti i ti b k dstatic approximation breaks down

2/21/2015 54

Basic BTI/HCI projection methodology

Saturation drain current degradation at use condition translated by multiplying the current degradation at stresstranslated by multiplying the current degradation at stress condition with various acceleration factors

percentilelengthwidthtemptimeVdVgstressuse AFAFAFAFAFAFAFIdId

%)

Idstress is the current degradation atreference Vg Vd TOX T and frequently

1

10margin

egra

da

tion

(

stresstarget

AFreference Vg, Vd, TOX, T and frequentlycall the pre-factor (e.g. A) 0.1

use

n cu

rre

nt d

e

TVdVgAId

The various acceleration factors are related to the

10-1 101 103 105 107 1090.01

Dra

in

Stress time (s)

refrefrefstress TVdVgAId ,,

The various acceleration factors are related to the reference condition

2/21/2015 55

Outline



Scaling Roadmap and its enablement What is scaling and what is not scaling…

Basics of FEoL Reliability Mechanisms BTI

HCI

TDDB

M i b d 20Moving beyond 20nm Product level degradation

New Channel materials New Channel materials

2/21/2015 56

Product Reliability

Reduction in Intrinsic Lifetime with S li

ADefect Driven Wearout Scaling

Limited to no Vdd reduction with node scaling

Tinv /Design Rule @ ~ same Vdd

Higher power density: Temperature A

Early Life Useful Life End of Life

Defect Driven Wearout

More functionality, SOC complexity: Chip Area Aggressive Burn-In incorporation leads to earlier

wear-out

Enhanced product wear out correlationBC

No BI

B Enhanced product wear out correlation to Device/Circuit-level REL models Better understanding of physics of wear out

Methodology enhancements: TDDB PBD, BTI recovery EM SEB BTS SBB

With BI

B

recovery, EM SEB, BTS SBB

Design for Reliability Degradation-aware design

Increased margin to failure by circuit- and hit t l l l ti

CWearout from GOX, EM, SM, ILD BTS

Predictive capability improvement and increased design for reliability required to offset margin reduction from scaling to

architectural-level compensation

produce reliable products.572/21/2015

Enabling technology via device to circuit correlation understandingcorrelation understanding

1st Breakdown does not destroy Transistor functionality1 Breakdown does not destroy Transistor functionality

Impact of oxide breakdown on circuits then depends on post breakdown defect generation and circuit sensitivity to g yenhanced leakage. Successive breakdown and circuit implications

Multiple breakdown spots in a given area Multiple breakdown spots in a given area

Progressive breakdown and circuit implications Growth of the 1st SBD spot into HBD

Fmax guard banding critical for products Using RO degradation as proxy one can provide a DC to AC level correlation

going from device level models to circuit implicationgoing from device level models to circuit implication

SRAM sensitivity to BTI Using simple circuits like Cross coupled Inverters device degradation and g p p g

recovery in SRAM like environment can be studied

2/21/2015 58

Current jumps correlated to gate oxide BDs

A)

VOSC = 4.4 V5

10

I OS

C(m

AVINP = 0 V

0

5o

ff I

0 200 400Stress time (s)

“Satellite” spots identified as hot carrier emission by spectral and SPICE analysis

2/21/2015 59

Progressive breakdown in TDDB (HK MG)

1E-2

1E-3

Progressive BD Successive BD

1E-4

2nd BD

Progressive BD

Successive BD

1E-6

1E-5

0 1 1 10 100 1000

1st BD Suñé/Wu/Lai, TED,2004Alam, IEDM 2002

Monsieur et al. IRPS, 45, 2002,Hosoi et al IEDM 155 20020.1 1 10 100 1000 Hosoi et al. IEDM, 155, 2002,Linder/Stathis et al. EDL, 661, 2002; IRPS, 402, 2003

Progressive and successive breakdown is observed for large area devices.

Both enhance lifetime and increases Weibull slope.

2/21/2015 60

Progressive Breakdown (HK MG)

Probability Plot for C8-C10Weibull Distribution - ML Estimates - 95.0% CI

C l t D tIfail Weibull Vmax

If=10 uA

If=50uA

If=5uA

70 80

90 95

99

Complete Data

Shape Scale AD* F/C

Slope (V)

1uA 1.1 1.0

10

20

30

40 50 60

Pe

rce

nt

Shape Scale AD F/C

1.8096 7.2669 0.717 24/0

2.1433 49.980 1.06 21/0

1.3319 2.0048 1.11 24/0

5uA 1.35 1.1

10uA 1.8 1.25

1

2

3

5

50uA 2.14 1.35

Both t63 and Weibull slope increases with increase in acceptable Ifail

0.01 0.10 1.00 10.00 100.00

Time to Failure

Both t63 and Weibull slope increases with increase in acceptable Ifail.

Vmax boost of 350mV if Ifail increase to 50uA.

2/21/2015 61

Product lifetime extraction

TAP •Voltage Scaling

•Temperature Scaling10 years

BD)

•Temperature Scaling

•Area Scaling

Ln(T

B Area Scaling

•Percentile Scaling

•Percentile Scaling with n SBD or

Ln(Vg)Voper

with n-SBD or progressive SBD

Ln(Vg)

2/21/2015 62

6T SRAM Cell – role of PBTI and NBTI

Read disturb example

Wh th ll h ld t i t t ( ‘0’) WL Pullup When the cell holds a certain state (say ‘0’) PD1 and PU5 are under “DC” PBTI stress

Weaker PD1 + weaker PU6 increases read disturb PU5

WL Pullup

PU6

VDD

disturb

Increases read Vmin

Area of Focus needed

BTI(Vdd ti t d )

‘1’

U5

PG3

Access

CH

‘0’

PD2

PG4

BTI(Vdd, time exponent, and recovery)

Recovery at time scales that matter (<us)

Understanding of these mechanisms

PD1

BL

Pulldown

Access PD2

BL

better will aid in a better overall attribute for SRAMs

BL BL

2/21/2015 63

Comparison of measured and modeled CCI transfer characteristics

Simulated CCI transfer Post: Force SNL Force SNR

Pre: Force SNL Force SNR

A. Kerber, et al., IRPS 2011

characteristics using SPICE model match experimental SNL=GND

R (

V)

0 40.50.60.7

Force SNR Simulation

Force SNR Simulation

data well Based on pre- and

SN

R

0 7

0.00.10.20.30.4

post- stress device characteristics

SRAM d d i

SNL=VDD

NR

(V

)

0 20.30.40.50.60.7

SRAM degradation follows device level BTI d ift d0 5

0.60.7

SN

)

AC

0.00.10.2

drift and recovery

0.00.10.20.30.40.5

SN

R (

V)

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7-0.10 0

SNL (V)2/21/2015 64

RO Frequency Degradation

)I/I)/(I/I)/((1

f/f

T. Nigam, et al., IRPS 2009

)I/I)./(I/I)./((2

f/f dsatpdsatppdsatndsatnn

Vin=VG

NMOS HCIstress

VDDNBTI stress

• HCI Occurs only during switching and the equivalent stress time is a function of rise and fall time (teq=tuse.Z(tr/tf))

• NBTI occurs only during off state and so teq= tuse/2

2/21/2015 65

Individual Components - IIT. Nigam, et al., IRPS 2009

100%

on

60%

80%

cont

ribut

io

nbtihci(p)

20%

40%

rmal

ized

c hci(p)hci(n)

0%

20%

sec

hrs

yrs

sec

hrs

yrs

sec

hrs

yrs

Nor

10k

s

100

h

10 y

10k

s

100

h

10 y

10k

s

100

h

10 y

1.2V 1.4V 1.6V

• Process optimization needs to comprehend the individual components at the typical operating voltage

2/21/2015 66

Beyond 20nm: What’s Next?

Immersion Lithography

3D Integration

Extreme Ultraviolet (EUV)

Ultra Low-k Dielectrics

32/28nm 16/14nm45/40nm 22/20nm

Strained Silicon

High K/Metal Gate

Non-Planar Structures

Source Mask Optimization

October 17, 2011 67IIRW 2011 Keynote

14nm and Beyond

Multi-gate FinFETN t i t t t

ETSOI New transistor structure Smaller geometries Low operating voltage for

power/performance improvement

Geometrical confinement reduces leakage

Further innovationspower/performance improvement Successfully demonstrated in SRAM

Source Mask Optimization

PackagingNovel device architectures (III-V, Ge channels)

Improves pattern fidelity on wafers by computational optimization of lithography light source and reticle

Ultimate replacement for the CMOS switch

Gate

25 nm

FinFin


Summary

Semiconductor industry on path towards sub 20 nm Semiconductor industry on path towards sub 20 nm technology Key Challenges continue to be

Lithography

Material innovation and integration with an eye towards manufacturability

Building in Reliability Margins

Reliability Challenges Comprehend and model the impact of material change

Develop fundamental physical understanding Develop fundamental physical understanding

Leverage learning from other areas

Comprehend and link device level degradation to circuit level degradation

Provide designer with tools to build reliability aware designs


Acknowledgements

GLOBALFOUNDRIES FEOL Reliability TeamGLOBALFOUNDRIES FEOL Reliability Team A. Kerber, B. Parameshwaran, B. McMahon, P. Justison

2/21/2015 70

Trademark Attribution

GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners. o t e espect e o e s

©2011 GLOBALFOUNDRIES Inc. All rights reserved.

2/21/2015 71

reliabilityyg challenges in sub 20nm technologiestinv scalinggg challenge tinv scaling severely...

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