report on ical electronics to the ino collaboration

REPORT ON ICAL ELECTRONICS

TO THE INO COLLABORATION

B.Satyanarayana, TIFR, MumbaiFor and on behalf of ICAL electronics team

INO Collaboration Meeting VECC, Kolkata July 11-13, 2011

Parallel Session 1 - ICAL ElectronicsDate and time: 11th July 2011, 10am

Venue: Ajay Divatia Lecture Hall, VECC, Kolkata

Update and status of ICAL Electronics activities: B.Satyanarayana, TIFR Study of Anusparsh based front-end board with RPCs: B.Satyanarayana, TIFR Report on chip development activities at IITM: Anil Prabhakar, IITM Development of prototype RPC-DAQ module: Mandar Saraf, TIFR Feasibility studies of DRS for ICAL Electronics: Deepak Samuel, TIFR Alternate approach for ICAL backend DAQ: P.Nagaraj, TIFR Validation of ICAL trigger scheme: Sudeshna Dasgupta, TIFR Progress on ICAL power supply systems: Satyajit Saha, SINP Roadmap and action plan till the next meeting: All

2


Functional diagram of RPC-DAQ

8, LVDS pairs of unshaped comparator signals (I)

1, amplified & multiplexed RPC pulse on 50 (I)

3-bit channel address bus for multiplexer (O)

Power supplies (O) Threshold control (d.c.

or DAC bus) (O)

Front-end to RPC-DAQ bus

3


Design tools for TDC design Agreement with IMEC Already have an agreement for 0.35μm for the

front-end ASIC Now signed UMC NDA and IP agreement for

0.18μm mixed mode + RF (L180 MMRF) technology design kit & process

Europractice Faraday standard cell libraries

5

Licensed IPs


Chip design activities at IIT Madras Front end amplifier (gain ~100, BW ~500MHz) Time to digital converter (delay line based, 50ps) Analog memory (64 samples, 2GSPS, 8-bit 10MHz ADC)

Comment: Right now DRS seems a good solution. Indigenous developments with similar capabilities will be welcomed

Designs will be submitted next month (August 2011) Chips expected sometime in October 2011 Characterisation and benchmarking will follow Requested detailed specifications of all these chips FPGA based TDC efforts are in good shape – 8-channel

chip seems possible. Useful right away

7


Networked DAQ scheme Alternate to the “conventional” VME backend scheme The idea:

RPC module gets the capability to “acquire” and store its own data. Call this “Level 0” data

One “data concentrator server”, (one per N number of RPC's) collects RPC data, by either push or pull method, on master trigger. Call this “Level 1” data

One higher “Level 2” machine reads all “level 1” data

Benefits: Simple, standard, cheaper, hierarchical scheme Software development is easier Simpler data cabling (because terminated on local hubs) Interrupt driven data acquisition (level 0), client-server based DAQ (level 1),

monitoring and slow control are all handled this way Complete testing of RPC with a laptop and a HV/LV supply

8


SBC's based on ARM9 32 bit ARM9 cpu, fanless, 0.25W to 2W Board sizes 65mm x 65mm (approx) Example: Atmel Corp's AT91SAM9M10-CU,

400MHz Price: $18 per piece for MOQ of 100‘s Connectivities: Ethernet (Fast), USB, SPI General purpose digital i/o lines (few 10's of

them), 2 x 12-bit ADC 64KB ROM, 128KB RAM Linux 2.6, RTOS..

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Work to be done Study rates of data i/o in controlled network

environment, using normal servers/desktops with Linux/RTLinux

Obtain a few of the sample boards to get hands on experience

Understand network performance Integrating/interfacing, read out RPC signals

10


Trigger scheme for ICAL Validation of the trigger schemes; document in good shape Ready to go for implementation Integration issues

Segment trigger module positions Pre-trigger signal driving issues

Specifications: Coincidence window: 100ns Maximum trigger latency: 1us Singles rate for RPC detector pickup strips: 250 Hz The skew and jitter in arrival instant of the global trigger at different RPCs should be

as low possible

News: BARC team (Anita Behere et al) joined the trigger team for implementation

Document on the implementation scheme is not yet place

11


Software News: BARC team (Diwakar, Padmini et al) joined the software

team Backend Data Acquisition and Monitoring System

Event Data Acquisition Periodic Online Monitoring of RPC Parameters Event Data Quality Monitoring Control and Monitoring Console Local and Remote Consoles

Front-end firmware/software will be responsibility of the TIFR group Scope for more players (especially physicists) Technical document which will form part of the ICAL Electronics

TDR initiated

12


Power supply issues HV (RPCs) and LV (electronics)

Generation, distribution, control and monitoring (V & I) Centralised versus local (DC-DC/DC-HVDC) Solutions for both schemes identified Technical, integration and cost considerations Consolidated proposals based on prototype

development and studies are needed urgently Only then the collaboration can choose one or the

other scheme Efforts to be led by SINP, ECIL, etc. Man power requirement from SINP

13


Integration issues Mounting of electronics on top of RPC is not liked – wasting

of space/volume Suggestion to mount on the sides Increase the shamperred areas on four corners of the RPC Mount DAQ for two planes (X & Y) and power supplies (LV,

HV) in these areas Front-ends to be mounted along the planes Issue of pickup-strips to the front-end solved automatically! Modeling and prototyping in progress Industrial dimensions of glass is helping this scheme

14


More electrons well come Happy to listen to Samit Mandal’s talk It will be nice to direct and integrate these efforts

towards ICAL Electronics We all must all work in the same “cave” – the

cave where ICAL will be located There are many unclaimed areas that could be

grabbed Slow control and monitoring Signal fan-out, synchronisation and calibration

issues

15


Documentation and refereeing TDC specifications finalised, thanks for your feedback Specifications of trigger system will be announced very soon Recent work and characterisation done (ref. DRS studies etc.)

helped improve front-end specifications Reflection problem encountered during DRS studies needs

further understanding about impedance matching. Or is there something that we are missing?

Progress towards preparing the ICAL electronics document is not satisfactory. Is the end of this year a reasonable deadline?

The document should be wetted by a panel of external experts (national and international)

16


Additional tools For effective communication – among the collaborators (not chips

for a change) Anil Prabhakar proposed a package called “Redmine”. Will explore

and setup Improvements to INO Wiki were suggested BTW: If you have not subscribed to HyperNews already, please do

it TODAY – it is a pain to send mass mails, always with a potential danger of missing some key names

Please write to [email protected] with your name, affiliating institute/university, groups to be subscribed to by default etc.

Everybody will be subscribed to “News and Announcements” and “Meetings” groups by default

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mailto:[email protected]


Questions to the Collaboration Noise rates and trigger rates underground

Noise rate numbers used by SudeshnaTrigger rate numbers in the Blue bookMy proposed experiments with sealed RPCs

Pitch and number of pickup strips Area(s) of RPC gas gaps

18


19

Backup slides


Discussions at the ICAL Electronics Meeting, IIT Madras, August 9-11, 2010 Interconnection between RPC strips and preamp inputs (SINP/TIFR) Problems with FPGA TDC (Hari, Sudeshna) Problem with ASIC TDC (3rd stage interpolation, Pooja) ASIC or FPGA TDC? If FPGA TDC, can we include all other logic (+ data transmitter) into it? Can the 8-in-one FE board have TDC as well? This automatically means we will have TDC data for all channels. FE output in LVDS? Depends on the above Power supplies (LV and HV), distribution and monitoring – indigenous, commercial, semi-commercial, dc-hvdc

(SINP/VECC) Network interface from RPC to the backend: Ethernet, fibre, w/l (IITM)

Controller, n/w controller, Beegle board, Msp430 TI chip 6-9 weeks

Problem regarding FPGA as trigger element (Mandar) Calibration/synchronisation of global signals and data paths Backend standard, alternate to VME Distributed backend? Trigger system – segmentation (James, Mandar, Sudeshna, Pooja) Trigger-less system – any takers, on back foot for now? Supernova trigger? Waveform sampler (Nagendra) GPS based RTC

20


Discussions at the ICAL Electronics Meeting, IIT Madras, August 9-11, 2010 Interconnection between RPC strips and preamp inputs (SINP/TIFR) Problems with FPGA TDC (Hari, Sudeshna) Problem with ASIC TDC (3rd stage interpolation, Pooja) ASIC or FPGA TDC? If FPGA TDC, can we include all other logic (+ data transmitter) into it? Can the 8-in-one FE board have TDC as well? This automatically means we will have TDC data for all channels. FE output in LVDS? Depends on the above Power supplies (LV and HV), distribution and monitoring – indigenous, commercial, semi-commercial, dc-hvdc

(SINP/VECC) Network interface from RPC to the backend: Ethernet, fibre, w/l (IITM)

Controller, n/w controller, Beegle board, Msp430 TI chip 6-9 weeks

Problem regarding FPGA as trigger element (Mandar) Calibration/synchronisation of global signals and data paths Backend standard, alternate to VME Distributed backend? Trigger system – segmentation (James, Mandar, Sudeshna, Pooja) Trigger-less system – any takers, on back foot for now? Supernova trigger? Waveform sampler (Nagendra) GPS based RTC

21

Discussion meeting on ICAL electronics SINP, Kolkata April 29-30, 2011

Software components RPC-DAQ controller firmware Backend online DAQ system Local and remote shift consoles Data packing and archival Event and monitor display panels Event data quality monitors Slow control and monitor consoles Database standards Plotting and analysis software standards OS and development platforms


Architecture of front-end ASIC

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Amp_out

8:1 Analog Multiplexer

Channel-0

Channel-7

Output Buffer

Regulated Cascode

Transimpedance Amplifier

Differential Amplifier Comparator

LVDS output driver

Regulated Cascode Transimpedance

Amplifier

Differential Amplifier Comparator LVDS output

driver

Common threshold

LVDS_out0

LVDS_out7

Ch-0

Ch-7

C 1 2

J 7

I / P 7

1

2

SW

01

2

R 1 7

C 6

SW

11

2

U 1C L C C 4 8

lv d s _ ou t n 32 9

lv d s _ ou t p 32 8









gn d !1 9

vdd!

18

lvds

_cm

_bia

s_in

42

com

p_bi

as_i

n41

diff

_bia

s_in

40

rcm

_bia

s_in

39

vth

38

vcm

37

vss

36

lvds

_out

n135

lvds

_out

p134

lvds

_out

n233

lvds

_out

p232

dvdd

31

d g nd3 0

lv d s _ b ia s _ in43

v d d44

v s s45

in146

in247

in348

in41

in52

in63

in74

in85

v s s 16

vdd1

7

buff

_bia

s8

buff

_out

9

vdd1

10

vss1

11

S0

12

S1

13

S2

14

S3

15

lvds

_out

p816

lvds

_out

n817

R 1

+ 3 . 3V (A )

R 2R 3R 4R 5

SW

212

R 1 8

R 6R 7

P 2

R 8

R10

SW

31

2

AGR 9

C 9 C 1 0

R 19

C 1 1

L 3

AG

+3 .3 V (D )

D 1 D 2

+ 3 . 3V (A )

C 1 3

P 3

D 3 D 4

D 5 D 6

L2

D 1 8

AG

DG

C 14

L 1

10mH

10mH

10mH

C 2 5

1N4148D1-D16

10mH

10mH

AG

C 4

L 5

P 1

C 3

P 8

+3 . 3V (D )

AG

C 2 9

DG

R26

R 1 3

C 2 6

D 7 D 8

AG

D 9

AG

AG

D 10

D 1 1 D 12

D13

AG

D 14

OUT8+

D15

OUT8-

OUT1-OUT1+

OUT7-OUT7+

D 16

OUT3+OUT4-OUT4+OUT5-OUT5+OUT6-OUT6+

OUT2-OUT2+OUT3-

RPC OUTPUT SIGNAL

R 1 4

AG

DIFF

EREN

TIAL

OUT

C 20

R 2 4

C 2 1

DG

TP 6 1

R 2 3

C 2 2

AG AG AG

AG

R 2 2

DG

L4

C24 to C320.1uF

+3 . 3V (A )

R 2 1 R 2 0

C 7

C 2 3

DG

R1 to R818E

AG

+3 .3 V (A )

C 3 0

C 27

DG

AG

R 27

TP 7

1

VSS1 = Analog Ground

10mv , Tr= 10ns , C+100pf ~ 100uA

+ 3 . 3V (A )

VSS = Analog Ground

C 8

ANUSPARSH TEST BOARD

DGND = DigitalGround

AG

R 1 2

AG

AG

C 31

J 1 0L E M O

1

2

AG

+3 . 3 V (A )

D 1 7

R 1 5

P 7

+ 3 . 3V (A )

+3 . 3 V (A )

J 6

I / P 6

1

2

AG+ 3 . 3V (A )

R25

J 5

I / P 5

1

2

C 1 5

J 4

I / P 4

1

2

P 6

J 3

I / P 3

1

2

J 2

I / P 2

1

2

J 1

I / P 1

1

2

J9

J 8

I / P 8

1

2

C 1 6

+ 3 . 3V (I )

P 5

C 2

AG

+3 . 3 V (D )

J 1 1

C O N N F L E X 16

123456789

1 01 11 21 31 41 51 6

D G

P 4

+ 3 . 3V (A )

AG

AG

C 5

C 2 8

C 1 7

C 3 2

C 2 4

D 2 0

C 1 8

+ 3 . 3V (A )

C 1

AG

DG

DG

R 1 6

C 1 9

Testing of front-end board on RPC


8-channel front-end board

25


Features of the front-end board 8 amplifier + discriminator channels Gain = Output voltage/ Input current Typical gain obtained with the test setup 4-5mV/μA The designed gain was 8mV/μA; but reduced on board to contain

instability 0.1μF capacitor is placed at input as RPC strips are terminated

using 50Ω Resistors. Multiplexed buffered analog (inverted) output available

Buffered analog signal = ½ actual output (due to 50Ω termination) Comparator threshold = Voltage@pin38 – Voltage@pin9 Discriminator output in LVDS logic (4mA)

26

Linearity studies of the front-end board

Channel-to-channel gain variation is a concern


Testing of front-end boards with pulser

FEB - 1

FEB - 2

28


Work in progress and action plan Study of amplifier gain and buffer output signal linearity using

external pulser Detailed study of threshold adjustment and its stability Try finer threshold adjustment by connecting a 100KΩ resistor to

either side of P2 trim-pot (which is100KΩ) Calibration of threshold for RPC using noise rate and efficiency

parameters Integration of front-end board with RPC stack at TIFR Revision of the chip

Solve instability problem while the multiplexer is turned onSeparate chips for positive and negative inputs as well as amplifier

and discriminator might anyway solve this problem

29


Role of waveform sampler for ICAL Walk correction of TDC data Leading edge discriminator Time over threshold information Pulse profile, height and width monitoring Remote display of RPC signals

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8+1 channels, 1024 cells

700MSPS to 6 GSPS

Cascading of channels or chips allows deeper sampling depth

2.5V supply, 140 to 320mW

Multiplexed or parallel output

Differential I/O (950MHz BW)

Maximum readout of 40MHz

Specifications of DRS4 waveform sampler

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSRO UT

CONFIG REGISTER

RSRLOAD

DENABLE

W SRIN

DW RITE

DSPEED PLLO UT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

ABLE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/M UXOUT

BIASO-O FS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SHIF

T R

EGIS

TER

WR

ITE

CO

NFI

G R

EGIS

TER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS


Can be tested today on the RPC stacks Front-end board with the current board’s form-factor, but using ASICs RPC-DAQ board with:

TDC Waveform sampler Strip-hit latch and rate monitor Controller + data transreceiver Firmware for the above Pre-trigger front-end TPH monitoring Pulse width monitoring Front-end control Signal buffering scheme and GP area or ports for accommodating new blocks

VME data concentrator module Result: Complete readout chain is tested Can we use this for RPC QC test stands or what?

Proof of principle effort (RPC-DAQ) D

iscussion meeting on IC

AL E

lectronics S

INP, K

olkata, A

pril 29-30, 2011

32


Prototyping of RPC-DAQ module Using IITM designed MSP430 board Digital logic (rate scalers, latches etc.) in FPGA

on a trainer kit SPI interface between the two Serial interface between the MSP board and the

PC/host Appropriate signal translators for the existing

system Will lead to a pilot RPC-DAQ board design

33

report on ical electronics to the ino collaboration

Documents

rpc data

daq level

ical backend daq

ical electronicsdate

rpc module

kolkata update

rpcdaq bus3 design tools

multiplexed rpc pulse