reram research

IEEE.org | IEEE Xplore Digital Library | IEEE Standards | IEEE Spectrum | More Sites For Institutional Users: Institutional Sign In Athens/Shibboleth Browse Conference Publications > Solid-State Circuits Conferen ... This paper appears in: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International Date of Conference: 17-21 Feb. 2013 Author(s): Liu, Tz-Yi Sandisk, Milpitas, CA, USA Yan, Tian Hong; Scheuerlein, Roy; Chen, Yingchang; Lee, Jeffrey KoonYee; Balakrishnan, Gopinath; Yee, Gordon; Zhang, Henry; Yap, Alex; Ouyang, Jingwen; Sasaki, Takahiko; Addepalli, Sravanti; Al-Shamma, Ali; Chen, Chin-Yu; Gupta, Mayank; Hilton, Greg; Joshi, Saurabh; Kathuria, Achal; Lai, Vincent; Masiwal, Deep; Matsumoto, Masahide; Nigam, Anurag ; Pai, Anil; Pakhale, Jayesh; Siau, Chang Hua; Wu, Xiaoxia; Yin, Ronald; Peng, Liping; Kang, Jang Yong; Huynh, Sharon; Wang, Huijuan; Nagel, Nicolas; Tanaka, Yoichiro; Higashitani, Masaaki; Minvielle, Tim; Gorla, Chandu; Tsukamoto, Takayuki; Yamaguchi, Takeshi; Okajima, Mutsumi; Okamura, Takayuki; Takase, Satoru; Hara, Takahiko; Inoue, Hirofumi; Fasoli, Luca; Mofidi, Mehrdad; Shrivastava, Ritu; Quader, Khandker Page(s): 210 - 211 Product Type: Conference Publications Available Formats Non-Member Price Member Price PDF US$31.00 US$13.00 A 130.7mm 2-layer 32Gb ReRAM memory device in 24nm technology ABSTRACT ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have been used for several megabit test-chips and memory macros [1–3]. This paper presents a MeOx-based 32Gb ReRAM test chip developed in 24nm technology. Conference Location : San Francisco, CA, USA ISSN : 0193-6530 Print ISBN: 978-1-4673-4515-6 Digital Object Identifier : 10.1109/ISSCC.2013.6487703 Sign In | Create Account IEEE Account Change Username/Password Update Address Purchase Details Payment Options Order History Access Purchased Documents Profile Information Communications Preferences Profession and Education Technical Interests Need Help? US & Canada: +1 800 678 4333 Worldwide: +1 732 981 0060 Contact & Support About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies A non-profit organization, IEEE is the world's largest professional association for the advancement of technology. © Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions. NEW! 2 Additional Details IEEE Xplore - A 130.7mm2 2-layer 32Gb ReRAM memory dev... http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=648770... 1 of 1 4/29/13 9:54 AM

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IEEE.org | IEEE Xplore Digital Library | IEEE Standards | IEEE Spectrum | More Sites

For Institutional Users:Institutional Sign InAthens/Shibboleth

Browse Conference Publications > Solid-State Circuits Conferen ...

This paper appears in:Solid-State Circuits Conference Digest of Technical Papers (ISSCC),2013 IEEE InternationalDate of Conference: 17-21 Feb. 2013Author(s): Liu, Tz-YiSandisk, Milpitas, CA, USAYan, Tian Hong; Scheuerlein, Roy; Chen, Yingchang;Lee, Jeffrey KoonYee; Balakrishnan, Gopinath; Yee, Gordon;Zhang, Henry; Yap, Alex; Ouyang, Jingwen; Sasaki, Takahiko;Addepalli, Sravanti; Al-Shamma, Ali; Chen, Chin-Yu;Gupta, Mayank; Hilton, Greg; Joshi, Saurabh; Kathuria, Achal;Lai, Vincent; Masiwal, Deep; Matsumoto, Masahide; Nigam, Anurag; Pai, Anil; Pakhale, Jayesh; Siau, Chang Hua; Wu, Xiaoxia;Yin, Ronald; Peng, Liping; Kang, Jang Yong; Huynh, Sharon;Wang, Huijuan; Nagel, Nicolas; Tanaka, Yoichiro;Higashitani, Masaaki; Minvielle, Tim; Gorla, Chandu;Tsukamoto, Takayuki; Yamaguchi, Takeshi; Okajima, Mutsumi;Okamura, Takayuki; Takase, Satoru; Hara, Takahiko;Inoue, Hirofumi; Fasoli, Luca; Mofidi, Mehrdad; Shrivastava, Ritu;Quader, KhandkerPage(s): 210 - 211Product Type: Conference Publications

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A 130.7mm 2-layer 32Gb ReRAM memory device in 24nm technology

ABSTRACT

ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory,given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have beenused for several megabit test-chips and memory macros [1–3]. This paper presents a MeOx-based 32Gb ReRAMtest chip developed in 24nm technology.

Conference Location : San Francisco, CA, USAISSN : 0193-6530Print ISBN: 978-1-4673-4515-6Digital Object Identifier : 10.1109/ISSCC.2013.6487703

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IEEE Xplore - A 130.7mm2 2-layer 32Gb ReRAM memory dev... http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=648770...

1 of 1 4/29/13 9:54 AM

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