review digital logic - gunadarma...
TRANSCRIPT
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Review Digital Logic
Eri Prasetyohttp://staffsite.gunadarma.ac.id/eri
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Definisi Gerbang logika
..
..
V1V2V3
Vi
VN
Vout
Vdd
Gnd
Rangkaian logika menghasilkan sebuah nilai luaran Vout
dengan fungsi boolean masukan V1, V2, …, VN
Rangkaian logika
Vout = "1" terhubung ke Vdd
Vout = "0" terhubung ke Gnd
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Definisi Gerbang Logika
..
..
V1V2V3
Vi
VN
Vout
Vdd
Gnd
Rangkaian logika
Gnd
Vdd
..V1V2
VN
..V1V2
VN
Vout
Pmos
Nmos
Rangkaian logika menghasilkan sebuah nilai luaran Vout
dengan fungsi boolean masukan V1, V2, …, VN
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Contoh : NOR
1. Jaringan NMOS driven dan jaringan PMOS me-blok2. Jaringan NMOS me-blok dan jaringan PMOS driven
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Contoh dasar : NOR
Fungsi :
3. Va = 1 dan/atau Vb = 1
satu dari 2 transistors NMOS driven
Vout = 0
6. Va = 0 dan Vb = 0
2 transistors PMOS driven
Vout = 1
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Layout NOR
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Contoh Lain : NAND
Fungsi :
3. Va = 1 dan Vb = 1
2 transistors NMOS driven
Vout = 0
6. Va = 0 dan/atau Vb = 0
salah satu transistors PMOS conduit
Vout = 1
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Layout NAND
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??
Contoh Desain gate
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gerbang logika fungsi logika
F = A + B
Jar. N
jar. P
metodologi
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Jar. P
metodologi
skematik
Jar. N
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Gerbang Kompleks
Examples :
F = A.B.C.D
F = (A+B) . (C+D)?
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Jaringan N et P komplementer satu dari dua jaringan driven
jaringan P menggambarkan luaran 1jaringan N mempunyai luaran 0
Desain gerbang logika kompleks
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Exemple :
Rangkaian Logika
Pertama ekspresi logika , kita bangun dari jaringan transistor tipe N
S = (A.B) + (C.(D+E))
Bagaimana merealisasikan lebih lanjut ?
NMOS melewatkan arus jika luarannya = 1
S = (A.B) + (C.(D+E))
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Logika And : S = 0 jika A = B = 1
Logika OR : S = 0 jika A = 1 atau B = 1
Fungsi NMOS
2 kemungkinan : logika OR dan logika And
NMOS kondisi seri
NMOS kondisi paralel
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Desain jaringan NMOS
OR : Transistors paralelAnd : Transistors seri
S = (A.B) + (C. (D+E) )A
B
C
D E
0V
S
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Desain jaringan PMOS
Or : Transistors seriAnd : Transistors paralel
S = (A.B) + (C. (D+E) )
S
D
E
C
A B
Vdd
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Metode 2 : menggunakan metode komplemen
Desain jaringan PMOS
ingat : A . B = A + B dan A + B = A . B
S = (A.B) + (C.(D+E)) S = (A.B) . (C.(D+E))
S = (A+B) . (C+(D+E))S = (A+B) . (C+(D.E))
PMOS melewatkan jika input = 0 input = 1
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S = (A+B) . ( C + (D.E) )
S = (A.B) + (C.(D+E))
Desain Jaringan PMOS
S
D
E
C
A B
Vdd
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A
B
C
D E
Definisikan graph pd jaringan N :
Metode 3 : trace graph pada jaringan NMOS
Desain jaringan PMOS
0V
S
Puncak dari graph adalahSebuah potensial jaringan
P2P1
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A
B
C
D E
definisi graph di jaringan N :
Desain jaringan PMOS
0V
S
Puncak graph adalah Sebuah potensial jaringan
arc dari graph adalah rangkaian transistor N
P2P1
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A
B
C
D E
Graphe pada jaringan N :
hasil : 4 puncak dan 5 arcs
Desain jaringan PMOS
0V
S
P2P1
0V
S
P1 P2
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Gerbang yang lebih besar
AB
S
YMUX 2-1
Y = A.S + B.S
Multiplexers N - 1
1011
0100
1110
0101
1100Y1000S1010B1100A
Berapa banyak transistor yang diperlukan untuk merealisasikan MUX 2 - 1 ?QUIZZ
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Multiplexer 2 - 1AB
S
YMUX 2-1
QUIZZsolusi ;-)
a – belum mengerti ?
b – ini bukan untuk saya !
c – berfikir … Definisikan satu gerbang kompleks
!gerbang compleks = dirancang dari komplemen OR, AND
Diperlukan pengulangan lagi
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Multiplexer 2 - 1AB
S
YMUX 2-1
QUIZZSolusi akhir ;-)
Y = (A + S) . (B + S)
Banyaknya transistor = 3 * 2 + 2 * 4 = 14
resume3 input inverter A, B et S
4 fungsi input A, B, S et S
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Multiplexer 2 - 1AB
S
YMUX 2-1
solusi akhir ;-)
Terlalu kompleks ?
tidak ??
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Multiplexer 2 - 1AB
S
YMUX 2-1
Solusi lebih sederhana ?
Y = A.S + B.S memerlukan 8 transistors
Kita tambahkan inverter dengan dua transistortotal 10 transistors.
Tetapi apakah tidak dapat lebih ringkas lagi?QUIZZ
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Multiplexeur 2 - 1AB
S
YMUX 2-1
Solusi lain ?
Lihat fungsi logik dari MUX : Y = A.S + BS
Fungsi dari S, kita dapatkan A atau B pada luaran
A
BS
Y S mengendalikan 2 saklar masukan pada keluaran
transistors MOS tak dapat didefinisikan pada saklar ?
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Sebuah saklar bernama TG
Gerbang transmisi (TG) sebuah saklar digunakan untuk lewat atau blok sebuah signal dalam circuit
Dibentuk dari 2 transistors MOS komplementer disusun paralel
Dikendalikan oleh signal komplementer S dan S
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Fungsi dari TG
S = 0 dan S = Vdd
A B
S = Vdd dan S = 0
A B
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Layout dari TG
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A
B
SY
Multiplexeur 2 - 1AB
S
YMUX 2-1
review : methode classique desain multiplexer memerlukan 14 Transistors MOS :
6 transistors untuk input inverter 8 transistors untuk logic circuit
Methode TG : memerlukan 6 transistors
2 saklar untuk TG sama dengan 4 transistors 2 transistors signal kendali S inverter
Optimum permukaan circuit
6 Transistors
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Multiplexeur 2 - 1AB
S
YMUX 2-1
Final :
S
A
B
S
Y
TG1
TG2
TG1 passTG2 block
S = 0
Y = A
TG1 blockTG2 pass
S = 1
Y = B
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Multiplexeur 2 - 1AB
S
YMUX 2-1
Version Layout :
S
A
B
S
Y
TG1
TG2
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Multiplexeur N - 1 AB YMUX N-1
Kita dapat membuat MUX lebih kompleks :
S1-Sm
Example MUX 4-1 :
2 signal seleksi : S1, S2
2 inverter signal seleksi
8 gerbang transmisi
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dan jika kita bicara XOR ?
XOR :
Berapa transistors yang dibutuhkan XOR ?QUIZZ
AB YXOR
Y = A ⊕ B = A . B + A . B
A B Y
0 0 00 1 11 0 11 1 0
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XOR
Kita lihat persamaan akhir
Berapa transistor ?QUIZZ
Y = A ⊕ B = A . B + A . B
Y = A . B . A . B Y = (A + B) . (A + B)
Y = A . B + A . B
jawab : 4 * 2 + 2 * 2 = 12
AB YXOR
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XOR (version TG)
Apakah bisa lebih optimum
AB YXOR
A B Y
0 0 00 1 11 0 11 1 0
A = 0 Y = B
TG input B dan Y diatur oleh A pada PMOS dan A pada NMOS
2 + 2 = 4 transistors
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A = 1 Y = B
XOR (version TG) AB YXOR
A B Y
0 0 00 1 11 0 11 1 0
2 cas dissociables
2 * 2 + 2 = 6 transistors
TG input B & Y diatur oleh A pada NMOS dan A pada PMOS
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XOR (version TG)
final :
AB YXOR
8 transistors
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Optimasi kedua AB YXOR
A B Y
0 0 00 1 11 0 11 1 0
A = 0 Y = B
2 + 2 = 4 transistors
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A = 1 Y = B
XOR (version TG) AB YXOR
A B Y
0 0 00 1 11 0 11 1 0
2 + 2 =4 transistors
XOR adalah inverter !
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XOR (version TG)
final :
AB YXOR
6 transistors
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Logic Sequential
Umum
output ditentukan dari input dan et output sebelumnya
Rangkaian logic kombinatorik
memori
XyYZ
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Logic sequential
umum
Circuit logic
kombinatorik
Bistable Monostable Astable
sekuensial
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sistems bistables
sistem bistable mempunyai 2 kondisi stables
Contoh dalam digital :
(Latch, Flip Flop), register, elemen memori.
Kita lihat sistem bistable terdiri dari 2 inverter
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Contoh sistem bistable
Vi1
Vo2
VO1
Vi2
1
2
Vi1
VO1VOH
VOL
VIL VIH
Vth
Vo2
Vi2 VIH
VIL
Vth
VOL VOH
Vo2=Vi1
V i2=
V o1
Vth
VOH
VIL
VOL
VIH
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Vo2=Vi1
V i2=
V o1
Vth
VOH
VIL
VOL
VIH
Vo2=Vi1
V i2=
V o1
B
C
A
Vo2=Vi1
V i2=
V o1 A
C
B
Contoh sistem bistable
Vi1
Vo2
VO1
Vi2
1
2
Stable
Stable
δδ
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Contoh sistem bistable
Vi1
Vo2
VO1
Vi2
1
2 Vi1 Vo2
VO1 Vi2
Dalam technologi CMOS
+Vdd
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Contoh sistem bistable
Dalam technologi CMOS
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RS flip-flop
Kita modifikasi dari rangkaian sebelumnya
S R
+Vdd
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RS flip-flop
prinsip :
S R
+Vdd 2 input : S dan R
2 output : Q dan Q
RS flip-flop dalam kondisi Reset jika Q=0 dan Q=1
RS flip-flop dalam kondisi Set jika Q=1 dan Q=0
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RS flip-flop
Principe de fonctionnement :
S R
+Vdd 2 Nmos paralel 2Pmos seriQUIZZ
S
Q
RQ
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RS flip-flop
Prinsip dasar :
S
Q
RQ
input kontrol S dan R input langsung yang dipengaruhi aksi langsung dari Q dan Q
S = 0, R = 0 : Output gerbang NOR sama dengan inverter dari output kedua
(hold) dari kondisi sebelumnya untuk output Q et Q
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RS flip-flop
Prinsip dasar :
S
Q
RQ
S = 1, R = 0 :
Flip-flop di « set » sama dengan kondisi sebelumnya
output Q diforce 1 dan output Q diforce 0
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RS Flip-flop
Prinsip dasar :
S
Q
RQ
S = 0, R = 1 :
Flip-flop kondisi « reset »
output Q di force ke 0 dan output Q
di fore ke 1
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RS flip-flop
S
Q
RQ
S = 1, R = 1 :
Tidak diperbolehkan
output Q di force ke 0 dan output Q diforce ke 0
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RS flip-flop
resume :
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RS flip-flop
Dilihat dari transistor :
S R
+Vdd
M1 M2 M3 M4
M5 M7
M6 M8
M1,M3,M4 block M2 pass0100
M1,M4 pass M2, M3 block
0011
M1,M2 block M3, M4 pass
1010
M1,M2 pass M3, M4 block
0101
M1,M4, M2 block M3 pass1000
transistorsQnQnRS
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Sejarah memori
Calculus - Abaques - Bouliers …
Memori kuno
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Sejarah memori
1950 : Mémoires à tores
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sejarah
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Un peu d’histoire
50 diskDiameter 61 cm 5 Mb.
1956 : HD pertama (RAMAC dari IBM)
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Elemen memori
Evolusi pasar
Source : 1999 Technology roadmap for Semiconductors
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Elemen memori
Classificasi
memori
memori R atau ROM
SRAM DRAM
Memori R/W atau RAM
ROM
EEPROM EPROM
PROM
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