review of test strategies and resources used in high ...tames-2 d.1.1, version 1.1 testability of...

Review of Test Strategies and Resources used in

High-Resolution Interface Testing

Deliverable 1.1, TAMES-2, IST Project 2001-34283

Version 1.2, September 2002

Contact Author: Andreas Lechner

Authors: K. Georgopoulos, M. Burbidge, A. Lechner, A. Richardson & D. De Venuto1 1 On secondment from the Politecnico Di Bari, Italy

Testability of Analogue Macrocells Embedded in System-on-Chip

TAMES-2 D.1.1, Version 1.1 Testability of Analogue Macrocells Embedded in System-on-Chip

List of Content List of Content ........................................................................................................................................ I List of Figures ........................................................................................................................................II List of Tables........................................................................................................................................ III Glossary................................................................................................................................................ IV 1 Introduction and Management Summary....................................................................................1 2 Conventional ADC Test Techniques.............................................................................................2

2.1.1 Histogram Testing ............................................................................................................2 2.1.2 Servo-Loop Verification and Testing ...............................................................................5 2.1.3 Sine-wave Curve Fitting ...................................................................................................6 2.1.4 Beat Frequency Testing ....................................................................................................7 2.1.5 FFT Analysis ....................................................................................................................8 2.1.6 Summary.........................................................................................................................10

3 Review on Generic BIST Techniques for ADCs ........................................................................11 3.1 Histogram-Related BIST for Converters ................................................................................11

3.1.1 HABIST : Histogram-Based Analogue BIST ..............................................................11 3.1.2 Embedded ADC Characterisation Technique.................................................................13 3.1.3 Hardware Minimisation for Histogram-Based ADC BIST.............................................13 3.1.4 Digital BIST Technique for ADCs Containing DACs....................................................14 3.1.5 Histogram-Based BIST through Transition Computation ..............................................15 3.1.6 Concurrent Ramp Stimulus Test Evaluation...................................................................15 3.1.7 Converter BIST Scheme Including Test Stimulus Generation .......................................18 3.1.8 Partial BIST Methodology for ADCs .............................................................................20 3.1.9 Summary and Discussion on Histogram-Based BIST ....................................................21

3.2 Oscillation-Based BIST Approaches ......................................................................................22 3.2.1 Generic Oscillation-Based BIST (OBIST) .....................................................................22 3.2.2 Oscillation-Based Functional BIST for Converters ........................................................23 3.2.3 Oscillation-Based Structural BIST for Σ∆ Converters....................................................24 3.2.4 Summary and Discussion on Oscillation-Based BIST ...................................................26

3.3 BIST Approaches Related to FFT-Based Testing ..................................................................26 3.3.1 Mixed Analogue-Digital BIST (MADBIST)..................................................................26 3.3.2 BIST for ADCs and DACs in a Single-Chip Speech CODEC .......................................28 3.3.3 Pseudo-Random Patterns for Second-Order Σ∆ Modulator Test....................................29 3.3.4 Summary and Discussion on FFT-Based BIST Solutions ..............................................30

3.4 Other Converter BIST Solutions ............................................................................................30 3.4.1 adcBIST Simplified Polynomial-Fitting Algorithm for Converters............................31 3.4.2 Analogue Unified BIST (AUBIST)................................................................................33 3.4.3 Reconfiguration-Based BIST for Sigma-Delta Modulators............................................35 3.4.4 Hybrid BIST (HBIST) ....................................................................................................36

3.5 Summary ................................................................................................................................36 4 Ideas Towards an Embedded Test Solution for High-Resolution Σ∆ Converters ..................38

4.1 Facilitating the Sw-Opamp Concept.......................................................................................38 4.2 Stimulus Injection at Quantiser ..............................................................................................39 4.3 Test Data Injection at DAC ....................................................................................................40 4.4 Decomposition of Modulator..................................................................................................40 4.5 Analysis of Bit-Stream ...........................................................................................................41 4.6 Dedicated Test Solution for Input Sampling Circuitry ...........................................................41 4.7 Manipulation of Feedback Loop.............................................................................................42 4.8 Other Initial Ideas ...................................................................................................................42 4.9 Summary ................................................................................................................................42

5 Conclusions ...................................................................................................................................43 6 References .....................................................................................................................................44 Appendix A: ADC Characteristics......................................................................................................51

A.1 Characterisation of ADCs.......................................................................................................52 A.1.1 Static Performance Parameters .......................................................................................52 A.1.2 Dynamic Performance Parameters..................................................................................55

A.2 Histograms of Fault Free and Fault Affected ADCs ..............................................................57 References for Appendix......................................................................................................................60

I


List of Figures Figure 2-1: Generation of ideal linear histogram ................................................................................3 Figure 2-2: Generation of ideal sine-wave histogram .........................................................................3 Figure 2-3: Basic configuration for servo-loop testing........................................................................5 Figure 2-4: Beat frequency test set-up.................................................................................................7 Figure 2-5: Beat frequency testing ......................................................................................................7 Figure 2-6: Envelope testing ...............................................................................................................7 Figure 2-7: The problem of discontinuity............................................................................................8 Figure 3-1: HABIST scheme .........................................................................................................12 Figure 3-2: Digital BIST technique for successive approximation ADCs.........................................14 Figure 3-3: Basic principle of concurrent histogram evaluation .......................................................15 Figure 3-4: Block diagram for concurrent histogram evaluation.......................................................16 Figure 3-5: Histogram window, counter contents and clocking scheme ...........................................17 Figure 3-6: BIST technique for ADC and DAC linear histogram testing .........................................18 Figure 3-7: BIST structure containing TSG and ORA ......................................................................19 Figure 3-8: Non-ideal I/O curve ........................................................................................................19 Figure 3-9: Gain estimation...............................................................................................................19 Figure 3-10: Partial BIST scheme .......................................................................................................20 Figure 3-11: LSB linearity data...........................................................................................................21 Figure 3-12: LSB processing block.....................................................................................................21 Figure 3-13: OBIST block diagram and configuration........................................................................23 Figure 3-14: OBIST ADC test configuration (SC start conversion, EC end conversion) ...................23 Figure 3-15: ADC input voltage oscillation between VTk and VTj+1.....................................................23 Figure 3-16: Schematic of testable first order Σ∆ modulator based on OBIST method......................25 Figure 3-17: Reconfiguration of second order low-pass Σ∆ modulator to oscillator...........................25 Figure 3-18: Mixed signal IC, including DSP, Σ∆ ADC and DAC.....................................................27 Figure 3-19: Configuration and routing...............................................................................................27 Figure 3-20: Control flow for ADC test ..............................................................................................27 Figure 3-21: Configuration for BIST applied to a CODEC.................................................................28 Figure 3-22: The non-ideal second-order Σ∆ modulator model ..........................................................29 Figure 3-23: Mapping from spectral powers to SNR ..........................................................................29 Figure 3-24: Ramp stimulus response showing the four regions.........................................................31 Figure 3-25: adcBIST illustration in [LOG99] ................................................................................32 Figure 3-26: Fully differential circuit (DOP: differential operation amplifier) ...................................33 Figure 3-27: Common mode checker circuit .......................................................................................34 Figure 3-28: Block diagram of an example double loop band-pass Σ∆ modulator .............................35 Figure 3-29: BIST operation by reconfiguration of resonators and response comparison ..................35 Figure 4-1: Basic sw-opamp structure...............................................................................................38 Figure 4-2: Sw-opamp implementation.............................................................................................39 Figure 4-3: Test input at the quantiser...............................................................................................39 Figure 4-4: Test data input at the feedback loop ...............................................................................40 Figure 4-5: Combination of test signal and known transfer function ................................................40 Figure 4-6: Block diagram of Sigma-Delta modulator used in Dolphin Int. NACRE chip...............41 Figure 4-7: Basic input sampling circuitry ........................................................................................42 Figure A-1: Ideal 3-bit DAC ..............................................................................................................51 Figure A-2: Ideal 3-bit ADC ..............................................................................................................51 Figure A-3: Ideal quantisation noise ..................................................................................................52 Figure A-4: ADC with offset error.....................................................................................................54 Figure A-5: ADC with gain error .......................................................................................................54 Figure A-6: ADC with DNL deviation...............................................................................................54 Figure A-7: ADC with INL deviation ................................................................................................54 Figure A-8: Non-monotonic ADC .....................................................................................................54 Figure A-9: ADC with missing code..................................................................................................54 Figure A-10: Functional failure modes of ADCs illustrated in ramp stimulus histograms ..................58 Figure A-11: Functional failure modes of ADCs illustrated in sine-wave histograms.........................59

II


List of Tables Table 1: Example Σ∆ converter performance parameter specifications ...................................................2 Table 2: Number of samples required for DNL testing through histograms ............................................4 Table 3: Comparison of generic ADC test methodologies .....................................................................10 Table 4: Comparison of generic BIST techniques for converters...........................................................37

III


Glossary AAF Anti Aliasing Filter ADC Analogue-to-Digital Converter adcBIST Particular BIST solution for ADCs from LogicVision AGC Automatic Gain Control ASIC Application Specific Integrated Circuit ATE Automatic Test Equipment AUBIST Analogue Unified BIST BIST Built-In Self-Test clk clock signal CMOS Complementary Metal Oxide Semiconductor CNT CouNTer CODEC Device containing ADC and DAC CUT Circuit Under Test DAC Digital-to-Analogue Converter DfT Design for Testability DFT Discrete Fourier Transform DNL Differential Non-Linearity DOT Defect-Oriented Test DSP Digital Signal Processor / Processing ENOB Effective Number Of Bits FFT Fast Fourier Transform FS Full Scale HABIST HistogrAm BIST I/O Input/Output (pins or nets) IC Integrated Circuit IMEKO International Measurement Confederation INL Integral Non-Linearity IP Intellectual Property (block) LSB Least Significant Bit MADBIST Mixed Analogue Digital BIST MSB Most Significant Bit OBIST Oscillation BIST SINAD SIgnal-to-Noise And Distortion ratio SNR Signal to Noise Ratio SOC System On Chip sw-opamp switchable operational amplifier THD Total Harmonic Distortion TSG Test Stimulus Generator / Generation

IV


1 Introduction and Management Summary This document summarises the state-of-the-art in Analogue-to-Digital Converter test technology. The objectives in the publication of this deliverable is to document existing techniques, evaluate the applicability of these techniques to high-resolution analogue interfaces and define the route to re-designed existing solutions or novel new techniques.

Test strategies considered include conventional ATE based techniques, methods for improving the efficiency of testing through test strategies or design modification (Design-for-Testability), partial and full Built-in-self-test (BIST) and indirect structural or parameter monitoring techniques.

Chapter 2 documents existing ATE based test methods for converters; a summary can be found on page 10. Chapter 3 reviews existing DfT and BIST proposals for low, medium and high-resolution converters. It should be noted that the reader with limited time may wish to address only the discussion sections (pages 21, 26, 30, relevant discussion paragraphs in section 3.4) and the summary table (section 3.5, page 36). Note that all existing techniques have been considered for application to high-resolution designs. Chapter 4 documents current ideas for the way forward within the TAMES-2 project. This chapter will form the basis for further tasks of the project where results of investigations will be added. Chapter 5 presents conclusions and further background material on static and dynamic converter performance parameters and fault affected histograms are provided in Appendix A.

Since approval of the workprogram, there have been a number of discussions within the microelectronics community on issues relating to high-resolution mixed signal interfaces, mixed signal re-usable designs (IP blocks) and advanced test strategies for mixed signal blocks. At DATE 2002 [VAR02], the “Hot Topic: How to choose semiconductor IP?” addressed the issues of robust design and integration of test and repair. Although the target was memory, it was acknowledged that the philosophy should permeate through to the mixed signal community. Also at DATE2002, the embedded tutorial “The need for infrastructure IP in SoCs” [VAR02-1] addressed the need for the insertion of fault tolerant structures in IP blocks for robustness and the need for effective techniques for rapid debug and fault diagnostics. Also of interest where further requests for solving difficult test and validation problems in the front-end of the design cycle.

Finally a number of more general papers relating to TAMES-2 have been published that make interesting reading in the context of strategies for IP use, design automation in deep-submicron technologies and robustness, test integration and cost in reusable designs [CAS02, OTT02, PAN02].

1


2 Conventional ADC Test Techniques Analogue-to-Digital Converters are one of the most frequently used mixed-signal circuits. ADCs are precision products and their test usually requires high quality test equipment. With the advances of ADCs, the required test equipment is becoming increasingly expensive.

This section outlines five of the most mature ADC testing techniques and discusses their advantages and disadvantages with regard to on-chip high-resolution converter testing. A performance parameter specification for an example Σ∆ ADC is presented in the table below which will be used as a reference. Also, the specifications for the “hiCOD Virtual Component” [DOL02] are included.

Table 1: Example Σ∆ converter performance parameter specifications

Performance parameter Parameter Example specification hiCOD Input signal swing ISS +/- 2.5V +/- 2.5V Resolution N 21 bits 24/20/18/16 bits Conversion speed fADC 1-25 kHz 8-48 kHz

Five ADC test techniques are described: Histogram analysis, servo-loop testing, sine-wave curve fitting, beat frequency testing, and discrete Fourier analysis. While beat frequency testing provides a qualitative illustration for ADC failure, the remaining techniques require some data analysis involving different analysis algorithms. The accuracy of the test stimuli is crucial for all techniques.

The interested reader is referred to [BUR01, CAB99, GRO97, MAH87] where more details on the techniques outlined in this document are provided and other generic test and measurement issues are addressed. Regarding standards, the “1241-2000 IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters” is active [IEE01]. The “1057-1994 IEEE Standard for Digitizing Waveform Recorders" [IEE94] is currently withdrawn, and a revised version should become active in the near future [IEE02]. In this context, recent activities and progress may relax some of the pressing issues identified in IMEKO workshop series on ADC modelling and testing [DAL02, DAP00, DAP02, DAP96] reaching from standardisation and determination of primary test targets and (fault) models for ADCs to required new test solutions.

2.1.1 Histogram Testing

One of the most popular techniques used for external testing of ADCs is the histogram test technique [PEE83, DOE84]. It is based on a statistical analysis of how many times each digital code word appears on the ADC output, commonly referred to as code count, in order to determine the ADC characteristic parameters. Figure 2-1 illustrates the histogram generation for a 3-bit ADC when a triangular stimulus is applied; Figure 2-2 depicts a sine-wave histogram. Note that the sine-wave covers the entire ADC input range but does not cause clipping. For the ramp stimulus an ADC is assumed that computes underflow (unf) and overflow (ovf). As histogram-based testing may best illustrate failure modes of ADCs, some histograms of typical functional failures are illustrated for ramp and sine-wave input stimuli in Appendix A.2.

Generally, histograms support analysis of the converters static performance parameters. Missing bins are easily identified where the corresponding code count is equal to zero, offset errors cause a shift in the code counts, and gain errors result in a change in average code count. The converter’s linearity can be assessed via the determination of code transitions [BLA94, MAX99].

2


ovf 7 6 5 4 3 2 1 0

unf FS v(in)

code count

code

time

Figure 2-1: Generation of ideal linear histogram

76543210

amplitude

FS

v(in)

code count

code

time

Figure 2-2: Generation of ideal sine-wave histogram

A code transition voltage V can be computed when a triangular wavelet is applied to the ADC as follows: compute n1 (sum of code counts from code D and above), and n2 (sum of code counts from code D-1 and below), and then determine the location of the code transition edge, V, by evaluating:

21

12nn

nAACV+

+−= (2.1.1-1)

where C is the voltage level at the centre of the triangular wavelet, and A is ½ of the peak-to-peak amplitude of the triangular wavelet. Similarly, the code transition voltage V can be evaluated for a cosine wavelet at the ADC input:

21

1cosnn

nACV+⋅+= π

(2.1.1-2)

where C is the voltage level at the centre of the cosine wavelet, and A is ½ of the peak-to-peak amplitude of the wavelet. Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) values can be determined from transition edges, as summarised in Appendix A.1.1.

Alternatively, one can determine DNL more directly as deviation of code count divided by total number of samples from ideal, and INL through accumulating DNLs [DOE84]. Also, noise effects may be analysed by computation of a histogram for a zero input [LIS95, SCH02]. Generally, measurement accuracy may be increased through sampling of additional data or the use of different test stimuli.

Usually, the input test signal is either a linear stimulus (triangular wavelet or sequence of ramps) or a sine-wave input. The major advantage that the linear stimulus has got over the sine-wave test stimulus is that the ideal number of hits per code bin is to be constant for all codes. However, non-linearity in the stimulus would quickly accumulate and make particularly INL testing unfeasible. Obviously the stimulus must be verified and known with better precision than the converter under test. Ideally one would choose a stimulus of random voltage with an equal probability of all voltages over the converter’s input signal swing. Here the use of linear feedback shift registers to generate pseudo-random bit sequences fed to an analogue low-pass filter has attracted interest. Further investigation is required regarding the accuracy requirements on the linear feedback shift register and the filter structures.

3


Sine-wave histogram testing may also be used, as the verification of a low distortion sine-wave may be easier to achieve than verification of ramp linearity. Also, when a high-frequency sine-wave is chosen, the test has a more dynamic character than the triangular histogram test, where high-frequency stimuli are difficult to generate [BUR01]. In the case of non-equal ideal code counts, the probability density function of a sine-wave stimulus is well defined [DOE84, PEE83, VAN86]. Usually the input stimulus amplitude is chosen to slightly overdrive the ADC which avoids the large code probability caused by the sinusoid cusp, which is the relatively flat region around the sinusoid’s minimum an maximum [PEE83]. When choosing the test stimulus frequency, it has to be assured that samples are not taken repetitively at the same level. An input stimulus frequency which is a sub-multiple of the sample frequency will result in sampling of the same few codes each input cycle. Using an input stimulus frequency that has a large common divisor with the sample frequency generates similar problems since the codes repeat after each cycle of the divisor frequency. Ideally, the period of the greatest common divisor should be as long as the record length to ensure coherence [MAH87]. Any jitter in the sample timing or drift in signal frequency will just tend to randomise the sampling process.

With regard to high-resolution converter testing, a second challenge apart from test stimulus accuracy concerns the amount of data required for statistical analysis. In the appendix of [DOE84] an equation is derived to determine the number of samples required for histogram based testing. To find the minimum number of samples needed for estimating the DNL, a 100(1-a) percent confidence interval of the form [µ-Za/2σ, µ+Za/2σ] is set up. This says that the measured DNL lies in the range [µ-Za/2σ, µ+Za/2σ] with 100(1-a) percent probability. The parameter a is chosen for the desired confidence level. Za/2σ is the precision to which the measured value differs from the true value µ. The minimum number of samples Nt needed for a b-bit precision and 100(1-a) percent confidence in DNL evaluation for an n-bit converter is derived in the appendix of [DOE84] as:

2

122/ 2

bZN

na

t

−⋅⋅≥ π (2.1.1-3)

where Za/2 can be found in a table of the standard normal distribution function. A table for the required number of samples is given below for DNL testing of n-bit converters to within 0.10-bit precision with a 95% confidence. The different number of samples which may be required for DNL or INL testing including the effect of overdriving the converter with a sine-wave stimulus is evaluated in [BLA94]. The number of samples required for a noise histogram is determined in [LIS95].

Table 2: Number of samples required for DNL testing through histograms

Converter resolution (n-bit) 8-bit 12-bit 21-bit 24-bit Required samples (Nt) 109,000 1.7*106 89*106 7.13*109

The huge amount of data required for high-resolution converter test will result in an intolerable test time and with regard to a straightforward on-chip implementation will also cause a significant area overhead. In [BLA94] it is proposed to test high-resolution ADCs for a small subset of code transition levels. While some ADC architectures allow identifying a subset of code transitions which require verification, further investigation is required with regard to Σ∆ converters. In [ALE01, ALE02, MAX89] it is proposed to use small-amplitude triangular waves in histogram testing to avoid limitations in linear histogram testing caused by a limited test stimulus linearity. The basic idea is to apply the small-amplitude signal and sequentially collect histogram data in a subsection of the ADC’s input range. Different subsections of the ADC can be analysed by sequentially increasing the offset of the test stimulus.

4


2.1.2 Servo-Loop Verification and Testing

The Servo-loop verification and testing was first introduced in 1975 [COR75] and since then it has been a popular method of testing ADCs. Moreover, several techniques based on this methodology have been developed during subsequent years.

The servo-loop testing technique is based on the hypothesis / assumption that the errors of an ADC can be precisely measured for inputs near the code transition edges. A code transition edge is located where for any ADC input voltage the probabilities for occurrence of two adjacent ADC output codes are both equal to 50%. The deviation of the code transition edges from ideal indicates major characteristics of the A-to-D conversion accuracy, and may provide more accurate test results than the determination of code centres, as analysed and illustrated in [BUR01, page 454].

D

N

COMP

D<CD>=CADC

CNT C

N M-bit counterClkin Increment S Decrement S DAC

S

M

Clock TSG

Figure 2-3: Basic configuration for servo-loop testing

A basic configuration of the servo-loop method is illustrated in Figure 2-3. A feedback loop is created that forces the N-bit ADC to any desired code transition edge. The ADC input test stimulus may be generated by an M-bit DAC, as illustrated, with M>N and additional low-pass filtering may be incorporated. Alternatively, the feedback signal can be generated by an analogue integrator which integrated either a positive or negative reference voltage depending on the comparator output [BUR01, COR75]. In any case, the ADC output code D is compared to some value C. When the ADC output is smaller than the value C, the DAC input will be incremented by the M-bit counter. When the ADC output reaches the value C, the M-bit counter will decrement the DAC input. Effectively, the ADC input will oscillate around the particular code transition edge, and the value can be measured as the average voltage on the ADC input. All code transition edges can be tested by incrementing the value C from 1 to 2N-1. The measurement of the code transition edges allows to determined static performance parameters, such as offset and gain error, DNL, and INL (see Appendix A.1.1).

In practical application, the step size of the feedback loop must be chosen taking noise effects into account. The dynamics of the feedback loop with regard to this step size is analysed in more detail in Appendix A of [MAX99, MAX99-1]. The paper also provides more detail on the number of conversions that are required to measure code transition edges. The value depends on the noise of the ADC, the delay introduced by the feedback loop, the time required for the feedback loop to settle, and the number of points that must be averaged to achieve the require measurement accuracy.

In [SOU81] the application of servo-loop testing for 12- to 18-bit ADCs is described. A basic linearity test is performed on 1024 codewords formed by the ten most significant bits. The DNL is tested for 1024 randomly selected N-bit (12≤N≤18) codes to avoid escalating test time.

The main potential limitation of the conventional servo-loop test method is linked to the delay introduced by the feedback loop. For ADCs with conversion delays below the feedback loop delay, it may be difficult to achieve narrow oscillation around the code transition edge or the oscillation may even become instable. For such converters histogram testing can be more efficient. Also, the time required for the servo-loop to settle causes a significant test time contribution.

5


2.1.3 Sine-wave Curve Fitting

The sine-wave curve fitting test [IEE01, IEE94, PEE83] is based on a comparison between a digital model of the test stimulus and the actual converter response. This comparison yields a global description of the ADC, meaning that all the errors in the test measures are averaged together to give a general measurement of the ADC transfer function. The result of this test is a figure of merit referred to as the effective bits that the ADC exhibits. The intent of the test is for the effective bit number to be used as a general measure of how much the ADC non-linearity has impaired the overall ADC usefulness at specified frequency and amplitude. The number of effective bits is obtained by analysing a record of data (sequence of samples) taken when the sine-wave is applied to the converter. The analysis consists of generating a sine-wave in software that is a best-fit to the data record. Any difference between the data record and the best-fit sine-wave is assumed to be error. The standard deviation of the error is compared to the error an ideal ADC (ideal code width being 1 LSB) of the same number of bits (N) might generate:

−=

−=

12LSB

error rms actuallogerror rms idealerror rms actuallogbits effective 22 NN (2.1.3-1)

The ideal rms error corresponds to equation A.1.2-2 derived on page 55.

For a data record x1,…,xM taken at time instants t1,…,tM, a data model y1,…,yM can be defined:

( ) CPtAy ii ++= ωcos (2.1.3-2)

where A is the amplitude, P the phase and C the offset. The actual rms error can be determined to be:

( )[ ]∑=

−+−=M

iii CPtAxE

1

2 cos ω (2.1.3-3)

The minimisation of the error E is used to determine the best-fit sine-wave for a taken data record. If the frequency ω is known, the three-parameter fitting algorithm is a close-form solution providing values for amplitude, phase and offset to achieve a best-fit. If the actual frequency applied to the converter deviates from the frequency ω the three-parameter fitting will be poorer than the four-parameter fitting which is outlined next. If the frequency is unknown, four-parameter fitting is employed. Here an iterative method is used, where an initial guess for the frequency value is updated in each iteration. Potential problems due to non-convergence is mentioned in [PEE83] and discussed in [BAC99, HAE00] where some proposals for test improvements can be found. The result of the test is, as mentioned above, a single figure of merit. However, some conclusion can be drawn from the test results. The sorts of errors that cause degradation in this test are non-linearity effects, such as harmonic distortion, noise, and aperture uncertainty which may be identifiable, as explained in [PEE83]. Gain, offset and phase errors do not affect the results since they are ignored by the curve fitting process.

Some shortcomings of the test approach can be identified. Firstly, as the input stimulus frequency is a sub-multiple of the sample frequency, the same points are sampled at exactly the same voltages each cycle. In the worst case, when samples are taken in the code centres, the quantisation error would not be measured at all. Secondly, the curve fitting algorithm may not converge. Thirdly, compared to sine-wave histogram testing where the sine-wave is overdriving the ADC, the sine-wave applied in this test technique does not cover the entire ADC input range, as clipping would lead to incorrect measurements. This means that sections of the ADC conversion range are actually not tested, as described in more detail in [GIA97].

6


2.1.4 Beat Frequency Testing

Beat frequency testing provides a simple visual demonstration of individual local ADC dynamic failures [BUR00, PEE83]. An input frequency is selected that provides worst-case range changes and maximal input slew rates that the ADC is expected to see in use. The output is then viewed on a display in real time (Figure 2-4).

fs + ∆f

Memory

ADC

DAC

Time Base

fs

Visualisation of stimulus response

Stimulus Generation

Waveform recorder

Figure 2-4: Beat frequency test set-up

The name beat frequency describes the reasoning behind the test. The input sine-wave frequency is chosen to be a multiple of the sample frequency plus a small incremental frequency. Successive samples of the input waveform step slowly through the sine-wave as a function of the small difference or beat frequency. Ideally, the multiplicative properties of sampling would yield a sine-wave at the beat frequency, as illustrated below. Errors can be seen as deviations from a smooth sine function. Missing codes, for example, would appear as local discontinuities in the sine-wave. By choosing an arbitrary low beat frequency, a slow accurate DAC may be used for viewing the test output.

fs

Fsine = fs + ∆f

t

ampl

itude

∆f

∆f

Figure 2-5: Beat frequency testing

For envelope testing, instead of using a multiple of the sampling frequency, an input frequency close to half the sampling rate is used. As illustrated below, the ideal output is two out of phase sine-waves at the beat frequency. As successive samples are of larger difference than above, the ADC is assessed for dynamic performance with this technique. For visualisation, every second sample is removed before the D-to-A conversion.

fs

Fsine = fs/2 + ∆f

t

ampl

itude

∆f

Figure 2-6: Envelope testing

While FFT and histogram analyses and sine-wave curve fitting are quantitative, beat frequency and envelope testing are qualitative illustrations of the ADC’s failing.

7


2.1.5 FFT Analysis

With the advent of inexpensive digital signal processing devices, the FFT had become a commonly used measurement technique. The FFT is basically a fast way of computing the discrete finite Fourier transform of a signal which determines the amplitude of a particular frequency sine-wave or cosine-wave in a signal. The algorithm multiplies the signal, point by point, with a unit amplitude sine-wave. The result is averaged over an integer number of sine-wave cycles. If the sine-wave is not present in the signal being analysed, the average will tend to zero.

The Fourier transform of a signal x(t) is defined as:

( ) ( )∫+∞

∞−

⋅⋅⋅⋅−= dtetxfX tfi π2 (2.1.5-1)

whereas the discrete finite Fourier transform (DFT), used for sampled data, is:

( ) ( ) ( )∑−

=

∆⋅⋅⋅⋅− ∆∆=1

0

2M

m

tmfi tetmXfXD π (2.1.5-2)

While X(t) has infinite spectral resolution, XD(f) has a discrete frequency resolution of f = 1/M∆t. Since the DFT assumes that the record repeats with a period of M∆t sharp discontinuities at the points where the start of one record joins the end of the preceding record (Figure 2-7) cause the spectral components of X(f) to be spread or smeared in XD(f) [CAB99, MAH87, PEE83].

Signal to be analysed

Signal acquisition block

Signal analysis block

Signal as it appears in analysis buffer

Figure 2-7: The problem of discontinuity

For the reduction of the leakage a suitable windowing function is performed. Commonly used windows are discussed and illustrated in [CAB99]. The Fourier transform of the Hann window (commonly used with sine-waves), for example, shows the main lobe twice as wide as that for the rectangular function, while the amplitudes of the side lobes decay by 18 dB/octave. The reduced level of the side lobes reduces leakage, but the wider main lobe limits the ability to resolve closely spaced frequencies [BUR01].

Another major characteristic of this technique concerns the Nyquist criterion. If X(f) contains components that exceed the Nyquist frequency Fs / 2, then these components are folded back, or aliased, onto spectral lines below Fs / 2 causing aliasing errors. The end result is that the spectrum of XD(f) is displayed only from DC to Fs / 2 and the maximum input frequency must be limited to less than Fs / 2 to avoid aliasing.

8


The noise floor, the harmonic level and the spurious level are three DFT spectrum features, which provide useful information about the ADC’s performance. Two classes of noise sources determine the level of the noise floor. The first is the quantisation noise and is the error, bounded by ½ LSB that is due to the quantisation of the input amplitude into discrete levels. The second is non-ideal noise sources such as aperture uncertainty and code discontinuities.

The second feature of the DFT spectrum that indicates the ADC’s level of dynamic performance is the harmonic content. Static and dynamic integral non-linearities cause curvature in the ADC’s transfer function. If the input frequency is much less than the Nyquist frequency, than the harmonic components will appear at multiples of the input frequency. On the other hand, if the harmonics of the input frequency are greater than Fs / 2, then these frequencies will be aliased on top of components below Fs / 2. In actual practise, the frequency should be chosen so that the harmonics are far enough away to be easily resolvable from the fundamental, whose energy has been spread into several adjacent bins by the windowing process.

The third feature of the DFT spectrum is that of the spurious level. Spurious components are spectral components that are not harmonically related to the input. A good example is that of a strong signal near the ADC that may somehow contaminate the ADC’s analogue ground and appear in the spectrum.

The signal-to-noise ratio (SNR) is used for a generic representation of all the above error features and the quantitative estimation of their effect on the converter performance. An ideal N-bit ADC (having quantisation noise only) is known to have an SNR equal to (6N + 1.8) dB. For a real ADC, the difference in SNR compared to ideal indicates the contribution of other noise sources. A quick evaluation of DFT results to assess ADC dynamic performance is described in [PEE83] and DFT plots are provided in [BUR00]. If all harmonic and spurious components are at least 6N dB below the full-scale amplitude of the fundamental frequency, then the ADC is performing satisfactorily since each error component has a peak-to-peak amplitude smaller than an LSB. However, if these components are less than 6N dB below the fundamental component or if the noise floor is elevated, then other tests may be performed which test for non-linearity more directly, such as histogram testing.

Appendix A.1.2 provides definitions for the dynamic performance parameters which can be determined through FFT analysis. Also the analysis of the frequency spectrum to determine the SNR, the Signal-to-Noise And Distortion ratio (SINAD) and the Total Harmonic Distortion (THD) is outlined.

9


2.1.6 Summary

In this chapter, the main conventional ADC test approaches are outlined. Main characteristics are discussed for each technique. Table 2 provides a brief summary regarding the five converter testing techniques.

Regarding a potential on-chip test solution for high-resolution converters, each technique has a number of limitations. Histogram testing, for example, will require a large amount of data to be stored and evaluated on-chip while requiring large test time. For servo-loop based solutions, the oscillation around a single transition edge may be difficult to achieve under realistic noise levels. Sine-wave fitting will require some significant area overhead for the on-chip computation, as do FFT-based solutions, and may still not achieve satisfying measurement accuracy and resolution. Further work is required to quantify test times, associated cost and measurement accuracies.

Some recently published BIST techniques are reviewed in the following chapter, focusing on ADC test solutions. These will be classified regarding their correlation to one of the conventional testing techniques.

Table 3: Comparison of generic ADC test methodologies

Technique Performance parameters tested

Major advantages Main limitations

Histogram-based

Static performance parameters (offset and gain error, DNL, INL, missing codes, and others)

Well-established, Complete linearity test

Long test time, Huge amount of data, No test for dynamic performance, Test stimulus accuracy

Servo-loop Static performance parameters (offset and gain error, DNL, INL)

Accurate measurement of transition edges (not based on statistics)

Test stimulus accuracy Measurement accuracy

Sine-wave curve-fitting

DNL, INL, missing codes, aperture uncertainty, noise

Tests for dynamic performance

Input frequency is a sub multiple of sample frequency, Lack of convergence of the curve fit algorithm, measurement accuracy

Beat frequency testing

Dynamic characteristic Quick and simple visual demonstration of ADC failures

No accurate test

FFT-based Dynamic performance parameters (THD, SINAD, SNR, ENOB)

Tests for dynamic performance, Well-established

No tests for linearity

10


3 Review on Generic BIST Techniques for ADCs This chapter provides a review on published and some commercialised BIST solutions for A-to-D

converters. Section 3.1 includes a number of BIST techniques which are related to conventional

histogram testing. Test methodologies which are oscillation-based are reviewed in section 3.2, where

most techniques are purely defect-oriented and one solution employs conventional servo-loop testing.

BIST structures which include an FFT analysis are discussed in section 3.3, while other BIST

approaches are included in section 3.4. The review is summarised in section 3.5.

3.1 Histogram-Related BIST for Converters A histogram represents circuit activity statistically and can be compared against a reference histogram to extract gain, offset, noise and distortion errors affecting the analogue or mixed signal circuit (section 2.1.1). Frisch and Almy published their Histogram-based Analogue BIST (HABIST ) at the ITC’97 [FRI97]. HABIST is currently commercialised by Fluence Technology [FLU00, TUR01, TUR01-1] and is possibly the most straightforward implementation of on-chip histogram testing. The second technique (section 3.1.2) is very similar, while the third technique aims at area reduction for a full histogram test solution. The approaches reviewed from section 3.1.4 onwards, however, do not test the ADC activity in a purely statistical manner. In most of these cases a single ramp is applied to the converter, where the linearity is tested by measuring the code widths. These techniques may seem related to the servo-loop test method, as transition voltages may be monitored, however, the test stimulus is not altered by a feedback loop, which is the essential characteristic of servo-loop testing. An extension to testing multiple ramp or saw tooth periods in order to accumulate a statistical representation of the converter activity externally may be viable for some single ramp test techniques. While each technique is discussed separately, common characteristics especially with regard to the application to high-resolution converters are discussed in section 3.1.9.

3.1.1 HABIST : Histogram-Based Analogue BIST

For ADC testing, the statistical representation of circuit activity can be gathered for predefined ranges. Typically for converters, each range corresponds to one digital output code, and the number of occurrences (code count) holds statistical data. For test evaluation, the CUT’s histogram can be tested to remain within a predefined range, where a signature may be used for pass/fail tests. The test algorithm contains the following steps and sequences:

1. Generate histogram for expected signal (and for all desired conditions of test stimulus)

2. Determine the range of offset, gain, noise and distortion variance

3. Provide accessibility to each test point

4. Generate the histogram of the signal at each test point for the CUT

5. Extract the difference-histogram signature by processing the acquired histogram

6. Obtain a signature that can be used as both pass/fail test or as a basis for diagnosis

By comparing the reference or expected histogram (HEXP) and the histogram of the CUT (HCUT), differences between these can be analysed to obtain data on offset component, gain error or noise. The

11


HABIST approach (Figure 3-1) is not limited to a specific test stimulus, however, typically a sine-wave or ramp stimulus is applied.

TSG optional DAC CUT S&H,

ADC histogram generator

HEXP difference compress,encode

test clock

signature of CUT

Figure 3-1: HABIST scheme

The histograms can be analysed for the following performance parameters:

• Offset Error: The offset component is determined by calculating the difference between the centroids of both histograms. Prior to any other evaluation, the offset error is eliminated by subtracting it from the expected histogram.

• Gain Error: Minimising the variance between both histograms, by changing the range of data in the CUT’s histogram, determines the gain component. Prior to any other evaluation, the gain error is eliminated by multiplying the expected histogram by the range ratio.

• Noise: Subtracting an estimated noise level from the CUT’s histogram and evaluating the difference to the expected histogram results in a histogram containing information on local distortion. The histogram can also be used to extract clipping and crossover measurements.

In [FRI97] several difference histograms are depicted for a sinusoid and a square wave some of which are included in Appendix A.2. These can be analysed and allow the diagnosis of the faulty behaviour (classification as clipping, crossover, noise, tilt, overshoot etc.).

HABIST Implementation

To accumulate a histogram of 8-bit samples in 32 bins on-chip, a 32 bytes RAM and an XOR gate have to be added. The histogram can be analysed by the use of a histogram processor which can realise read-modify-write cycles on the bin data. The area overhead could be reduced by sharing the HABIST processing hardware for a number of analogue or mixed signal components or within a multi chip module. In [ALM99] the approach is described with a software solution for the evaluation of signal amplitude, offset, clipping and crossover distortion measurements.

A potential limitation for a full BIST implementation may be the size of the RAM required to accumulate the histogram of the CUT. The reference histogram also has to be stored on-chip. Finally a stimulus generator has to be added to implement a full BIST structure.

Discussion

The HABIST is the only commercialised histogram-based BIST technique. It is the most straightforward implementation of testing through statistical verification of converter activity. However, the area overhead for collecting histograms and storing reference histograms on-chip will be excessive, especially for high-resolution converters. Also, requirements on the test stimulus accuracy need to be discussed, which is especially the case, as the issue of stimulus generation is not discussed in the publications. Aspects regarding the application to high-resolution converters are discussed in section 3.1.9.

12


3.1.2 Embedded ADC Characterisation Technique

A similar histogram-based data optimisation technique has been published in [RAC95, RAC96, RAC96-1]. The main histogram test problem has been identified as an observability limitation. The amount of data required for histogram evaluation is difficult to shift off-chip. Data compression and the use of on-chip test stimulus generator for triangular waveforms is proposed and investigated. A triangular waveform is generated on-chip from a pulse sequence and applied to the ADC under test via an analogue multiplexer. The histogram is collected in a RAM where the ADC’s output data acts as an address and memory cell contents are incremented on code occurrence. The amount of data serially shifted out to the ATE is therefore significantly reduced.

Off-chip histogram data analysis is performed by comparison against an ideal reference histogram obtained from a software ADC model. For noise analysis, a reduced number of samples is taken to avoid averaging of noise effects. The obtained data is compared against histograms generated by the ADC model which can also take expected noise levels into account. It is noted that comparing an ideal to a noise-affected transfer curve (both obtained from the ADC model) will establish relationships between histogram, simulated noise levels and their effect on the SNR. Hence a histogram plot obtained can be analysed for noise effects which allow determination of the SNR. However, process and device parameter deviations are not modelled in the ADC software model.

Discussion

Main limitations for the HABIST hold for this technique as well. Furthermore this technique does not evaluate the test response completely on-chip and further off-chip analysis is required. Aspects regarding the application to high-resolution converters are discussed in section 3.1.9.

3.1.3 Hardware Minimisation for Histogram-Based ADC BIST

Renovell et al. presented an approach for an on-chip output response analyser for histogram-based testing [REN00, AZA01-1, AZA01-3]. The aim is to further reduce area overhead compared to the HABIST concept. The output response analyser provides information on ADC offset, gain and non-linearities. When a triangular test stimulus is applied, the offset can be obtained by calculating the difference between the two extreme bin counts. The gain is extracted by comparing a number of non-extreme bin counts against their ideal values. The average difference is the reverse of the gain error, with accuracy increasing with the number of bins analysed. The DNL is evaluated for each code from the relative bin count deviation from the ideal. The INL is estimated by adding DNL figures from both current and previous codes.

A time decomposition has been proposed to reduce area overhead. When the triangular waveform is applied, the number of occurrence is counted sequentially for each code word separately. All parameters are calculated and accumulated phase-by-phase. The hardware required is reduced to a comparator, a counter, a register, an adder/subtractor, and a small control unit. The authors propose the same technique for output response analysis of histograms obtained for sine-wave input stimuli [AZA00]. The basic assumption is that the offset can be extracted from the extreme bin counts, and the gain can be estimated by evaluating the bin counts in the linear region around the centre code in the same way as for ramp stimuli. A suitable test stimulus generator has been proposed by the same authors [AZA01, AZA01-2, BER01]. It is based on a MOS transistor current source, controlled by its gate to source voltage. It is proposed to modify this control voltage (VCTRL) to compensate for process parameter spreads by using a cyclic DAC based on charge distribution between two capacitors. An extension to a triangular-wave generator is published in [BER02].

13


Discussion

The trade-off between reduced area overhead and increasing test time needs to be analysed in more detail. The technique seems limited to low-resolution and high-speed ADCs. Higher resolution and slower conversion will result in escalating test time due to the time decomposition applied. Also the area overhead for the test stimulus generator needs to be considered. Computing more than one bin count at a time by investing more area may provide some trade-off to control test time. Other aspects regarding the application to high-resolution converters are discussed in section 3.1.9.

3.1.4 Digital BIST Technique for ADCs Containing DACs The first single ramp test BIST approach reviewed is based on re-use of the DAC contained in the ADC under test has been published [EHS96, EHS98]. The technique is limited to low to medium speed ADCs and requires a small area. INL, DNL, gain and offset error can be extracted.

An n-bit ADC under test consists of a comparator, a DAC, decision logic and decision registers. The converter can be set into a test configuration, where the internal DAC resolution is increased by one. To implement the test stimulus generator, an (n+1)-bit counter is connected to the DAC in test configuration and the DAC output is saved in a sample-and-hold circuit (S&H). The generated analogue voltage is then applied to the ADC in functional configuration. The aim is to compute the ADC’s transition edges in order to determined linearity errors by using the higher-resolution DAC to generate the input voltage sequence. The routine is based on relative error detection at the digital ADC output. While the digital value held in the counter is understood as a representative for the real converter characteristic, the ADC output is interpreted as the ideal characteristic of the CUT.

For each BIST cycle, the converter is put into its test configuration and an input voltage is generated while the counter content is saved in a register. In the following step, the converter is in functional configuration converting the sampled voltage and the ADC output is stored. If the new ADC output is larger than the previous output, a transition edge has been detected; otherwise the routine is repeated with incremented counter content. The extraction of performance parameters from measured transition edges is described in detail in [EHS98].

S1

functional configuration

COMPS&H

n)-b

it

Decision Logic clk

Decision Register

n

MUX1

n+1 bit CNT registers & subtractor

Digital BIST DNLmax INLmax OE GE

s

n

n+1

MUX2MSB

n

n

original ADC components

BIST components

test configuration

in

S2

(1+

DAC

test

test

test

test MSB

Figure 3-2: Digital BIST technique for successive approximation ADCs

Discussion

The main problem with this technique is the use of the CUT itself for stimulus generation and clearly limited measurement accuracy. It should be assumed that this technique results in fault masking, especially as INL and DNL have been defined for the entire D-to-A-to-D loop. Additionally the performance of the sample and hold circuitry needs to be analysed taking leakage effects into account. Further investigation is required regarding realistic measurement resolution and accuracy, as the DAC facilitated for stimulus generation has a resolution of (n+1) bits only. In addition to the limitations discussed in section 3.1.9, this approach is not suitable for high-resolution converters, as noise effects will prevent the computation of transition edges.

14


3.1.5 Histogram-Based BIST through Transition Computation

Another histogram related BIST solution testing static performance parameters is proposed in [WEN00]. On the test stimulus generation side, a ramp stimulus is generated by a differential integrator where the ramp is sectioned into 2n+1 segments over the n-bit ADC’s input range. When the ramp stimulus is applied to the ADC under test, the ADC output is compared to the output of an (n+1)-bit counter.

In test mode, the counter outputs serve as the references for the output response analysis when the ramp stimulus is synchronised with the counter outputs. The counter is incremented at twice the ADC sampling frequency. When a transition at the ADC output is observed the current counter content is used to determine code widths and INL from the number of occurrences for the previous ADC output code.

Discussion

The publication is not reviewed with great detail in this document, as the test (evaluation) technique is very similar to the previous approach. Again measurement accuracies are unsatisfying (ideal accuracy of ½ LSB). These will decrease further if linearity limitations in the ramp stimulus are taken into account.

3.1.6 Concurrent Ramp Stimulus Test Evaluation

While full histogram BIST results in a large area overhead (section 3.1.1) and the time decomposition technique results in an escalating test time (section 3.1.3), another histogram related test approach is currently under investigation at Lancaster, which avoids either of these major drawbacks. The essential idea is to compute the number of all code occurrences within a code or histogram window which is adjusted over time. The technique is aimed to test low resolution, high-speed ADCs, in the particular case a 6-bit folding and interpolating ADC with a sampling frequency of 330 MS/s.

Two major principles can be identified. Firstly, to reduce test time and to avoid non-coherent sampling, the histogram for a single ramp input stimulus has to be computed. Secondly, to achieve minimum area overhead, the converter’s histogram has to be gathered concurrently where a histogram evaluation window around expected ADC output values is adjusted during test. The principle of the suggested concurrent histogram evaluation is illustrated in Figure 3-3.

3bitCW_ CNT1

3bitCW_ CNT3

3bitCW_ CNT4

3bitCW_ CNT2

ADC

COMP D>C+2D=C+2D=C+1

D=CD=C-1D<C-1

window control macro

CW

_max

+1

CW

_dat

a

6bit CNT

C 6

Counter Chain

OF CNT1CNT2CNT3CNT4UF

evaluation macro

Load operation

D 6

Figure 3-3: Basic principle of concurrent histogram evaluation

The main output response analysis blocks are a window control macro and an evaluation macro. Within the window control macro, each ADC sample (D) is compared to an expected output (C). The number of code occurrences, corresponding to the code width is computed within the evaluation

15


macro. As illustrated above, the evaluation macro contains a chain of counters which are used to compute the number of occurrences of an expected ADC output. When a new ADC output is available, the window control macro will enable a decrement in one of the evaluation macro’s counters. Here, the assumed maximum tolerable code width for an ADC under test equals seven samples. As illustrated in a more detailed block diagram in Figure 3-4, the histogram window is adjusted by the window control macro when two consecutive ADC output codes larger than the expected value have been evaluated. When this is the case, the signal incr becomes high and a load operation is performed on the four 3-bit counters and the code width data latch 3bitLAT. Effectively, code width data are right shifted during the load operation. At the same time, the 6-bit counter that holds the expected ADC output has to be incremented, and the available CW_data can be analysed.

d5 D<C-1d4 D=C-1d3 D=Cd2 D=C+1d1 D=C+2d0 D>C+2 c5 c4 c3 c2 c1 c0

clkc

6bit COMPD

C

clka

Clock Generator r_t: reset test p_w: preset window incr: increment signal

clka: ADC clock clkc: comparison clock clkw: window control clockclke: evaluation clock

r_t clke

6bit CNT1

delay delay delay delay

clkc

clkw

clke

r_t clkw

1bitLAT

p_w d1 q1

r_t clke

3bit CNT1

EN LOAD DO d1 q1d2 q2d3 q3

CW

_dat

a

CW

_max

+1

r_t clkw

1bitLAT

d1 q1

UFr_t clkw

1bitLAT

d1 q1

OF

1

q5 EN q4 q3 q2 q1 q0

r_t clke

3bit CNT2

r_t clke

3bit CNT3

r_t clke

3bit LAT

EN d1 q1 d2 q2 d3 q3



p_w

1 1

window control macro

evaluation macro

Incr

r_t clke

3bit CNT4

EN LOAD DO d1 q1 d2 q2 d3 q3

1

clkl

code_C+1 code_C code_C+2

code_C-1

Figure 3-4: Block diagram for concurrent histogram evaluation

The diagram below illustrates the clocking scheme and the content of the 3-bit counters for the concurrent histogram test concept when a ramp stimulus is applied. The upper part of the figure shows the ADC ramp response and the histogram evaluation window over time. In the example, an ADC input stimulus is defined to allow sampling each output code four times in the ideal case. When a code width of 7 samples is interpreted as the upper code width test boundary (CW_max), the use of 3-bit counters is sufficient for the concurrent histogram testing scheme. As the 3-bit counters are initialised to all-one in this case, an all-zero in a particular set of captured CW_data means that the corresponding code width is larger than 7 samples. Otherwise the corresponding code width can be determined in the range of 0 to 7 samples, and INL can be computed by accumulating the code width deviations. Note that simple digital circuitry can be added to the evaluation macro for accumulation of code width deviations, the comparison to test thresholds stored on-chip for code width and INL tests, and failure diagnosis. When an INL failure is detected, for example, the corresponding ADC output code could be stored and also (where the stimulus is generated by a DAC) the corresponding input could be provided with the BIST results.

When the stimulus response of a CUT is outside the histogram window, a flag will be set in the UF or OF bit (Figure 3-4). In such cases, non-monotonic behaviour is detected in excess of a 2 LSB decrease (UF = 1) or the slope of the ADC transfer curve exceeds an increase of 2 LSB in two consecutive samples (OF = 1). Where wider test thresholds have to be applied, such as for high-resolution ADCs,

16


the number of counters in the evaluation macro has to be increased. For a 16-bit ADC, for example, noise with an amplitude of 2 LSB has to be expected [SUN01]. In this case, 6 counters will have to be included in the evaluation macro; the corresponding wider histogram window is also included in Figure 3-5.

D (ADC output)

histogram window for 4 3-bit counters histogram window for 6 3-bit counters

ADC sample point clkc comparison clock clkw window control clock clkl delay of clkw incr increment & shift

time

001001001000000111000011000010000001000000

unf

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 CNT1 7 7 7 7 7 7 7 7 7 6 5 7 7 6 5 7 7 6 5 7 7 CNT2 3-bit 7 7 7 7 7 6 5 4 3 3 3 4 3 3 3 4 3 3 3 4 3 CNT3 counter 7 6 5 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CNT4 contents 0 0 0 0 0 0 0 0 0 0 0 3 3 3 3 3 3 3 3 3 3 LAT

analyse results

C for 4 3-bit counters C for 6 3-bit counters

clke evaluation clock

Figure 3-5: Histogram window, counter contents and clocking scheme

Regarding the test evaluation, the technique has to be understood as an embedded test solution rather than a full BIST technique. The motivation for this work was to relax the speed requirements for test data capturing through digital DfT structures and ATE. The aim is to provide a sequence of code counts to the ATE, which can be analysed for DNL, INL, offset and gain error off-chip. Ongoing work is addressing the test solution for a periodic saw-tooth test stimulus. Again, a sequence of code counts will be passed to the ATE which can be accumulated off-chip to apply a full histogram test.

Discussion

This work is aimed at high-speed converter test, in the particular case a 6-bit folding and interpolating ADC. As most other techniques reviewed in this deliverable, the proposed technique has to be understood as an embedded test solution rather than a complete BIST scheme. Regarding the applicability of this technique to high-resolution converter testing, the main challenge may be found in the generation of very high-resolution test stimuli. Also, it has to be born in mind that the test time compared to conventional histogram-based test will not decrease unless fewer ramp (or saw-tooth) periods have to be applied. This, however, will not be possible when high measurement accuracy is required, as noise effects and jitter will directly degrade the measurement. With regard to the high-speed target converter it is possible to detect failure modes even when DNL and INL testing does not lead to test failure, as particular failure mode characteristics can still be identified through a specific number of local code width maxima and minima (for failure modes [LEC01]).

17


3.1.7 Converter BIST Scheme Including Test Stimulus Generation

While most histogram-based BIST techniques require an additional high-resolution DAC on-chip or appropriate off-chip stimulus generation, the approach published in [CHE99, HUA00] incorporates a test stimulus generator composed of a pattern memory and a simple 1-bit DAC. The structure illustrated in Figure 3-6 is capable of testing an ADC or DAC for linearity by applying linear histogram computation.

load incr

only for DAC testing

BIST component

Converter under test

only for ADC testing

1-bit DAC

1-bit pattern memory LPF

+COMP- DAC

pattern counter

data

reset acquire

index counter

code / index

memory MU

X

ADC

control logic

Figure 3-6: BIST technique for ADC and DAC linear histogram testing

On the stimulus generation side, the 1-bit pattern memory holds a test pattern generated by a software sigma-delta modulator model for the desired stimulus. The pattern contains an integer number of test stimulus periods and is applied to a 1-bit DAC followed by a low-pass filter (LPF).

For ADC testing, the stimulus (covering the entire input signal swing) is fed to the converter under test and code occurrences are computed in the code/index memory. No further test response analysis is performed on-chip, DNL and INL values can be computed as in conventional linear histogram testing within the ATE.

For DAC testing, the converter is stimulated by a (pattern) counter. In DAC testing, a particular input word is applied to the DAC, and its output is compared to the ramp stimulus generated as described above. As long as the analogue comparator output is low (constant DAC output larger than ramp stimulus), the index counter performs a time measurement which can be related to the DAC’s code width. The comparator output switches to the high state when the ramp stimulus exceeds the DAC output. Now the content of the index counter is loaded to the code/index memory, the DAC input is incremented and the index counter reset. If the comparator output is able to return to its low output before the next positive edge should arise, then testing can continue in the same manner. Otherwise the index count may have to be performed in a sequential manner. Again, as for ADC testing, the complete test response analysis to determine DNL and INL values is performed off-chip from the code widths (measured in time).

The achievable measurement or test accuracy mainly depends on the inherent quantisation error (in the DAC time computation or ADC code count) and the noise or inaccuracy of the test stimulus. The accuracy is increasing with the ramp stimulus length which can be extended by:

• adjustment of depth of pattern memory,

• choice of configuration and order of sigma-delta modulator model, and

• modification of the saw-tooth stimulus shape (ratio rising to falling ramp)

18


In the paper, for example, the test accuracy is evaluated for the application of a single rising ramp stimulus generated by a 2nd order sigma delta modulator model. The parameters are: 1-bit pattern depth of N = 214, nominal output levels of the 1-bit DAC of +/-5 V, A/D (D/A) converter input signal swing of +/-3 V at a resolution of 8-bit. With inaccuracies introduced by the 1-bit DAC (for details see original publications), the authors claim a measurement deviation of less than 5% of an LSB.

Related technique to achieve generic BIST solution

The same research group proposed a similar scheme to implement a mixed signal BIST structure [HUA00-1]. The TSG is based on a D-to-A conversion of a bit-stream stored on-chip, as above. The TSG is verified by programming a ramp stimulus, performing the stimulus generation, and evaluating the analogue comparator’s output (Figure 3-7) similarly to the DAC testing routine described above. Once the test stimulus generation has been verified, the ORA structure (a 1-bit Σ∆ modulator) is subject to verification.

1-bit DAC

Programmable core & memory

DSP

LPF

1-bitΣ∆

CUT1

MU

X M

UX

CUT2 + - analogue comparator

Vref

reponse acquisition

signal generation

select

Figure 3-7: BIST structure containing TSG and ORA

input -0.2 -0.1 0 0.1

0.2

0.1

0

-0.2

-0.1

0.2

ideal line

outp

ut

limit cycle for 0 input 01

Figure 3-8: Non-ideal I/O curve

input -0 v0 v v0+v

ideal line

outp

ut

A1

Figure 3-9: Gain estimation

non-ideal I/O

curve

non-ideal

A2

An essential characteristic of a non-ideal DC I/O transfer curve for the 1st order modulator is that the transfer curve is symmetric to a DC value, as illustrated in Figure 3-8. Accordingly, the integration of the output of a non-ideal modulator with respect to a ramp input over a period when the ramp input varies from (v0- -v) to (v0+v), the result will be zero. Thus v0 can be determined in the following way (further considerations regarding the measurement accuracy can be found in the paper):

• Apply a ramp stimulus and start integration of the modulator response from a pre-determined voltage v1. The integration of a bit-stream corresponds to a simple up/down counting process.

• Record the value of the linear ramp, v2, when the result of the integration is zero again.

• Calculate offset from v0 = 0.5*( v1 + v2)

19


The gain of the non-ideal modulator is also determined through integration. S is the sum of the ideal ramp response from 0 to a voltage v corresponding to area A1 in Figure 3-9; S’ is the sum for the non-ideal ramp response from v0 to v0 + v corresponding to area A2. The gain can be estimated from the ratio S’/ S.

Once the output response analyser has been verified, the BIST structure is tested and can be used to generate and apply stimuli to further analogue structures (CUT1 and CUT2 in Figure 3-7) and converting their test responses to bit-streams which can be post-processed for testing in the DSP core.

Discussion

The paper describes the application of histogram testing to Σ∆ modulators. Regarding the potentially excessive area overhead for the output response analyser, the same reservations apply as in the HABIST scheme. The proposed test stimulus generator may require further analysis to assess whether the stimulus accuracy is sufficient for high-resolution converter test. Aspects regarding the application to high-resolution converters are discussed in section 3.1.9.

3.1.8 Partial BIST Methodology for ADCs

De Vries et al. published a partial BIST methodology at the ED&TC’97 [VRI97]. An observation problem is identified, and the technique is aimed at a reduction in data, namely the number of bits, to be monitored off-chip for test evaluation. For low frequencies, it is proposed to monitor the LSB only and evaluate the upper bits on-chip. The technique is not strongly related to histogram testing, however, for ADC testing the code width is assessed through counting the number of code occurrences (not through accurate computation of transition voltages, as in servo-loop testing).

n-bi

t AD

C

fsample

Com

pare

(n-q

) bit

coun

ter

(n-q

) bit

coun

ter

conv

entio

nal t

est

pass/fail on-chip off-chip

clk clk q

MSB

LSB

Vin

Figure 3-10: Partial BIST scheme

Figure 3-10 illustrates the proposed BIST scheme which allows testing for static and dynamic performance. While the LSBs up to bit q are evaluated off-chip, the remaining higher bits (q+1 to the Most Significant Bit (MSB)) are tested on-chip by comparison to a counter clocked by a falling edge on bit q. As the upper bits are reconstructed by an identical off-chip counter, the signal frequency at bit q must satisfy Shannon’s theorem. Hence, the saw-tooth test stimulus frequency (fstimulus) and the ADC’s sampling frequency (fsample), resolution (n-bits), and linearity specifications given by NL determine the minimum number of bits to be monitored off-chip (qmin) as:

+= + NL

ff

ceilq n

sample

stimulus 12min 2log (3.1.8-1)

where ceil means that the term in brackets is rounded off to the larger integer. The parameter NL in equation 3.1.8-1 corresponds to the largest deviation of the real transfer curve of the CUT compared to

20


the ideal transfer function over the range of 2qmin-1 codes and can be determined from DNL and INL specifications of the ADC under test:

{ }2,2min 1min ⋅⋅= − INLDNLNL q (3.1.8-2)

As long as equation 3.1.8-1 is satisfied, the total output code word can be reconstructed off-chip by monitoring q bits directly.

In [VRI97] the approach is optimised to test static linearity only. Here, only the LSB (q = 1) is monitored while the functionality of the ADC is tested by comparing the remaining bits of the ADC with a counter clocked by the LSB (Figure 3-12).

11

10

01

00

1

0

ideal code width 1LSB

width code 00

width code 01

width code 10 C

ode

LSB

Vin

Vin Figure 3-11: LSB linearity data

pass/fail on INL

counter

ideal code width

INL

DNL

compare

lower/upper limit (INL spec)

compare

lower/upper limit (DNL spec)

pass/fail on DNL

LSB

fsample

+

+

-

clk edge reset

edge detect

+

Figure 3-12: LSB processing block

Each code’s width is computed by a counter which is reset on a code transition. By comparison to the ideal code width, DNL and INL values can be determined on-chip and compared against thresholds, as illustrated in Figure 3-11. All codes are tested for linearity in a successive manner during one ramp input where the measurement resolution can be varied by changing the slope of the test stimulus.

Discussion

The counting process for the LSB, used to determine the code widths, introduces measurement errors just like conventional test approaches, due to a finite sampling frequency and jitter. Also, testing an ADC by applying a single ramp requires a high-resolution input stimulus where the effect of potential non-linearities requires further investigation. As transition noise causes toggles in the LSB, some kind of digital filtering will be required. Also, the measurement accuracy is limited, as noise effects are not compensated. Monitoring the LSB only is not suitable for high-resolution ADCs, as noise amplitudes will be in the region of two LSBs. To extend this approach to a full BIST technique, the same stimulus generation problems and limitations discussed for histogram-based BIST apply.

3.1.9 Summary and Discussion on Histogram-Based BIST

As histogram-based ADC test is well established, the application of the test methodology in a BIST scheme is promising. However, as the approach is based on a statistical representation of the converter activity, the amount of data to collect on-chip prior to any response evaluation results in very large area overhead especially for high-resolution converters. Reducing the area overhead, as proposed by Renovell et al., will result in an intolerable escalation of test time for slow or high-resolution ADCs. The technique under investigation at Lancaster is developed for high-speed converters. The scheme

21


may be extended to the evaluation of periodic tests stimuli, however, this will not lead to a full BIST solution but rather an embedded test solution. Regarding the solution reviewed in section 3.1.7, the amount of data to collect on-chip is as extensive as for the HABIST, hence causing a large area overhead. The paper may be of interest regarding the stimulus generation from a bit sequence stored on-chip.

The reviewed histogram-related BIST techniques seem suitable for low-resolution converters only. For high-resolution ADCs, it may be suitable to apply the techniques in stages to reduce the area overhead where sub-ranges of the converter’s input signal swing are subject to test. However, for such converters, noise levels will be in the region of two LSBs which have to be averaged during the sampling process. It has to be born in mind that histogram-based converter test verifies static performance parameters only. Also, the risk of fault masking between the TSG and ADC under test, the risk of non-coherent response sampling, and the challenge of sufficient ramp stimulus resolution requires further investigation.

3.2 Oscillation-Based BIST Approaches Oscillation-based testing is possibly the best example of a more defect-oriented test approach. As described in section 3.2.1, the CUT is reconfigured into an oscillator in test mode. A deviation in oscillation frequency from the fault free value is interpreted to indicate a fault in the CUT. As explained in section 3.2.2, oscillation can also be facilitated to extract static converter performance parameters. The BIST solution is a straightforward application of the servo-loop testing methodology (section 2.1.2). Recent publications regarding defect-oriented oscillation-based testing of Σ∆-converters are reviewed in section 3.2.3. A discussion and summary of oscillation-based testing is provided in section 3.2.4 which also discusses aspects of particular relevance for high-resolution converters.

3.2.1 Generic Oscillation-Based BIST (OBIST)

Generally, in oscillation-based test techniques, the CUT (filter, operational amplifier, ADC) is converted to a circuit that oscillates. Additional BIST circuitry, such as an analogue multiplexer (AMUX) and the control logic (CL) enables a partitioning of the CUT into appropriate building blocks (BB) which are re-arranged sequentially as oscillators. The building blocks’ oscillation frequency may be related to performance parameters or a deviation from its nominal value may be used as a fault detection criterion [ARA96, ARA97, ARA97-1]. This frequency can be converted to a digital value through a frequency-to-number converter (FNC), containing a level-crossing detector (LCD) and a counter (Figure 3-13). The rectangular waveform obtained by passing the oscillating signal through the level-crossing detector is fed to a counter whose digital output can be given as:

ref

oscM f

fB

2,1 = (3.2.1-1)

To achieve higher fault coverage, it has been proposed to test additionally for the oscillation amplitude [HUE99]. The referenced paper also describes the implementation of the oscillation-based BIST technique for a dual tone multi-frequency detector filter bank facilitating the sw-opamp technique (section 4.1). In [HUE00] a Σ∆ modulator is employed to convert the analogue (oscillation) waveform to a digital signature. It is also proposed to connect the summing point in front of the integrator to more than one internal circuit nodes of the CUT. Weighting the different signals and conversion to digital

22


can enable the computation of a digital signature representing the oscillation at those circuit nodes. In [VAZ02] the technique is applied to a switched capacitor filter, where the oscillation waveform is digitised by a Σ∆ modulator and analysed for its frequency, amplitude and DC level by a number of counters connected to the modulator output.

VDD

VD

LCD

BB 1

AMUX

BB 2 BB n-1 BB n

CL

pass

/fail

out-puts

inputs

K

fosc

TMSTest

fREFreset

en reset CTR

CLK

M BIST

FNC

B1 B2 BM

CUT

VTkA

VTj+1A

Vin

Figure 3-13: OBIST block diagram and configuration

3.2.2 Oscillation-Based Functional BIST for Converters

With regard to converters, the application of this BIST structure allows testing an ADC functionally for its conversion time, DNL and INL at each code transition edge, which is based on an adaptation of conventional, external servo loop testing (section 2.1.2). An ADC can also be tested structurally by setting the CUT into an oscillation mode and measuring the oscillation frequency. Main characteristics are a digital test response and that no test stimulus is required.

CL

I2

VDD

I1

VSS

ADC C

SCECVin

fosc

test busypass

Figure 3-14: OBIST ADC test configuration

(SC start conversion, EC end conversion)

ADC output codes Ck-1 Ck Ck-1 Cj+1 Cj Cj+1

0 time

2* TC

2*TC

Figure 3-15: ADC input voltage oscillation

between VTk and VTj+1

Proposed ADC test structure: An ADC can be forced to oscillate around predetermined codes by use of a feedback path. Evaluating the oscillation frequency at the two lowest bits allows computation of ADC performance parameters, such as conversion time, DNL, or equivalent rms noise. The ADC is assumed to be continuously converting its input voltage. Figure 3-15 illustrates the oscillation around two predetermined codes, Cj and Ck. All operations are directed by the control logic. When the ADC

23


output reaches the code Ck the integrator input current is switched to I1 ramping down the ADC input (Figure 3-14). When the output reaches the code Cj the current I2 is selected to ramp up the ADC input. Neglecting the operating delay of the control logic, the period of the oscillation frequency is given by:

( ) ( )C

Aj

ATk

Aj

ATk T

ICVV

ICVV

T 41

1

2

1 +−

+−

= ++ (3.2.2-1)

where C represents the capacitor shown in Figure 3-14. Considering I = I1 = I2, the oscillation frequency is:

( )C

ATj

ATk

osc TI

CVVf 4

21 1 +

−= + (3.2.2-2)

Conversion Testing: Enforcing oscillation between two adjacent codes Ck and Ck-1 allows measuring the conversion time TC of the ADC for each possible output code. When an increasing ADC input reaches Vtk

A the ADC output will change to Ck after time TC, causing the control logic to alter the input current to I1. After the same time TC, the ADC input will reach Vtk

A as I1 is supposed to be equal to I2. It takes a further time TC to obtain a decrement at the ADC output to Ck-1 which will cause the charging current to be altered to I2 ramping up the ADC input. As indicated in Figure 3-15, the conversion time can be determined to be:

oscC f

T4

1= (3.2.2-3)

DNL Testing: Analogously, enforcing oscillation around one code (between Ck and Ck-2) allows evaluation of the code width CWk for Ck. As the input Vin oscillates between VTk

A and VTk-1A, the

oscillation frequency and corresponding code width can be given as:

( )

+−= −

C

ATk

ATk

osc TI

CVVf 421 1 ;

−

=−= −Cosc

ATk

ATkk TfC

IVV4

12

CW 1 (3.2.2-4)

in which term TC has already been measured during conversion time testing. The FNC output is compared to the nominal value for test evaluation.

INL and gain error Testing: Apart from accumulating DNL values, the INL at code Ck can also be evaluated by enforcing oscillation between C0 (00…0) and Ck+1. Consequently, Vin oscillates between V1

A and VTk+1A. The INL is obtained by subtracting the nominal values V1

N and VTk+1N. The oscillation

frequency and corresponding INL can be given as:

( )

+−= +

C

AATk

osc TI

CVVf 421 11 ; ( ) ( NNTk

AATkk VVVV 1111INL −−−= ++ ) (3.2.2-5)

3.2.3 Oscillation-Based Structural BIST for Σ∆ Converters

An alternative approach, which consists of structural testing of ADCs based on the OBIST, is introduced for a first order Σ∆ converter. Figure 3-16 shows the application to a first-order Σ∆ modulator where only the dashed line is added for test purposes. In operational mode, S2 selects Vin and S1 the modulator output. In test mode, S1 connects to the output of OP1 and S2 to ground. When the oscillation frequency has been captured, S2 connects to VTEST and the new oscillation frequency is analysed. Both frequencies are converted to a digital code and can be used as fault detection criteria. To enhance results by a functional test, the voltage VTEST is converted to a digital word using the Σ∆ ADC

24


and the output code is considered as the third test signature. A fault coverage of 98.5% has been reported for catastrophic faults.

Vin VTEST

TM

S2

R2

C1

D Q Clk Q’

Clk

R3

R1

fosc

TM

+1/2VREF-1/2VREF S1

1 bit output

OP3

OP1

OP2

Figure 3-16: Schematic of testable first order Σ∆ modulator based on OBIST method

Previous research at the Microelectronics Institute at the University of Seville (IMSE-CNM) on oscillation-based filter test is currently extended to address Σ∆ converter test. In [HUE01] the transformation of the second order Σ∆ low-pass modulator into an oscillator is described. The modulator is illustrated in Figure 3-17, including the added feedback loops (green dashed lines) which will enforce the oscillation.

V’

-V’

1

z-1 1

z-1 x1 x2

k0 k1

k3 k4

Figure 3-17: Reconfiguration of second order low-pass Σ∆ modulator to oscillator

The transfer function of the circuit illustrated above can be as:

[ ]102

232

2

2

1

)()()()()(1)()(

kzHkzHANkzHkzHANzH

XX

+⋅−−−⋅= where

11)(−

=z

zH (3.2.3-1)

N(A) is the function of the quantiser. In the publication, the oscillation frequency and amplitude are determined as functions of the coefficients (ki) for three quantiser options: a non-linear comparator without hysteresis with or without extra delays, or with hysteresis but no extra delay. Plots of these functions allow the selection of suitable coefficient values (ki) to achieve desired oscillation frequency and amplitude. It is summarised, “that a judicious election of the additional” k3 and k4 “parameters provides enough freedom to force oscillations which can be worthwhile for testing purposes”. The effect of gain deviations in the first and second integrator on the oscillation characteristics is analysed in the paper. For higher order designs it is proposed to decompose the circuitry into smaller (second order) sub-systems which are then converted to oscillators sequentially. In each of the sequences, the aim has to be to maintain a digitised output corresponding the oscillation waveform.

25


In [HUE02] oscillation-based test is considered for a Σ∆ band-pass modulator. For a second order modulator, the parameters of the feedback to enforce oscillation are determined through the calculation of the transfer function’s pole locations. Also, a fourth order Σ∆ band-pass modulator is considered. Again the system is split into smaller second order sub-systems which are reconfigured for oscillation. Further details are given in the paper regarding the sensitivity of the oscillation frequency and amplitude to fault effects, such as gain deviations or deviations in the modulator coefficients.

3.2.4 Summary and Discussion on Oscillation-Based BIST

Generally, oscillation-based test is a good example for a more DOT approach. There is large potential to significantly reduce the (production) test time compared to conventional (functional) test approaches, especially for high-resolution converters. Also, the area overhead compared to more specification-oriented BIST solutions should be significantly smaller, as no dedicated test stimulus generator has to be implemented. However, as for any test methodology which does not strongly correlate to the CUT’s performance parameters, further analysis is required on the following main issues:

• Determination of realistic test thresholds for the DOT measurement

• Potential test escapes

• Potential decrease in yield

To address these issues, it would be necessary to determine the correlation between the oscillation characteristics (frequency and amplitude) to the converter’s performance parameters, which seems from the authors’ point of view impossible, as the circuitry is reconfigured to a great extend in test mode.

Regarding an oscillation-based functional BIST solution, the oscillation around two predetermined codes faces a number of potential problems. Especially the oscillation around one code word to measure DNL is sensitive to noise. Where higher-resolution ADCs are subject to test, noise levels exceeding an LSB will prevent precise the computation of code transition edges. Also the accuracy requirements for the stimulus generation need to be determined, as minor slope variations as well as mismatched reference current (I1 and I2 in Figure 3-14) will directly impact the measurement accuracy.

3.3 BIST Approaches Related to FFT-Based Testing In this section, three published BIST techniques are described. A discussion is included in each of the sub-section. A brief summary is provided in section 3.3.4.

3.3.1 Mixed Analogue-Digital BIST (MADBIST)

Toner and Roberts proposed the MADBIST for Σ∆ converters [TON93, TON95, TON96]. The work reported in [TON93, TON95] covers single-tone implementation of the MADBIST for Signal-Noise Ratio (SNR), gain tracking and frequency response tests of the ADC. In [TON96], the scheme is extended to a multi-tone MADBIST for the frequency response, harmonic distortion and inter modulation distortion tests of the ADC. A pulse density modulated multi-tone signal is generated on-chip and applied to the ADC as a test stimulus. For the ORA, a narrow band multi-output digital filtering approach enables separation of signals at multiple frequency bands. The evaluation of these signals is performed in an on-chip DSP core.

26


analogue output

anti-aliasing filter

V f

A

f

analogue section

decimator

analogue input

2041 kHz1 bit

8 kHz16 bit

DSP

DAC

digi

tal i

nput

digi

tal o

utpu

t

ADC

mixedsignal

IC

Figure 3-18: Mixed signal IC, including DSP, Σ∆ ADC and DAC

Implementation

Any BIST scheme requires that both the stimulus and the response must be generated and measured on-chip. The DAC contains an interpolation filter and a digital Σ∆ modulator; it is fully digital apart from the analogue smoothing filter on its output. The MADBIST scheme adds three components to the chip: a TSG, a multiplexer (MUX), and a switch at the ADC output (Figure 3-19). The analogue TSG is fully digital and is designed to operate in an oversampling mode. The DAC is set to run in its oscillation mode to provide a precision sine-wave, and the analogue stimulus is fed via the multiplexer to the ADC input (not through the smoothing filter of the DAC, to prevent fault masking). The ADC can then be used to measure the performance of the DAC by setting the switch and the multiplexer appropriately. Also other external analogue circuitry may be tested with the DAC as a TSG and the ADC as an ORA.

DSP

mixed signal IC

Signal Generator

DAC

Smoothing

Filter

ADC

Anti-Aliasing Filter (AAF)

digital digital

analogue input

analogue output

switch MUX

external analogue component

Figure 3-19: Configuration and routing

AAF Σ∆

PDM analogue

TSGsignal & noise

extraction noise signal output output

( )( ) ( )( )( )( )11

12

2

−−

−= ∑∑ MM

nn

MP

ηηη

( )( )∑−= 2

11 ns

MPη

noise power signal power

digital comparator

Ps,MIN < Ps < Ps,MAX

and Pη,MIN < Pη < Pη,MAX

?

Digital Memory

Pη,MIN Ps,MIN Pη,MAX Ps,MAX

pass fail

yes no

digtal

η(n) s(n)

Pη Ps

ADC under test

Figure 3-20: Control flow for ADC test

MADBIST Routine

The test configurations are depicted in Figure 3-19. The self-test routine is as follows:

• A digital BIST is applied to test the digital signal generator.

• The signal generator output is connected to the ADC (not via smoothing filter) which is subject to all tests.

• Once the ADC has passed its tests, it may be used as a calibrated measuring instrument.

• The signal generator is connected to the smoothing filter whose output is monitored by the ADC. In conjunction with the on-chip DSP, the ADC enables testing the filter performance.

27


• Now the combination of the signal generator and the smoothing filter can be used as a calibrated analogue TSG. Also external analogue components can be tested.

The control flow during ADC test is illustrated in Figure 3-20. The digital control unit initialises the other modules to begin the test. The analogue signal generator is programmed to output a sine-wave at the appropriate frequency and amplitude, providing a precision test stimulus, which is digitised by the ADC. The ADC output is connected to the DSP, which separates the signal from the noise. Values for the separated signal and noise powers can be checked against stored pass/fail thresholds.

Discussion

The MADBIST is certainly the most complex BIST technique reviewed in this chapter. A strong link to a wide range of circuit performance parameters is established. As for the work published by the same research laboratory at the ITC 2000 [HAF00], the aim is to implement a tester-on-chip based on the use of a complex DSP and memory. Further issues on FFT-based BIST are discussed in section 3.3.4.

3.3.2 BIST for ADCs and DACs in a Single-Chip Speech CODEC

Teraoka et al. devised a BIST approach for ADCs and DACs for an embedded DSP-core ASIC in [TER93, TER97]. The aim is to reduce the demands on the external ATE and to reduce the test time by the use of on-chip TSG and ORA. While conventional tests measure the performance of the analogue-to-analogue system, the BIST evaluates the performance of the digital-to-digital system where the DSP core is connected to the digital ends of the ADC and DAC.

ATE

external DAC A

ADC DAC RAM ROM

DSP core test ctrl. circuit

B CODEC

Figure 3-21: Configuration for BIST applied to a CODEC

In test mode, two measurements can be performed, where either the analogue ports of the ADC and DAC are shorted externally (A in Figure 3-21) or an external DAC is connected to the ADC input (B). Test coefficient data and the BIST program are stored in an on-chip ROM (Read Only Memory). The test flow can be summarised as follows:

• Generate a 512-point sinusoidal waveform of predefined tone frequency and level which is stored in the data RAM.

• Send the test stimulus twice to the DAC every sampling cycle by direct memory access. The ADC converts the analogue output immediately and a last 512-point output waveform is stored in the data RAM by direct memory access.

• Perform an FFT analysis of the 512-point waveform, compare to standard limits and finally store the compared results in the data RAM.

This test flow is valid for both measurements, where either the on-chip DAC or the external DAC is used. The DSP can handle the process analysis of previous measurements and the data generation for the next measurement at the same time with a data transmission in a pipeline manner. Thus the total test time equals approximately the total data transmission time. The BIST structure allows the measurement of eight characteristics, either for the ADC or the DAC-ADC system, and is evaluated for three out of eight performance characteristics showing good agreement compared to the ATE results. The authors claim a test time reduction of 90% and an area overhead of 0.5%.

28


Discussion

Apart from common limitations of FFT-based BIST solutions discussed in section 3.3.4, this technique prevents full BIST, as an external DAC has to be facilitated to avoid fault masking. It remains questionable whether most SOCs do contain an ADC and DAC with matched analogue signal ranges. Also, to test an n-bit ADC, an (n+2)-bit DAC will be required to achieve some measurement accuracy. While the ADC may be tested with an external higher-resolution DAC as a TSG, the use of the (tested) ADC for on-chip testing of the DAC limits the maximum DAC resolution.

3.3.3 Pseudo-Random Patterns for Second-Order Σ∆ Modulator Test

While most ADC test techniques require a high accuracy test stimulus, a pseudo-random bit sequence generated by a linear feedback shift register is facilitated for testing a single-bit 2nd order sigma-delta modulator for its SNR in [ONG01]. The test approach is described in great detail in the referenced paper, here the solution is outlined in terms of application.

y output

x input

Z-1

t

DAC 1st integrator

Z-1 -2

2nd integrator

e

L1

L2 I1 I2

a

b Figure 3-22: The non-ideal second-order Σ∆ modulator model

The non-ideal model of a second order modulator is given in Figure 3-22, where L1 and L2 are the leakage factors of the integrators, t is the threshold of the two-level quantiser, a and b are the output levels of the differential DAC. It is argued in the publication, that changes in t or a and b do not influence the modulator’s SNR significantly. The aim of the technique is to extract the parameters L1 and L2 and to estimate the SNR from these values. Deviations in the leakage parameters from their (ideal) unity values cause distortion to the modulators output spectrum, which is inherently flat in the ideal case when a pseudo-random sequence is applied. As shown in [ONG01], the average power P1 in a frequency range FR1 can be used to determine the parameter L1. Similarly, the parameter L2 can be determined from a second average power P2 for a frequency range FR2 when L1 is known (Figure 3-23).

P1

map2

map3

map1

P2

L1

L2

SNR

Figure 3-23: Mapping from spectral powers to SNR

The correlation of the signal powers to the leakage parameters and finally to the SNR value is realised by construction of three mapping tables. Firstly, the oversampling ratio of the modulator is determined from the modulator’s ideal SNR. Secondly, the leakage parameters for a maximum tolerable deviation in the SNR are calculated. Thirdly, both frequency ranges (FR1 and FR2) are determined using an exhaustive search method. Finally three mapping tables are constructed to allow estimation of L1 from the value for P1, L2 from the values of L1 and P2, and the SNR from the values for L1 and L2. In test application, the pseudo-random bit sequence used to construct the mapping tables is applied to the modulator. The test response is captured and an FFT is performed to determine the signal powers in the

29


predetermined frequency ranges. From these values, the SNR can be estimated as mentioned above and compared against test thresholds.

In the paper the methodology is evaluated against a set of 1000 simulated modulators with different values for L1 and L2. For about 82% of those simulated devices, the estimated SNR falls into the same category (pass or fail test) at the simulated SNR. About 50% of the misclassifications fall within 3 dB of the test threshold.

Discussion

Firstly it needs to be mentioned that this technique is not a complete BIST solution, as the test evaluation (FFT, mapping, comparison to thresholds) is performed off-chip. The proposed technique is described as a structural test approach in the paper, which may be due to the fact, that only a single performance parameter is estimated (not determined). However, it is mentioned that the test analysis is performed on the modulator output prior to digital filtering avoiding the down-sampling and therefore achieving a shorter test time compared to conventional converter testing. Common limitations of FFT-based BIST solutions (section 3.3.4) do apply. Also the on-chip storage of the mapping tables will require additional memory resources.

3.3.4 Summary and Discussion on FFT-Based BIST Solutions

The MADBIST is certainly the most complex BIST technique reviewed in this chapter. Commonly for the three reviewed techniques, an on-chip DSP core is required for full BIST. However, for this project - aiming to propose DfT and BIST for analogue ViCs - the availability of suitable DSP cores and other structures may not be given and area overheads for such complex circuitry cannot be justified. Interestingly in the International Technology Roadmap for Semiconductors 1999 [SIA99] it was forecasted in the context of analogue BIST, that so-called tester-on-chip solutions will be of interested in the longer term. However, this forecast was dropped from the 2001 Roadmap [SIA01] where further circuit specific BIST solutions are expected in the longer term, as long as dedicated cheaper ATE (digital only or DfT testers) will be available.

For high-resolution ADC testing, the on-chip processing of the FFT will become more complex and may require additional resources due to a higher number of samples which need to be included in the analysis to maintain measurement accuracy. Also, the use of on-chip D-to-A converters for ADC testing requires careful investigation. Firstly the potential for fault masking needs to be assessed. Secondly, matched voltage ranges are required. Also, additional filtering of the DAC output may be necessary and/or higher DAC resolution may be required to ensure accurate stimulus generation.

3.4 Other Converter BIST Solutions This section provides information on further converter BIST solutions which cannot be classified as histogram-based, oscillation-based or FFT-based techniques. Firstly, the LogicVision adcBIST structure and test approach is described. In the second sub-section a purely DOT technique for differential circuits is described which also enables online testing. Thirdly, a DOT reconfiguration-based BIST solution for Σ∆ modulators is summarised. Finally, one of the best-known mixed signal BIST proposals, the Hybrid BIST is mentioned for completeness. Discussions about each of the test approaches and BIST implementations are included in the sub-sections.

30


3.4.1 adcBIST Simplified Polynomial-Fitting Algorithm for Converters

Sunter and Nagi presented the polynomial fitting algorithm at the ITC’97 [SUN97], which is a method to extract DC offset, gain and harmonic distortion from the coefficients of a best-fit third order polynomial. These coefficients are calculated from the sums taken for four separate sections (time slots) of a ramp stimulus response. The approach is efficient enough to be implemented as a BIST for an IC, and is particularly suitable for Σ∆ converters. LogicVision sells the purely digital BIST cell for ADCs in three different versions delivered as synthesisable RTL code [LOG99].

Best-Fit Third Order Polynomial

To allow on-chip extraction of best-fit polynomial coefficients, the order of the polynomial has been limited to three. The best-fit curve is described by:

33

2210 xbxbxbby +++= (3.4.1-1)

The impact of coefficients can be qualitatively evaluated as follows:

• Positive coefficients for second and higher order even terms increase (decrease) the slope for positive (negative) x.

• Positive coefficients for third and higher order odd terms increase the slope for positive and negative x.

When considering third order polynomials and defining slopes for positive and negative x regions, the impact of higher order terms can be deduced by comparing the two slopes for all data points. If the transfer curve is partitioned into four regions, as illustrated in Figure 3-24, those two slopes, m1 and m0 can be determined from the four integrals S0 to S3 [SUN97]. Similarly, the impact of second and third order coefficients can also be expressed in terms of the four integrals.

m: slope for all data points m0: slope for x < 0 m1: slope for x > 0 S0: sum from i = -n/2 to i =-n/4 S1: sum from i = -n/4 to i = 0 S2: sum from i = 0 to i = n/4 S3: sum from i = n/4 to i = n/2

-n/2 -n/4 0 n/4 n/2

y

x S0

S1

S2

S3

Figure 3-24: Ramp stimulus response showing the four regions

When extracting dynamic circuit performance parameters, a sine-wave is used as an input stimulus instead of a ramp. By insertion of x = cosω t and its amplitude A = n/2 into the third order polynomial (3.4.1-1), the coefficients of cosω t and its multiples can be calculated. When these coefficients are known, the performance parameters DC offset, gain and distortion to second and third order harmonics can be calculated as:

31


12312

020

4324

131

212

Bn

BBn

gain

Bn

BBn

offset

≈

+=

≈

+=

1

3

3

1

1

2

31

2

32

123

13

322

BB

BBharmonic

BB

BB

Bhamonic

rd

nd

≈+

=

≈+

=

(3.4.1-2)

with the signatures B0 to B3 relating to the four integrals S0 to S3 as:

01232

01230

SSSSBSSSSB

+−−=+++=

01233

01231

33 SSSSBSSSSB−+−=

−−+=(3.4.1-3)

Each parameter is proportional to one of the digital signatures. Hence extracting B0..4 on-chip would allow testing for thresholds when limits are stored on-chip. The approach is especially efficient for testing Σ∆ converters, as the Σ∆ bit-stream may be integrated (summed) using a binary counter which increments each time a one is detected.

The Product

Currently LogicVision sells the adcBIST illustrated in Figure 3-25. The BIST circuitry generates an analogue stimulus for connection to the ADC via a multiplexer and RC network (with ±20% accuracy), which may be on-chip or off-chip, depending on the sampling rate, number of bits, RC linearity and ADC input impedance. The outputs of the adcBIST are either intermediate results (signatures B0..4, for off-chip calculation), values for the tested specification (for external comparison to limits), or a simple pass/fail result (specifications are calculated and compared to the thresholds inside the BIST cell).

test access

adcBIST

fs

ADC

test access

ADC

adcBIST

fs

Figure 3-25: adcBIST illustration in [LOG99]

Discussion

The approach has been verified mathematically and compared to commercial FFT software on a 12-bit DAC-ADC system (National Instruments). The results showed good agreement [SUN97], and ongoing work indicates suitability for ADC with a resolution of up to 16 bits [SUN01-1]. However, results are only accurate if fourth and fifth harmonics are significantly less than the levels of the second and third harmonics. This is not the case when clipping occurs. When the estimates for second and third order harmonics become inaccurate, gain and offset values extracted will also be affected. Additionally, a best-fit curve for a CUT with local DNL or INL failure may not result in a detectable deviation from the ideal case. Hence the adcBIST™ may have to be supported by some additional tests for linearity. The problem source may be found in the assumption that a faulty test response will lead to a detectable deviation in a best-fit third order polynomial. If the test response shows only minor, localised deviations, or the failure mode is averaged over the integration time slot (examples are illustrated in [LEC01]), test escapes will occur.

32


To enhance the test to check for transient effects, the authors propose the use of a modulated ramp. As the approach is based on monitoring the behaviour of a DAC-ADC loop (tested as a pair), the use of a reference DAC or ADC may be required to avoid fault masking problems.

Future work of LogicVision will address the use of other TSGs to enable digital testing for stand-alone ADCs or DACs [SUN97]. Also, to test transfer functions with higher order polynomials, sub-ranges of the total signal range may be measured.

STMicroelectronics™ describe the test strategy, implementation of BIST and use of digital only testers for a mixed signal VLSI system in [APP99]. For ADC and DAC testing, a concept built on the adcBIST is chosen. The on-chip DSP controls the test and performs the analysis, including the integration over four equal time windows. The signatures are passed to the external ATE for functional parameter computation and comparison to specifications. The algorithm is applied to the ADC/DAC loop; however, due to fault masking problems mentioned above, the ADC also has to be tested using an external high-precision reference DAC located on the load board. From the ATE’s point of view, the entire VLSI system test remains digital only.

3.4.2 Analogue Unified BIST (AUBIST)

Mir and Lubaszewski proposed the AUBIST for linear and non-linear switched capacitor circuits [LUB97, MIR96, MIR96-1]. The test circuitry supports concurrent/on-line testing and high fault coverage is reported. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. In on-line mode, the BIST circuitry simultaneously monitors the balance of common mode signals in a fully differential structure (Figure 3-26) by the use of common mode checkers (see below). During off-line testing, single differential signals are observed, one at a time by means of a checker.

diff. input DOP1

Vi1 Vo1

DOPm

Vim Vom

diff. output

Analogue Checkers control error

Figure 3-26: Fully differential circuit (DOP: differential operation amplifier)

The approach does not verify circuit specifications. The DOT methodology is best described by explaining the use of the on-line checker. This circuitry is proposed for testing algorithmic converters designs or cascaded filter structures. In [FRA96, KOL93, KOL95, MIR94] the authors evaluated the use of on-line checkers in fully differential designs. The circuit proposed exploits the advantages provided by the Σ∆ technique and by fully differential architectures.

On-Line Common Mode Checker

33


e1

V ref

I

I

S p S n

e2

gI

gI

V c

V c’

Figure 3-27: Common mode checker circuit

The on-line checker continuously monitors the circuit function and supports concurrent error detection. A differential voltage S is represented by two physical signals Sp and Sn, which are carried by different wires. The common mode signal Scm can be used to check the correct operation of the circuit.

refnp VSS 2≈+ ; ( )npcm SSS +=21 (3.4.2-1)

For the demonstrator, each differential signal S is monitored by a common mode checker which signals a fault once a common mode threshold has been exceeded. The basic structure of a common mode checker is illustrated in Figure 3-27. If the differential signal S is balanced, AC (Alternating Current) signals Vc and Vc’ remain approximately at their DC voltages. A common mode signal at the inputs of the checker different from Vref (which corresponds to the nominal common mode) changes the current (and voltage) in node Vc and the opposite effect results in node Vc’. The AC gain of signal Vc and Vc’ is proportional to the common mode signal. The threshold of the output inverters is then designed such that they signal a double-rail error when the common mode signal exceeds a given threshold. For example, with a total power supply of 5 V and an analogue ground (Vref) at 2.5 V, Vc and Vc’ remain at approximately 1.5 V if no common mode exists at the inputs. With a gain of 10, a common mode of 100 mV will corrupt the output code. For a positive (negative) common mode at the input, Vc (Vc’) increases and therefore output e1 (e2) is incorrect. The double-rail output code 01 or 10 indicates correct performance, while 00 and 11 indicate circuit malfunction. Further information concerning the implementation of the checker, simulation results and fault coverages can be found in papers referenced above.

Discussion

It must be noted, that the use of the on-line checker for fault detection has to go hand in hand with an optimisation of the layout for the differential block monitored. To achieve high fault coverage, certain faults have to be prevented, which otherwise will not be detected by the checker. This can be achieved by easy to apply DfT guidelines that have to be integrated into the layout rules. A short between the differential inputs of an operation amplifier (OP), for example, will not cause a detectable deviation in the common mode signal. This fault can simply be avoided at the layout level by increasing the distance between the lines carrying the differential signal, or adding a metal path between them which carries a signal of different DC voltage. Any short in the optimised layout will cause a detectable deviation in the common mode signal. Also, different fault detection thresholds will require redesign of the common mode checker. The most interesting aspect of the AUBIST is the application in online monitoring. Regarding ADC test, however, the approach lacks any correlation to converter performance parameters.

34


3.4.3 Reconfiguration-Based BIST for Sigma-Delta Modulators

Mir et al. proposed a reconfiguration technique for a double-loop Σ∆ modulator to enable a defect-oriented BIST at the IMSTW’97 [MIR97]. The BIST approach can also be applied to a second order Σ∆ ADC. It is based on a defect-oriented rather than a specification-driven test philosophy.

Approach

The basic configuration of the Σ∆ modulator is illustrated in Figure 3-28. The BIST approach is based on breaking the modulator feedback loops, placing each resonator in a unity-gain feedback loop, and stimulating both blocks in parallel. The reconfigured circuit and the comparison of the outputs of the two blocks with a tolerance window (±c.Vtol) is shown in Figure 3-29. A comparator is already available in the modulator, but subtracting the signals requires an amplifier summing node (c in Figure 3-29) to obtain good precision. In test mode, the resonator gains (a and b) have to be made equal.

-az-2

1+z-2 -bz-2

1+z-2

quantiser

x[n] g

y[n]

resonatorresonator

1-bitDAC

Figure 3-28: Block diagram of an example double loop band-pass Σ∆ modulator

In [MIR97], the application of this approach to a double-loop band-pass modulator in a fully differential switched current architecture is described. The structure corresponding to Figure 3-29 has been fault simulated (stuck-on, stuck-open and shorts in all switches, short and open faults in capacitors, and 50% and 200% deviations in the capacitor values), and fault coverages above 90% for a test threshold of 20 mV are reported. To achieve a full BIST, including the TSG, the authors propose the use of another on-chip Σ∆ modulator.

-az-2

1+z-2

-bz-2

1+z-2

x[n]

TS

y1[n]

block2

block1

y2[n]

TS

c.Vt

ol

-c.V

tol

error

TS

TS

c

Figure 3-29: BIST operation by reconfiguration of resonators and response comparison

Discussion

The approach is based on reconfiguration for test. This means that the CUT is not in its functional mode and reconfiguration switches may have an impact on the device performance. Further investigation is required on the TSG to identify demands on stimulus accuracy and associated area overhead for full BIST. For system test, it needs to be investigated how many tolerance threshold voltages have to be provided on-chip. When those thresholds are generated on-chip, the impact of

35


device and process deviations on the generated threshold voltages needs to be considered. The computed test coverage may alter when a more realistic fault list is extracted from the layout. Also potential fault masking requires further investigation, as process shifts in global parameters may affect both resonators in the same way, preventing fault detection.

3.4.4 Hybrid BIST (HBIST)

The HBIST concept [OHL91] is based on the conversion of existing digital BIST structures to support analogue BIST. The test stimulus is obtained from the D-to-A conversion of the test pattern generated by the digital test pattern generator (alternatively pattern can be loaded from an external tester). The analogue test stimulus can be fed to different analogue sub circuits. The output response analysis takes place after the A-to-D conversion of the test response, thus a linear feedback shift register (part of built-in logic block observer (BILBO) structures needed for digital BIST) can be used to perform a signature analysis. The concept is applicable to systems which contain digital BIST structures and is based on testing the analogue portion digitally in a D-to-A-to-D loop.

Discussion

The concept has not proven its industrial strength so far, as a number of problems have not been addressed. Test evaluation by signature analysis, for example, may cause difficulties in determination of threshold values. Fault masking effects, especially within both converters, require further investigation. As the test stimulus is not suitable for testing specifications, proof of achievable test coverages is required, and may have to be provided for each type of CUT separately.

3.5 Summary As each BIST technique reviewed in this chapter has been discussed in terms of advantages and disadvantages above, some common aspects are discussed in this section. Particular aspects for the BIST techniques are summarised in Table 4. Regarding the application of the BIST techniques to the target high-resolution converter designs in the TAMES2 project, the following aspects can be summarised.

A straightforward on-chip integration of histogram testing will result in an unacceptable area overhead and escalating test time. Further work would be required to evaluate the feasibility of testing sub-sections of the transfer function, or reducing the amount of data to gather in form of a histogram while accepting decreased accuracy.

Any purely defect oriented BIST technique will require proof regarding the correlation of test results to the actual device performance and an acceptable artificial yield loss. Verification of converter performance parameters in an oscillation BIST scheme, related to conventional servo-loop testing, may not be applicable to high-resolution converters due to an increase sensitivity to noise effects.

BIST solutions that require an on-chip DSP will result in an unacceptable area overhead when the solution is aimed to be provided with virtual components.

Generally, a new BIST solution has to be found which may be based on a more structural test approach. Crucial sub-circuit performance parameters may be identifiable which have a strong correlation to the overall converter performance. For the on-chip verification of such sub-circuit performance parameters some of the limitations of reviewed BIST techniques may not apply.

36


Table 4: Comparison of generic BIST techniques for converters

Approach Specification Application Pro Con Section Histogram BIST

Offset error Gain error DNL INL (noise)

ADC Typically low resolution, high-speed ViC

Various stimuli Conventional technique

Area overhead Test time (Time/area trade-off) TSG missing Measurement accuracy Lack of dynamic performance parameter tests

3.1

DOT OBIST

DOT Oscillation ViC

Vector free Area overhead

Lack of correlation to performance parameters

3.2.1 3.2.3

Functional OBIST

Conversion time Gain error DNL, INL

Low to medium resolution ADC ViC

Vector free Area overhead

Lack of dynamic performance parameter tests

3.2.2

MADBIST SNR Gain tracking Harmonic distortion Frequency response Inter modulation distortion

ADC DAC DSP required

Full BIST Area overhead 3.3.1

BIST for CODEC

Gain error Inter modulation distortion, Distortion, crosstalk

ADC DAC DSP required

Full BIST Verification of BIST hardware Fault masking, or external DAC;

3.3.2

BIST for Σ∆ converter

SNR Σ∆ ADCs DSP required

Dynamic performance test

Area overhead Limited test set

3.3.3

adcBIST Offset error Gain error 2nd & 3rd harmonics

ADC/DAC ViC

Digital only; Area overhead; Commercialised

No DNL or INL External DAC Potential test escapes

3.4.1

AUBIST DOT Differential ViC

Universal; Internal nodes; On-line

No specifications 3.4.2

Reconfigu-ration BIST

DOT Identical cells ViC

Area overhead No specifications No TSG

3.4.3

HBIST DOT Generic Full BIST Difficult ORA No correlation to performance parameters

3.4.4

37


4 Ideas Towards an Embedded Test Solution for High-Resolution Σ∆ Converters

In the previous chapter recently published partial and full BIST solutions for ADCs are reviewed. This chapter contains some initial ideas for test solutions applicable to the target converter designs that were generated during the TAMES2 meeting by various consortium members [TAM02]. At a later TAMES-2 meeting in August 2002 [TAM02-1], it has been discussed that the THD measurement will require the largest number of samples for the FFT analysis (depending on the specification, see reference test times generated at TAM02-1). Also further initial ideas were proposed which are included in this chapter. However, further work is required to investigate the feasibility of these ideas and to determine the target designs’ test requirements, as discussed in chapter 5. This chapter will form the basis for further tasks of the project where results of investigations will be added.

The first section in this chapter briefly introduces a DfT structure, the sw-opamp, which allows to access analogue circuit nodes for stimulus injection and response observation. Two proposed approaches for test stimulus injection at the Σ∆ converter’s quantiser and DAC are outlined in sections 4.2 and 4.3. The decomposition of the circuitry into smaller more manageable blocks is discussed in section 4.4, while the use of transformation techniques more suitable for analysis of bit-streams is briefly addressed in section 4.5. The input sampling circuitry is expected to be the source for distortion, as discussed in section 4.6. The manipulation of the feedback loop for testing is proposed in section 4.7, while other comments on potential test solutions are included in section 4.8. As pointed out in the summary (section 4.9), further research is required to evaluate practical issues and assess the feasibility of these initial ideas for testing the target design.

4.1 Facilitating the Sw-Opamp Concept The idea behind the implementation of a sw-opamp (switchable operational amplifier) in a circuit design is to break connections between analogue blocks and inject test stimuli [BRA93, BRA95]. The structure also allows observation of the block under test’s response while keeping performance loss, due to the insertion of switches, to a minimum.

test

vtestS1

bias

test

in+ S2

in-

Vss

Vdd

out

Figure 4-1: Basic sw-opamp structure

The basic sw-opamp structure (Figure 4-1) includes two interchangeable input stages where the configuration is controlled by a digital signal (test). When test is low, switch S2 is closed and the circuit operates in normal mode. When test is high, an injected test stimulus (vtest) is propagated to the output and applied to the succeeding analogue block. Further work has led to a differential sw-opamp design. In [VAZ97] the structure is presented and its application is discussed.

38


The application of the sw-opamp at block level for both multiplex and by-passing is illustrated in Figure 4-2. For the multiplex mode, the structure can provide direct access to an individual embedded analogue block (ABi). The test stimulus is passed from test data input net (TDI) via ABi-1, with the sw-opamp in unity gain configuration, to the block under test. Its output is connected to the test data output net (TDO) for direct observation. Test data nets TDI and TDO can be connected to the analogue bus in the IEEE 1149.4 standard scan bus [IEE99]. The use of additional test pins can be avoided in the by-pass configuration, where the test stimulus is applied to the primary input (in) and the response is observed at the primary output (out). Analogue blocks that are not subject to test are set into the sw-opamp’s buffer mode for simple signal propagation.

The sw-opamp structure may be facilitated to provide a test stimulus input to the Σ∆ modulator. The structure could also be employed to inject stimuli into the modulator’s feedback loop.

in

ABi-1

TDO

dig. ctrl

TDI

ABi ABi+1

out

multiplex implementation by-passing implementation

swop-amp

swop-amp

swop-amp

Figure 4-2: Sw-opamp implementation

4.2 Stimulus Injection at Quantiser The aim of the idea outlined in this section is aimed at testing the integrator transfer function Z -n, where n represents the order of the modulator. Analytically, it is possible to add an extra connection to the quantiser input. As the test stimulus is fed directly into the quantiser and thus does not experience the filtering effects that the integrator in the modulator loop introduces (Figure 4-3).

test signal

outputinput

Integrator

Quantiser

DAC

-

+

-

Integrator

Figure 4-3: Test input at the quantiser

For example, by applying a sine-wave to this extra input while the signal input to the modulator is kept zero will facilitate monitoring the unfiltered quantisation noise generated due to the quantiser. Additionally, electronic noise can be separated from unfiltered quantisation noise and thus an estimate of noise introduced by the quantiser can be deduced. Consequently, the integrator transfer function for filtering all the out-of-band quantisation noise can be checked. A further adaptation of this DfT method could involve application of correlated signals to the converter input and the quantizer input simultaneously. That is, it may be possible to select suitable signals, that when applied to the relevant inputs produce an output signal that is easy to monitor, whilst at the same time produces a confident indicating of correct circuit operation. For example, it may be possible to analyse and synthesize two signals that will produce a null output of the modulator under correct operating conditions. However, PDM sine-wave stimuli contain high levels of noise, and other TSG techniques may be required.

39


4.3 Test Data Injection at DAC This approach suggests that pulse-code modulated test data can be injected into the DAC of the modulator (Figure 4-4) while in input is isolated.

input

Integrator -

+

-

Integrator

test signal

output

Quantiser

DAC

Figure 4-4: Test data input at the feedback loop

A test signal with a known transfer function can be injected at the DAC. This test signal will undergo combination with the known noise transfer function of the modulator (Figure 4-5). When the transfer function of this test data signal is defined with an appropriate characteristic, the combination with the noise transfer function, should produce an already known, ease to evaluate response. Any deviation from the expected response, could be used to indicate any possible faults and deficiencies in the modulator circuitry.

Frequency/Hz

Pow

er/d

B

Frequency/Hz

Pow

er/d

B

& Frequency/Hz

Pow

er/d

B

Test data transfer function Noise transfer function Circuit response Figure 4-5: Combination of test signal and known transfer function

4.4 Decomposition of Modulator As mentioned in section 3.5, compared to conventional converter test a more structural test approach should be chosen. The target design can be intelligently decomposed into constituent blocks, which may be verified separately to meet their performance requirements. It can be expected that the verification of the overall converter function will not require testing for the complete performance parameter set.

Individual measurements of separate blocks imply that critical blocks of the structure will have to be identified and tested, for example the first integrator of the modulator is a critical block as it provides the most significant impact on noise shaping. Afterwards the less critical blocks may need to be assessed as well and the outputs from passed individual test results could be combined to give a confident indication of the likely full operational output response. This way, the necessity of carrying out conventional, time-consuming tests may be avoided.

The target design could be decomposed as follows: Firstly, the decomposition of the modulator output bit-stream and the FIR filter output. A multi-tone transfer function test could be carried out upon the FIR filter and a comparison of the modulator bit-stream with identified masking functions could take place. Also, it is felt that vast improvements in test time and required data storage could be realised by the selection of suitable fast algorithms to ascertain the output of the modulator bit-stream, when it is subjected to a known input signal, as outlined in the next section.

40


For the case of the audio CODEC, the Σ∆ converter possesses a fourth order modulator (Figure 4-6) which could be decomposed as follows: As the first integrator’s performance is very important, it is proposed that initial test effort should be focussed towards this block. Therefore, it has been proposed that the fourth order modulator could be reconfigured into lower performance modulators. The first stage may be removed and verified by a dedicated test solution while the second to fourth stages shall be kept as a unit. In that way, a lower resolution converter is built and can possibly be tested with conventional converter test solutions under acceptable test time constraints.

s1

a1I(z)

a2I(z) s2

a3I(z) s3

a4I(z) s4 e

+Vref -Vref

sum

Figure 4-6: Block diagram of Sigma-Delta modulator used in Dolphin Int. NACRE chip

However, as discussed at the TAMES-2 August meeting [TAM02-1], the most time consuming test of the entire ADC is the THD measurement, requiring 16,384 samples for the FFT analysis to achieve a verification of a 90 dB THD. If the decomposition of the high-resolution converter into a first stage filter and a lower-resolution converter still requires testing for 90 dB THD, then no significant test time reduction should expected. Also, any decomposition or reconfiguration based test methodology requires strong evidence for the correlation of tested block performance and overall converter performance parameters. Additionally, the potential for increase yield loss would require careful investigation.

4.5 Analysis of Bit-Stream Discrete Fourier transforms are well suited for the analysis of continuous smoothly varying waveforms. Noting that the output of the modulator is essentially a bit-stream that possesses sharp discontinuities, it seems sensible to investigate transform techniques that are tailored to signals of this nature. Typical traditional transforms that are ideally suited to the analysis of signals with sharp discontinuities are the Walsh-Hadamard and related transforms. In addition, it is felt that discrete wavelett transforms such as the Walsh-Harr wavelet transform could be beneficial for converter testing in terms of both test time reduction and data record size reduction. Also the processing of these transforms may be more suitable for on-chip implementation than conventional discrete Fourier transforms.

4.6 Dedicated Test Solution for Input Sampling Circuitry Eric Compagne explained at the TAMES-2 meeting in August that he expects the source of distortion to be charge injection at the input sampling circuitry in front of the first stage modulator. A basic schematic of the circuitry is given in Figure 4-7. After sampling, the NMOS transmission gate 1a is opened first, followed by CMOS transmission gate 1b. When charge injection occurs, an inaccurately sampled input voltage will result in increased distortion. However, currently no solution can be found on how to test for this effect in the particular circuitry. Dolphin has simulated the sampling stage to analyse THD, however, confidence in the simulation results is low, as the measurement results varied with the chosen simulation step size.

41


VIN

CS

analogue ground

1b

1a

Figure 4-7: Basic input sampling circuitry

4.7 Manipulation of Feedback Loop Varying the feedback loop, to relax the test thresholds for the closed-loop 4th order converter was discussed. Introducing additional delay will make the system instable. However, varying the reference voltages at the feedback loop (differential) DAC was discussed. Eric Compagne mentioned that reducing the reference voltage would amplify the noise. Therefore test thresholds may be relaxed and therefore fewer points will be required for FFT analysis, shortening the test time.

As mentioned earlier, the source of the large number of samples for THD measurements is caused when the distortion components have a similar magnitude as noise components. Ronny Vanhooren proposed to investigate the use of a technique which allows to filter out noise components around the harmonics. The noise shaping may be implemented by a digital band-pass filter within the feedback loop DAC.

These technique will be investigated further trough behavioural simulations at Lancaster.

4.8 Other Initial Ideas Other aspects briefly mentioned in the brainstorm meetings are listed in this section. Further analysis regarding the feasibility of these ideas is required.

To test for linearity it was proposed to use a more than (specified) full-scale input signal, as the linearity is worsening with increasing signal amplitude. This may relax test thresholds and hence reduce test time.

Regarding the particular Dolphin design, a stereo CODEC, one may also consider a test solution which facilitates the duplicity of the system. Reconfiguration techniques may allow to test the two ADCs against each other, for example. Also, the available DACs can be used for TSG, as long as fault masking effects are carefully analysed. Such test methodologies, however, would restrict the test solution to stereo CODEC designs.

4.9 Summary Due to the limitations of conventional test and recently published converter BIST approaches regarding the application to high-resolution converter, it seems that an intelligent decomposition of the converter may be the most promising approach to prevent unacceptable test time.

Some initial ideas are outlined in this chapter, which will form the basis for further tasks of the project where results of investigations will be added. The methodology which may be chosen is discussed in the next chapter.

42


5 Conclusions In this deliverable, conventional A-to-D converter test techniques have been described in Chapter 2. The most widely used conventional test approaches are the FFT analysis and histogram-based testing techniques. The FFT enables analysis of the dynamic converter performance effectively but it does not test for linearity and sometimes it can be time consuming, depending on the amount of data that need to be collected. The histogram-based test method verifies critical static converter performance parameters but unfortunately it poses some major drawbacks from a BIST implementation point of view. First of all it requires a large area overhead to store all the necessary information collected during the testing procedure along with the reference data for the comparison stage of the test. Secondly, the collection of the converter data consumes a large amount of time making this method difficult to implement for the purpose of this project. Histogram-based BIST schemes are included in the third chapter, were a review of recently published converter BIST techniques can be found. The potential for application to high-resolution converters was analysed for all techniques discussed; a summary can be found in section 3.5. Essentially, none of the BIST techniques reviewed can be applied to high-resolution ADC testing without an intolerable increase in test time or area overhead.

The fourth chapter outlined the initial ideas discussed at the TAMES-2 kick-off meeting. These require further investigation to assess their feasibility. The investigation will be based on an analysis of architecture and application specific test requirements. Sensitivities of converter performance to particular sub-circuits will be evaluated to define a structural test approach. This may lead to dedicated test solutions for critical circuit functions while a reconfiguration of remaining circuitry to a lower-resolution converter may allow adaptation of conventional test approaches and/or BIST techniques.

New embedded test solutions for high-resolution Σ∆ converters may be proposed at various levels:

• on-chip pre-processing of the test response for further off-chip analysis, with on-chip or off-chip stimulus generation,

• full on-chip test response evaluation with off-chip stimulus generation, or

• full BIST (including on-chip stimulus generation).

In this context, the authors of this deliverable feel that an embedded test solution for high-resolution converters which can be adapted and applied at one or more of the levels listed above will prove to be of superior industrial strength and feasibility. Further analysis is required to determine if off-chip analysis or stimulus generation can be performed by digital-only or so-called DfT testers. Where necessary, some components may be located on the device interface board. Regarding the application of the test stimulus generated off-chip, further work is required to determine the influence of parasitics on stimulus accuracy. Where the stimulus is generated on-chip, further work is required on the verification of test stimulus accuracy.

43


6 References ALE01 F. Algeria, P. Arpaia, A. M. da Cruz Serra & P. Daponte: ADC histogram test by

triangular small-waves, IEEE Instrumentation and Measurement Technology Conference, IMTC01, 21-23rd May 2001, Budapest, Hungary, pp. 1690-1695

ALE02 F. C. Alegria, P. Arpaia, P. Daponte & A. Cruz Serra: An ADC histogram test based on small-amplitude waves, Measurement, 2002, vol. 31, no. 4, pp. 271-279

ALM99 T. Almy: HABIST case study, www.fluence.com/bistmaxx/, 1999

APP99 D. Appello, S. Audrain, E. Chioffi, A. Daolio & F. Di Giovanni: An economic driven test strategy selection for a mixed VLSI circuit using swBIST solutions, European Test Workshop, ETW99, 25-28th May 1999, Constance, Germany

ARA96 K. Arabi, B. Kamiska & J. Rzeszut: BIST for D/A and A/D converters, IEEE Design & Test of Computers, 1996, vol. 13, no. 4, pp. 40-49

ARA97 K. Arabi & B. Kaminska: Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal circuits, IEEE International Test Conference, ITC97, 3-5th Nov. 1997, Washington, DC, USA, pp. 786-795

ARA97-1 K. Arabi & B. Kaminska: Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology, 15th IEEE VLSI Test Symposium, VTS97, 27th April -1st May 1997, Los Alamitos CA, USA, pp. 166-171

AZA00 F. Azais, S. Bernard, Y. Bertrand & M. Renovell: Towards an ADC BIST scheme using histogram test technique, IEEE European Test Workshop, ETW00, 23-26th May 2000, Cascais, Portugal, pp. 129-134

AZA01 F. Azais, S. Bernard, Y. Bertrand, X. Michel & M. Renovell: On-chip generation of high-quality ramp stimulus with minimal silicon area, 2nd IEEE Latin-American Test Workshop, LATW01, 11-14th Feb. 2001, Cancun, Mexico, pp. 112-117

AZA01-1 F. Azais, S. Bernard, Y. Bertrand & M. Renovell: Implementation of a linear histogram BIST for ADCs, Design, Automation and Test in Europe, DATE01, 13-16th March 2001, Munich, Germany, pp. 590-595

AZA01-2 F. Azais, S. Bernard, Y. Bertrand, X. Michel & M. Renovell: A low-cost adaptive ramp generator for analog BIST applications, 19th IEEE VLSI Test Symposium, VTS01, 29th April - 3rd May 2001, Marina Del Rey, California, USA, pp. 267-271

AZA01-3 F. Azais, S. Bernard, Y. Bertrand & M. Renovell: A low-cost BIST architecture for linear histogram testing of ADCs, Journal of Electronic Testing: Theory and Applications, 2001, vol. 17, no. 2, pp. 139-147

BAC99 A. Baccigalupi: ADC testing methods, Measurement, 1999, vol. 26, no. 3, pp. 199-205

BER01 S. Bernard, F. Azais, Y. Bertrand & M. Renovell: Efficient on-chip generator for linear histogram BIST of ADCs, 7th IEEE International Mixed-Signal Testing Workshop, IMSTW01, 13-15th June 2001, Atlanta, GA, USA, pp. 89-96

BER02 S. Bernard, F. Azais, Y. Berntrand & M. Renovell: A high accuracy triangle-wave signal generator for on-chip ADC testing, 7th IEEE European Test Workshop, ETW02, 26-29th May 2002, Corfu, Greece, pp. 365-370

BLA94 J. Blair: Histogram measurement of ADC nonlinearities using sine waves, IEEE Transactions on Instrumentation and Measurement, 1994, vol. 43, no. 3, pp. 373-383

BRA93 A. H. Bratt, R. J. Harvey, A. P. Dorey & A. M. D. Richardson: Design-for-test structure to facilitate test vector application with low performance loss in non-test mode, Electronics Letters, 1993, vol. 29, no. 16, pp. 1438-1440

BRA95 A. H. Bratt, A. M. D. Richardson, R. J. Harvey & A. P. Dorey: A design-for-test structure for optimising analogue and mixed signal IC test, European Design & Test Conference, ED&TC95, 6-9th March 1995, Paris, France, pp. 24-34

44


BUR00 Burr Brown: Application bulleting: dynamic tests for A/D converter performance, http://www-s.ti.com/sc/psheets/sbaa002/sbaa002.pdf, 1999, pp. 1-10

Publication is based on [PEE83]

BUR01 M. Burns & G. W. Roberts: An introduction to mixed-signal IC test and measurement, Oxford University Press, 2001

CAB99 R. C. Cabot: Fundamentals of modern audio measurement, Journal of the Audio Engineering Society, vol. 47, no. 9, September 1999

Also available at: http://www.audioprecision.com/ftp/publications/technical_papers/FundamentalsofModernAudioMeasurement.pdf

CAS02 R. Castro-Lopes, F. V. Fernandez, M. Delegado-Restituto, F. Medeiro & A. Rodriguez-Vazquez: Generation of technology-portable flexible analog blocks, IEEE International Symposium on Circuits and Systems, ISCAS02, 26-29th May 2002, Scottsdale, Arizona, USA, pp. 61-64

CHE99 K.-T. Cheng: Analog and mixed signal testing, Final Report for MICRO Project 98-023, Dept. of Electrical and Computer Engineering, University of California, 1999

COR75 J. J. Corcoran, T. Hornak & P. B. Skov: A high resolution error plotter for analog-to-digital converters, IEEE Transactions on Instrumentation and Measurement, 1975, vol. IM-24, no. 4, pp. 370-374

DAL02 D. Dallet & P. Daponte: Introduction to special issue on ADC modelling and testing; 4th workshop on ADC modelling and testing, Measurement, 2002, vol. 31, no. 1, pp. 1-2

DAP00 P. Daponte & L. Michaeli: Introduction to special issue on ADC modelling and testing; 3rd workshop on ADC modelling and testing, Measurement, 2000, vol. 28, no. 2, pp. 61-64

DAP02 P. Daponte & L. Michaeli: Introduction to special issue on ADC modelling and testing: 5th workshop on ADC modelling and testing, Measurement, 2002, vol. 31, no. 4, pp. 219-221

DAP96 P. Daponte & L. Michaeli: Introduction to selected papers on ADC modelling, Measurement, 1996, vol. 19, no. 3/4, pp. 129-130

DOE84 J. Doernberg, H. S. Lee and D. A. Hodges: Full-speed testing of A/D converters, IEEE Journal of Solid-State Circuits, 1984, vol. SC-19, no. 6, pp. 820-827

DOL02 Dolphin Integration: hiCOD Spcifications, V 0.8.1, preliminary confidential draft, March 2002

EHS96 M. Ehsanian, B. Kaminska & K. Arabi: New digital test approach for analog-to-digital converter testing, 14th IEEE VLSI Test Symposium, VTS96, 28th April - 1st May 1996, Los Alamitos CA, USA, pp. 60-65

EHS98 M. Ehsanian, B. Kaminska & K. Arabi: New on-chip digital BIST for analog-to-digital converters, Microelectronics and Reliability, 1998, vol. 38, no. 3, pp. 409-420

FLU00 BISTMaxx Product Catalog

FRA96 F. Francesconi, V. Liberali, M. Lubaszewski & S. Mir: Design of high-performance band-pass sigma-delta modulator with concurrent error detection, 3rd IEEE International Conference on Electronics, Circuits and Systems, ICECS96, 13-16th Oct. 1996, Rodos, Greece, pp. 1202-1205

FRI97 A. Frisch & T. Almy: HABIST: histogram-based analog built in self test, IEEE International Test Conference, ITC97, 3-5th Nov. 1997, Washington, DC, USA, pp. 760-767

GIA97 N. Giaquinto & A. Trotta: Fast and accurate ADC testing via an enhanced sine wave fitting algorithm, IEEE Transactions on Instrumentation and Measurement, 1997, vol. 46, no. 4, pp. 1020-1025

45


GRO97 A. Grochowski, D. Bhattacharya, T. R. Viswanathan & K. Laker: Integrated circuit testing, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1997, vol. 44, no. 8, pp. 610-633

HAE00 P. Hädel: Evaluation of a standardized sine wave fit algorithm, IEEE Nordic Signal Processing Symposium, NORSIG00, 13-15th June 2000, Vildmarkshotellet, Sweden, pp. 453-456

HAF00 M. Hafed, N. Abaskharoun & G. W. Roberts: A stand-alone integrated test core for time and frequency domain measurements, IEEE International Test Conference, ITC00, 1-6th Oct. 2000, Atlantic City, NJ, USA, pp. 1031-1040

HUA00 J. Huang, C. Ong & K. Cheng: A BIST scheme for on-chip ADC and DAC testing, Design, Automation and Test in Europe, DATE00, 27-30th March 2000, Paris France, pp. 216-220

HUA00-1 J.-L. Huang & K.-T. Cheng: Testing and characterization of the on-bit first-order delta-sigma modulator for on-chip analog signal analysis, IEEE International Test Conference, ITC00, 1-6th Oct. 2000, Atlantic City, NJ, USA, pp. 1021-1030

HUE00 G. Huertas, D. Vazquez, A. Rueda & J. L. Huertas: A practical method for reading test outcomes in oscillation-based test, 6th IEEE International Mixed-Signal Testing Workshop, IMSTW00, 21-23rd June 2000, Montpellier, France, pp. 135-138

HUE01 G. Huertas, D. Vazquez, E. Perelias, A. Rueda & J. L. Huertas: Oscillation-based test in oversampling A/D converters, 7th IEEE International Mixed-Signal Testing Workshop, IMSTW01, 13-15th June 2001, Atlanta, GA, USA, pp. 35-46

HUE02 G. Huertas, D. Vazquez, A. Rueda & J. L. Huertas: Oscillation-based test in bandpass oversampled A/D converters, 8th IEEE International Mixed-Signal Testing Workshop, IMSTW02, 18-21st June 2002, Montreux, Switzerland, pp. 39-48

HUE99 G. Huertas, D. Vazquez, A. Rueda & J. L. Huertas: Effective oscillation-based test for application to a DTMF filter bank, IEEE International Test Conference, ITC99, 28-30th Sept. 1999, Atlantic City, NJ, USA, pp. 549-555

IEE01 IEEE Standard 1241-2000: IEEE standard for terminology and test methods for analog-to-digital converters, 2001

IEE02 IEEE TC-10 Home Page: http://grouper.ieee.org/groups/1057/index.html

IEE94 IEEE Standard 1057-1994: IEEE standard for digitizing waveform recorders, 1994

IEE99 IEEE Standard 1149.4-1999: IEEE Standard for a Mixed-Signal Test Bus, 1999

KOL93 V. Kolarik, M. Lubaszewski & B. Courtois: Towards self-checking mixed-signal integrated circuits, Proceedings of the 19th European Solid-State Circuits Conference, ESSCIRC93, 22-24th Sept. 1993, Seville, Spain, pp. 202-205

KOL95 V. Kolarik, S. Mir, M. Lubaszewski & B. Courtois: Analog checkers with absolute and relative tolerances, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 1995, vol. 14, no. 5, pp. 607-612

LEC01 A. Lechner, A. Richardson & B. Hermes: Short circuit faults in state-of-the-art ADC's - are they hard or soft, 10th Asian Test Conference, ATS01, 19-21st Nov. 2001, Kyoto, Japan, pp. 417-422; also published in:

A. Lechner, A. Richardson & B. Hermes: Short circuit faults in state-of-the-art ADC's - are they hard or soft, 10th Anniversary Compendium of Papers from Asian Test Symposium, 2001, pp. 343-348

LIS95 J. Lis: Crystal Semiconductor, Application Note: noise histogram analysis, Electronic Engineering Times: 1999 http://www.eetasia.com/ARTICLES/2001APR/2001APR17_AMD_AN7.PDF

LOG99 LogicVision: adcBIST, features and benefits, http://www.lvision.com, 1999, pp. 1-6

46


LUB97 M. Lubaszewski, S. Mir & B. Courtois: Self-testing and self-checking analog integrated circuits, AMATIST ESPRIT Open Workshop, AMATIST97, 13th May 1997, Enschede, Netherlands

MAH87 M. Mahoney: DSP-based testing of analog and mixed-signal circuits, IEEE Computer Society, 1987

MAX89 S. Max: Fast accurate and complete ADC testing, IEEE International Test Conference, ITC89, 29-31th Aug. 1989, Washington, DC, USA, pp. 111-117

MAX99 S. Max: Testing high speed high accuracy analog to digital converters embedded in systems on a chip, IEEE International Test Conference, ITC99, 28-30th Sept. 1999, Atlantic City, NJ, USA, pp. 763-771

MAX99-1 S. Max: Optimum measurement ADC transitions using a feedback loop, 16th IEEE Instrumentation and Measurement Technology Conference, IMTC99, 24-26th May 1999, Venice, Italy, pp. 1415-1420

MIR94 S. Mir, V. Kolarik, M. Lubaszewski, C. Nielsen & B. Courtois: Built-in self-test and fault diagnosis of fully differential analogue circuits, IEEE/ACM International Conference on Computer Aided Design, ICCAD94, 6-10th Nov. 1994, San Jose, California, USA, pp. 486-490

MIR96 S. Mir, M. Lubaszewski & B. Courtois: Unified built-in self-test for fully differential analog circuits, Journal of Electronic Testing: Theory and Applications, 1996, vol. 9, no. 1-2, pp. 135-151

MIR96-1 S. Mir, M. Lubaszewski & B. Courtois: Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets, Journal of Electronic Testing: Theory and Applications, 1996, vol. 9, no. 1-2, pp. 43-57

MIR97 S. Mir, A. Rueda, J. L. Huertas & V. Liberali: A BIST technique for sigma-delta modulators based on circuit reconfiguration, 3rd IEEE International Mixed Signal Testing Workshop, IMSTW97, 3-6th June 1997, Seattle, Washington, USA, pp. 179-184

OHL91 M. J. Ohletz: Hybrid built in self-test (HBIST) for mixed analogue/digital ICs, 2nd European Test Conference, ETC91, 10-12th April 1991, Munich, Germany, pp. 307-316

ONG01 C. K. Ong, J. L. Huang & K. T. Cheng: Testing second-order delta-sigma modulators using pseudo-random patterns, 7th IEEE International Mixed-Signal Testing Workshop, IMSTW01, 13-15th June 2001, Atlanta, GA, USA, pp. 55-71

OTT02 R. H. J. M. Otten, R. Camposano & P. R. Groeneveld: Design automation for deepsubmicron: present and future, Design, Automation and Test in Europe, DATE02, 4-8th March 2002, Paris, France, pp. 650-657

PAN02 Panel: B. Lewis, I. Bolsons, R. Lauwereins, C. Wheddon, B. Gupta, Y. Tanurhan: Reconfiguration SoC -- what will it look like, Design, Automation and Test in Europe, DATE02, 4-8th March 2002, Paris, France, pp. 660-662

PEE83 B. E. Peetz: Dynamic testing of waveform recorders, IEEE Transactions on Instrumentation and Measurement, 1983, vol. IM-32, no. 1, pp. 12-17

Some additional graphs and plots are included in [BUR00].

RAC95 J. Raczkowycz & S. Allott: Embedded ADC characterisation techniques, IEE Proceedings: Circuits, Devices and Systems, 1995, vol. 142, no. 3, pp. 145-152

RAC96 J. Raczkowycz & S. Allott: Embedded ADC characterization techniques using a BIST structure, an ADC model and histogram data, Microelectronics Journal, 1996, vol. 27, no. 6, pp. 539-549

RAC96-1 J. Raczkowycz & S. Allott & T. I. Pritchard: Data optimization test technique for characterizing embedded ADCs, Journal of Electronic Testing: Theory and Applications, 1997, vol. 9, no. 1-2, pp. 165-175

47


REN00 M. Renovell, F. Azais, S. Bernard & Y. Bertrand: Hardware resource minimization for histogram-based ADC BIST, 18th IEEE VLSI Test Symposium, VTS00, 30th April - 4th May 2000, Montreal, Quebec, Canada, pp. 247-252

SCH02 R. Schreiber, Texas Instruments: Achieving better performance in high-resolution ADCs, understanding the sources and types of errors in ADCs can help you obtain maximum performance from them, EDN, 2/5/2002;

http://www.e-insite.net/ednmag/contents/images/194929.pdf

SIA01 Semiconductor Industry Association: International Technology Roadmap for Semiconductors, 2001 Edition, 2001

SIA99 Semiconductor Industry Association: International Technology Roadmap for Semiconductors, 1999 Edition, 1999, and

Semiconductor Industry Association: International Technology Roadmap for Semiconductors, 2000 Update, 2000

SOU81 T. M. Sounders & R. D. Flach: An NBS calibration service for A/D and D/A converters, IEEE International Test Conference, ITC81, 27-29th Oct. 1981, Philadelphia, PA, USA, pp. 290-303

SUN01 S. Sunter: Mini Tutorial: Mixed signal test, 7th IEEE International Mixed-Signal Testing Workshop, IMSTW01, 13-15th June 2001, Atlanta, GA, USA

SUN01-1 Private conversation with S. Sunter at 7th IEEE International Mixed-Signal Testing Workshop, IMSTW01, 13-15th June 2001, Atlanta, GA, USA

SUN97 S. K. Sunter & N. Nagi: A simplified polynomial-fitting algorithm for DAC and ADC BIST, IEEE International Test Conference, ITC97, 3-5th Nov. 1997, Washington, DC, USA, pp. 389-395

TAM02 TAMES-2 kick-off meeting, 21-22nd March 2002, Lancaster, UK

TAM02-1 TAMES-2 meeting, 27th August, Grenoble, France

TER93 E. Teraoka, T. Kengaku, I. Yasui, K. Ishikawa, T. Matsuo, H. Wakada, N. Sakashita, Y. Shimazu & T. Tokada: A built-in self-test for ADC and DAC in a single chip speech CODEC, IEEE International Test Conference, ITC93, 17-21st Oct. 1993, Baltimore, MD, USA, pp. 791-796

TER97 E. Teraoka, T. Kengaku, I. Yasui, K. Ishikawa, T. Matsuo & H. Wakada: Built-in self-test for ADC and DAC in a single-chip speech CODEC, IEICE Transactions on Fundamentals of Electronics Communications and, 1997, vol. e80a, no. 2, pp. 339-345

TON93 M. F. Toner & G. W. Roberts: A BIST scheme for an SNR test of a sigma-delta ADC, IEEE International Test Conference, ITC93, 17-21st Oct. 1993, Baltimore, MD, USA, pp. 805-814

TON95 M. F. Toner & G. W. Roberts: A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995, vol. 42, no. 1, pp. 1-15

TON96 M. F. Toner & G. W. Roberts: A frequency response, harmonic distortion test for BIST of a sigma-delta ADC, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1996, vol. 43, no. 8, pp. 608-613

TUR01 J. Turino: Reducing mixed-signal SoC test cost using BIST, 7th IEEE International Mixed-Signal Testing Workshop, IMSTW01, 13-15th June 2001, Atlanta, GA, USA, pp. 103-107

TUR01-1 J. Turino: Built-in self-test streamlines testing of mixed-signal SoCs, Electronic Design, 2001, vol. 49, no. 14, pp. 67-74

VAN86 M. Vanden Bossche, J. Schoukens & J. Renneboog: Dynamic testing and diagnosis of A/D converters, IEEE Transactions on Circuits and Systems, 1986, vol. 33, pp. 775-785

48


VAR02 Hot Topic, various contributions: How to choose semiconductor IP?, Design, Automation and Test in Europe, DATE02, 4-8th March 2002, Paris, France, pp. 13-17

VAR02-1 Embedded Tutorial: M. Milligan, Y. Zorian, S. Pateras & M. Nicolaidis: The need for infrastructure IP in SoCs, Design, Automation and Test in Europe, DATE02, 4-8th March 2002, Paris, France, pp. 237-246

VAZ02 D. Vazquez, G. Huertas, G. Leger, A. Rueda & J. L. Huertas: Practical solutions for the application of the oscillation-based-test in analog integrated circuits, IEEE International Symposium on Circuits and Systems, ISCAS02, 26-29th May 2002, Scottsdale, Arizona, US, pp. 589-592

VAZ97 D. Vazquez, A. Rueda, J. L. Huertas & E. Peralias: Unified off- and on-line testing in analog circuits: concept and practical demonstrator, 3rd IEEE International Mixed Signal Testing Workshop, IMSTW97, 3-6th June 1997, Seattle, Washington, USA, pp. 169-174

VRI97 R. de Vries, T. Zwemstra, E. M. J. G. Bruls & P. P. L. Regtien: Built-in self-test methodology for A/D converters, European Design & Test Conference, ED&TC97, 17-20th March 1997, Paris, France, pp. 353-358

WEN00 Y.-C. Wen & K.-J. Lee: An on chip ADC test structure, Design, Automation and Test in Europe, DATE00, 27-30th March 2000, Paris France, pp. 221-225

49

TAMES-2 D.1.1, Version 1.1Appendix: Testability of Analogue Macrocells Embedded in System-on-Chip

APPENDIX

50


Appendix A: ADC Characteristics The appendix provides some definitions of converter performance parameters and describes statistical representations of converter activity with histograms for a ramp and sine-wave input stimulus. Functional converter failure is illustrated and discussed for evaluating the transfer characteristics in the time domain and by analysing histograms.

In literature, it is frequently stated that ADC characteristics are almost identical to that of DACs if input and output definitions are interchanged [GEI90]. However, this is not strictly true, as the A-to-D conversion is not mathematically the inverse of a D-to-A conversion [JOH97, MAH87]. The difference can be illustrated in converter transfer functions, which usually describe the converter response to a ramped input. For DACs, a digital, discrete input pattern is converted to a single corresponding output voltage, resulting into point map ideal transfer characteristic (Figure A-1). For ADCs, a continuous range of the input voltage is converted into a single, digital, discrete output word. In the ideal case, one can give the output code for a particular ADC input voltage. However, predicting the exact ADC input voltage by knowing the output code is impossible due to the one-way uncertainty, which is illustrated by horizontal lines for each output code with a width of 1 LSB (Figure A-2). The figure also depicts the last and first transition edge. These are usually defined as the ADC input voltage where the ADC output changes from the lowest output word to the second lowest, and from the second highest to the highest output word. For ADCs which indicate underflow (unf) or overflow (ovf), the first transition edge can be defined as the analogue input voltage where the transition from underflow to the lowest output word occurs. Analogously, the last transition occurs at the change from the highest output word to ADC overflow.

DAC input 000 001 010 011 100 101 110 111

FS

7/8FS

3/4FS

5/8FS

1/2FS

3/8FS

1/4FS

1/8FS

DAC

out

put

0

Figure A-1: Ideal 3-bit DAC

ADC input

1/8F

S

111

110

101

ADC

out

put

1/4F

S

3/8F

S

1/2F

S

5/8F

S

3/4F

S

7/8F

S FS

100

011

010

001

000 code centre

codewidth

Figure A-2: Ideal 3-bit ADC

representational line

representational ideal line

1st tr

ansi

tion

edge

last transition edge

In literature, converter transfer characteristics are frequently represented by a staircase wave. However, for this work transfer characteristics may be represented by best-fit lines or curves through the transfer points of DACs or the centres of ADC code widths, as included in the figures above.

51


A.1 Characterisation of ADCs As techniques for ADC testing are reviewed within this deliverable, some definitions of static and dynamic performance parameters are given for ADCs only. For more details and other converter performance parameters see [GEI90, MAH87, PHI99-1, PLA94, TIL00].

A.1.1 Static Performance Parameters

Static performance parameters are independent of time and are defined in this section. Most performance parameters compare the converter against the ideal case by approximating the transfer characteristics by a straight line. The straight line can be either the best-fit one (linear regression computation, [PHI99-1]) or the line drawn through the end points zero and full-scale.

Resolution

Resolution is the smallest change in analogue input voltage that has to cause a change in the digital output of an ideal ADC. For a converter with N bits and a full-scale (FS, difference between maximum and minimum input voltage with N approaching infinity), the resolution is given as:

LSB 12

== N

FSresolution (A.1.1-1)

Where the resolution is given in percentage of full-scale or as 1 LSB. The finite converter resolution causes an inherent uncertainty, as mentioned above, called quantisation noise. Assuming that a ramp stimulus is applied to the ADC which is followed by an ideal DAC and subtracting the analogue output from the original ramp signal, reveals the quantisation signal (Figure A-3).

time

111

110

101

digi

tal d

omai

n

100

011

010

001

000

ADC input ADC output DAC output

FS

7/8FS

3/4FS

5/8FS

1/2FS

3/8FS

1/4FS

1/8FS

0

anal

ogue

dom

ain

Quantisation noise

Figure A-3: Ideal quantisation noise

Offset error

An offset error can be identified as a uniform displacement of the transfer curve in x-direction, as depicted for an ideal ADC affected by an offset error only in Figure A-4. For real ADCs, the centres of the transfer regions do usually not fall on a straight line. Hence the offset is usually defined as the voltage where a best-fit straight line for the centres of transfer regions intersects with the x-axis. The offset error is the deviation of the intersect compared to the ideal case. Values can be given in milli-volts, percentage of full-scale or in LSB equivalent. Commonly in the context of ADC BIST solutions the offset error is assessed when a ramp stimulus is applied to the ADC, and is defined as the deviation of the first transition edge from its nominal value.

52


Gain error

A gain error can be visualised as a deviation in the slope of the transfer curve (Figure A-5). For real ADCs, a gain error is defined as the deviation in slope for a best-fit straight line for the centres of transfer regions compared to the ideal case. Commonly in the context of ADC BIST solutions the gain error is assessed when a ramp stimulus is applied to the ADC, and is defined as the deviation of the last transition edge from its nominal value when offset effects have been cancelled.

Differential Non-Linearity (DNL)

In real ADCs, irregularities or non-uniformity in code widths can occur, which usually have their strongest effect at the centre of the transfer curve where the MSB changes. For an n-bit ADC, the code width, which is usually calculated from measured code transition edges [PLA94], can deviate from its nominal value of FS/(2N) or 1 LSB. Hence DNL, an indicator for variation in the code width itself, can be given for each potential output code. However, the ADC’s absolute DNL is the maximum of all codes’ DNLs. Figure A-6 illustrated a DNL of approximately +½ LSB for one particular output code. A differential linearity failure does not necessarily manifests itself as a deviation in the best-fit straight line. Commonly in the context of ADC BIST solutions the (absolute) DNL is assessed when a ramp stimulus is applied to the ADC, and is defined as the maximum deviation in code width compared to the ideal case. Additionally, local DNL maxima are considered for failure diagnosis.

Integral Non-Linearity (INL)

The INL, a measure for the relative accuracy, identifies the deviation of code centres from the ideal straight line and can be given for each output code. An ADC’s absolute INL is the maximum INL of all code words, given in the same units as DNL values. Even though Figure A-7 illustrates INL deviation for one particular code, DNL and INL are strongly correlated. INL values, for example, can be computed from measured transition edges, as well. Commonly in the context of ADC BIST solutions the (absolute) INL is assessed when a ramp stimulus is applied to the ADC, and is defined as the maximum deviation of a code centre from the ideal straight line. INL values for each code are computed by accumulating DNL values from the lowest code up to the code under test. Additionally local INL maxima can be considered for failure diagnosis.

Monotonicity and Missing Codes

In literature, the following definitions for monotonicity can be found [PLA94]. For DACs “monotonicity … means that the output of … a DAC never decreases with an increasing digital input code. A minimum increase of zero is allowed for a 1 LSB increase in input signal in a DAC. … In an ADC, monotonicity means that no missing codes can occur.” In [PHI99-1] monotonicity is defined as the requirement that an “ADC ramp response must have a constant slope sign.” Commonly in the context of ADC BIST solutions monotonicity is assessed when a ramp stimulus is applied to the ADC, where monotonicity means that digital output never decreases with an increasing analogue input (which does not guarantee the presence of each code). However, when a single ADC output sample is affected by a hazard or toggle in the LSB (compared to both of its neighbours in the time domain) it is usually not interpreted as monotonicity failures but as a noise effect. For a particular analogue input stimulus, a code is called missing when it cannot be observed at the output.

Non-monotonic behaviour (without missing codes) is illustrated in Figure A-8. Another example for rather catastrophic malfunction is depicted in Figure A-9, where a whole code is missing due to excessive non-linearity (code’s DNL < -1 LSB), while monotonicity is maintained.

53


ADC input

111

110

101

ADC

out

put

1/4F

S

3/8F

S

1/2F

S

5/8F

S

3/4F

S

7/8F

S FS

100

011

010

001

000

ideal line

OE

1/8F

S

Figure A-4: ADC with offset error

ADC input

111

110

101

ADC

out

put

100

011

010

001

000

ideal line

1/4F

S

3/8F

S

1/2F

S

5/8F

S

3/4F

S

7/8F

S FS

1/8F

S

Figure A-5: ADC with gain error

111

110

101

ADC

out

put

100

011

010

001

000

ideal code width

ADC input

1/4F

S

3/8F

S

1/2F

S

5/8F

S

3/4F

S

7/8F

S FS

1/8F

S

Figure A-6: ADC with DNL deviation

111

110

101

ADC

out

put

100

011

010

001

000

ADC input

1/4F

S

3/8F

S

1/2F

S

5/8F

S

3/4F

S

7/8F

S FS

1/8F

S

Figure A-7: ADC with INL deviation

111

110

101

ADC

out

put

100

011

010

001

000

ADC input

1/4F

S

3/8F

S

1/2F

S

5/8F

S

3/4F

S

7/8F

S FS

1/8F

S

Figure A-8: Non-monotonic ADC

ADC input

1/8F

S

111

110

101

ADC

out

put

1/4F

S

3/8F

S

1/2F

S

5/8F

S

3/4F

S

7/8F

S FS

100

011

010

001

000

Figure A-9: ADC with missing code

line for offset error affected

ADC

line for gain error affected

ADC

DNL affected code width

INL

Non-monotonic behaviour

missing code

DNL

INL

54


A.1.2 Dynamic Performance Parameters

Primarily, dynamic characteristics of an ADC have to do with the speed of operation and the effect of noise contributions.

Conversion time

Due to the conversion of a continuous analogue input to a digital word, sampling or discrete time signals are inherent. Therefore, the rate at which the converter can operate is of interest. The conversion time is the time from the application of the signal to start conversion to the availability of the output signal, sometimes referred to as settling time [PLA94].

Compared to DACs with relatively short conversion times, ADCs may require one or more clock cycles following the application of the analogue input signal before the output digital word is available. This is particularly the case for successive approximation or tracking ADC architectures [GEI90], where the conversion time also varies for different ADC input voltages. For full-flash and folding ADC architectures, the conversion time is usually smaller than the clock period. Another important aspect of the conversion time is the aperture uncertainty which is the time jitter in the sample-and-hold point that causes amplitude uncertainty.

Signal-to-Noise Ratio (SNR)

Possibly the most important dynamic performance parameter is the SNR. It is defined as the square root of the ratio of the output signal power to the noise power (excluding harmonics power, see SINAD).

=

noise

signal

PP

SNR 10log10]dB[ (A.1.2-1)

The SNR should ideally follow a theoretical formula derived below. In the ideal case, noise consists entirely of quantisation error (Figure A-3). For a full-scale ramp input signal Vfs, the ideal noise power can be determined to:

12

2

,LSBP idealnoise = (A.1.2-2)

Hence, the ideal SNR is given as:

( )

[ ]( )dB 76.102.6

812log202log20

8122log10

121

281

log10

12

241

21

log10

12

221

log10log10]dB[

1010

2

10

2

102

2

10

2

2

10,

10

+=

+=

=

⋅=

⋅⋅

=

⋅

=

=

n

LSB

LSB

LSB

V

PP

SNR

NN

NN

fs

idealnoise

signalideal

(A.1.2-3)

55


Signal-to-Noise And Distortion ratio (SINAD)

The SINAD is defined as the square root of the ratio of the output signal power to the noise and distortion power:

=

+distortionnoise

signal

PP

SINAD 10log10]dB[ (A.1.2-4)

Effective Number Of Bits (ENOB)

A measure for the actual ADC accuracy, or effective resolution can be obtained from the ENOB, which is derived from SINAD and gives the number of bits an ideal ADC would require to match the SINAD of the real ADC:

dB02.61.76dB[dB]−= SINADENOB (A.1.2-5)

Total Harmonic Distortion (THD)

The THD is the ratio of the power of the harmonics to the power of the fundamental. Usually, the power up to the fifth harmonic is considered.

=

signal

harmonics

PPTHD 10log10]dB[ (A.1.2-6)

Usual computation of dynamic performance parameters for ADCs

The converter is stimulated with a sine-wave signal and a sequence of ADC output samples is computed in a transient analysis. The sequence of, for example, 512 samples is transformed into a frequency spectrum where the following algorithm is performed to extract the fundamental frequency, SNR, SINAD and THD.

The frequency bins are partitioned in the following manner:

characterise all bins initially as noise (N), • • • • •

mark bin 0 and its roll off bins (to account for spectral leakage) as the DC component (D), mark the last bin and its roll off bins as Nyquist (Q), mark the maximum remaining bin and its roll off bins as the fundamental component (F), calculate the ideal centres for five harmonics, find the true centres, and mark them and their

roll offs bins as harmonics (H).

With those frequency components and Ai being the amplitude of bin i, SNR, SINAD and THD can be given as:

=

+−=

=

∑∑

∑∑

∑

∑

∑

∈

∈

∈∈

∈

∈

∈

Hii

Hii

Hii

Nii

N

H

Fii

Nii

N

Fii

A

ATHD

AAF

FF

ASINAD

AFF

ASNR

2

2

10

22

2

10

2

2

10

log10]dB[

log10]dB[

log10]dB[

(A.1.2-7)

56


A.2 Histograms of Fault Free and Fault Affected ADCs Compared to the figures in section 2.1.1, histograms of higher resolution ADCs are represented by curves in this section. Also, to illustrate the functional failure in the time domain, the equivalent analogue voltage (v(out)) for the digital ADC output is depicted, which would be obtained by an ideal D-to-A conversion. Typically the histogram of the CUT is tested against a golden reference histogram; hence, difference histograms are also included. The effect of the failure mode has been exaggerated and noise floors are excluded. Note that single failures are illustrated in most cases and real histograms may include any combination of these. Figure A-10 shows ramp stimulus responses and Figure A-11 the responses to sine-wave stimuli.

57


Case Time domain Histogram Difference Histogram

Idea

l

time

v(ou

t)in

put s

igna

l sw

ing

bin

bin

coun

t

unf ovf

Off

set E

rror

time

v(ou

t)

ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

Gai

n E

rror

time

v(ou

t)

ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

Non

-Lin

eari

ty

time

v(ou

t)

ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

Dis

tort

ion

time

v(ou

t)

ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

offset error offset error

gain error

gain error

non-linearity

error

non-linearity

error

crossover distortion

crossover distortion

Figure A-10: Functional failure modes of ADCs illustrated in ramp stimulus histograms

58


Case Time domain Histogram Difference Histogram

Idea

l time v(

out)

inpu

t sin

gal s

win

g bin

bin

coun

t

Off

set E

rror

time

v(ou

t)

ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

Gai

n E

rror

time

v(ou

t) ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

Non

-Lin

eari

ty

time

v(ou

t)

ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

Dis

tort

ion

time

v(ou

t)

ideal

bin

bin

coun

t

ideal

bin

∆bin

cou

nt

offset error offset error

gain error

gain error

non-linearity

error non-

linearity error

crossover distortion crossover

distortion

Figure A-11: Functional failure modes of ADCs illustrated in sine-wave histograms

59


References for Appendix GEI90 R. L. Geiger, P. E. Allen & N. R. Strader: VLSI design techniques for analog and

digital circuits, McGraw-Hill, New York, 1990

JOH97 D. A. Johns & K. Martin: Analog integrated circuit design, John Wiley & Sons Inc., 1997

MAH87 M. Mahoney: DSP-based testing of analog and mixed-signal circuits, IEEE Computer Society, 1998

PHI99-1 Philips Internal Document: Mixed signal testing cookbook, version 2.1, Nat.Lab. Report 7103, 1999

PLA94 R. van de Plassche: Integrated analog-to-digital and digital-to-analog converters, Kluwer Academic Publishers, 1994

TIL00 S. J. Tilden, T. E. Linnenbrink & P. J. Green: Standard for terminology and test methods for analog-to-digital converters: a case study of utilization of IEEE-STD-1241, Computer Standards & Interfaces, 2000, vol. 22, pp. 103-112

60

review of test strategies and resources used in high ...tames-2 d.1.1, version 1.1 testability of...

Documents