round robin prioritizer
TRANSCRIPT
1
Round Robin Prioritizer:
Barrel Shifters & Priority Resolvers
2
Muxes and their application EXERCISE
3
SOLUTIONMuxes and their application
4
Muxes and their application EXERCISE
5
Muxes and their application SOLUTION
6
Barrel Shifter
7
Barrel Shifter
84-bit Right-Shifting Barrel Shifter implementation using 4-to-1 muxes
S1S0
S1S0
S1S0
S1S0
0
0
1
1
EXERCISE
94-bit Right-Shifting Barrel Shifter implementation using 4-to-1 muxes
S1S0
S1S0
S1S0
S1S0
0
0
1
1
SOLUTIONPART 1
104-bit Right-Shifting Barrel Shifter implementation using 4-to-1 muxes
S1S0
S1S0
S1S0
S1S0
0
0
1
1
SOLUTIONPART 2
114-bit Right-Shifting Barrel Shifter implementation using 4-to-1 muxes
S1S0
S1S0
S1S0
S1S0
0
0
1
1
SOLUTIONPART 3
I0
I1
I1
I2
I2
I3
I3
I0
124-bit Right-Shifting Barrel Shifter implementation using 4-to-1 muxes
S1S0
S1S0
S1S0
S1S0
0
0
1
1
SOLUTIONPART 4
I0
I1
I2
I3
I1
I2
I3
I0
I2
I3
I0
I1
I3
I0
I1
I2
134-bit Right-Shifting Barrel Shifter implementation using 2-to-1 muxes
S1 S0
S1 S0
S1 S0
S1 S0
0
0
1
1
EXERCISE
144-bit Right-Shifting Barrel Shifter implementation using 2-to-1 muxes
S1 S0
S1 S0
S1 S0
S1 S0
0
0
1
1
SOLUTIONPART 1
154-bit Right-Shifting Barrel Shifter implementation using 2-to-1 muxes
S1 S0
S1 S0
S1 S0
S1 S0
0
0
1
1
SOLUTIONPART 2
164-bit Right-Shifting Barrel Shifter implementation using 2-to-1 muxes
S1 S0
S1 S0
S1 S0
S1 S0
0
0
1
1
SOLUTIONPART 3
I0
I2
I1
I3
I2
I0
I3
I1
17Fixed Priority Resolver
EXERCISE
18
SOLUTION
Fixed Priority Resolver
19Rotating Prioritization
20
Input
Rotator
(a barrel
shifter)
Output
Rotator
(a barrel
shifter)
Fix
ed P
rio
rit
y R
esolv
er
Rotating Prioritizer: We can implement it using 2 barrel-shifters and 1 fixed priority resolver in the center as shown.
All signal are active-high here.
21
Input
Rotator
(a barrel
shifter)
Non-standard
00=shift right by 1
RQ0
RQ1
RQ2
RQ3
Output
Rotator
(a barrel
shifter)
Non-standard
00=shift left by 1
GT0
GT1
GT2
GT3
Fix
ed P
rio
rit
y R
esolv
erR0
R1
R2
R3
G0
G1
G2
G3
RIGHT LEFT
I1 I0 is the ID of the Most Recent Grantee
I0
I1
Rotating Prioritizer: We can implement it using 2 barrel-shifters and 1 fixed priority resolver in the center as shown.
22
23
One-hot coded grants to 2-bit encoded ID of the grants
GT3 GT2 GT1 GT0 ID1 ID0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
0 0 0 0
24
One-hot coded grants to 2-bit encoded ID of the grants
GT3 GT2 GT1 GT0 ID1 ID0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
0 0 0 0 X X
25
I0
I1
S
Y
CLK
D Q
Preset
~Reset
ID0GT1
GT3
I0
I1
S
Y
CLK
D Q
Preset
~Reset
ID1GT2
GT3
EXERCISE
26
I0
I1
S
Y
CLK
D Q
Preset
~Reset
I0ID0GT1
GT3
I0
I1
S
Y
CLK
D Q
Preset
~Reset
I1ID1GT2
GT3
GT0
GT1
GT2
GT3
0 “0” means no one got grant, so we should
not update the ID (I1 I0) in the 2 FFs. We
should retain the information by
recirculating the current value
SOLUTION
27
1 0
2 3
1 0
2 31st level
2nd level
2-level Rotating Prioritization
28
Input
Rotator
(a barrel
shifter)
Non-standard
00=shift right by 1
RQ0
RQ1
RQ2
RQ3
Output
Rotator
(a barrel
shifter)
Non-standard
00=shift left by 1
GT0
GT1
GT2
GT3
Fix
ed P
rio
rit
y R
esolv
erR0
R1
R2
R3
G0
G1
G2
G3
RIGHT LEFT
I1 I0 is the ID of the Most Recent Grantee
I0
I1
From previous single-level PPR (Rotating Priority Resolver)
29
I0
I1
S
Y
CLK
D Q
Preset
~Reset
I0ID0GT1
GT3
I0
I1
S
Y
CLK
D Q
Preset
~Reset
I1ID1GT2
GT3
GT0
GT1
GT2
GT3
0 “0” means no one got grant, so we should
not update the ID (I1 I0) in the 2 FFs. We
should retain the information by
recirculating the current value
30
EXERCISE
31
GT0_2nd
GT1_2nd
GT2_2nd
GT3_2nd
1st level2nd level
GT3_1st
GT3_1st
GT0_2ndSOLUTION
In the presence of this AND gate, we can use the original labels
GT[3:0] to reduce timing path delays.
Negative-logic
OR gate same as
positive-logic
AND gate
32
EXERCISE
33
ARQ0 𝟏
𝟐, BRQ0
𝟏
𝟒, CRQO
𝟏
𝟖, and CRQ1
𝟏
𝟖
SOLUTION
AGT0, BGT0, AGT0, CGT0, AGT0, BGT0, AGT0, CGT1, ….