rpn oxynitride gate dielectrics for 90 nm low power ......© imec 2002 a. veloso, presentation at...

© imec 2002

RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS

Applications

A. Veloso1, M. Jurczak1, F. N. Cubaynes2, R. Rooyackers1, S. Mertens1, A. Rothschild1, M. Schaekers1,

H. N. Al-Shareef3, R. W. Murto3, C. J. J. Dachs2, G. Badenes1

1IMEC, Kapeldreef 75, 3001 Leuven, Belgium2Philips Research Leuven, Leuven, Belgium

3 International Sematech, Austin-TX, USA

© imec 2002 A. Veloso, Presentation at ESSDERC, September 24-26th, 2002 2

Outline

• Growth of oxynitride films using Remote PlasmaNitridation (RPN)

• Gate dielectric optimization:- Physical analysis of RPN oxynitrides- Electrical results

• Device fabrication (90 nm CMOS process)

• Transistor performance

• Summary and conclusions

© imec 2002

Growth of oxynitride films using Remote Plasma Nitridation (RPN)


Growth of oxynitride films: reactions

1) Growth of a pure thin oxide film (dry or wet OxidationOxidation):

RTORTO=Rapid Thermal Oxidation (1-700 Torr)

Si + O2 ⇒ SiO2

ISSGISSG=In Situ Steam Generation (< 20 Torr)

2 H2 + O2 ⇒ 2 H2OSi + 2 H2O ⇒ SiO2 + 2 H2

2) NitridationNitridation:

RPNRPN=Remote Plasma Nitridation (< 4 Torr)

N2 + He ⇒ N*SiO2 + N* ⇒ SiOxNy

3 kW


General aspects of RPN

• Microwave plasma source activates nitrogen (N*)• Nitrogen is diluted with helium:

↑ helium ⇒ easier activation of nitrogen

20% He + 80% N2 ⇒ lower [N*]80% He + 20% N2 ⇒ higher [N*]

• “Remote” plasma source prevents plasma damage (no direct wafer exposure to the plasma)


Mechanism of nitridation by RPN

Generation of active nitrogen N* in a plasma

Transport of N* to the substrate in the RTP chamber

Diffusion of N* into SiO2 film (also nitrogen profile control)

Reaction of N* with SiO2 to form SiOxNy

© imec 2002

Gate dielectric optimization: physical analysis


Nitrogen incorporation in NO post-annealed oxides (REF)

0 200 400 600 8000

300

600

900

1200

1500

1800

30S

i Int

ensi

ty (c

ount

s)

Sputter time (sec)

0 200 400 600 800

0

50

100

150

200

250

300

Si 2N

Inte

nsity

(cou

nts)

Si/SiO2 interface

N is mainly present at the SiOxNy/e-Si interface

Build-up of fixed positive charge, mobility degradation


10 20 30 40 50 600

1500

3000

4500

6000

7500

30S

i Int

ensi

ty (c

ount

s)

Depth (nm)

50 100 150 200 250 300

0

500

1000

1500

2000

2500

Si 2N

Inte

nsity

(cou

nts)

Sputter time (sec)

Nitrogen incorporation in RPN oxynitrides

1.5nm ISSG +

RPN (65% He)

• N profile more homogeneous than in NO post-annealed (O2 + NO) oxides• [N] in RPN oxides > [N] in (O2+NO) oxides

Si/S

iO2

inte

rfac

e


N distribution in RPN oxynitrides

0

0.2

0.4

0.6

4 12 20 28

Depth (Å)

fract

ion

on N

in S

iOxN

y 80 % He

[N] = 17.8 at.%

0

0.3

0.6

0.9

2.5 7.5 12.5 17.5Depth (Å)

fract

ion

on N

in S

iOxN

y 20 % He

[N] = 11.7 at.%

• Most of the nitrogen is detected as N in a silicon (oxy)nitride

• RPN time ↑ ⇒ N content ↑

• % He ↑ ⇒ N content ↑

• % He ↑ ⇒ N distribution more homogenous

• Thickness variations across the wafer related to variations in theamount of N and not of O

© imec 2002

Gate dielectric optimization: electrical results


EOT and VFB extraction (NMOS)

14

44

74

104

134

-2.1 -1.6 -1.1 -0.6 -0.1VG (V)

Cap

acita

nce

(pF)

data @ 100 kHz

model fit

EOT, VFB estimated from C-V measurements using the CVC model*

V

Substrate

Oxide Gate

I

DrainSource

Model fit agrees well with experimental data

100 × 100 µm2 measurements on square capacitors / double transistors

(shorted source/drain)

* J. R. Hauser et al., Characterization and Metrology for VLSI Technology, pp. 235-239 (1998)


JG vs. EOT (NMOS)

1.65 1.80 1.95 2.10 2.251E-3

0.01

0.1

1

10

LSTP SPEC

LOP SPEC

- ISSG (850 °C) + RPN- ISSG (950 °C) + RPN- RTO (1000 °C) + RPN- RTO (950 °C) + RPN

J G (A

/cm

2 ) @

V

G-V

T = 1

V

EOT (nm)

20 % He

80 % He

REF

∆JG

1.65 1.80 1.95 2.10 2.251E-3

0.01

0.1

1

10

LSTP SPEC

LOP SPEC


J G (A

/cm

2 ) @

V

G-V

T = 1

V

EOT (nm)

20 % He

80 % He

REF

∆JG

REF

∆JG

I-Vs measured on transistors with W = 150 µm and L = 5 µm

% He ↑ ⇒ [N] ↑ ⇒ EOT ↑ + JG ↓


Electron mobility (µeff, NMOS)

1.65 1.80 1.95 2.10 2.25175

200

225

250


µ ef

f,max

(cm

2 /V.se

c)

EOT (nm)

80 % He

20 % He

REF∆µeff,max

1.65 1.80 1.95 2.10 2.25175

200

225

250


µ ef

f,max

(cm

2 /V.se

c)

EOT (nm)

80 % He

20 % He

REF∆µeff,max

• µeff (RPN oxynitrides) > µeff (NO post-annealed oxides)• % He ↑ ⇒ [N] ↑ ⇒ EOT ↑ + µeff ↑• EOT ≥ 2.0 nm ⇒ µeff ≈ 230 cm2/V.sec

LWCVG

oxDS

meff ..=µ

mVVG

Dm

DSVIG

50=

∂∂

=

EOTC SiOox

2ε

=mLmW

µµ

5150

==


Field effect electron mobility (µeff, NMOS)

0.0 0.5 1.0 1.5 2.00

50

100

150

200

250

300

350

400

ef

fect

ive

mob

ility

µef

f (cm

2 /V.se

c)

Eeff (MV/cm)

µeff

universal mobility curve

µeff(Eeff) curve agrees well with the universal mobility curve, peaking around 300 cm2/V.sec

- 2.2 nm RTO (950 °C) + RPN

LWQVI

invDS

DSeff ..=µ

Split CV methodSplit CV methodusing


EOT vs. long channel VT (NMOS)

∆VT ≈ 37 mV ⇒ RPN oxynitrides exhibit more positive charges at theinterface than NO post-annealed oxides (1.95 nm EOT)

For EOT ≥ 2.0 nm, % He ↑ ⇒ [N] ↑ ⇒ slightly ↑ VT

1.65 1.80 1.95 2.10 2.250.25

0.30

0.35


VT (V

)

EOT (nm)

20 % He

80 % HeREF

∆VT

1.65 1.80 1.95 2.10 2.250.25

0.30

0.35


VT (V

)

EOT (nm)

20 % He

80 % HeREF

∆VT

∆VT ≈ 2.2 %RTORTO

ISSGISSG


Oxynitride uniformity

1.9

2.0

2.1

2.2

2.3

2.4

2.5

south centre north

ISSG (850 °C) + RPN RTO (950 °C) + RPN

EOT

(nm

)

Position within wafer

66 % He

20 % He

20 % He66 % He

REF

RTO

ISSG

• RPN oxynitrides exhibit ↑ non-uniformity than NO post-annealed oxides• % He ↑ ⇒ [N] ↑ ⇒ non-uniformity ↑

66% He ⇒ EOT changes 1-2 Å across the wafer

© imec 2002

Transistor performance


Device fabrication(90 nm CMOS process flow diagram)

CMOS : nCMOS : n--MOS + pMOS + p--MOSMOS

n np p

n-well p-well n-well

HDD spacers

Extensions Pocket implants

Silicide, Co/Ti

SiOxNy dielectric

150 nm Polysilicon

HDD implants


Device fabrication

90nm CMOS process:

• 2 nm nitrided oxide/150nm polysilicon gate• NMOS gate predoping• Extensions: As, 5 keV (NMOS) and B, 1 keV (PMOS)• Halos: BF2, 65 keV (NMOS) and As, 120 keV (PMOS)• Spacers: 80nm• HDD:

• NMOS: As, 40 keV + P, 10 keV• PMOS: B, 3keV

• RTA spike anneal at 1100 °C, 0s• Silicidation: CoSi with Ti cap: 10nm/8nm


ITP curves

100 200 300 400 500 600 7001E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

LOP SPEC

VDD = 1.2 V

2nm RTO + RPN2nm ISSG + RPN

VDD = 1.0 V

I OFF

(A/µ

m)

ION (µA/µm)

100 200 300 4001E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

LOP SPEC

2nm RTO + RPN2nm ISSG + RPN

VDD = - 1.2 V

VDD = - 1.0 V

I OFF

(A/µ

m)

ION (µA/µm)

•NMOS: ION = 427 µA/µm for IOFF = 16 pA/µm•PMOS: ION = 170 µA/µm for IOFF = 16 pA/µm

ForVDD = 1.2 V

PMOSNMOS


Gate leakage

IOFF = ID = Ichannel + IG + Ijunction

OffOff--state leakagestate leakage≈≈ overlap gate leakageoverlap gate leakage

Uniform gate Uniform gate leakageleakage

VD = VDD

Vbulk = 0

VS = 0

VG = 0

IOFF

e-e-e-e-e-e-

e-e-e- VD = VDD

Vbulk = 0

VS = 0

VG = 0

IOFF

e-e-e-e-e-e-

e-e-e-

Vbulk = 0

VS = 0

VG = VDD

VD = 0

e-e-e-e-e-

Vbulk = 0

VS = 0

VG = VDD

VD = 0

e-e-e-e-e-

IOFF/W = JGLpoly


Overlap gate leakage

NMOS PMOS

0.1 1 101E-14

1E-13

1E-12

2 nm ISSG + RPN2 nm RTO + RPN2 nm Ref. (oxynitride O2+NO)

VDS = -1.2 V, VGS = 0 V

I gate (A

/µm

)Gate length (µm)

0.1 1 101E-13

1E-12

1E-11

1E-10

2 nm ISSG + RPN2 nm RTO + RPN2 nm Ref. (oxynitride O2+NO)

VDS = 1.2 V, VGS = 0 V

I gate (A

/µm

)

Gate length (µm)

VDS = 1.2 V, VGS = 0 V VDS = -1.2 V, VGS = 0 V

Overlap leakage is ∼ 10× smaller for RPN oxynitridesJG(L) ≈ const ⇒ gate-to-junction leakage path dominates IG

in the transistor off-state


Uniform gate leakage

NMOS PMOS

0.1 1 101E-12

1E-11

1E-10

1E-9

2 nm ISSG + RPN2 nm RTO + RPN

VDS = 0 V, VGS = -1.2 V

I gate (A

/µm

)Gate length (µm)

0.1 1 101E-11

1E-10

1E-9

1E-8

1E-7

1E-6

2 nm ISSG + RPN2 nm RTO + RPN

VDS = 0 V, VGS = 1.2 V

I gate (A

/µm

)

Gate length (µm)

JG ≈ 40 mA/cm2 JG ≈ 6 mA/cm2

VDS = 0 V, VGS = 1.2 V VDS = 0 V, VGS = -1.2 V

IG/W = JGLpoly ⇒ RTO and ISSG based oxynitrides exhibit similar JG


Threshold voltage

0.1 1 10-0.5

-0.4

-0.3

-0.2

-0.1

0.0Lg = 80 nm

VDS = - 1.2 V

2 nm ISSG + RPN 2 nm RTO + RPN

VT (V

)as-drawn gate length (µm)

0.1 1 10

0.1

0.2

0.3

0.4

0.5

0.6

Lg = 80 nm

VDS = 1.2 V

2 nm ISSG + RPN 2 nm RTO + RPN

VT (V

)

as-drawn gate length (µm)

PMOSNMOS

VDS = 1.2 V VDS = -1.2 V

Short channel effects well controlled down to L = 80 nmNo significant difference between RTO and ISSG based oxynitrides


Summary and Conclusions

• Suitability of RPN-based oxynitrides for 90 nm Low OperatingPower (LOP) applications demonstrated

• RPN process requires careful optimization to reduce JG withoutincreasing EOT and oxide thickness non-uniformity:

% He ↑ ⇒ [N] ↑ ⇒ EOT ↑ + JG ↓ + non-uniformity ↑

• RPN oxynitrides exhibit- ↑ electron mobility - ↓ JG

than NO post-annealed oxides

• RTO and ISSG based oxynitrides are equivalent in terms ofgate leakage, mobility and intrinsic transistor performance

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rpn oxynitride gate dielectrics for 90 nm low power ......© imec 2002 a. veloso, presentation at...

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