ruud haring - modeling complex systems
DESCRIPTION
Slides presented by Ruud Haring, at the 2011 Urban Systems Symposium. http://urbansystemssymposium.org/TRANSCRIPT
© 2011 IBM Corporation
Chip design as a metaphor -- providing services to the millions
Ruud Haring, IBM Research
© 2011 IBM Corporation2 May 11, 2011
A chip design is a complex system
A well-defined set of functions, performed by
100s of millions of transistors
each requiring services – power supply, ground
each with individual connections
Constraints
area
timing
power distribution / noise
power dissipation
resources – routing channels for interconnections
manufacturability , testability
…..
© 2011 IBM Corporation3 May 11, 2011
Chip Design – modeling approaches
Levels of abstraction
transistors– solid state physics, materials science– abstracted to electrical characteristics: current/voltage/capacitance
logic gates: and, or, not, latch– digital 0 and 1– physical abstraction: small box with pins + area, power, delay
units: arithmetic unit, memory array– large set of interconnected logic gates or transistors– well characterized sub-function
•captured in logic design language : C <= (A + B) when ( D=1 ) else (not E);
– physical abstraction: bigger box with pins + area, power, delays, blockages
chip: microprocessor, memory chip, ….– interconnected units– has well defined abstraction for software team
•register set•programming guide
GS D
Un it
Un it Un it
Un it
Un it Un itUn it
Un it
6 4 6 4
6 4
+
© 2011 IBM Corporation4 May 11, 2011
Chip Design team -- use of the abstractions Technologists
– transistors (lithography, charcteristics)– interconnect levels– device modelers – I/V curves– manufacturability rules
Library designers– create logic gates, arrays + defining rules (pins, area, delay, …)
Architects– overall function of the chip, in the system. Try to be smarter…– logic abstraction for software team
Logic designers– implement architecture -- at digital (0/1) level– verification team keeps them honest << software team
Physical designers– floorplanning– placing logic, routing interconnects, distributing power, clocks -- per unit / per chip– timing closure -- per unit / per chip– noise– rules – checking – rules – checking … more checking…
Fabricators– generate masks from layout– lithography/implant/deposit/etch/polish/plate … 100s of steps for 50 or so layers
Testers– weed out manufacturing defects– tell us what went wrong …
Project managers, other managers…
© 2011 IBM Corporation5 May 11, 2011
Chip Design as a metaphor for an urban system ?
Chip designers can handle the complexity– because different teams can work with different levels of abstraction … while checking tools assure that their level is consistent with the whole.
– because the abstractions fit the math (or the math fits the abstractions?)– because the software tools fit the math/abstractions and rules/checkers– because nature is – mostly – obliging the abstractions
It is “easy” because…
transistors do not have opinions…
signals only have a single place (or few fixed places) to go– over dedicated wires
no eminent domain problems
10 or so vertically stacked, non-intersecting levels of signal traffic – and no transistor minds living under them– or… inverted view: no signal minds doing all their traveling underground.