schottky barrier engineering for contact resistance ... · 2.5 summary and conclusion 34 2.6...

SCHOTTKY BARRIER ENGINEERING FOR

CONTACT RESISTANCE REDUCTION IN

NANOSCALE CMOS TRANSISTORS

MANTAVYA SINHA

NATIONAL UNIVERSITY OF SINGAPORE

2010

SCHOTTKY BARRIER ENGINEERING FOR

CONTACT RESISTANCE REDUCTION IN

NANOSCALE CMOS TRANSISTORS

MANTAVYA SINHA

(B. TECH. (HONS.)), BANARAS HINDU UNIVERSITY

A THESIS SUBMITTED

FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2010

i

ACKNOWLEDGEMENTS

First and foremost I would like to express my sincere gratitude to my PhD

supervisors, Prof. Chor Eng Fong and Prof. Yeo Yee Chia. I have benefited

immensely from their wealth of knowledge and experience in the field of

nanotechnology, and semiconductor process and device design. They have been

instrumental in instilling a strong work ethic in me and in developing acumen for

solving challenging problems. It has been fun learning the art of high quality research

from them.

I would like to acknowledge the support of the following friends and fellow

students at silicon nano-device laboratory (SNDL) and the centre of optoelectronics

(COE), both at the National University of Singapore: Lina, Shao Ming, Hock Chun,

Hoong Shing, Alvin, Ms. Oh, Kian Ming, Tong Yi, Phyllis, Rui Long, Litao, Shen

Chen, Eric, Ashvini, Gong Xiao, Huaxin, Vivek, Liu Chang, Janis, Huang Leihua,

Chuan Beng and Tian Feng. They have been a part of this enlightening journey in

more ways than one, professionally as well as socially. Working overnight to rush for

key device conference deadlines would not have been so exciting without the support

of most of them.

I am especially grateful to Dr. Tan Chung Foong for helping me start on my

first research project, and also to my friend Rinus Lee for the various insightful

discussions that we had on silicides and FinFETs.

The staff at SNDL and COE was always forthcoming. I would like to thank

Mr. Yong, Patrick, and O Yan for their continuous support. Special thanks go to Mr.

Tan Beng Hwee for always being there to lend a helping hand. I also appreciate the

support extended by the staff at the Institute of Materials Research and Engineering

(IMRE) and the Institute of Microelectronics (IME), along with that of my co-

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supervisor Dr. Patrick Lo Guo-Qiang, in helping me gain access to the state of the art

tools for semiconductor device fabrication and metrology. Without their efforts, some

of the work entailed in this thesis would not have been possible. Thank you Debbie

for the countless hours spent during SIMS characterization.

I really appreciate the care and concern that my parents have given me. Most

of all, I would like to thank Harshada, the love of my life, for her patience,

encouragement and love during this wonderful chapter of my life.

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TABLE OF CONTENTS

Acknowledgments i

Table of Contents iii

Abstract vii

List of Tables ix

List of Figures x

List of Symbols xxii

Chapter 1. Introduction and Motivation 1

1.1 Challenges to CMOS Scaling: A Background 1

1.2 The Parasitic Series Resistance Challenge 3

1.2.1 Components of Parasitic Series Resistance 7

1.2.2 Impact of Contact Resistance RC 9

1.3 Objectives of Research 11

1.4 Thesis Organization 12

1.5 References 15

Chapter 2. Material Screening 19

2.1 Introduction 19

2.2 Motivation 19

2.3 Device Fabrication 22

2.4 Results and Discussion 25

iv

2.4.1 Impact of Acceptor-type Impurity 25

2.4.1.1 Effect of Silicide Thickness on Schottky Barrier Height 29

2.4.2 Impact of Donor-type Impurity 32

2.5 Summary and Conclusion 34

2.6 References 36

Chapter 3. Schottky Barrier Height Tuning of NiSi/Si 37

3.1 Introduction 37

3.2 Aluminum Implant for Schottky Barrier Height Tuning in p-FETs 37

3.2.1 Motivation 37

3.2.2 Device Fabrication 39

3.2.3 Results and Discussions 40

3.2.3.1 Material Characterization 40

3.2.3.2 Electrical Results: p-FinFET Integration 51

3.2.4 Summary and Conclusion 58

3.3 Si:C Bandgap Engineering for Electron Schottky Barrier Tuning 58

3.3.1 Motivation 58




3.4 References 67

Chapter 4. Aluminum Implant Technology for Contact Resistance

Reduction in Strained p-FinFETs with SiGe

Source/Drain 72

v

4.1 Introduction and Motivation 72

4.2 Device Fabrication 74

4.3 Results and Discussions 79

4.3.1 Material Characterization 79

4.3.2 Electrical Results: p-FinFET Integration 92

4.4 Summary and Conclusion 102

4.5 References 104

Chapter 5. Novel Cost-effective Single Silicide Solutions for

Simultaneous Contact Resistance Reduction in both

p- and n-channel FETs 109

5.1 Introduction 109

5.2 Ni-Dy Metal Alloy based Single-Silicide Solution using Al+ Implant 110

5.2.1 Motivation 110




5.3 NiSi based Single-Silicide Contact Technology using Al+ and S+ Double

Implant 125

5.3.1 Motivation 125

5.3.2 Contact Technology: Implant Interactions 126

5.3.3 FinFET Integration and Electrical Results 133


5.4 References 141

vi

Chapter 6. Summary and Future Work 143

6.1 Summary 143

6.1.1 Material Screening for Modulation of Hole Schottky Barrier

Height of NiSi on p-Si 145

6.1.2 Hole Schottky Barrier Height Tuning of NiSi on p-Si using

Aluminum Implant and Segregation 146

6.1.3 Study of Modulation of Electron Schottky Barrier Height of NiSi

on Si1-xCx using Substrate Engineering 147

6.1.4 Aluminum Implant Technology for Contact Resistance Reduction

in Strained p-FinFETs with SiGe Source/Drain 148

6.1.5 Novel Cost-effective Single Silicide Solutions for Simultaneous

Contact Resistance Reduction in both p- and n-channel FETs 149

6.2 Future Work 151

6.3 References 156

Appendix A 160

Appendix B 163

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ABSTRACT

Schottky Barrier Engineering for Contact Resistance Reduction in

Nanoscale CMOS Transistors

by

Mantavya Sinha

Doctor of Philosophy – Electrical and Computer Engineering

National University of Singapore

This thesis involves the development of simple and low cost solutions to

reduce contact resistance RC in CMOS FETs. RC at the interface between silicide and

heavily-doped source/drain (S/D) region is a major fraction of the total parasitic series

resistance RSD. RSD is a bottleneck for device performance at the sub-22 nm

technology node, where multiple-gate transistors (for e.g., FinFETs) are slated to be

introduced. RSD is an even bigger issue in FinFETs with narrow fin width. New

materials and processes are needed to achieve target contact resistance and contact

resistivity levels determined by the ITRS roadmap.

Contact resistivity at the interface between metal silicide (for e.g., nickel-

silicide NiSi) and heavily-doped source and drain (S/D) region in a MOSFET is

dependent exponentially on the Schottky barrier height ΦB at the interface. In this

thesis, novel ion-implantation based techniques to modulate the ΦB have been

developed. These have been demonstrated in FinFETs with S/D made of silicon (for

p-FETs and n-FETs), silicon-germanium SiGe (for strained p-FETs) or silicon-carbon

Si1-xCx (for strained n-FETs). Only nickel(Ni)-based silicides (either pure nickel-

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silicide or a silicide formed of an alloy of nickel and a rare-earth metal) are used in

this work for their ease of adoption by the semiconductor industry with minimal

process and cost overheads. Furthermore, substrate engineering has also been studied

for RC reduction in n-FETs with Si1-xCx S/D.

In particular, through ion-implantation of impurity elements at the interface

between metal-silicide and the S/D material of MOSFETs, modulation of ΦB is

demonstrated. A range of materials (impurity elements), such as aluminum (Al),

cobalt (Co), cadmium (Cd), zinc (Zn), and magnesium (Mg) are screened to

investigate their possible application in lowering the effective hole Schottky barrier

height ΦBp of nickel silicide (NiSi) on p-Si. With Al implant and segregation, a 70 %

lowering of ΦBp of NiSi on p-Si is achieved. The mechanism responsible for the

modulation of ΦBp is also studied through extensive material characterization. When

the Al implant technology is integrated in the S/D of p-FinFETs, ~15 %

enhancements in drive current IDSAT is achieved. Furthermore, the Al implant

technology is also developed for strained p-FETs with SiGe S/D. The achievement of

one of the lowest reported ΦBp for NiSiGe on SiGe of 0.068 eV is demonstrated.

Finally, two novel single-silicide integration schemes are developed that

demonstrate independent and simultaneous RC reduction in both, p- and n- channel FETs.

In the first approach, a silicide formed of an alloy of Ni and dysprosium (Dy) is

demonstrated, coupled with the Al implant technology. The second approach

demonstrates a single-mask integration scheme using a double-implant of Al and sulfur

(S) to achieve dual near-band-edge barrier heights. Compensation effect of Al and S is

studied to achieve significant RC reduction and IDSAT enhancement in both p- and n-

channel FinFETs.

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LIST OF TABLES

Table 1.1 Front End Processes (FEP) requirements - near term Years [1.1]. ……………………………………………………………..

1

Table 2.1 Experimental splits detailing the energy, dose and range (RP) of the ion-implanted species. ……………………………………….

24

Table 6.1 A summary of effective Schottky barrier height and drive current enhancement achieved by the various Schottky barrier engineering technologies demonstrated in this thesis, except for two entries taken from [6.7] and [6.8]. Note that ΦB

p + ΦBn ≈

bandgap of semiconductor. ……………………………………...

144

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LIST OF FIGURES

Fig. 1.1 Scaling of transistor size (physical gate length LG) to sustain Moore’s Law [1.2]. ………………………………………………..

1

Fig. 1.2 Schematic showing the impact of RSD on drain current IDS. Note that RSD = RSOURCE + RDRAIN and leads to lowering of IDS as evident from the IDS vs V′DS plot. ……………………………………………

5

Fig. 1.3 Simulation study showing the increase in ratio of RSD over RCH with technology node [1.22]. …………………………………….............

6

Fig. 1.4 Increase of RSD in n-FinFETs with scaling down of WFin [1.23]. Inset shows a schematic of a tri-gate FinFET, where HFin is the height of the fin and LG is the gate length. ……………………….....

6

Fig. 1.5 Components of source (or drain) parasitic series resistance in a MOSFET. Dotted lines show the flow of charge carriers (current) from the silicide contact into the channel. Only a half cross-section of the transistor (cut vertically through the centre of the gate) is shown in this figure. The other half of the transistor has the same set of resistances. RSD = 2RS = 2RD, assuming that the source and drain are symmetrical. Half of the channel resistance (RCH/2) is also shown for completeness. ………………………………………

7

Fig. 1.6 Fraction (in %) of RC, RSDE and RDSD to the total series resistance at LG = 50 nm, for (a) n-FETs, and (b) p-FETs [1.25]. ………………..

9

Fig. 1.7 Energy band diagram of a metal or a metal-silicide contact on n+-Si showing electron tunneling through the thin barrier height. In the case of a nickel-silicide (NiSi) contact, the Schottky barrier height ΦB for electron conduction has been reported to be ~0.67 eV [1.26]. ……………………………………………………………….

10

Fig. 2.1 Energy band diagram of NiSi contact on p-Si showing (a) flat-band condition and (b) a case where the conduction and valence bands bend downwards due to the acceptor-type trap level ET introduced at the interface by the ion-implanted element (or impurity). For simplicity, it is assumed that the effective workfunction Φ of NiSi and p-Si is the same. EF,M is the Fermi level of NiSi, EC is the conduction band edge energy level and EV is the valence band edge energy level. ………………………………………………………...

20

Fig. 2.2 List of trap levels ET introduced in the silicon bandgap by Al, Zn, Cd, Co, and Mg [2.2]. These elements are ion-implanted into Si for the purpose of modulation of ΦB

p at the NiSi/p-Si interface. ………

21

Fig. 2.3 (a) Key process steps carried out in the fabrication of NiSi/p-Si contact junction with ion-implanted impurities. (b) Schematic of

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the final device showing the shaded region (red color) of interest where the ion-implanted impurities are present after silicidation. .....

23

Fig. 2.4 Room temperature (RT) I-V characteristics of NiSi/p-Si contact junctions with and without the implanted acceptor-type impurity, namely (a) Al, (b) Zn, (c) Cd, and (d) Co. Effect of ion-implantation dose on ΦB

p is studied in each of the 4 plots. ………...

27

Fig. 2.5 TOF-SIMS depth profile of the ion-implanted species (Al, Zn, Cd and Co) within the NiSi/p-Si contact device. The profile of each of these impurity species is taken from their respective contact device with the implantation dose of 2×1014 atoms/cm2. The first peak in each of these profiles is due to the as-implanted peak of that species in Si before being consumed by nickel during silicidation. ……………………………………………………….....

28

Fig. 2.6 I-V characteristics of NiSi/p-Si contact devices with Co and Cd ion-implantation at dose of 2×1014 atoms/cm2. Effect of the thickness of the formed NiSi on ΦB

p is studied. The control device did not undergo any ion-implant. …………………………………………...

30

Fig. 2.7 TOF-SIMS depth profile of Co in the NiSi/p-Si contact devices with Co ion-implantation at dose of 2×1014 atoms/cm2. Two devices are used for the profiling of Co, one with NiSi formed from 10 nm of Ni and the other with NiSi formed from 30 nm of Ni. The difference in intensity (or concentration) of Co at the NiSi/p-Si interface between the two devices is observed and is shown by the dotted line in red. …………………………………...........................

31

Fig. 2.8 Room temperature I-V characteristics of NiSi/p-Si contact devices with and without Mg ion-implant at dose of 2×1015 atoms/cm2. …...

33

Fig. 2.9 TOF-SIMS depth profile of Mg in the NiSi/p-Si contact device with Mg implant at dose of 2×1015 atoms/cm2. Significant segregation of Mg at the interface between NiSi and p-Si is observed. ……………………………………………………………

34

Fig. 3.1 (a) I-V characteristics of NiSi on p-Si with and without Al ion-implantation. (b) Activation energy measurements to extract the ΦB

p of NiSi on p-Si, which was implanted with Al at dose of 2×1014

cm-2. The slope of the linear fit of the curve (solid line) in the low temperature part is used to extract ΦB

p. (c) I-V characteristics of the sample with Al implant at dose of 2×1014 cm-2, measured at different temperatures. For the sake of clarity, some temperature plots have been omitted here, but are still used in part (b). Inset shows the schematic of the fabricated contact device. ………………………………………………………………

41

Fig. 3.2 TOF-SIMS depth profile of Al after 30 nm Ni deposition and silicidation, as well as the as-implanted Al profile (in silicon). The

xii

as-implanted profile is shifted so that it indicates where the original Al peak is located, i.e., in the Si region which has been converted into NiSi. ……………………………………………………………

42

Fig. 3.3 (a) I-V characteristics of two NiSi/p-Si contact junctions, one formed with 20 nm Ni and the other formed with 10 nm of Ni, and both implanted with Al at dose of 2×1014 atoms-cm-2 and energy of 10 keV. Silicidation is done at 500 °C for 30 s, for both these devices. Also shown are I-V characteristics of a NiSi/p-Si contact devices formed with 30 nm Ni (with same Al ion-implantation parameters) and the control sample without any Al, that are taken directly from Fig. 3.1(a). (b) Activation energy measurements to extract the ΦB

p of NiSi (formed with 10 nm Ni) on p-Si, which is implanted with an Al dose of 2×1014 cm-2 at 10 keV. The slope of the linear fit of the curve (solid line) in the low temperature part is used to extract ΦB

p. …………………………………………………

44

Fig. 3.4 TOF-SIMS depth profile of Al in three NiSi/p-Si contact devices, with NiSi formed from 30 nm of Ni, 20 nm of Ni and 10 nm of Ni. For all samples, Al implant is done at dose of 2×1014 atoms/cm2. …

46

Fig. 3.5 ΦBp as a function of concentration of Al at NiSi/p-Si interface, as

well as a function of the Al ion-implantation dose. The three data points at the same Al ion-implantation dose of 2×1014 cm-2

correspond to progressively thinner NiSi (formed from 30 nm, 20 nm and 10 nm of Ni) leading to increase of concentration of Al at the NiSi/p-Si interface and hence lowering of effective ΦB

p. For the rest of the three data points at lower Al ion-implantation dose, NiSi is formed from 30 nm of Ni. …………………………………..

46

Fig. 3.6 (a) I-V characteristics of NiSi/p-Si contact junctions with Al implant at a dose in the range of 2×1014 - 2×1015 atoms/cm2. Control device without any al implant is also shown for comparison. NiSi is formed from 10 nm of Ni for all the contact devices. Inset on the left shows the schematic of the fabricated junctions. Inset on the right shows the extracted ΦB

p values for all the NiSi/p-Si junctions, with and without Al implant. (b) XRD theta/2theta (θ/2θ) phase analysis of blanket NiSi film on p-Si substrate, with and without Al implant dose of 2×1014 atoms/cm2. Inset shows the sheet resistance RS of the blanket NiSi films on p-Si substrate, with Al implant dose in the range of 0 - 2×1015

atoms/cm2. …………………………………………………………..

49

Fig. 3.7 TOF-SIMS depth profile of Al in NiSi/p-Si contact devices with Al implant at a dose in the range of 2×1014 atoms/cm2 - 2×1015

atoms/cm2, and using NiSi formed from 10 nm of Ni. Inset shows the schematic diagram of the contact devices with negatively-charged acceptor-type Al atoms segregated near the NiSi/p-Si interface. ………………………………………………………….....

50

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Fig. 3.8 Schematic on the left shows the process flow to fabricate p-channel FinFETs. Schematic on the top-right shows the device structure after spacer etch and deep S/D implant and activation, and undergoing Al implant. The gate also received the Al implant since the hard mask on it is removed before the deep S/D implant step. The schematic on the bottom-right shows the final device structure after nickel silicidation. The Al segregated NiSi/p+-Si interfacial region are denoted with negative charge due to the filled acceptor-type traps introduced by Al near the Si valence band. ………………………………………………………………...

51

Fig. 3.9 Cross-sectional TEM of a complete p-FinFET with 170 nm LG, after Al implant and Ni silicidation. FIB cut along A-A' (shown in the tilt-SEM in the inset of the figure) overestimates the LG. ………

52

Fig. 3.10 (a) IDS-VDS characteristics of a pair of FinFETs with LG = 165 nm and fin width WFin = 55 nm, with and without Al implant at dose of 2×1014 atoms/cm2. (b) Y-axis on the left shows the IDS-VGS

characteristics of the same pair of FinFETs. Y-axis on the right plots the graph of RTotal versus VGS for the same pair of devices. RTotal = |VDS|/IDS,lin, where VDS = -50 mV and IDS,lin is the linear drain region. Solid lines show the first order exponential fit used to extract RSD at VGS = -10 V. …………………………………….........

53

Fig. 3.11 Plot of ON current (IDSAT) versus OFF current (IOFF), both for devices with and without Al implant. IDSAT and IOFF are extracted at gate voltage VGS of -1.2 V and 0 V, respectively. …………………..

54

Fig. 3.12 (a) Plot of drive current IDSAT versus drain induced barrier lowering (DIBL), both for devices with and without Al implant. IDSAT is extracted at gate overdrive (VGS–VT) of -1.2 V. (b) Plot of drive current IDSAT versus subthreshold swing SS, both for devices with and without Al implant. IDSAT is extracted at gate overdrive (VGS–VT) of -1.2 V. ………………………………………………..............

55

Fig. 3.13 Y-axis on the left shows the plot of mean IDSAT versus LG, for devices with and without Al implant. Y-axis on the right shows the plot of enhancement in IDSAT (with Al implant against control devices) versus LG. ……………………………………………….....

56

Fig. 3.14 p-FinFETs with and without Al implant have comparable short channel effects, e.g. similar VT, VT roll-off, DIBL (inset at top-left) and SS (inset at top-right). …………………………………………..

57

Fig. 3.15 The parasitic series resistance RSD extracted at zero gate length shows a drop of 13 % for p-FinFETs with Al implant (over the control FinFETs). …………………………………………………...

57

Fig. 3.16 (a) Variation of sheet resistance (RS) with annealing temperature for nickel silicide film on n-Si and Si0.996C0.004. Silicidation is done

xiv

using RTA for 1 minute in N2 ambient at the specified temperature. (b) XRD θ/2θ phase analysis of NiSi on n-Si and Si0.996C0.004. Silicidation is done using RTA at 500 ˚C for 1 minute in N2

ambient. ……………………………………………………………..

61

Fig. 3.17 Current-Voltage (I-V) characteristics of NiSi on Si1-xCx with x = 0, x= 0.0015, x = 0.0028 and x = 0.0040. Silicidation is done using RTA at 500 ˚C for 1 minute in N2 ambient. Inset shows the schematic of the fabricated contact device. ………………………...

63

Fig. 3.18 (a) Experimental variation of ΦBn of NiSi with percentage carbon

concentration and extrapolation of the linear fit to x = 0.013. Error bar at each data point corresponds to the statistical variation in ΦB

n

about its mean value. Inset shows the drop in ΦBn with in-plane

tensile strain (εxx). (b) Projected linear variation of ΦBn of YbSi2-y

with percentage carbon concentration. ……………………………..

64

Fig. 4.1 HRXRD rocking curve of a p-Si (100) wafer with SiGe epilayer. The Ge concentration in SiGe and the epilayer thickness are extracted to be ~26 % and 100 nm, respectively. …………………..

74

Fig. 4.2 (a) Schematic showing the NiSiGe/SiGe device structure just after the SiGe epilayer growth and undergoing Al implant. (b) Schematic showing the final NiSiGe/SiGe device structure with Al implant, which is used for I-V characterization. The Al atoms have been shown to have segregated near the NiSiGe/SiGe interface. …..

75

Fig. 4.3 (a) Process flow used for fabricating strained p-channel tri-gate FinFETs with Al implant and segregation at the NiSiGe contact. The Al implant step was skipped for control p-FinFETs. Critical process steps for the formation of Al segregated NiSiGe/p+-SiGe S/D contact are also schematically illustrated in (b)-(d). After SiGe epitaxial growth to form raised S/D stressors in strained p-FinFETs, dopant implant and activation were performed, followed by the first step in the contact formation process: (b) blanket Al implant at a dose of 2×1014 atoms/cm2 and an energy of 10 keV. This was followed by (c) 10 nm nickel deposition. Finally, (d) germano-silicidation was performed at 400 °C for 30 s, followed by SPM clean to remove the unreacted nickel. During NiSiGe formation, Al segregates near the NiSiGe/p+-SiGe interfacial region. …………….

77

Fig. 4.4 (a) I-V characteristics of NiSiGe/SiGe contact junctions, with and without Al ion-implantation. 10 nm of Ni is germano-silicided using RTA at 400˚C for 30 seconds to form the NiSiGe contact on SiGe. The inset shows the schematic of the fabricated device used for I-V characterization. (b) Activation energy measurements to extract the effective ΦB

p for NiSiGe on SiGe. For this device, the SiGe substrate was implanted with Al at a dose of 2×1014 atoms-cm-2. With the y-axis plotted on log-scale, the slope of the linear fit of the curve (solid line) in the low temperature part of the plot is

xv

used to extract the effective ΦBp. (c) Series of I-V curves of the

same NiSiGe/SiGe junction [as mentioned in (b)] measured at different temperatures (180 K – 240 K). Inset shows the same set of I-V plots, but in an extremely small forward bias voltage range (0.06 V ≤ VF ≤ 0.1 V). Data points are fitted using a best-fit line. ..

80

Fig. 4.5 The variation of the effective ΦBp of NiSiGe on SiGe, with and

without Al implant, extracted using activation energy method. Error bars are also drawn to show the variation in the extracted ΦB

p

at different forward bias voltage VF, about its mean value. 10 nm of Ni is germano-silicided using RTA at 400˚C for 30 seconds to form the NiSiGe contact on SiGe, for all the samples. …………………...

82

Fig. 4.6 TOF-SIMS depth profile of Al in NiSiGe/SiGe junctions, with Al implant dose in the range of 2×1014 - 2×1015 atoms-cm-2. Segregation of Al near the NiSiGe/SiGe interface is clearly seen. The starting thickness of Ni used to form the NiSiGe contacts is 10 nm. ………………………………………………………………….

84

Fig. 4.7 (a) XRD theta/2theta (θ/2θ) phase analysis of NiSiGe on SiGe with and without Al implant. .Germano-silicidation is done using RTA at 400 ˚C for 30 seconds on 10 nm of Ni. (b) Sheet resistance of NiSiGe contact formed on SiGe, with and without Al implant. Germano-silicidation is done using RTA at 400 ˚C for 30 seconds on 10 nm of Ni. Error bars are also drawn to show the spread in the measured sheet resistance within a set of devices due to statistical process variation. …………………………………………………...

86

Fig. 4.8 (a) I-V characteristics of two NiSiGe/SiGe junctions with Al implant at a dose of 2×1014 atoms-cm-2, formed from 10 nm and 30 nm of Ni. For the NiSiGe contact formed from 30 nm of Ni, germano-silicidation was done using RTA at 400 ˚C for 1 minute. The control device without any Al implant is also shown. The inset shows the schematic of the fabricated device used for I-Vcharacterization. (b) Activation energy measurements to extract the effective ΦB

p for NiSiGe on SiGe, for the device with Al implant at a dose of 2×1014 atoms-cm-2 and formed by germano-silicidation of 30 nm of Ni. With the y-axis plotted on log-scale, the slope of the linear fit of the curve (solid line) in the low temperature part of the plot is used to extract the effective ΦB

p. ……………………………

88

Fig. 4.9 (a) The effective ΦBp of two NiSiGe/SiGe junctions, with Al

implant at a dose of 2×1014 atoms-cm-2, and formed from 10 nm and 30 nm of Ni. The ΦB

p is extracted using activation energy method. (b) TOF-SIMS depth profile of Al in NiSiGe/SiGe junctions, with Al implant dose in the range of 2×1014 - 2×1015

atoms-cm-2. The starting thickness of Ni used to form the NiSiGe contacts is 30 nm. The inset shows the corresponding effective ΦB

p

of all the NiSiGe/SiGe junctions with Al implant in the range of 2×1014 - 2×1015 atoms-cm-2 and NiSiGe contact formed from 30 nm

xvi

of Ni. The ΦBp values are much higher than those extracted for

thinner NiSiGe contacts (formed from 10 nm of Ni) with the same Al implant dose. Error bars are also drawn to show the variation in the extracted ΦB

p at different forward bias voltage, about their mean value. ………………………………………………………………..

89

Fig. 4.10 XTEM image of the SiGe film implanted with Al at a dose of (a) 2×1014 atoms-cm-2 showing amorphization of the top 20 nm, (b) 1×1015 atoms-cm-2 showing amorphization of the top 30 nm, and (c) 2×1015 atoms-cm-2 showing amorphization of the top 35 nm. (d) XTEM image of NiSiGe/SiGe junction with Al implant dose of 2×1014 atoms-cm-2, formed from 10 nm of Ni. A continuous NiSiGe film is formed which consumes all of the α-SiGe. ………...

91

Fig. 4.11 (a) Top-view SEM image of a strained p-FinFET device that went through Al segregated NiSiGe/p+-SiGe S/D contact formation. The introduction of Al does not affect the NiSiGe film morphology. (b) Cross-sectional TEM image of a strained p-FinFET. Focused Ion Beam (FIB) cut is done along line A-A' as shown in (a), which is not on the part of the gate line which runs across the active fin region. The actual physical gate length for this device is therefore slightly smaller than 125 nm. The NiSiGe film thickness is estimated to be ~25 nm. …………………………………………….

93

Fig. 4.12 (a) IDS - VGS characteristics of a pair of strained p-FinFETs with and without Al implant. The devices have a gate length LG of 105 nm and a fin width WFin of 50 nm, and have comparable short channel effects. (b) IDS-VDS characteristics of the same pair of p-FinFETs show that Al implant and segregation contributes to ~30 % higher IDSAT at VDS = VGS - VTSAT = -1.2 V. ………………………………...

94

Fig. 4.13 (a) IDSAT - IOFF plot for strained p-FinFETs with and without Al implant showing a saturation drain current IDSAT enhancement of ~25 %. (b) IDLIN - IOFF plot shows a linear drain current enhancement of ~29 % for devices with Al implant over the control FinFETs. The best-fit lines were obtained using least-square-error fitting. ……………………………………………………………….

95

Fig. 4.14 Plot of RTotal versus LG for strained p-FinFETs with and without Al implant in the linear region at VGS - VTLIN of -1.8 V and -2 V. Linear regression fit of data gives a y-axis intercept that allows for extraction of RSD. RSD for p-FinFETs with Al segregated NiSiGe/p+-SiGe S/D junction is lowered by 21 % with respect to control p-FinFETs without Al implant. …………………………….

96

Fig. 4.15 Mean saturation drain current in p-FinFETs with and without Al implant at a gate length LG of 230 nm and 80 nm. IDSAT

enhancement increases with gate length reduction. ………………...

99

Fig. 4.16 Plot of saturation drain current IDSAT versus Drain Induced Barrier

xvii

Lowering (DIBL) for strained p-FinFETs. All measured data are plotted as circles for p-FinFETs without Al implant (control) and as solid triangles for p-FinFETs with Al implant. Best-fit lines were obtained using least-square-error fitting. At a fixed DIBL of 100 mV/V, Al implant and segregation gives ~25 % enhancement in IDSAT. ………………………………………………………………..

99

Fig. 4.17 IOFF extracted at VGS = 0 V is plotted against VTSAT, which shows that the transistor off-state leakage current is not affected by Al implant at a dose of 2×1014 atoms/cm2. …………………………….

101

Fig. 4.18 Cumulative distributions of (a) VTSAT, (b) DIBL, and (c) SS in strained p-FinFETs with and without Al implant. Both device splits have comparable VTSAT, DIBL and SS, suggesting that gate control of short-channel effects is unaffected by the Al implant and segregation process. ………………………………………………...

101

Fig. 4.19 Cumulative distributions of NiSiGe contacted p+(SiGe/Si)/n(Si) diode junction leakage current, measured at a reverse bias voltage of -1.2 V. The inset shows a schematic of the fabricated diode used for this measurement. The result suggests that the Al implant and segregation does not affect the drain-to-substrate junction leakage characteristics. ………………………………………………………

102

Fig. 5.1 (a) I-V characteristics of NiDySiGe/SiGe contact junctions with Al implant in the range of 0 to 2×1015 atoms/cm2 and formed at 500 °C. The control NiSiGe/SiGe contact junction formed at 450 °C is also shown for comparison. Inset shows the schematic of the fabricated contact devices. (b) Comparison of the sheet resistivity of blanket NiDySiGe film (with Al implant of 1×1015 atoms/cm2) with that of the NiSiGe control film (without any Al). A germano-silicidation temperature in the range of 350 – 700 °C for 30 s, at intervals of 50°C is used for the analysis. (c) XRD theta/2theta (θ/2θ) phase analysis of blanket NiDySiGe film (with Al implant of 1×1015 atoms/cm2), formed at a temperature in the range of 450 °C – 700 °C. NiSiGe control film (formed at 450 °C) is also shown for comparison. (d) SIMS depth profile of Al in NiDySiGe/SiGe contact junctions (with Al implant at dose of 1×1015

atoms/cm2). …………………………………………………………

113

Fig. 5.2 (a) Arrhenius plot to extract the ΦBp of NiDySiGe on SiGe, for the

NiDySiGe/SiGe contact device with Al implant at dose of 2×1014

atoms/cm2. IF on the y-axis is the forward bias current measured at a particular forward bias voltage VF at temperature T. (b) Lowering of ΦB

p of NiDySiGe on SiGe, with increase in Al implant dose. All data points are extracted by using the Arrhenius plot method [5.14]. The ΦB

p of NiSiGe on SiGe (without any Al implant, and formed at 450°C) is also shown for reference, at 0.53 eV. Inset shows the I-Vcurves measured at different T for the contact device used in Fig. 2(a). …………………………………………………………………

115

xviii

Fig. 5.3 Cross-sectional TEM image of a NiDySiGe/SiGe contact device

with Al implant at dose of 1×1015 atoms/cm2. ……………………...

116

Fig. 5.4 Cross-sectional TEM of a p-FinFET with 115 nm gate length. FIB cut along A-A' (shown in the SEM image of the device in the inset of the figure) does not run over the centre of the gate enveloping the fin and hence overestimates the LG slightly. ……………………

117

Fig. 5.5 (a) IDS-VDS characteristics of a matched pair of p-FinFETs with LG

= 115 nm and WFin = 40 nm, one with NiDySiGe S/D contact (with Al implant at dose of 2×1014 atoms/cm2), and the other one being that of the reference device with NiSiGe S/D contact (without any Al implant). (b) Y-axis on the left shows IDS-VGS characteristics of the same pair of FinFETs used in Fig. 5.5(a). Y-axis on the right shows a graph of RTotal versus VGS for the same pair of devices. RTotal = |VDS|/IDS,lin, where VDS = -50 mV and IDS,lin is the linear drain region. Hyphened line shows the first order exponential fit used to extract RSD at VGS = -10 V [5.10]. …………………………..

118

Fig. 5.6 (a) Plot of drive current IDSAT versus DIBL for p-FinFETs with NiDySiGe S/D silicide (with 2×1014 Al/cm2) and for p-FinFETs with NiSiGe S/D silicide, each with a set of 30-40 devices. (b) Plot of drive current IDSAT versus Subthreshold swing SS for p-FinFETs with NiDySiGe S/D silicide (with 2×1014 Al/cm2) and for p-FinFETs with NiSiGe S/D silicide [for the same set of devices used in Fig. 5.6(a)]. ………………………………………………………

119

Fig. 5.7 (a) Plot of drive current as a function of LG. Each data point corresponds to an average of 5-7 devices. P-FinFETs with NiDySiGe S/D silicide (with 2×1014 Al/cm2) demonstrate higher IDSAT compared to p-FinFETs with NiSiGe S/D silicide. (b) Plot of RTotal versus LG for p-FinFETs with novel NiDySiGe contacts (with Al implant of 2×1014 atoms/cm2) and p-FinFETs with conventional NiSiGe contacts, at a linear gate overdrive of -3 V, and VDS = -50 mV. The drop in RSD is calculated with respect to the RSD of p-FinFETs with NiDySiGe S/D contacts (with Al implant). …………

120

Fig. 5.8 Junction leakage in p-FinFETs with NiDySiGe S/D silicide (with 2×1014 Al/cm2) and p-FinFETs with NiSiGe S/D silicide is compared. Inset shows the schematic of the fabricated diode. …….

122

Fig. 5.9 Schematics of the proposed single silicide integration solution. (a) A masking layer is deposited on the n-FETs followed by Al+ ion implant on the entire wafer. (b) 5 nm Dy is deposited on the entire wafer followed by 15 nm Ni deposition (c) A 500 °C anneal is performed to form NiDySiGe for p-FET S/D contact (with Al implant) and NiDySi:C for n-FET S/D contact (without Al implant). (d) Unreacted metal is etched away selectively using SPM. ………………………………………………………………...

122

xix

Fig. 5.10 (a) IDS-VGS characteristic of a NiDySi:C contacted strained n-

FinFET and a NiSi:C contacted strained n-FinFET, having similar DIBL, SS and IOFF. (b) IDS-VDS characteristic of the same pair of devices show 40 % IDSAT enhancement with NiDySi:C S/D contacts. …………………………………………………………….

123

Fig. 5.11 Plot of ON current (IDSAT extracted at VGS = 1.4 V) versus OFF current (IOFF extracted at VGS = 0.2 V) for strained n-FinFETs with NiDySi:C S/D contact against devices with NiSi:C S/D contacts. A VDS of 1.2 V is used for the data extraction. ………………………..

124

Fig. 5.12 I-V characteristics of NiSiGe/SiGe contact junctions with Al and S double-implant. Al is implanted first, followed by S. The control NiSiGe/SiGe contact junction is also shown for comparison. ……...

127

Fig. 5.13 (a) Arrhenius plot to extract the ΦBp of NiSiGe on SiGe, for the

NiSiGe/SiGe contact device with Al implant at dose of 1×1015

atoms/cm2 and S implant at dose of 5×1013 atoms/cm2. IF on the y-axis is the forward bias current measured at a particular forward bias voltage VF at temperature T. Schematic of the fabricated contact devices is shown in the inset. (b) Lowering of ΦB

p of NiSiGe on SiGe with the Al and S double-implant. The ΦB

p of NiSiGe on SiGe (without the double-implant) is also shown for reference, at 0.53 eV. ……………………………………………….

127

Fig. 5.14 SIMS depth profile of Al and S in the four NiSiGe/SiGe contact junction splits with the double-implant of Al and S ions. …………..

128

Fig. 5.15 (a) Comparison of sheet resistance RS of the four blanket NiSiGe films (corresponding to the four Al + S double-implant splits) with that of the NiSiGe control film (without any implant). (b) XRD theta/2theta (θ/2θ) phase analysis of blanket NiSiGe film (with Al and S double-implant). NiSiGe control film is shown for comparison. …………………………………………………………

129

Fig. 5.16 I-V characteristics of NiSi/p-Si contact junctions with S implant in the range of 0 to 1×1014 atoms/cm2 and formed at 450 °C. The reference NiSi/p-Si contact junction without S implant is shown for comparison purposes. Inset shows the schematic of the fabricated device. ………………………………………………………………

130

Fig. 5.17 Extracted ΦBp of NiSi contact on p-Si with and without S implant.

With increase in S implant dose, ΦBp increases leading to a

corresponding drop in ΦBn since the sum of ΦB

p and ΦBn is the

bandgap of Si. ………………………………………………………

130

Fig. 5.18 (a) SIMS depth profile of S in the two NiSi/p-Si contact devices implanted with S. There is clear evidence of S segregation at the NiSi/p-Si interface. Inset shows the sheet resistance RS of the

xx

blanket NiSi films with and without S implant. (b) XRD theta/2theta (θ/2θ) phase analysis of blanket NiSi films (formed on p-Si substrate) with and without S implant dose of 1×1014

atoms/cm2. Only mono-silicide peaks are observed for both the films, with exactly the same orientation as that of the ref. device. …

131

Fig. 5.19 Cross-sectional TEM images of contact devices before and after silicidation. (a) Double-implant (Al at dose of 2×1014 atoms/cm2

and S at dose of 1×1014 atoms/cm2) into SiGe amorphizes top 20 nm. (b) S implant at dose of 1×1014 atoms/cm2 in Si amorphizes top 10 nm. (c), (d) Silicide formed consumes the amorphized region. ………………………………………………………………

132

Fig. 5.20 (a) Key Process steps for the fabrication of p-FinFETs with NiSiGe silicided S/D contacts, and integrated with the double-implant of with Al and S for contact resistance reduction. Control devices did not receive the double-implant. (b) Cross-sectional TEM image of a fabricated p-FinFET. Inset shows the top-view SEM of the device. FIB is done along the line A-A' which overestimates LG. …

134

Fig. 5.21 (a) IDS-VGS characteristics of a pair of p-FinFETs with and without the double-implant (Al and S) and having comparable short channel effects. (b) IDS-VDS characteristics of the same set of p-FinFETs, showing 27 % higher IDSAT for the device with double-implant (Al and S). ………………………………………………………………

135

Fig. 5.22 Plot of total resistance RTotal versus VGS for the pair of p-FinFETs used in Fig. 5.21. RTotal = |VDS|/IDS,lin, where VDS = -50 mV and IDS,lin is the drain current in the linear region. RSD is extracted at a high gate voltage of -10 V using a first order exponential fit [5.10]. The drop in RSD is measured with respect to the RSD of the p-FinFET that went through the double-implant. ……………………..

135

Fig. 5.23 (a) Plot of drive current IDSAT as a function of DIBL, both for p-FinFETs with and without the double-implant of Al + S. (b) Plot of IDSAT versus subthreshold swing SS, both for p-FinFETs with and without the double-implant. In both the plots [5.23(a) and 5.23(b)], best-fit lines (solid line for the devices with the double-implant and dashed line for the control devices) are drawn using linear regression. IDSAT for all devices is extracted at a fixed gate overdrive of -1.2 V, with drain voltage kept at -1.2 V. ……………..

136

Fig. 5.24 Plot of mean IDSAT as a function of LG for devices with and without the double-implant (Al and S). Both, IDSAT (for both sets of devices) and ∆IDSAT (increase in IDSAT for devices with double-implant over control devices) increase with LG scaling. Each data point is an average of ~5-7 devices. P+\n drain-to-body junction leakage is shown in the inset, and is unaffected by the double-implant technology. Best-fit lines (solid line for the devices with the double-implant and dashed line for the control devices) are

xxi

drawn using linear regression. ………………………………….......

136

Fig. 5.25 Plot of RTotal versus LG showing reduction in RSD by 58 % (calculated with respect to the control devices) for p-FinFETs with the double implant of Al and S ions. Best-fit lines for the two sets of devices, with and without the double-implant are drawn using linear regression. Solid line is for the devices with the double-implant and dashed line is for the control devices. RSD is extracted by extrapolation of the best-fit lines to zero gate length LG. No mobility variation is observed in the two set of devices due to the same slope of the best-fit lines. RTotal is calculated at a linear gate overdrive of -3 V for every data point. ……………………………..

137

Fig. 5.26 Schematics of the proposed single silicide integration solution. (a) A masking layer is deposited on the n-FETs followed by Al ion-implant. (b) Blanket S implant is done afterwards. (c) Ni is deposited on the entire wafer. (d) A 450 °C anneal is performed to form NiSiGe for p-FET S/D contact and NiSi for n-FET S/D contact, followed by unreacted metal removal using SPM. ………...

138

Fig. 5.27 (a) IDS-VGS characteristic of a pair of n-FinFETs (LG = 75 nm, WFin

= 30 nm) with and without S implant. Both the devices have comparable short channel effects, due to similar DIBL (~52 mV/V), SS (~88 mV/decade), VT (~0.1 V) and OFF state current. (b) IDS-VDS characteristics of the same pair of devices show 29 % IDSAT

enhancement for the device with S implant, at a gate overdrive of 1.2 V, with VDS also at 1.2 V. ………………………………………

139

Fig. 5.28 Plot of ON current (IDSAT extracted at VGS = 1.2 V) versus OFF current (IOFF extracted at VGS = 0 V) for n-FinFETs with and without S implant. VDS is kept at 1.2 V. 30-40 devices each are used for the statistical plot. …………………………………………

139

xxii

LIST OF SYMBOLS

Symbol Description Unit

A Device active area μm2

A* Richardson constant A/(cm2K2)

COX Capacitance of gate oxide F

EF.M Fermi energy level of a metal or metal-silicide eV

HFIN Fin height nm

I Junction current A

IF Junction forward bias current A

IDS Drain current (per unit width) μA/μm

IDSAT Saturation drive current (per unit width) μA/μm

IOFF Off state current (per unit width) A/μm

ION On state current (per unit width) μA/μm

IS Junction reverse current A

k Permittivity of dielectric

λ Channel length modulation parameter V-1

L Transistor effective channel length nm

LG Transistor gate length nm

ΦB Schottky barrier height eV

ΦBp Schottky barrier height for hole conduction eV

ΦBn Schottky barrier height for electron conduction eV

q Electronic charge C

ρ Resistivity μΩ-cm

ρC Interfacial contact resistivity Ω-cm2

xxiii

R Junction series resistance Ω

RC Silicide junction contact resistance Ω-μm

RCH Channel resistance Ω-μm

RDRAIN Drain parasitic series resistance Ω-μm

RSOURCE Source parasitic series resistance Ω-μm

RSD Source/drain total parasitic series resistance Ω-μm

RS Sheet resistivity or sheet resistance Ω/sq

RTotal Transistor total resistance Ω-μm

T Temperature K

μ Effective channel mobility cm2/V-s

V Junction voltage V

VF Junction forward bias voltage V

VDS Drain voltage V

VGS Gate voltage V

VT Threshold voltage V

VTSAT Saturation threshold voltage V

W Effective channel width nm

WFin Fin width nm

x or y Mole fraction of Ge or C

1

CHAPTER 1

Introduction and Motivation

1.1 Challenges to CMOS Scaling: A Background

The rapid pace of metal-oxide semiconductor field-effect transistor (MOSFET)

scaling (Fig. 1.1) has been the main stimulus to the growth of the silicon integrated

circuits (IC) industry [1.1]. Transistor feature size has been scaled down at a rate of

approximately 0.7 times every two years, a law that has become known as Moore’s

law. Periodic shrinking of devices and interconnects and once-a-decade increase of

wafer size have been the main approaches to reduce cost. Also, the more an IC is

scaled, the higher becomes its speed of operation (due to higher drive current) and

packing density. These have been the key in the evolutionary progress leading to

today’s computers and communication systems that offer superior performance.

Fig. 1.1 Scaling of transistor size (physical gate length LG) to sustain Moore’s Law [1.2].

2

As scaling continues, reducing the power supply voltage (VDD) is an effective

option available to device technologists for lowering the active power. The basic

drain current equation for a long channel n-MOSFET operating in saturation region is

given by

DS2

TGSOXnDS 12

1λVVV

L

WCμI , (1.1)

where IDS is the drain current, μn is the channel mobility, COX is the gate oxide

capacitance, W is the channel width, L is the effective channel length, VGS is the gate

voltage, VT is the threshold voltage, λ is the channel length modulation parameter, and

VDS is the drain voltage. It can be seen that reducing VDD (and hence VDS)

unfortunately reduces the drain current of the transistor and its abilities to drive device

and interconnect capacitances speedily. The current can be increased by reducing the

threshold voltage, VT and thinning the gate dielectric (which increases the oxide

capacitance, COX). However, reducing the threshold voltage raises the subthreshold

leakage and oxide scaling increases the gate leakage, thereby increasing the power

consumption of the device. These issues get further amplified by the fact that we are

fast reaching fundamental limits to device scaling.

The industrial and academic research communities are pursuing two avenues

to meet these challenges: new materials and new transistor structures. New materials

include those used in the gate stack to enhance COX and hence drive current without

adversely affecting gate leakage (high-κ dielectric and metal gate [1.3]-[1.6]), those

used in the conducting channel that have improved carrier mobility (for e.g., III-V,

germanium, and carbon based electronics [1.7]-[1.11]), as well as new materials used

in the source/drain regions with reduced parasitic resistance and improved carrier

injection properties (for e.g., silicon-germanium S/D for p-MOSFETs and silicon-

carbon S/D for n-MOSFETs [1.12]-[1.17]). New transistor structures seek to improve

3

the electrostatics of the MOSFET, provide a platform for introduction of new

materials, and accommodate the integration needs of new materials (for e.g., Tunnel-

FETs, Impact-Ionization FETs, ultra-thin body (UTB) silicon-on-insulator (SOI)

devices and Multiple-gate Transistors [1.17]-[1.20]).

1.2 The Parasitic Series Resistance Challenge

As scaling of MOSFET device dimension continues, engineering the

source/drain is becoming critically important to maintain the S/D parasitic series

resistance RSD to a reasonable fraction (∼17-33 %) of the total resistance RTOTAL

(=VDS/IDS) [1.1]. RTOTAL is essentially the resistance that charge carriers encounter

while being conducted from the source to drain of a MOSFET, and can be divided

into the channel resistance RCH and the parasitic series resistance RSD. According to

the 2007 ITRS roadmap there are no known manufacturable solutions to keep RSD

within the stipulated limits, for future bulk-silicon technology nodes slated for

production as early as the year 2010 (Table 1.1). Simultaneously, maintaining a low

contact resistance also faces a similar challenge, which will be discussed in more

detail later in section 1.2.1 and section 1.2.2.

The impact of RSD on device performance can be seen in the schematic drawn

in Fig. 1.2. V′GS and V′DS are the applied gate and drain voltages, respectively, taking

into consideration the presence of source and drain parasitic resistance, RSOURCE and

RDRAIN, respectively. In the presence of RSD, the drain current IDS drops due to the

lowering of VGS and VDS which are the intrinsic gate and drain voltages, respectively,

in the absence of RSD, used in Equation (1.1). VGS and VDS are given by

GS GS DS SOURCE'V V I R , and DS DS DS SOURCE DRAIN' ( )V V I R R (1.2)

4

Table 1.1 Front End Processes (FEP) requirements - near term Years [1.1].

Year of Production 2008 2009 2010 2011 2012

MPU/ASIC Metal 1 ½ Pitch

(nm) (contacted)

59 52 45 40 36

MPU Physical Gate Length

(nm)

23 20 18 16 14

Drain extension junction

depth for bulk MPU/ASIC

(nm)

11 10 9 8 7

Maximum allowable parasitic

series resistance for bulk

NMOS MPU/ASIC × width

(Ω−μm)

200 200 180 180 180

Maximum drain extension

sheet resistance for bulk

MPU/ASIC (NMOS) (Ω/sq)

740 810 900 1015 1160

Extension lateral abruptness

for bulk MPU/ASIC

(nm/decade)

2.3 2.0 1.8 1.6 1.4

Contact junction depth for

bulk MPU/ASIC (nm)

25.3 22 19.8 17.6 15.4

Contact maximum resistivity

for bulk MPU/ASIC (Ω-cm2)

1.0×10-7 9.2×10-8 7.0×10-8 6.2×10-8 5.6×10-8

Manufacturable solutions

Exist and are being optimized

Known (Bold Font)

NOT known (Underlined)

5

Gate

Source

Drain

RSOURCE

RDRAIN

V′GS

VGS

V′DSVDSV

GS < V

DDRSD

> 0

Drain Voltage V'DS

(V)

Dra

in C

urr

ent

I DS (A

/m

)

RSD

= 0

Lowering of IDS

VGS

= VDD

Fig. 1.2 Schematic showing the impact of RSD on drain current IDS. Note that RSD =

RSOURCE + RDRAIN and leads to lowering of IDS as evident from the IDS vs V′DS plot.

As device dimensions scale down to follow Moore’s law, RSD increases due to

silicide contact area and S/D junction depth reduction. This will be shown in more

detail in section 1.2.1 and section 1.2.2. On the other hand, RCH drops as it is

proportional to gate length LG. RCH is also inversely proportional to channel mobility.

Enhanced strain engineering (coupled with device scaling led technology

development) lead to an increase in channel mobility, which further reduces RCH. At

the 90 nm technology node, RCH dropped substantially (from the previous technology

node) as strain engineering was introduced for the first time to enhance channel

mobility [1.7]. This trend of increase in RSD/RCH as the IC industry progresses to the

next technology node is shown in Fig. 1.3 [1.22]. It is projected that at the 32 nm

technology node, RSD will be approximately equal to RCH and at the 22 nm node, RSD

will be twice of RCH. In other words, the impact of RSD on the transistor performance

is increasing. At the 22 nm technology node and beyond, multiple gate transistors

(MuGFETs), for example, FinFETs are projected to be introduced.

6

0.0

0.5

1.0

1.5

2.0

Technology Node (nm)

RSD

dominates RCH

FinFETs slated to beintroduced

22 nm

90 nm65 nm

45 nm

32 nmRSD

RCH

Par

asit

ic S

erie

s R

esis

tan

ce /

Ch

anne

l Res

ista

nce

(RS

D /

RC

H)

Fig. 1.3 Simulation study showing the increase in ratio of RSD over RCH with technology

node [1.22].

The impact of series resistance in FinFETs (with narrow fin width WFin) is

even worse [1.23]. WFin is the most critical dimension in the FinFET device

architecture. An exponential increase in RSD is shown with scaling of fin width, as

shown in Fig. 1.4 [1.23].

20 30 40 50 60 70

3

4

5

6

7

8

9

RS

D (

k

)

Fin Width WFin

(nm)

Fig. 1.4 Increase of RSD in n-FinFETs with scaling down of WFin [1.23]. Inset shows a

schematic of a tri-gate FinFET, where HFin is the height of the fin and LG is the gate length.

S/DFin

G

S DWFin

HFin

FinFETs

LG

S/DFin

G

S DWFin

HFin

FinFETs

LG

LG = 30 nm HFin = 60 nm

7

1.2.1 Components of Parasitic Series Resistance

Figure 1.5 shows a cross-sectional schematic of half of a MOSFET depicting

the various resistance components between source (or drain) and the channel that the

charge carriers encounter. The resistance in the channel region is RCH/2 and every

other resistive component contributes to source (or drain) series resistance RSOURCE (or

RDRAIN). Please note that the total parasitic series resistance RSD and the total channel

resistance is twice that of RSOURCE (or RDRAIN) and RCH/2, respectively shown in Fig.

1.5. Broadly speaking, RSD consists of 3 components. First is the S/D extension

(SDE) resistance RSDE. Second is the deep S/D resistance RDSD and the final

component is the contact junction resistance RC at the interface between silicide and

RCHRDSD

RSOURCE or RDRAIN

RC

RSDE

Gate Silicide

1

2

Fig. 1.5 Components of source (or drain) parasitic series resistance in a MOSFET. Dotted

lines show the flow of charge carriers (current) from the silicide contact into the channel.

Only a half cross-section of the transistor (cut vertically through the centre of the gate) is

shown in this figure. The other half of the transistor has the same set of resistances. RSD =

2RS = 2RD, assuming that the source and drain are symmetrical. Half of the channel resistance

(RCH/2) is also shown for completeness.

8

heavily doped S/D region. RSDE consists of the sheet resistance RSH,SDE (in Ω) of the

SDE body where current flows uniformly and the spreading resistance RSPR which is

associated with the resistance when current crowds into the thin inversion channel

beneath the gate from the uniform SDE body. RSH,SDE and RSPR are given by [1.24]

W

S

W

S

xR SDE

JSDESH,

, and (1.3)

C

JSPR 75.0ln

π

2

x

x

WR

(1.4)

where, ρ is resistivity of the SDE region, xJ is the SDE junction depth, S is the spacing

between the gate edge and silicide contact edge, W is the device width, ρSDE is the

sheet resistivity of the SDE region in Ω/sq, and xC is the thickness of the inversion

channel. RDSD is essentially the sheet resistance (in Ω) of the deep S/D part of the

transistor. It is given by

W

SR SDDSD , (1.5)

where ρSD is the sheet resistivity of the deep S/D region in Ω/sq. RC is the contact

resistance when current flows from metal silicide (or metal lines) into the S/D. It is

given by [1.24]

T

CCSDC coth

L

L

WR

, (1.6)

where ρC is the interfacial contact resistivity in Ω-cm2, LC is the length of the contact

silicide, and LT is the transfer length given by SDCT L . LT is a measure of the

length of that part of the silicide through which effectively the drain current flows.

When LC << LT

WLR CCC , (1.7)

and under the condition that LC >> LT

9

WLR TCC . (1.8)

1.2.2 Impact of Contact Resistance RC

It can be clearly seen from Equations (1.3) – (1.8) that as transistor dimensions

(for example, critical parameters such as junction depth, contact length and device

width) are scaled down while moving to the next technology node, parasitic series

resistance increases. Figure 1.6 shows the relative contribution of RC, RSDE and RDSD

to the total parasitic resistance in both n-FETs and p-FETs, at a LG of 50 nm [1.25]. It

is evident that the contact resistance RC has a major impact on RSD. It is one of the

biggest contributors to the parasitic resistance.

Equation (1.7) and Equation (1.8) show that RC is directly proportional to the

interfacial contact resistivity ρC. ρC at the interface between a metal or a metal-

silicide (for example nickel silicide) and a heavily-doped semiconductor (for example

50 75 1000

10

20

30

40

50

50 75 1000

10

20

30

40

50

(b)p-FET

RSDE

RDSD

Rel

ativ

e C

ontr

ibu

tion

to

RS

D (

%)

Gate Length (nm)

RC

n-FET(a)

RSDE

RDSD

Gate Length (nm)

RC

Fig. 1.6 Fraction (in %) of RC, RSDE and RDSD to the total series resistance at LG = 50 nm,

for (a) n-FETs, and (b) p-FETs [1.25].

10

silicon) depends exponentially on the Schottky barrier height ΦB at the interface and

the semiconductor doping density N. This relationship is given by [1.24]

BexpCρN

. (1.9)

Figure 1.7 shows energy band diagram of a metal-silicide contact on n+-Si showing

the Schottky barrier height ΦB for electron conduction. Equation (1.9) assumes that

the contact is ohmic and the current conduction is dominated by tunneling.

From Equation (1.9) it is clear that there are essentially two approaches to

reduce RC. The first one is to increase the semiconductor doping concentration N in

the S/D of transistor. The S/D doping level in the state-of-the-art transistors is already

near the dopant solid-solubility limits [1.1]. Milli-second anneal involving laser and

n-Si

ΦB

ΦB = 0.67 eV for NiSi

Schottky Barrier Height

ECEF

Tunneling Current

metal/ metal-silicide

EVn+-Sin-Si

ΦB

ΦB = 0.67 eV for NiSi

Schottky Barrier Height

ECEF

Tunneling Current

metal/ metal-silicide

EVn+-Si

Fig. 1.7 Energy band diagram of a metal or a metal-silicide contact on n+-Si showing

electron tunneling through the thin barrier height. In the case of a nickel-silicide (NiSi)

contact, the Schottky barrier height ΦB for electron conduction has been reported to be ~0.67

eV [1.26].

11

flash annealing tools are being investigated by various research groups and

semiconductor companies to enhance the doping level beyond the solid-solubility

limits [1.27]-[1.29]. This is achieved by keeping the dopant atom in a meta-stable

state. Schottky barrier engineering (SBE) is the second approach to reduce RC. This

involves the use of various techniques to lower the Schottky barrier height ΦB at the

interface between silicide and heavily-doped deep S/D. These techniques include the

use of novel nickel-alloy silicides, selenium passivation, dopant segregation, and

sulfur and selenium segregation, among others [1.30]–[1.37].

1.3 Objectives of Research

As described in the preceding sections, contact resistance RC is a significant

component of the parasitic series resistance RSD and is a major obstacle to device

scaling led approach to drive current enhancement for 22-nm CMOS technology and

beyond. This is an even bigger issue in multiple-gate transistors (for example

FinFETs) which are slated for introduction at around the 16-nm technology node.

The focus of this thesis is on Schottky barrier engineering for contact resistance

reduction in CMOS FETs. Various material and process innovations are explored for

the lowering of Schottky barrier height at the interface of silicide and heavily-doped

deep S/D region and then they are integrated in FinFETs for drive current

enhancement. Extensive material and device characterization are performed to

achieve the stated results and will be shown in the chapters to follow.

12

1.4 Thesis Organization

Chapter 1 provides a brief introduction to the technological challenges and

bottlenecks in MOSFET scaling, which motivated this thesis work. It provides the

background information needed to understand the impact of contact resistance and

series resistance on the performance of CMOS transistors. Finally, this chapter

discusses the objectives of the thesis.

Chapter 2 deals with the selection of material to be ion-implanted at the

interface between nickel-silicide (NiSi) and p-Si for reduction of hole Schottky barrier

height ΦBp of NiSi on p-Si. The conceptual selection criterion is discussed which

forms the starting point for these sets of experiments. A range of materials were

experimented. Extensive material characterization results are presented which form

the basis for integration of novel materials and processes in the S/D region of p-

channel FETs for the reduction of contact resistance and series resistance. An attempt

is also made to understand the mechanism behind the modulation of the Schottky

barrier height achieved in this work.

Chapter 3 is on the Schottky barrier height tuning of NiSi on Si and is divided

into two parts. In part 1, material results for the reduction of ΦBp of NiSi on p-Si

using aluminum (Al) implant and segregation are discussed. In essence, an Al

implant technology is developed for reduction of contact resistance in p-FETs.

Extensive optimization of the metal silicidation process and of the Al implant

parameters is performed to achieve maximum benefit during integration of this

technology in p-channel multiple-gate FETs (e.g., FinFETs). Electrical results

corresponding to series resistance reduction and drive current enhancement in p-

FinFETs are presented. In part 2 of this chapter, material characterization results

corresponding to the modulation of electron Schottky barrier height ΦBn of NiSi on

13

silicon-carbon (Si:C) substrate are presented. The impact of carbon content (in Si:C)

on the ΦBn of NiSi on Si:C is studied. This study finds application in fabricating high

performance n-channel Schottky S/D transistors (n-SSDT), and also conventional n-

FETs (planar FETs or MuGFETs) where a small ΦBn at the interface between metal

silicide (e.g., NiSi) and heavily n-doped Si is a necessity.

Chapter 4 discusses the tuning of the Schottky barrier height for holes ΦBp of

nickel germano-silicide (NiSiGe) contact on SiGe, for application in strained p-

channel FETs. Al implant technology is developed and optimized to achieve the

desired lowering of ΦBp and then integrated in p-FinFETs for contact resistance

reduction leading to drive current enhancement. Detailed fabrication process flow of

p-FinFETs and electrical results are presented.

In chapter 5, two single silicide integration schemes for a low cost solution to

contact resistance minimization in CMOS transistors are developed. In part 1 of this

chapter, a novel metal alloy [composed of nickel(Ni) and dysprosium(Dy)] is used to

form a low work function Ni-Dy silicide for n-FETs exhibiting low contact resistance.

Simultaneously, a low contact resistance is also achieved on p-FETs using Al implant

technology to move the Fermi level of Ni-Dy germano-silicide (formed on strained p-

FinFETs with SiGe S/D) towards the valence band of SiGe. In the second part of the

chapter, as even more promising single silicide process flow is discussed. This

method utilizes only one mask and two ion-implant steps to independently lower the

Schottky barrier height at the interface between conventionally used nickel-silicide

and heavily doped S/D region in both p- and n-FETs. Sulfur (S) implant is used for

contact resistance reduction in n-FETs and the compensation effect of a double-

implant consisting of Al and S is developed for p-FETs. Significant drive current

14

enhancement is achieved when this technology is integrated in CMOS FinFET

process flow.

An overall conclusion and possibilities for future work are furnished in

Chapter 6. Appendix A contains the list of publications that originated from this

thesis. Appendix B entails the activation energy method for extraction of Schottky

barrier height at the interface between metal (or metal-silicide) and semiconductor,

using the Thermionic Emission model.

15

1.5 References

[1.1] The International Technology Roadmap for Semiconductors (ITRS), Semiconductor

Industry Association, San Jose, CA, 2007.

[1.2] R. Chau, M. Doczy, B. Doyle, S. Datta, G. Dewey, J. Kavalieros, B. Jin, M. Metz, A.

Majumdar, and M. Radosavljevic, “Advanced CMOS transistors in the

nanotechnology era for high-performance, low-power logic applications,” Proc. 7th

International Conference on Solid-State and Integrated Circuits Technology

(ICSICT), pp. 26-30, Oct. 2004.

[1.3] S. Matsuda, H. Yamakawa, A. Azuma, and Y. Toyoshima, “Performance

improvement of metal gate CMOS technologies,” VLSI Symp. Tech. Dig., pp. 63-64,

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engineering on gate leakage of MOSFETs,” IEEE Trans. Electron Devices, vol. 51,

no. 11, pp. 1783-1789, Nov. 2004.

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materials on metal and silicon gate workfunctions,” IEEE Electron Device Lett., vol.

23, no. 6, pp. 342-344, June 2002.

[1.6] A. E.-J. Lim, R. T. P. Lee, X. P. Wang, W. S. Hwang, C. H. Tung, G. S. Samudra,

D.-L. Kwong, and Y.-C. Yeo, “Yttrium and terbium based interlayers on SiO2 and

HfO2 gate dielectric for work function modulation of nickel fully silicided gate in

nMOSFET,” IEEE Electron Device Lett., vol. 28, no. 6, pp. 482-485, June 2007.

[1.7] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffiann, K.

Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, J. Sandford, M.

Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A

90nm high volume manufacturing logic technology featuring novel 45nm gate length

strained silicon CMOS transistors,” IEDM Tech. Dig., pp. 978-980, 2003.

[1.8] K. W. Ang, K. J. Chui, V. Bliznetsov, A. Du, N. Balasubramanian, M. F. Li, G.

Samudra, and Y.-C. Yeo, “Enhanced performance in 50 nm n-MOSFETs with

silicon-carbon source/drain regions,” IEDM Tech. Dig., pp. 1069-1072, 2004.

[1.9] H. C.-H. Wang, Y.-P. Wang, S.-J. Chen, C.-H. Ge, S. M. Ting, J.-Y. Kung, R.-L.

Hwang, H.-K. Chiu, L. C. Sheu, P.-Y. Tsai, L.-G. Yao, S.-C. Chen, H.-J. Tao, Y.-C.

Yeo, W.-C. Lee, and C. Hu, “Substrate-strained silicon technology- process

integration,” IEDM Tech. Dig., pp. 61-64, 2003.

16

[1.10] C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, “A germanium NMOSFET

process integrating metal gate and improved hi- spl kappa dielectrics,” IEDM Tech.

Dig., pp. 437-440, 2003.

[1.11] F.-L. Yang, C.-C. Huang, H.-Y. Chen, J.-J. Liaw, T.-X. Chung, H.-W. Chen, C.-Y.

Chang, C.-C. Huang, K.-H. Chen, D.-H. Lee, H.-C. Tsao, C.-K. Wen, S.-M. Cheng,

Y.-M. Sheu, K.-W. Su, C.-C. Chen, T.-L. Lee, S.-C. Chen, C.-J. Chen, C.-H. Chang,

J.-c. Lu, W. C., C.-P. Hou, Y.-H. Chen, K.-S. Chen, M. Lu, L.-W. Kung, Y.-J. Chou,

F.-L. Liang, I.-W. You, K.-C. Shu, B.-C. Chang, J.-L. Shin, C.-K. Chen, T.-S. Gau,

B.-W. Chan, Y.-C. Huang, H.-J. Tao, J.-H. Chen, Y.-S. Chen, Y.-C. Yeo, S. K-H

Fung, C. H. Diaz, C.-M. M. Wu, B. I. Lin, M.-S. Liang, J. Y.-C. Sun, and C. Hu, “A

65nm node strained SOI technology with slim spacer,” IEDM Tech. Dig., pp. 627-

630, 2003.

[1.12] R. Rishton, “New complementary metal-oxide semiconductor technology with self-

aligned schottky source/drain and low-resistance Tgates,” J. Vac. Sci. Technol., p.

2795-2798, 1997.

[1.13] S. Zhu, J. Chen, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, M. F. Li, S. J. Lee, C.

Zhu, D. Chan, A. Du, C. H. Tung, J. Singh, A. Chin, and D.-L. Kwong, “Schottky-

barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode,” Proc.

7th International Conference on Solid-State and Integrated Circuits Technology

(ICSICT), pp. 53-56, Oct. 2004.

[1.14] D. Connelly, C. Faulkner, and D. E. Grupp, “Optimizing schottky S/D offset for 25-

nm dual-gate CMOS performance,” IEEE Electron Device Lett., vol. 24, no. 6, pp.

411-413, June 2003.

[1.15] Y. Nakahara, K. Takeuchi, T. Tatsumi, Y. Ochiai, S. Manako, S. Samukawa, and A.

Furukawa, “Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth

micron CMOS,” VLSI Symp. Tech. Dig., pp. 174-175, 1996.

[1.16] H.-J. Huang, K.-M. Chen, C.-Y. Chang, L.-P. Chen, G.-W. Huang, and T.-Y. Huang,

“Reduction of source/drain series resistance and its impact on device performance

for PMOS transistors with raised Si1-xGex source/drain,” IEEE Electron Device Lett.,

vol. 21, no. 9, pp. 448-451, Sep. 2000.

[1.17] Y.-K. Choi, D. Ha, T.-J. K. Liu, and C. Hu, “Ultra-thin body PMOSFETs with

selectively deposited Ge source/drain,” VLSI Symp. Tech. Dig., pp. 19-20, 2001.

17

[1.18] K. Gopalakrishnan, P. B. Griffin and J. D. Plummer, “Impact ionization MOS (I-

MOS)–Part I: Device and circuit simulations,” IEEE Trans. Electron Devices, vol.

52, no. 1, pp. 69-76, Jan. 2005.

[1.19] K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin and J. D. Plummer,

“Impact ionization MOS (I-MOS)—Part II: Experimental results,” IEEE Trans.

Electron Devices, vol. 52, no. 1, pp. 77-84, Jan. 2005.

[1.20] S. H. Kim, H. Kam, C. Hu and T.-J. K. Liu, “Germanium-source tunnel field effect

transistors with record high ION/IOFF,” VLSI Symp. Tech. Dig., p. 178, 2009.

[1.21] F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X.

Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C. Wu, C.-C. Chen, S.-C. Chen, Y.-

T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-

C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, “5 nm-gate nanowire

FinFET,” VLSI Symp. Tech. Dig., 2004, pp. 196-197.

[1.22] A. M. Noori, M. Balseanu, P. Boelen, A. Cockburn, S. Demuynck, S. Felch, S.

Gandikota, A. J. Gelatos, A. Khandelwal, J. A. Kittl, A. Lauwers, W.-C. Lee, J. Lei,

T. Mandrekar, R. Schreutelkamp, K. Shah, S. E. Thompson, P. Verheyen, C.-Y.

Wang, L.-Q. Xia, and R. Arghavani, “Manufacturable processes for ≤ 32-nm-node

CMOS enhancement by synchronous optimization of strain-engineered channel and

external parasitic resistances,” IEEE Trans. Electron Devices, vol. 55, no. 5, pp.

1259-1264, May 2008.

[1.23] A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. D. Meyer,

“Analysis of the parasitic S/D resistance in multiple-gate FETs,” IEEE Trans.

Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.

[1.24] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices, Cambridge, UK,

1998.

[1.25] S.-D. Kim, C.-M. Park, and J. C. S. Woo, “Advanced model and analysis of series

resistance for CMOS scaling into nanometer regime - Part II: Quantitative analysis,”

IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 467-472, Mar. 2002.

[1.26] K. Maex and M. Van Rossum, Properties of metal silicides, Eds. London, U.K.,

IEEE-Inspec, 1995, pp. 164-172.

[1.27] C. Park, S.-D. Kim, Y. Wang, S. Talwar, and J. C. S. Woo, “50nm SOI CMOS

transistors with ultra shallow junction using laser annealing and pre-amorphization

implantation,” VLSI Symp. Tech. Dig., pp. 69-70, 2001.

18

[1.28] J.-N. Gillet, J.-Y. Degorce, and M. Meunier, “General model and segregation

coefficient measurement for ultrashallow doping by excimer laser annealing,” Appl.

Phys. Lett., vol. 86, 222104, 2003.

[1.29] K. Osada, T. Fukunaga, and K. Shibahara, “Ge shallow junction formation by As

implantation and flash lamp annealing,” Trans. VLSI-TSA, pp. 15-16, 2009.

[1.30] D. Connelly, C. Faulkner, D. E. Grupp, and J. S. Harris, “A new route to zero-barrier

metal source/drain MOSFETs,” IEEE Trans Nanotech., vol. 3, no. 1, March 2004, pp.

98-104.

[1.31] D. Connelly, C. Faulkner, P. A. Clifton, and D. E. Grupp, “Fermi-level depinning for

low-barrier Schottky source/drain transistors,” Appl. Phys. Lett., vol. 88, 2006.

[1.32] M. Tao, S. Agarwal, D. Udeshi, N. Basit, E. Maldonado, and W. P. Kirk, “Low

Schottky barriers on n-type silicon (001),” Appl. Phys. Lett., vol. 83, no. 12, pp.

2593-2595, Sep. 2003,.

[1.33] M. Tao, D. Udeshi, S. Agarwal, E. Maldonado, and W.P. Kirk, “Negative Schottky

barrier between titanium and n-type Si (001) for low-resistance ohmic contacts,”

Solid-State Electronics, vol. 48, pp. 335-338., 2004.

[1.34] Q. T. Zhao, U. Breuer, E. Rije, St. Lenk, and S. Mantl, “Tuning of NiSi/Si Schottky

barrier height by sulfur segregation during Ni silicidation,” Appl. Phys. Lett., vol. 86,

062108, 2005.

[1.35] R. T. P. Lee, T.-Y. Liow, K.-M. Tan, A. E.-J. Lim, H. S. Wong, P. C. Lim, D. M. Y.

Lai, G. Q. Lo, C. H. Tung, G. S. Samudra, D. Z. Chi, and Y.-C. Yeo, “Novel nickel-

alloy silicides for source/drain contact resistance reduction in n-channel multiple-

gate transistors with sub-35nm gate length,” IEDM Tech. Dig., pp. 851-854, 2006.

[1.36] H.-S. Wong, L. Chan, G. Samudra, and Y.-C. Yeo, “Effective Schottky barrier

height reduction using sulfur and selenium at the NiSi/n-Si (100) interface for low

resistance contacts,” IEEE Electron Device Lett., vol. 28, no. 12, pp. 1102-1104, Dec.

2007.

[1.37] H.-S. Wong, F.-Y. Liu, K.-W. Ang, G. S. Samudra, and Y.-C. Yeo, “Novel nickel

silicide contact technology using selenium segregation for SOI n-FETs with silicon-

carbon source/drain stressors,” IEEE Electron Device Lett., vol. 29, no. 8, pp. 841-

844, Aug. 2008.

19

CHAPTER 2

Material Screening

2.1 Introduction

As discussed in chapter 1, reduction of contact resistance RC at the interface

between metal-silicide and the deep S/D region in MOSFET forms the main focus of

this thesis. In this chapter, focusing on p-channel MOSFETs, a range of materials

will be studied for possible application in reducing the hole Schottky barrier height

ΦBp at the interface between nickel-silicide (NiSi) and p-Si. These materials are

incorporated at the NiSi/p-Si interface by ion-implantation. In the sections to follow,

conceptual motivation behind choosing these elements will be discussed, followed by

device fabrication, and electrical results and discussions. Note that NiSi is the silicide

of choice at the 45 nm technology node, which is currently in production in leading

semiconductor companies [2.1].

2.2 Motivation

Figure 2.1 (a) shows the energy band diagram of NiSi contact on p-Si under

flat- band condition, in the absence of any externally introduced material (impurity) at

the NiSi/p-Si interface. The Schottky barrier height for hole conduction is shown in

the figure as ΦBp. If negative charges can be introduced in the thin interfacial region

on the Si side of the NiSi/p-Si interface, this will induce equal and opposite positive

charge on the NiSi side of the interface, leading to the generation of an interfacial

dipole, as shown in Fig. 2.1(a).

20

Impurity Segregated Interfacial Region

Direction

EF,M

EC

ETEV

EF,M

EC

EV

Effective

∆ΦBpHole

Tunneling

NiSi NiSi

p-Si

∆ΦBp

Dipole

(a) (b)

ΦBp

p-Si

ΦBp

Fig. 2.1 Energy band diagram of NiSi contact on p-Si showing (a) flat-band condition and

(b) a case where the conduction and valence bands bend downwards due to the acceptor-type

trap level ET introduced at the interface by the ion-implanted element (or impurity). For

simplicity, it is assumed that the effective workfunction Φ of NiSi and p-Si is the same. EF,M

is the Fermi level of NiSi, EC is the conduction band edge energy level and EV is the valence

band edge energy level.

The dipole will lead to an electric field that will bend the conduction and valence

bands of Si downward, which will result in thinning down of the Schottky barrier

width, thus allowing holes to tunnel through it, as shown in Fig. 2.1(b). As a result,

the effective Schottky barrier is lowered by ΔΦBp.

This idea can be evaluated by incorporating impurities (or species) at the

NiSi/p-Si interface that introduce acceptor-type trap level in the silicon bandgap near

the valence band. This is shown schematically in Fig. 2.1(a) by the energy level ET

introduced in the shaded impurity-segregated interfacial region. When acceptor-type

21

traps are filled, they are negatively charged [2.2]. When these traps are empty, they

are neutral. The closer the trap level is to the valence band, the higher is its

probability of being filled, according to the Fermi distribution function [2.2].

Literature review was performed to select elements with trap levels close to

the valence band of silicon [2.2]. The selected elements are aluminum (Al), zinc (Zn),

cadmium (Cd) and cobalt (Co). All of them introduce one or more acceptor-type trap

levels near the silicon valence band. Note that when a donor-type trap level is empty,

it is positively charged and when it is filled, it is neutral [2.2]. Thus, the donor-type

traps in the case of Al would not induce any interfacial dipole as they will most likely

be neutral. Also note that a fifth element, magnesium (Mg), has been experimented in

Acceptor-type Trap Donor-type Trap

0.0

0.2

0.4

0.6

0.8

1.0

En

ergy

(eV

)

Material Selection

Al Zn Cd Co

1.12 eV

MgE

V

EC

Si midgap

Fig. 2.2 List of trap levels ET introduced in the silicon bandgap by Al, Zn, Cd, Co, and

Mg [2.2]. These elements are ion-implanted into Si for the purpose of modulation of ΦBp at

the NiSi/p-Si interface.

22

this work, since it incorporates donor-type traps which will be positively charged

(being closer to the conduction band). Thus, a complementary effect should be seen

at the NiSi/p-Si interface in this case due to a dipole moment pointing in a direction

opposite to that shown in Fig. 2.1(a), i.e., from the NiSi region to the p-Si region. In

other words, the effective ΦBp should increase which will not only be beneficial for n-

MOSFET applications but will also lend further weight to the hypothesis that

interfacial dipole is a dominant mechanism behind modulation of Schottky barrier

height in this work.

2.3 Device Fabrication

200-mm p-type Si (100) wafers (4-8 Ω cm) were used as starting substrates in

the experiments to fabricate NiSi/p-Si contact junctions (or contact devices) for

extraction of the effective ΦBp of NiSi on p-Si, with and without ion-implanted

impurities. Figure 2.3(a) shows the key steps of the fabrication process. 150 nm of

field oxide (SiO2) was grown on the substrate wafers by wet oxidation. The oxide

was patterned using photo-lithography and then dry etched to define square-shaped

active areas of dimension 85 μm × 85 μm. The impurity element was then

incorporated into the active area within the p-Si substrate by ion-implantation. This

was done at a tilt angle of 7° to avoid extensive channeling. This was followed by

standard substrate cleaning involving a 10 minutes (min.) wash in 4:1 mixture of

sulfuric acid and hydrogen peroxide (SPM) with the bath maintained at 120°C, to

remove organic and metallic contaminants. Then, the wafers were dipped in a dilute

hydrofluoric acid (HF) solution prepared by mixing 1 part of concentrated HF in 100

parts of de-ionized (DI) water, for 2 min. to remove native oxide from the Si active

areas.

23

Isolation oxide growth.

Contact window lithography and etch.

Impurity ion-implantation.

Nickel deposition (30 nm).

NiSi formation at 500°C.

Wet etch to remove unreacted Ni.

Backside ohmic-contact formation (200 nm Al).

SiO

2

SiO

2

p-Si

NiSi

V, I

Al back-contact

(a) (b)

Fig. 2.3 (a) Key process steps carried out in the fabrication of NiSi/p-Si contact junction

with ion-implanted impurities. (b) Schematic of the final device showing the shaded region

(red color) of interest where the ion-implanted impurities are present after silicidation.

After this clean step, wafers were immediately loaded into an e-beam evaporator

chamber (with a base pressure of 2×10-6 Torr) to deposit 30 nm of nickel (Ni). Ni

silicidation was carried out using rapid thermal annealing (RTA) at 500˚C for 1 min.

in N2 ambient. The unreacted Ni on top of the isolation oxide was selectively etched

away using a SPM wash at 120 °C for 2 minutes. Finally, 200 nm of Al was

deposited on the backside of the wafer to provide an ohmic contact. Schematic of the

final device structure is shown in Fig. 2.3(b). One p-Si wafer was not implanted with

the impurity species and was used as the control sample.

As discussed in section 2.2, Table 2.1 shows the details of the various

implantation splits investigated in this work, involving 5 different ion species. The

variations are in the implantation dose of the impurity species, so as to study the effect

of dose and hence the concentrations of the implanted element at the NiSi/p-Si

interface on ΦBp. The implantation energy for every impurity is chosen such that the

24

implantation range (RP) is ~15 nm. This was done for consistency and comparison

sake and also to ensure that the thickness of Ni was enough to consume the ion-

implanted silicon region during silicidation. Note that during nickel silicidation, 1 nm

of Ni consumes ~1.8 nm of Si to form ~2.2 nm of NiSi [2.3]. RP is extracted from the

Table 2.1 Experimental splits detailing the energy, dose and range (RP) of the ion-implanted

species.

Split No. Ion Species Energy

(keV)

Dose

(atoms/cm2)

RP

(nm)

1 Al 10 1 × 1013 15

2 Al 10 5 × 1013 15

3 Al 10 2 × 1014 15

4 Zn 20 1 × 1013 15

5 Zn 20 5 × 1013 15

6 Zn 20 2 × 1014 15

7 Co 20 1 × 1013 15

8 Co 20 5 × 1013 15

9 Co 20 2 × 1014 15

10 Cd 30 1 × 1013 15

11 Cd 30 5 × 1013 15

12 Cd 30 1 × 1014 15

13 Mg 10 2 × 1015 15

25

as-implanted profile of the impurity species in Si using time of flight secondary-ion

mass spectroscopy TOF-SIMS (not shown). Overall, there are 14 samples

corresponding to the 13 splits mentioned in Table 2.1 and including the control

sample.

2.4 Results and Discussions

2.4.1 Impact of Acceptor-type Impurity

In this section, the impact of acceptor-type impurities (Al, Zn, Cd and Co) on

the current-voltage (I-V) characteristics of NiSi contacts on p-Si will be discussed.

Figure 2.4(a) shows the two terminal I-V characteristics of contact junctions with and

without Al implant. It can be clearly seen that the reverse current increases with Al

implant dose, pointing towards lowering of ΦBp. This can be explained using the

thermionic emission (TE) model for metal-semiconductor junctions, given by [2.4]

S

( )exp 1 exp

q V IR q V IRI I

nkT kT

, and (2.1)

* 2

BS

Φ = lnkT AA T

q I

, (2.2)

where IS is the reverse saturation current, q is the electronic charge, R is the device

series resistance, n is the ideality factor, k is Boltzmann constant, T is the temperature

in Kelvin, A is the diode area, A* is the Richardson constant (32 A/cm2K2 for p-type

Si), and ΦB is the Schottky barrier height obtained from I-V measurement. In this

case, ΦB is the same as ΦBp. From Equation (2.2), it is clear that as the reverse current

increases, the barrier height drops. At a dose of 2×1014 atoms/cm2, the I-V

characteristics become almost ohmic [Fig. 2.4(a)]. Thus, Al implant is able to achieve

the desired result in terms of achieving smaller ΦBp at the interface between NiSi and

26

p-Si and it is postulated that interfacial dipole is the dominant mechanism behind it, as

discussed in section 2.2. These results will be discussed in more detail in chapter 3

(section 3.2) and more data will be presented.

I-V characteristics of NiSi/p-Si contact devices remain virtually unaffected by

Zn and Cd implant, shown in Fig. 2.4(b) and 2.4(c), respectively. The variation in

reverse current with implantation dose is within the error bar of reverse current of the

control sample (introduced due to due to statistical process variation), without any

-2 -1 0 1 2

10-1

100

101

Increase in reverse

0

11013

5 1013

21014

Cu

rren

t D

ensi

ty (

A/c

m2 )

Voltage (V)

Al I/I Dose(atoms/cm2)

current with implant dose

(a)

-2 -1 0 1 2

10-1

100

101

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 ) (b)

0

1 1013

51013

2 1014

Zn I/I Dose(atoms/cm2)

Reverse Currentis unaffected

27

-2 -1 0 1 2

10-1

100

101

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 ) (c)

0

1 1013

5 1013

11014

Cd I/I Dose(atoms/cm2)

Reverse Currentis unaffected

-2 -1 0 1 2

10-2

10-1

100

101

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 ) (d)

0

1 1013

5 1013

21014

Co I/I Dose(atoms/cm2)

Drop in Reverse Current with Implant Dose

Fig. 2.4 Room temperature (RT) I-V characteristics of NiSi/p-Si contact junctions with

and without the implanted acceptor-type impurity, namely (a) Al, (b) Zn, (c) Cd, and (d) Co.

Effect of ion-implantation dose on ΦBp is studied in each of the 4 plots.

clear trend. Figure 2.4(d) shows the I-V characteristics of NiSi/p-Si contact devices

with Co ion-implantation. The reverse current decreases with implant dose, pointing

towards increase in ΦBp [from Equation (2.2)]. This unexpected behavior will be

further discussed in section 2.4.1.1.

In order to understand the modulation of ΦBp at the NiSi/p-Si interface, TOF-

SIMS depth profile of the implanted element (or impurity) in the contact devices was

28

extracted and is plotted in Fig. 2.5. It can be clearly seen that there is significant

presence of the implanted elements at the interface between NiSi and p-Si in all

contact devices. Furthermore, there is clear evidence of segregation of Zn and Cd at

the interface. However, it needs to be explicitly stated here that the actual

concentration of these species at the NiSi/p-Si interface may be too low (< 0.1 at. %)

to cause sufficient ΦBp modulation [especially for the case of Zn and Cd, as seen in

Fig. 2.4(b) and 2.4(c)], except for the case of Al, which introduces the shallowest

acceptor-type trap level in Si among the full range of materials investigated in this

study and so may not require a very high concentration at the NiSi/p-Si interface at all.

In section 2.4.1.1, I-V characteristics of contact devices formed with much thinner

0 20 40 60 80 100 120 140 160 18010-1

100

101

102

103

104

105

ZnCd

Co

Al

Ni

Si

Inte

nsi

ty (

cps)

Depth (nm)

NiSi

As-implanted Peak in Si

Si

Fig. 2.5 TOF-SIMS depth profile of the ion-implanted species (Al, Zn, Cd and Co) within

the NiSi/p-Si contact device. The profile of each of these impurity species is taken from their

respective contact device with the implantation dose of 2×1014 atoms/cm2. The first peak in

each of these profiles is due to the as-implanted peak of that species in Si before being

consumed by nickel during silicidation.

29

NiSi will be shown for the case of Zn, Cd and Co. As discussed before, thinner

silicide is formed using smaller Ni thickness consuming proportionally lesser Si

substrate during the silicidation process [2.3]. Thus, the NiSi/Si interface can be

tuned to form closer to the as-implanted peak of the impurity species in Si and hence

the concentration of the impurity at the NiSi/p-Si interface may be higher than that

shown in Fig. 2.5.

It should also be noted that the concentration of the implanted species inside

the silicide is also less than 0.1 at. % (calculated separately) because the highest

implantation dose used in these experiments (corresponding to the contact devices

with Al, Zn, Cd or Co) is only 2×1014 atoms/cm2. Thus, any variation in the bulk

electrical properties of NiSi film (e.g., its work function) is not expected.

2.4.1.1 Effect of Silicide Thickness on Schottky Barrier Height

Figure 2.6 shows the 2-terminal I-V characteristics of two NiSi/p-Si

contact devices, one with Co ion-implant and the other one with Cd ion-implant, both

at dose of 2×1014 atoms/cm2 and formed from 10 nm of Ni. I-V characteristics of the

control sample (without any ion-implantation) and another NiSi/p-Si contact device

with Co ion-implant (at dose of 2×1014 atoms/cm2) formed from 30 nm of Ni is also

shown for comparison (taken from Fig. 2.4). It can be clearly observed for the case of

NiSi/p-Si contact devices with Co ion-implant that with decrease in thickness of the

silicide formed, the reverse current is further modulated. ΦBp extracted using the TE

model [Equation (2.1) and Equation (2.2)] increases by ~110 meV, from 0.48 eV (for

the sample with NiSi formed from 30 nm of Ni) to 0.59 eV (for the sample with NiSi

formed from 10 nm of Ni). The control sample has a ΦBp of ~0.4 eV which is well

documented in literature as well [2.5], [2.6]. For the case of NiSi/p-Si contact device

30

-2 -1 0 1 2

10-4

10-3

10-2

10-1

100

101

102

0.48 eV

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 )

0.4 eV

0.59 eVControlCo, 30nm NiCo, 10nm NiCd, 10nm Ni

NiSi/p-Si

Increase in B

p

Fig. 2.6 I-V characteristics of NiSi/p-Si contact devices with Co and Cd ion-implantation

at dose of 2×1014 atoms/cm2. Effect of the thickness of the formed NiSi on ΦBp is studied.

The control device did not undergo any ion-implant.

with Cd ion-implant as well (formed from 10 nm of Ni), the ΦBp is extracted to be

~0.59 eV, an increase in 190 meV from that of the control sample. Results similar to

that for the case of contact devices with Cd ion-implantation were also achieved for

the case of contact devices with Zn ion-implantation (not shown). These results are

beneficial for application in n-MOSFETS since an increase in ΦBp leads to a

proportional decrease in electron Schottky barrier height ΦBn of NiSi contact on n-Si.

As discussed earlier, 10 nm of Ni should consume ~18 nm of Si to form ~22

nm of NiSi [2.3]. In this case (devices formed from 10 nm of Ni and shown in Fig.

2.6), the silicidation anneal was done at 500 °C for only 30 s to prevent possible

agglomeration of the thinner silicide [2.3]. Since the as-implanted peak of the

impurity (Cd or Co) in Si is at ~15 nm (from Table 2.1), 10 nm thick Ni film will still

31

0 20 40 60 80 100 12010-1

100

101

102

103

104

105SiNiSi

SiInte

nsi

ty o

f C

o (c

ps)

Depth (nm)

NiSi(10 nm Ni)

(30 nm Ni)

NiSi formed from- 30 nm Ni 10 nm Ni

Fig. 2.7 TOF-SIMS depth profile of Co in the NiSi/p-Si contact devices with Co ion-

implantation at dose of 2×1014 atoms/cm2. Two devices are used for the profiling of Co, one

with NiSi formed from 10 nm of Ni and the other with NiSi formed from 30 nm of Ni. The

difference in intensity (or concentration) of Co at the NiSi/p-Si interface between the two

devices is observed and is shown by the dotted line in red.

consume most of the impurity implanted region (during silicidation) and hence

suppress end-of-range defects, while keeping the interface between NiSi and p-Si very

close to the RP of the as-implanted profile. It can be observed from Fig. 2.7 that the

peak concentration of Co near the NiSi/p-Si interface increases by ~4 times by

thinning down the silicide. The actual thickness of NiSi as extracted from the SIMS

profile is ~70 nm and ~27 nm for the silicide formed from 30 nm and 10 nm of Ni,

respectively, which is within the standard statistical errors introduced during device

fabrication and characterization. Similar results are also expected for devices with Cd

or Zn ion-implantation, although they are not explicitly shown here. Thus, from Fig.

32

2.4 - Fig. 2.7 it can be concluded that the ΦBp of NiSi contact on p-Si increases with

ion-implantation of Co, Cd or Zn which can be further amplified by thinning down

the silicide thickness to ensure enhanced impurity concentration at or near the NiSi/p-

Si interface.

To understand the mechanism behind this anomalous increase in ΦBp

(corresponding to the presence of Co, Cd or Zn at the interface between NiSi and p-

Si), further work would be needed. One possible route is to use first-principle

calculations based on density functional theory to extract the density of states (DOS)

in the Si bandgap at the NiSi/p-Si interface with and without the presence of these

impurity atoms [2.7]. From here, the charge neutrality level ECNL at the interface and

the Fermi level EF,M can then be calculated. The energy difference ΔE between EF,M

and ECNL brings about the charge transfer through the interface, generating an electric

dipole at the interface [2.8], which can point towards in either direction depending on

the sign of ΔE, leading to a modulation in Schottky barrier height.

2.4.2 Impact of Donor-type Impurity

The impurity that introduces donor-type trap level in the Si substrate,

investigated in this work is Mg. Figure 2.8 shows the 2-terminal I-V characteristics of

NiSi/p-Si contact junctions with and without Mg implant at dose of 2×1015 atoms/cm2.

The reverse current drops with Mg implant, pointing towards an increase in ΦBp. It

should be noted here that for this contact junction involving Mg implant (split no. 13

in Table 2.1), 10 nm of Ni was used for nickel silicidation (NiSi formation) and the

silicidation was done at 500 ˚C for 30 s in N2 ambient. All the rest of the process

steps are the same as that discussed in section 2.3. The reason for selecting a thinner

33

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.010-6

10-5

10-4

10-3

10-2

10-1

100

101

102

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 )

NiSi/p-Si - Ref NiSi/p-Si - Mg I/I

Increase in B

p

B

p = 0.67 eV

B

p = 0.4 eV

Fig. 2.8 Room temperature I-V characteristics of NiSi/p-Si contact devices with and

without Mg ion-implant at dose of 2×1015 atoms/cm2.

silicide thickness in this case is the same as that discussed in the section 2.4.1.1 for Co,

Cd and Zn. The RP of Mg in Si at implantation energy of 10 keV is experimentally

extracted by TOF-SIMS to be ~15 nm (Table 2.1). Thus, 10 nm of Ni will still

consume most of the Mg implanted region, while having a high probability of

achieving a large concentration of Mg atoms near the interface between NiSi and p-Si.

Fig. 2.9 shows the TOF-SIMS depth profile of Mg in the NiSi/p-Si contact

device. There is clear evidence of Mg segregating near the NiSi/p-Si interface. This

will possibly result in a dipole moment pointing from the NiSi side of the interface

towards the Si substrate, causing the Si bands to bend upward and increase the ΦBp, as

discussed in section 2.2. Thus, these results indeed support the postulated theory that

interfacial dipole mechanism is responsible for the modulation in Schottky barrier as

observed in the case of Al and Mg impurities at the interface between NiSi and p-Si.

34

0 20 40 60 80 100 120 140

101

102

103

104

Inte

nsi

ty (

a.u

.)

Depth (nm)

Ni Si Mg

NiSi Si

Fig. 2.9 TOF-SIMS depth profile of Mg in the NiSi/p-Si contact device with Mg implant

at dose of 2×1015 atoms/cm2. Significant segregation of Mg at the interface between NiSi and

p-Si is observed.

The ΦBp for the contact device with Mg implant is extracted using Equation

(2.1) and Equation (2.2) to be 270 meV higher than that of the control sample (Fig.

2.8). This leads to a 270 meV lower electron barrier height on the complementary

device structure, namely NiSi on n-Si with Mg implant. Thus, Mg implant has a

strong potential to be used in n-MOSFETs, similar to Cd, Co and Zn, as shown in

section 2.4.1.

2.5 Summary and Conclusion

In this chapter, work related to the modulation of hole Schottky barrier height

ΦBp of NiSi contact on p-Si has been presented. A range of materials have been

screened for this purpose, namely Al, Co, Cd, Zn and Mg. The central motivation is

not only to reduce ΦBp but to eventually understand the mechanism behind it.

35

Extensive I-V characterizations and TOF-SIMS results have been discussed. It has

been shown that Al implant into p-Si before Ni deposition and silicidation leads to

lowering of ΦBp and hence fabrication of ohmic contact.

Mg implant leads to a complementary effect of reduction in electron barrier

height, which is beneficial for contact resistance reduction in n-MOSFETs. A

possible mechanism explaining the modulation in Schottky barrier at the interface

between NiSi and Si due to Al or Mg implantation has been postulated. The bending

of Si bands due to traps (acceptor-type or donor-type) introduced by these ion-

implanted species near the Si side of the NiSi/p-Si interface is believed to be the main

reason behind it.

For the case of Zn, Co and Cd impurities, an increase in ΦBp was observed.

This can find application in n-MOSFETs, but these observed results cannot be

explained by the interfacial dipole theory postulated in section 2.2. First-principle

calculations based on density functional theory may be useful [2.7]. It needs to be

stressed here that even for the case of Al and Mg, the postulated theory cannot be the

sole reason behind lowering of the hole barrier height ΦBp. Chemical bonding

information at the NiSi/p-Si interface can be a big step forward towards understanding

the complete mechanism. Recently, three-dimensional atom-probe tomographic

studies have been proposed which may permit the actual reconstruction of atoms near

the NiSi/p-Si interface in three dimensions [2.9]. The exact position of atoms as well

as their chemical identities can be ascertained using this experimental technique. This

technique may be extremely helpful in further understanding the observed modulation

of Schottky barrier lowering.

36

2.6 References

[2.1] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M.

Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R.

Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly,

P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B.

McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes,

M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D.

Simon, S. Sivakumar, P. Smith, C. Thomas, T. T Roeger, P. Vandervoorn, S.

Williams, and K. Zawadzki, “A 45nm logic technology with high-k+metal gate

transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and

100% Pb-free packaging,” IEDM Tech. Dig., pp. 247-250, 2007.

[2.2] S. M. Sze and K. K. Ng, Physics of semiconductor devices, 3rd edition, Wiley-

Interscience, NJ, 2007.

[2.3] L. J. Chen, Silicide technology for integrated circuits, IEE, London, UK, 2004.

[2.4] D. K. Schroder, Semiconductor material and device characterization, 3rd edition,

IEEE Press, 2006.

[2.5] Z. Zhang, Z. Qiu, R. Liu, M. Ostling, and S.-L. Zhang, “Schottky-barrier height

tuning by means of ion implantation into preformed silicide films followed by drive-

in anneal,” IEEE Electron Device Lett., vol. 28, no. 7, pp. 565-568, Jul. 2007.

[2.6] K. Maex and M. Van Rossum, Properties of Metal Silicides, IEE-INSPEC, London,

UK, 1995.

[2.7] T. Yamauchi, A. Kinoshita, Y. Tsuchiya, J. Koga, and K. Kato, “1 nm NiSi/Si

junction design based on first-principles calculation for ultimately low contact

resistance,” IEDM Tech. Dig., pp. 385-388, 2006.

[2.8] J. Tersoff, "Theory of semiconductor heterojunctions: The role of quantum dipoles,"

Phys. Rev. B, vol. 30,no. 8, pp. 4874-4877, Oct. 1984.

[2.9] P. Adusumilli, C. E. Murray, L. J. Lauhon, O. Avayu, Y. Rosenwaks, and D. N.

Seidman, “Three-dimensional atom-probe tomographic studies of nickel

monosilicides/silicon interfaces on a subnanometer scale,” ECS Trans., vol. 19, no. 1,

pp. 303-314, May 2009.

37

CHAPTER 3

Schottky Barrier Height Tuning of NiSi/Si

3.1 Introduction

This chapter has been divided into two parts. Part 1 (section 3.2) discusses the

tuning of the Schottky barrier height for hole conduction at the interface between NiSi

and p-Si using Al implant and segregation. Detailed material characterization results

will be presented here, followed by p-channel FinFET integration and electrical

results.

The results presented in part 2 of this chapter (section 3.3) have application for

n-FETs. Part 2 investigates the modulation of the electron Schottky barrier height at

the interface between NiSi and n-Si using silicon-carbon (Si:C) bandgap engineering.

Extensive material characterization results will be shown.

3.2 Aluminum Implant for Schottky Barrier Height Tuning in p-

FETs

3.2.1 Motivation

Multiple gate transistors or FinFETs alleviate short channel effects, enhance

device scalability, and are promising for possible adoption beyond the 22 nm

technology node [3.1] - [3.6]. Due to narrow fin widths, keeping the parasitic series

resistance RSD a small fraction of the channel resistance RCH is a big challenge in

FinFETs. A dominant component of RSD is the contact resistance RC at the interface

38

between the metal-silicide and the heavily-doped Source/Drain (S/D) region, which is

proportional to the Schottky barrier height at the interface [3.7], [3.8].

Novel metal-silicide, for e.g. platinum silicide (PtSi) has been demonstrated to

have an effective Schottky barrier height for holes ΦBp of ~0.22 eV [3.9]. However,

the resistivity of PtSi is 2-3 times higher than that of nickel silicide (NiSi), which is

currently the salicide material used in mainstream CMOS technology [3.9]. NiSi has

a ΦBp of ~0.4 eV on p-Si [3.10]. Dopant segregation involving boron implant and

segregation has been shown to reduce ΦBp at the NiSi/p-Si interface, but the effective

ΦBp that is achieved is still high (~0.2 eV), leaving plenty of room for further work

[3.10].

In this work, the tuning of the effective ΦBp at the NiSi/p-Si junction by the

introduction of aluminum (Al) using ion-implantation and its segregation after

silicidation is investigated. ΦBp has been found to decrease with increasing

concentration of Al at the NiSi/p-Si interface. One of the lowest reported ΦBp of 0.12

eV, with less than 0.1 at. % Al in NiSi is achieved. Extensive material

characterization results will be presented.

For the FinFET architecture where achieving low RC is especially important,

the benefit of Al segregation on ΦBp reduction is expected to be significant. For

FinFET integration, a wide range of Al dose is investigated. An Al dose which

provides the maximum reduction in ΦBp without degrading the resistivity or sheet

resistance (RS) of the mono-silicide phase of NiSi is chosen for integration in tri-gate

p-channel FinFETs. Significant drive current IDSAT enhancement is observed in p-

FinFETs with Al segregated at the NiSi/p+-Si interfacial region in the S/D. Extensive

electrical results will be shown.

39

3.2.2 Device Fabrication

200 mm p-type Si (100) wafers (4-8 Ω cm) were used as starting substrates for

current-voltage (I-V) measurements of NiSi/p-Si contact junctions to extract the

effective ΦBp of NiSi on p-Si. The contact junction fabrication procedure is the same

as that described in section 2.3. 150 nm of SiO2 was grown on the substrate wafer by

wet oxidation and then patterned using photo-lithography and dry etching to define

active areas of dimension 85×85 µm2. Al was then implanted at energy of 10 keV at

three different implant dose splits, namely, 1×1013, 5×1013 and 2×1014 atoms/cm2.

The control split did not receive any Al implant. After standard wafer cleaning and

dilute hydrofluoric acid (DHF) dip, 30 nm of Ni was immediately deposited using an

e-beam evaporator and silicidation was done using rapid thermal annealing (RTA) at

500˚C for 1 minute in N2 ambient to form NiSi. The unreacted Ni was selectively

etched away using 4:1 mixture of sulfuric acid and hydrogen peroxide (SPM) at 120

°C for 2 minutes. Finally a backside ohmic contact was formed using 200 nm of Al to

complete the junction fabrication process. One p-Si wafer that did not go through Al

ion-implantation is used as the control sample. Blanket NiSi films were also prepared

on p-Si substrate, with and without Al implant, for RS measurement and XRD phase

analysis studies.

To integrate the Al segregated NiSi/p+-Si S/D junctions into tri-gate p-

FinFET devices, 200 mm SOI substrates with 40 nm thick Si (Fin height, HFin = 40

nm) and 140 nm thick BOX were used. After threshold voltage (VT) adjust implant,

fin width (WFin) down to 55 nm were defined using 248 nm lithography, resist

trimming and reactive ion etching. Gate stack comprising poly-Si on 3.0 nm SiO2

was defined followed by SDE implant, spacer formation and deep S/D implant. After

implant activation at 1000 °C for 1 s, Al was implanted at energy of 10 keV and dose

40

of 2×1014 atoms/cm2. Finally 10 nm of Ni was deposited and thermally silicided at

500 °C to form the S/D and gate contact comprising of NiSi. The unreacted Ni was

selectively etched using SPM.

3.2.3 Results and Discussions

3.2.3.1 Material Characterization

A. I-V Measurements: Impact of Al Implantation Dose on Schottky Barrier Height

The experimental current-voltage (I-V) curves of NiSi/p-Si contact

junctions with and without Al ion-implantation are plotted in Fig. 3.1(a). This was

also shown in Fig. 2.4(a) but has been re-plotted here for clarity. With increase in

implanted dose of Al ions, the reverse current increases. This indicates a lowering of

effective ΦBp of NiSi on p-Si [using Equation (2.1)-(2.2)].

Rectification ratio (RR) is used to evaluate the device rectification

characteristics and is defined as the ratio of the forward current (IF) taken at a forward

voltage (VF) of 1 V to the reverse current (IR) taken at a reverse voltage (VR) of 1 V.

A higher effective ΦBp leads to a higher RR, and for an ohmic contact, RR is close to 1.

At Al dose of 2×1014 cm-2, the I-V characteristics [Fig. 3.1(a)] approach that of an

ohmic contact with RR of ~1.53. Since the known value of ΦBp of NiSi on p-Si

(without Al implant) is ~0.4 eV, to measure even smaller ΦBp, low temperature I-V

characterization (activation energy method) is used [3.10], [3.11]. Appendix B can be

referred for more details regarding the activation energy method. Fig. 3.1(b) shows

the plot for IF/T2 versus 1000/T at different VF for the sample with Al implant dose of

2×1014 cm-2, where T is the absolute temperature in Kelvin. This plot is extracted

from Fig. 3.1(c) which is the plot of I-V characteristics of the same sample measured

at different temperatures. The average value of effective ΦBp extracted from Fig.

41

-2 -1 0 1 210-1

100

101

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 )

No Al

11013Al/cm2

51013Al/cm2

21014Al/cm2

Increasing Reverse Current(a)

3.0 3.5 4.0 4.5 5.0 5.510-11

10-10

10-9

VF = 0.10 V

VF = 0.08 V

VF = 0.06 V

VF = 0.04 V

(b)

VF = 0.02 V

Temperature Range forB

p Extraction

I FT

2 (A

/K2 )

1000/T (K-1)

-2 -1 0 1 2

10-2

10-1

100

101

p-Si

V, I

SiO

2NiSi

SiO

2

C

urr

ent

Den

sity

(A

/cm

2 )

Voltage (V)

(c)

T = 193 K

T = 293 KT = 10 K

Fig. 3.1 (a) I-V characteristics of NiSi on p-Si with and without Al ion-implantation. (b)

Activation energy measurements to extract the ΦBp of NiSi on p-Si, which was implanted with

Al at dose of 2×1014 cm-2. The slope of the linear fit of the curve (solid line) in the low

temperature part is used to extract ΦBp. (c) I-V characteristics of the sample with Al implant

at dose of 2×1014 cm-2, measured at different temperatures. For the sake of clarity, some

temperature plots have been omitted here, but are still used in part (b). Inset shows the

schematic of the fabricated contact device.

42

3.1(b) is ~0.27 eV, which is 130 meV lower than the ΦBp extracted for NiSi on p-Si

with no Al implant (not shown). Linear fit of the curve in the low temperature part

[as shown in Fig. 3.1(b)] is used for accurate extraction of effective ΦBp [3.12]. For

the sample with Al implantation dose of 1×1013 cm-2 and 5×1013 cm-2, the average

value of extracted effective ΦBp is 0.34 eV and 0.32 eV, respectively (not shown).

To understand this lowering of effective ΦBp of NiSi/p-Si with increasing dose

of Al, the depth profile of Al in NiSi/p-Si contact junction was plotted using time-of-

flight secondary-ion mass spectroscopy (TOF-SIMS), and is shown in Fig. 3.2.

Although, the most probable mechanism has already been discussed in section 2.2

(chapter 2), it will be discussed here again for better clarity. Since the starting

thickness of Ni was 30 nm, the final NiSi thickness is ~70 nm (Fig. 3.2), which is

21014Al/cm2

11013Al/cm2

51013Al/cm2

0 20 40 60 80 100 120 140 160

1016

1017

1018

1019

1020

1021

1022

1023

11013Al/cm2

(After-Silicidation)

21014Al/cm2

Ni Si

Location of Al Peak

in Si (As-implanted)

Depth (nm)

Con

cen

trat

ion

(cm

-3) SiNiSi (As-implanted)

Fig. 3.2 TOF-SIMS depth profile of Al after 30 nm Ni deposition and silicidation, as well

as the as-implanted Al profile (in silicon). The as-implanted profile is shifted so that it

indicates where the original Al peak is located, i.e., in the Si region which has been converted

into NiSi.

43

consistent with existing reports [3.13]. The as-implanted depth profile of Al (in Si) is

also shown in the same plot by shifting it inside the silicide by 15 nm, which is the

approximate thickness of final NiSi surface from the initial Si surface (before Ni

deposition and silicidation), corresponding to 30 nm of Ni [3.13]. Hence, the first

peak of Al depth profile (in NiSi) is due to the as-implanted Al peak in Si.

Comparing with the as-implanted profile there is a clear observation of segregation of

Al at the NiSi/p-Si interface after silicidation, with the peak (the second peak in Al

depth profile) lying on Si side of the interface. Since the solubility of Al in NiSi

(~6×1020 cm-3) is higher than that in Si (~2×1019 cm-3), the segregation profile is not

abrupt [3.14]. What is important here is that the concentration of Al in NiSi is less

than 0.1 atomic percent, which would neither affect the morphology of NiSi film nor

its resistivity. Another point to note is that with increasing Al implant dose, there is

an increase in concentration of Al at the NiSi/p-Si interface (Fig. 3.2) leading to

lowering of effective ΦBp.

B. Impact of Silicide Thickness on Schottky Barrier Height

Moving further with the reasoning discussed above, another two NiSi/p-Si

contact junctions were prepared with Al ion-implantation energy of 10 keV and dose

of 2×1014 cm-2 and with a thinner silicide than before. By analyzing the as-implanted

Al profile in Fig. 3.2, it is believed that a thinner silicide would have a higher Al

concentration at the NiSi/p-Si interface and hence will lead to further ΦBp lowering.

A similar logic was also presented in section 2.4.1.1 for Schottky barrier height

modulation in NiSi/p-Si contact junctions with Cd, Zn and Co ion-implantation.

44

-2 -1 0 1 210-1

100

101

No Al 30nm Ni 20nm Ni 10nm Ni

Cu

rren

t D

ensi

ty (

A/c

m2 )

Voltage (V)

(a)

Increasing Reverse

Current

Temperature Range

for B

p Extraction

3.0 3.5 4.0 4.5 5.0 5.5 6.0

10-10

10-9

(b)

I F/T

2 (A

/K2 )

1000/T (K-1)

VF = 0.10 V

VF = 0.08 V

VF = 0.06 V

VF = 0.04 V

VF = 0.02 V

Fig. 3.3 (a) I-V characteristics of two NiSi/p-Si contact junctions, one formed with 20 nm

Ni and the other formed with 10 nm of Ni, and both implanted with Al at dose of 2×1014

atoms-cm-2 and energy of 10 keV. Silicidation is done at 500 °C for 30 s, for both these

devices. Also shown are I-V characteristics of a NiSi/p-Si contact devices formed with 30 nm

Ni (with same Al ion-implantation parameters) and the control sample without any Al, that

are taken directly from Fig. 3.1(a). (b) Activation energy measurements to extract the ΦBp of

NiSi (formed with 10 nm Ni) on p-Si, which is implanted with an Al dose of 2×1014 cm-2 at

10 keV. The slope of the linear fit of the curve (solid line) in the low temperature part is used

to extract ΦBp.

45

The thickness of nickel used for these two devices were 10 nm and 20 nm,

with both of them going through the rest of the same silicidation process as presented

in section 3.2.2. I-V characteristics of these two contact junctions are shown in Fig.

3.3(a). Also shown in the same figure are I-V characteristics of the contact device

with 30 nm Ni (with the same Al ion-implantation parameters) and that of the control

sample with no Al, both of which are taken from Fig. 3.1(a), for comparison purposes.

It can be observed that the reverse current further increases with thinner silicides, with

it being the highest for the thinnest silicide tried out in these experiments (formed

with 10 nm Ni). This points toward further lowering of effective ΦBp [using Equation

(2.1) and Equation (2.2)]. Again, activation-energy method is used to extract the

effective ΦBp of these two contact devices, and the measurements are shown in Fig.

3.3(b) (for the sample with silicide obtained from 10 nm Ni). The effective ΦBp is

calculated to be ~0.12 eV [from Fig. 3.3(b)], which is one of the lowest value reported

in the existing literature till date. For the silicide obtained from 20 nm Ni, the

effective ΦBp is extracted to be ~0.14 eV (not shown).

C. Mechanism for Lowering of Schottky Barrier Height

The TOF-SIMS profile for these two contact devices, one with silicide formed

from 10 nm of Ni and the other one with silicide formed from 20 nm of Ni show that

the concentration of Al at NiSi/p-Si interface is higher than that for the device with

silicide formed from 30 nm of Ni (Fig. 3.4). Figure 3.5 plots the lowering of the

effective ΦBp of NiSi on p-Si with increasing Al concentration at the NiSi/p-Si

interface and the results show a monotonic trend. It is believed that Al forms a thin

dipole layer at the NiSi/p-Si interface, which is responsible for the lowering of

46

0 20 40 60 80 100 120 140

1017

1018

1019

1020

Si(10 nm Ni)

SiNiSi

Depth (nm)

Con

cen

trat

ion

of

Al (

cm-3

)

9.518 cm-3

SiNiSi(20 nm Ni)

NiSi(30 nm Ni)

NiSi formed from- 30 nm Ni 20 nm Ni 10 nm Ni

4.418 cm-3

3.319 cm-3

Fig. 3.4 TOF-SIMS depth profile of Al in three NiSi/p-Si contact devices, with NiSi

formed from 30 nm of Ni, 20 nm of Ni and 10 nm of Ni. For all samples, Al implant is done

at dose of 2×1014 atoms/cm2.

0 5 10 15 20 25 30 350.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.450 5 10 15 20

S

chot

tky

Bar

rier

Hei

ght

(eV

)

Al Concentration at Interface (1018 cm-3)

Al Dose (1013atoms/cm2)

Fig. 3.5 ΦBp as a function of concentration of Al at NiSi/p-Si interface, as well as a

function of the Al ion-implantation dose. The three data points at the same Al ion-

implantation dose of 2×1014 cm-2 correspond to progressively thinner NiSi (formed from 30

nm, 20 nm and 10 nm of Ni) leading to increase of concentration of Al at the NiSi/p-Si

interface and hence lowering of effective ΦBp. For the rest of the three data points at lower Al

ion-implantation dose, NiSi is formed from 30 nm of Ni.

47

effective ΦBp of NiSi on p-Si. Conceptually, this mechanism is similar to sulfur

segregation that lowers the electron Schottky barrier height of NiSi on n-Si [3.15]. Al

is known to introduce acceptor-type trap level in Si bandgap near the valence band

and hence this will introduce negative charge on the silicon side of the interface [3.11].

This, in turn will induce equal and opposite positive charge on the NiSi side of the

interface leading to a very sharp electric field at the interface which pulls down the

Fermi level of NiSi, thus lowering the effective barrier height for hole conduction.

Alternatively, the shallow acceptor-type traps (introduced by Al) in the Si

bandgap near the NiSi/p-Si interface will lead to sharp downward band bending of the

Si valence band (and the conduction band), as proposed by J. M. Shannon [3.16].

This will reduce the barrier width, causing increase in probability of tunneling of

holes through it, thus lowering the effective ΦBp. M. Tao et al. has reported lowering

of the Schottky barrier height of pure metals, like Al and chromium (Cr) on n-Si by

using a monolayer of Se [3.17]. In his work, it was proposed that Se passivates the

dangling Si bonds at metal/Si interface, hence reducing the interface states that pin the

Fermi level of metal to the mid-gap of Si. The Schottky barrier height was shown to

become close to that postulated by the Schottky-Mott model [3.11]. But, in the case

of Al implant and segregation, the lowest ΦBp value that has been achieved (~0.12 eV)

is far smaller than that predicted by the Schottky-Mott model, if the workfunction of

NiSi is assumed to be ~4.7 eV [3.18]. Hence, surface passivation can be safely ruled

out as the reason behind lowering of ΦBp. In addition, since the concentration of Al in

NiSi is below 0.1 atomic percent (as discussed before), the bulk properties of NiSi

(and hence its work function) are not expected to change. Thus, it is believed that the

introduction of shallow acceptor-type traps by Al on the Si side of the NiSi/p-Si

48

interface is the most probable reason behind lowering of the effective ΦBp of NiSi on

p-Si.

D. Optimization of Metal Silicidation Conditions for p-FinFET Integration

As seen in Fig. 3.5, the lowest ΦBp (at the NiSi/p-Si interface) achieved in this

work is at a silicidation condition wherein 10 nm of Ni is used for NiSi formation

coupled with an Al implant at dose of 2×1014 atoms/cm2 (with implantation energy at

10 keV). Silicidation anneal is at 500 °C for 30 s. With this baseline, further

optimization is carried out to achieve even lower ΦBp (if possible) without any

degradation in the bulk electrical properties of the silicide film, for integration in p-

FinFETs.

Figure 3.6(a) shows the I-V characteristics of the fabricated NiSi/p-Si

junctions with an Al implant dose ≥ 2×1014 atoms/cm2. As is seen in Fig. 3.3(a), the

reverse current increases sharply (with respect to the control sample without Al) with

an Al implant dose of 2×1014 atoms/cm2 and the I-V characteristics tend towards that

of an ohmic contact. With a higher implant dose of 1×1015 or 2×1015 atoms/cm2, the

reverse current remains at approximately the same value. The effective ΦBp for NiSi

on p-Si drops from ~0.4 eV for the control device to an extremely low value of ~0.12

eV for the device with an Al implant dose of 2×1014 atoms/cm2, and then saturates at

approximately the same value (0.14 eV) for junctions with higher Al implant dose [as

shown in the right inset of Fig. 3.6(a)]. Thus, no further lowering of ΦBp is achieved,

below 0.12 eV, by any increase in Al implant dose (beyond 2×1014 atoms/cm2).

Again, the activation energy method using low temperature I-V characterization is

49

-2 0 210-1

100

101

0.0

0.2

0.4

20

Dose (1014 Al/cm2)

B

p (

eV)

0 102

p-SiNiSi

V, IS

iO2

SiO

2

(a)

21015

0 21014

11015

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 )

Al Dose(atoms/cm2)

30 35 40 45 50 55

0

4

8

12

2010Dose (1014 Al/cm2

)

RS (

/sq

)

2

0

37%

10%

In

ten

sity

(a.

u.)

2 Theta (degree)N

iSi(

011)

NiS

i(11

1)

NiS

i(11

2)

NiS

i(21

1)N

iSi(

103)

NiS

i(02

0)

21014Al/cm2

No Al

(b)

Fig. 3.6 (a) I-V characteristics of NiSi/p-Si contact junctions with Al implant at a dose in

the range of 2×1014 - 2×1015 atoms/cm2. Control device without any al implant is also shown

for comparison. NiSi is formed from 10 nm of Ni for all the contact devices. Inset on the left

shows the schematic of the fabricated junctions. Inset on the right shows the extracted ΦBp

values for all the NiSi/p-Si junctions, with and without Al implant. (b) XRD theta/2theta

(θ/2θ) phase analysis of blanket NiSi film on p-Si substrate, with and without Al implant dose

of 2×1014 atoms/cm2. Inset shows the sheet resistance RS of the blanket NiSi films on p-Si

substrate, with Al implant dose in the range of 0 - 2×1015 atoms/cm2.

used to extract the effective ΦBp for the two NiSi/p-Si contact junctions with Al

implant dose higher than 2×1014 atoms/cm2 [3.11]. Appendix B can be referred for

more details regarding the activation energy method. Fig. 3.6(b) shows the x-ray

diffraction (XRD) phase analysis of blanket NiSi film with and without Al implant

dose of 2×1014 atoms/cm2. Both films show the same orientation peaks, all

corresponding to the low resistivity nickel mono-silicide phase only. Thus, coupled

with the zero sheet resistance (RS) degradation of the NiSi film with the low dose Al

50

implant of 2×1014 atoms/cm2 [shown in the inset of Fig. 3.6(b)], this particular dose is

used for integration in p-channel FinFETs with p+-Si S/D. For higher Al implant dose

of 1×1015 and 2×1015 atoms/cm2, RS degrades by 10 and 37 %, respectively [inset of

Fig. 3.6(b)]. TOF-SIMS is also used to extract the Al depth profile in all the

fabricated NiSi/p-Si contact junctions. Clear evidence of Al segregating at the

NiSi/p-Si interface is observed (Fig. 3.7).

It should be noted here that the Al implant and segregation technique has

inherent advantages over heavily doped junctions for RC reduction in MOSFETs, in

terms of higher impurity concentration at the NiSi/(heavily-doped Si S/D) interface,

that is not limited by bulk solid solubility of the impurity in Si and has less stringent

constraints on lateral impurity (or dopant) profiling [3.10], [3.19].

21014Al/cm2 11015Al/cm2

21015Al/cm2

0 20 40 60 80 100 120100

101

102

103

104

SiO

2

SiO

2

p-Si

NiSi

Al

Interfacial RegionNiSi

Inte

nsi

ty o

f A

l (co

un

ts)

Depth (nm)

p-Si

Fig. 3.7 TOF-SIMS depth profile of Al in NiSi/p-Si contact devices with Al implant at a

dose in the range of 2×1014 atoms/cm2 - 2×1015 atoms/cm2, and using NiSi formed from 10

nm of Ni. Inset shows the schematic diagram of the contact devices with negatively-charged

acceptor-type Al atoms segregated near the NiSi/p-Si interface.

51

3.2.3.2 Electrical Results: p-FinFET Integration

Figure 3.8 summarizes the key process steps used in this work for the

fabrication of p-channel tri-gate FinFETs. Al implantation at a dose of 2×1014

atoms/cm2 after dopant activation, and its segregation at the NiSi/p+-Si interface in the

S/D of FinFET are explicitly shown. The control devices did not go through Al

implant. Cross-sectional TEM image of one of the fabricated p-FinFETs is shown in

Fig. 3.9. Al implant does not degrade the NiSi film morphology, as shown by the

uniform thickness of the contact film on S/D. The top-view SEM image of the same

device is also shown in the inset.

Channel implantFin definitionSiO2 gate oxidationPoly gate definitionSDE implantSpacer formation with stringer removalS/D implant and activation2×1014 atoms-cm-2 Al implant at 10 KeV10 nm Ni depositionSilicidation at 500 °CSelective Metal Etch

Gate

BOX

Si Fin

NiSi

Al

Segregated Al

Fig. 3.8 Schematic on the left shows the process flow to fabricate p-channel FinFETs.

Schematic on the top-right shows the device structure after spacer etch and deep S/D implant

and activation, and undergoing Al implant. The gate also received the Al implant since the

hard mask on it is removed before the deep S/D implant step. The schematic on the bottom-

right shows the final device structure after nickel silicidation. The Al segregated NiSi/p+-Si

interfacial region are denoted with negative charge due to the filled acceptor-type traps

introduced by Al near the Si valence band.

52

BOX

Si

Gate

Si S/D

NiSi with Al Segregated Interface

Si S/D

LG= 170 nm

A

A'

S/D

S/DGate

A

A'

S/D

S/DGate

A'

S/D

S/DGate

Fig. 3.9 Cross-sectional TEM of a complete p-FinFET with 170 nm LG, after Al implant

and Ni silicidation. FIB cut along A-A' (shown in the tilt-SEM in the inset of the figure)

overestimates the LG.

Figure 3.10(a) shows the IDS-VDS characteristics of a pair of p-channel

FinFETs with and without Al implant. The two devices have gate length (LG) of 165

nm and WFin of 55 nm. The channel width is defined as 2×HFin + WFin. At a fixed

gate overdrive of 1.2 V, ~20 % enhancement in drive current IDSAT is observed at VDS

= -1.2 V with Al implant. The IDS-VGS characteristics in Fig. 3.10(b) for the same pair

of devices show that they have comparable short channel effects (SCE) with drain-

induced barrier lowering (DIBL) of ~35 mV/V, subthreshold swing SS of ~0.12

V/decade, and saturation threshold voltage (VT) of ~ -0.4 V. The IDSAT/IOFF ratios of

~106 are also comparable, with no degradation of OFF-state leakage current. Thus,

the effective channel length for these two devices is comparable. The enhancement in

drive current is attributed to the reduction in series resistance RSD due to Al segregated

NiSi/p+-Si interfacial region in the S/D of p-channel FinFET, as shown in Fig. 3.10(b).

53

-1.2 -0.8 -0.4 0.0

0

50

100

150

200

250

300

Si S/D

VGS - VT= 0.2 V

Drain Voltage VDS (V)

Dra

in C

urr

ent I

DS

(A

/m

)

21014Al/cm2

20%

No Al

VGS - VT = -1.2 V

(a)

-3 -2 -1 010-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

0

4

8

Gate Voltage VGS (V)

Dra

in C

urr

ent I

DS

(A

/m

)

21014 Al/cm2

No Al

VDS = -1.2 VVDS = -0.05 V

RSDCtrl:RSD

Al = 1.19

(b)R

Total =

50 mV

/IDS

,lin (km

)

Fig. 3.10 (a) IDS-VDS characteristics of a pair of FinFETs with LG = 165 nm and fin width

WFin = 55 nm, with and without Al implant at dose of 2×1014 atoms/cm2. (b) Y-axis on the left

shows the IDS-VGS characteristics of the same pair of FinFETs. Y-axis on the right plots the

graph of RTotal versus VGS for the same pair of devices. RTotal = |VDS|/IDS,lin, where VDS = -50

mV and IDS,lin is the linear drain region. Solid lines show the first order exponential fit used to

extract RSD at VGS = -10 V.

RSD is calculated from the asymptotic behavior of the total series resistance

(RTotal = RCH + RSD) versus VGS plot using a first order exponential fit, where RCH is the

channel resistance [3.7]. At high VGS, RTotal ≈ RSD ≈ 1903 Ω-μm for the control

FinFET (RSDCtrl) and 1604 Ω-μm for the FinFET with Al segregated NiSi/p+-Si

junction (RSDAl). Thus, there is an RSD

Ctrl : RSDAl ratio of ~1.19 or drop in RSD of ~16

% (calculated with respect to RSDCtrl). As discussed earlier in section 3.2.1, RC at the

interface between NiSi and p+-Si S/D region is a major component of RSD in FinFETs.

Equations (1.6) – (1.9) show the dependency of RC on Schottky barrier height. Thus,

the ~16 % drop in RSD is attributed to the lowering of effective hole barrier height of

54

NiSi on p+-Si S/D through Al segregation. Accordingly, in this bias regime,

IDSAl/IDS

Ctrl ≈ RSDCtrl/RSD

Al, where IDSCtrl and IDS

Al are the drive currents for the control

and Al segregated FinFETs, respectively [3.8]. These results are in agreement with

the almost 1:1 correspondence between drive current enhancement (IDSAl/IDS

Ctrl) and

RSD enhancement factor (RSDCtrl/RSD

Al), as expected due to the dominance of RSD on

the performance of narrow width devices such as FinFETs [3.7].

On average, the IDSAT enhancement obtained with Al implant at an IOFF of 100

nA/μm is 15 %, as shown in Fig. 3.11. A set of 30-40 devices have been used for this

plot, both for devices with and without the Al implant. Devices with shorter LG show

higher drive current enhancement with Al implant, albeit at a higher IOFF. Device

performance compared at a fixed drain induced barrier lowering (DIBL) of 100 mV/V

show IDSAT enhancement of 14 % with Al implant [Fig. 3.12(a)]. Devices with shorter

LG have higher DIBL, higher IDSAT and higher IDSAT enhancement with Al implant.

Similarly, when IDSAT is compared at a fixed subthreshold swing SS of 120 mV/dec,

the enhancement is extracted to be ~13 % with Al implant [Fig. 3.12(b)].

0 100 200 300 400 50010-10

10-9

10-8

10-7

10-6

10-5

I OF

F @

VG

S =

0 V

(A

/m

)

IDSAT

@ VGS

= -1.2 V (A/m)

15 %

VDS

= -1.2 V

Al Implant Best Fit of Al Implant No Al - RefBest Fit of Ref Data

Fig. 3.11 Plot of ON current (IDSAT) versus OFF current (IOFF), both for devices with and

without Al implant. IDSAT and IOFF are extracted at gate voltage VGS of -1.2 V and 0 V,

respectively.

55

0 100 200 300 400

50

100

150

200

250

300

350 VDS

= -1.2 V

DIBL (mV/V)I DS

AT @

VG

S -

VT =

-1.

2 V

(A

/m

)

14 % Al Implant Best Fit of Al Implant No Al - RefBest Fit of Ref Data

(a)

80 120 160 200

50

100

150

200

250

300

350 (b)

I DS

AT @

VG

S -

VT =

-1.

2 V

(A

/m

)

VDS

= -1.2 V

Subthreshold Swing SS (mV/decade)

13 % Al Implant Best Fit of Al Implant No Al - RefBest Fit of Ref Data

Fig. 3.12 (a) Plot of drive current IDSAT versus drain induced barrier lowering (DIBL), both

for devices with and without Al implant. IDSAT is extracted at gate overdrive (VGS–VT) of -1.2

V. (b) Plot of drive current IDSAT versus subthreshold swing SS, both for devices with and

without Al implant. IDSAT is extracted at gate overdrive (VGS–VT) of -1.2 V.

Figure 3.13 shows the statistical plot of drive current at a fixed gate overdrive

of -1.2 V and VDS = -1.2 V for two sets of p-channel FinFET devices with and without

Al implant, for a range of LG varying from 165 nm to 1 μm. Every data point is an

56

0.1 1

0

50

100

150

200

250

0

10

20

30

40

VDS

= -1.2 V

I DS

AT @

VG

S -

VT =

-1.

2 V

(A

/m

)

I DS

AT E

nh

ance

men

t (

)

Gate Length LG (m)

Al Implant

No Al - Ref

Linear Fit of IDSAT

Enhancement

Fig. 3.13 Y-axis on the left shows the plot of mean IDSAT versus LG, for devices with and

without Al implant. Y-axis on the right shows the plot of enhancement in IDSAT (with Al

implant against control devices) versus LG.

average of approximately 5 devices. As expected, IDSAT increases with reduction in

gate length, both for devices with and without Al implant. Mean IDSAT enhancement

with LG scaling reaches ~20 % at a LG of 170 nm. The average saturation threshold

voltage VT, VT roll-off, DIBL and SS in these devices do not show any appreciable

shift with the Al implant (Fig. 3.14) and the small differences are only due to errors

introduced by statistical process variation in the device fabrication.

This increase in drive current, as evident from Fig. 3.10 – Fig. 3.13 is credited

to the lowering of parasitic series resistance from 931 Ω-μm to 814 Ω-μm with Al

implant, yielding a drop of 13 % (Fig. 3.15). This drop in RSD is in turn is attributed

to the lowering of effective hole barrier height of NiSi on p+-Si S/D through Al

segregation.

57

0.1 10.0

-0.2

-0.4

-0.6

-0.8

-1.0

0.1 10

100

LG (m)

SS

(mV

/dec

ade)

0.1 1

0

100

DIB

L (

mV

/V)

LG (m)

Mean of Al Implant Data Mean of Ref Data

Al Implant No Al - Ref

T

hre

shol

d V

olta

ge V

T (

V)

Gate Length LG (m)

Fig. 3.14 p-FinFETs with and without Al implant have comparable short channel effects,

e.g. similar VT, VT roll-off, DIBL (inset at top-left) and SS (inset at top-right).

0.0 0.2 0.4 0.6 0.8 1.0 1.2

2000

4000

6000

8000

10000

R

Tot

al (

m)

Gate Length LG (m)

13 %

Al Implant Linear Fit of Al Implant DataNo Al - RefLinear Fit of Ref Data

Fig. 3.15 The parasitic series resistance RSD extracted at zero gate length shows a drop of

13 % for p-FinFETs with Al implant (over the control FinFETs).

58

3.2.4 Summary and Conclusion

In this work detailed material study has been presented to lower the hole

Schottky barrier height ΦBp at the NiSi/p-Si junction by using Al implant and

segregation. An extremely low ΦBp of 0.12 eV has been achieved at a low Al implant

dose of 2×1014 atoms/cm2 with NiSi formed from 10 nm of Ni. The metal silicidation

conditions have been optimized for p-FinFET integration and detailed TOF-SIMS

data has been shown to understand the mechanism behind lowering of the barrier

height.

Furthermore, when this Al implant technology is integrated into the S/D

region of tri-gate FinFETs, ~15 % enhancement in drive current is achieved without

any degradation of short channel effects. This is attributed to the lowering of ΦBp of

NiSi on p-Si from 0.4 eV to 0.12 eV with Al implant, leading to a lowering of contact

resistance RC at NiSi/p+-Si S/D contact junction.

3.3 Si:C Bandgap Engineering for Electron Schottky Barrier

Tuning

3.3.1 Motivation

Schottky metal-silicide S/D junctions have been proposed for the continuous

scaling of silicon devices [3.20], [3.21]. They replace the ion-implanted S/D in

conventional MOSFETs and hence, alleviate the need for high temperature dopant

activation. Moreover, the parasitic S/D series resistance RSD is lowered and abrupt

silicide/silicon interfaces are formed leading to much improved device scalability.

For p-channel Schottky S/D transistors (p-SSDT), platinum silicide is widely regarded

as the S/D material of choice with a hole Schottky barrier height ΦBp of ~0.21 – 0.26

59

eV [3.9], [3.21]. For n-channel SSDT (n-SSDT), rare earth (RE) silicides, e.g.,

erbium silicide (ErSi2-y) and ytterbium silicide (YbSi2-y) have been proposed and have

achieved the lowest Schottky barrier height to electron conduction ΦBn of ~0.27 –

0.38 eV [3.9], [3.22], [3.23]. A simulation study has suggested that a finite positive

barrier of 60 – 100 meV is needed for the SSDT technology to be competitive against

conventional doped S/D MOSFETs [3.24]. Currently, in particular for n-SSDT, with

the wide range of metal-silicides already investigated for the S/D junctions, a

roadblock exists in further lowering the barrier height, with the exception of hybrid

Schottky-like devices which utilize an interfacial doping layer between the metal S/D

and channel region [3.25], [3.26].

Silicon-carbon (Si1-xCx or Si:C) with carbon mole fraction, x ≤ 0.013 has been

proposed as a possible S/D material for the drive current enhancement that it brings

about in n-MOSFET via channel strain engineering [3.27]-[3.33]. Lattice constant of

relaxed Si1-xCx is lower than that of Si and hence, Si1-xCx pseudomorphically grown on

Si is under lateral tensile strain and vertical compressive strain. Strain can reduce the

barrier height at a silicide/strained Si junction by energy-band splitting [3.34]. Hence,

incorporating metal-silicide contacts on Si1-xCx S/D could help fabricate high

performance Schottky S/D transistors.

Furthermore, the study of the modulation of ΦBn of NiSi on Si1-xCx is also

beneficial for conventional n-MOSFETs (with ion-implanted S/D), tensile strained

due to epitaxial growth of Si1-xCx on S/D regions, where low electron barrier at the

silicide/(n+-S/D region) is desirable for reduction of contact resistance [3.8].

In this work, the possibility of tuning the ΦBn of nickel silicide (NiSi) on Si1-

xCx by varying the carbon mole fraction has been investigated. NiSi has a reported

ΦBn of 0.67 eV to n-Si and it has been used in this work to demonstrate ΦB

n lowering

60

via Si1-xCx bandgap engineering [3.35]. By incorporating 0.4 % carbon, it has been

shown that ~27 meV drop in ΦBn can be achieved and with extrapolation to 1.3 %

carbon, the lowering of ΦBn is expected to be more than 85 meV. Thus, an alternative

approach to reduce ΦBn for n-SSDTs and conventional n-MOSFETs (with doped S/D)

has been demonstrated.


For the experiments, 100 nm of undoped Si1-xCx (x < 0.01) was epitaxially

grown on n-type Si (100) wafer (1-10 Ω cm) by low pressure chemical vapor

deposition (LPCVD). Methylsilane (SiH3CH3) flow rate was varied during the

process to grow wafers with 0.15 %, 0.28 % and 0.4 % carbon concentration epilayers.

An n-type Si (100) wafer (1-10 Ω cm) was used as the 0 % carbon control sample.

After a standard RCA clean and DHF dip to remove native oxide, 20 nm of nickel

was deposited using an e-beam evaporator. Silicidation was performed at 300 ˚C –

800 ˚C in steps of 100˚C for 1 minute in N2 ambient using rapid thermal annealing

(RTA). The unreacted nickel was selectively etched away using SPM solution (4:1

mixture of sulfuric acid and hydrogen peroxide) at 120 ˚C. Blanket films were used

for x-ray diffraction (XRD) and sheet resistance (RS) analysis. To prepare contact

junctions for current-voltage (I-V) characterization, the nickel silicide film was

patterned using standard photo-lithography and silicon isotropic etchant [3.36].

Junction areas of 2 × 104 µm2 were fabricated. 300 nm of aluminum was deposited on

the backside of the wafer to provide an ohmic contact.

61


Omega/2 theta (ω/2θ) high-resolution x-ray diffraction (HRXRD) rocking

curve (not shown) data were fitted using a nonlinear relationship to quantify the

carbon content in the Si1-xCx epilayer [3.37]. The sheet resistance of nickel silicide-

carbon (NiSi1-xCx or NiSi:C) blanket films on 0 % and 0.4 % carbon Si1-xCx epilayers

is plotted in Fig. 3.16(a) as a function of RTA temperature. The incorporation of

carbon widens the process window for the low resistivity NiSi phase (from 400 ˚C –

700 ˚C for 0 % carbon to 400 ˚C – 750 ˚C for 0.4 % carbon), as shown in Fig. 3.16(a)

and hence, enhances the thermal stability of the film. At 500 ˚C, RS of NiSi is 3.5

Ω/sq and NiSi1-xCx is 4.1 Ω/sq. There is a 17 % increase in RS which is consistent

300 400 500 600 700 8001

10

100 Ni2Si NiSi2

Sh

eet

Res

ista

nce

(oh

m/s

q)

Annealing Temperature ( C)

[C] = 0.4% [C] = 0%

NiSi

(a)

20 30 40 50 60

[C] = 0%

[C] = 0.4%

NiS

i (01

3)N

iSi (

103)

NiS

i (21

1)N

iSi (

112)

NiS

i (11

1)

NiS

i (10

1)

NiS

i (00

2)

Inte

nsi

ty (

a.u

.)

2 Theta (degree)

(b)

Fig. 3.16 (a) Variation of sheet resistance (RS) with annealing temperature for nickel

silicide film on n-Si and Si0.996C0.004. Silicidation is done using RTA for 1 minute in N2

ambient at the specified temperature. (b) XRD θ/2θ phase analysis of NiSi on n-Si and

Si0.996C0.004. Silicidation is done using RTA at 500 ˚C for 1 minute in N2 ambient.

62

with recent studies and is attributed to the incorporation of carbon in the NiSi film

[3.38], [3.39]. Since carbon in insoluble in NiSi, it is postulated to segregate at the

silicide grain boundaries and NiSi1-xCx/Si1-xCx interface where it passivates the

dangling bonds by forming strong directional covalent bonds [3.39]. This lowers the

grain boundary energy and interface energy of the silicide film, enhancing its thermal

and morphological stability. Silicide film agglomeration and NiSi-to-NiSi2 phase

transformation are responsible for increase in resistivity of the silicide film, at high

temperatures beyond the low resistivity NiSi phase window [3.38]. These

phenomenons are pushed by ~50 °C to ~750 °C for NiSi1-xCx films (as compared to

~700 °C for NiSi films) due to its higher thermal stability [Fig. 3.16(a)].

Figure 3.16(b) details the theta/2 theta (θ/2θ) XRD scan of NiSi1-xCx films on 0

% and 0.4 % carbon Si1-xCx epilayers, formed by RTA at 500˚C for 1 minute in N2

ambient. For both of the films, all peaks correspond to nickel monosilicide (NiSi)

phase only which implies the absence of high resistance Ni2Si and NiSi2 components,

despite the presence of 0.4 % carbon. From the low resistivity NiSi process window

(Fig. 3.16(a)), 500˚C has been chosen as the RTA temperature (with a trade-off

between the lowest possible RTA temperature and RS) for the I-V characterization of

contact junctions.

The Thermionic emission (TE) model is used to extract ΦBn from the

experimental I-V data in Fig. 3.17, given by [3.40]

S

( )exp 1 exp

q V IR q V IRI I

nkT kT

, (3.1)

* 2n

BS

lnkT AA T

q I

, (3.2)

where IS is the reverse saturation current, q is the electronic charge, R is the device

series resistance, n is the ideality factor, k is Boltzmann constant, T is the temperature

63

-1 0 110-5

10-4

10-3

10-2

10-1

100

101

n-Si

V, I

Si:C

NiSi:C

Cu

rren

t D

ensi

ty (

A/c

m2 )

Voltage (V)

Carbon Content [%] 0.00 0.15 0.28 0.40

Increase of carbon content

Fig. 3.17 Current-Voltage (I-V) characteristics of NiSi on Si1-xCx with x = 0, x = 0.0015, x =

0.0028 and x = 0.0040. Silicidation is done using RTA at 500 ˚C for 1 minute in N2 ambient.

Inset shows the schematic of the fabricated contact device.

in Kelvin, A is the diode area, A* is the Richardson constant (112 A/cm2K2 for n-type

Si) and ΦBn is the Schottky barrier height from I-V measurement. R is neglected by

fitting the curves in the low forward bias range (V < 0.2 V). Equation (3.1) and

Equation (3.2) are essentially same as Equation (2.1) and Equation (2.2), but have

been reproduced here for clarity. I-V data for all the four samples (NiSi on 0 %, 0.15

%, 0.28 % and 0.4 % carbon concentration Si1-xCx) follow the TE model, with n < 1.1,

showing that the current is dominated by the diffusion mechanism (and not

generation-recombination), thus indicating quality junctions. The increase in reverse

current with carbon concentration clearly shows the drop in ΦBn.

Figure 3.18(a) plots ΦBn of NiSi1-xCx with percentage carbon concentration. It

can be seen that ΦBn decreases with increasing carbon concentration with the data

fitting a linear trend extrapolated till 1.3 % carbon concentration. This can be

64

explained by the interface dipole theory for metal-semiconductor contacts, given by

[3.41]

nB M,eff S , (3.3)

where ΦM,eff is the effective metal (or metal-silicide) work function (which differs

from the ideal work function due to Fermi level pinning at the metal-semiconductor

interface), S is the electron affinity of semiconductor, and ΦBn is the electron

Schottky barrier height of metal (or metal-silicide) to n-type semiconductor. It has

been shown by Chang et al. that the energy of the conduction band edge of strained

Si1-xCx, grown epitaxially on Si (100) substrate, drops with carbon concentration

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.0 0.1 0.2

0.65

0.66

0.67

0.68

xx (%)

B

n (

eV)

(a)

Ele

ctro

n B

arri

er H

eigh

t (e

V)

Carbon Concentration (%)

0.595 eV

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.18

0.19

0.20

0.21

0.22

0.23

0.24

0.25

0.26

0.27 YbSi2-yBn n-Si

0.184 eVEle

ctro

n B

arri

er H

eigh

t (e

V)

Carbon Concentration (%)

(b)

Fig. 3.18 (a) Experimental variation of ΦBn of NiSi with percentage carbon concentration

and extrapolation of the linear fit to x = 0.013. Error bar at each data point corresponds to the

statistical variation in ΦBn about its mean value. Inset shows the drop in ΦB

n with in-plane

tensile strain (εxx). (b) Projected linear variation of ΦBn of YbSi2-y with percentage carbon

concentration. The slope of the dashed line is the same as that for the linear fit in Fig. 3.18(a).

65

[3.42]. The strain causes an energy split between the ΔXY valley and ΔZ valley

(conduction band valley perpendicular to the epilayer growth direction and along it,

respectively). With increasing carbon concentration, ΔXY valley remains at almost the

same position as in the bulk Si but the energy of ΔZ valley drops linearly (at a rate of

~6.5 meV/ (0.1 % carbon) up to 2 % carbon), leading to an equivalent increment in

S . Thus, the ΦBn reduces linearly from Equation (3.3), assuming that ΦM,eff is

constant (i.e., the silicide Fermi level is pinned at a fixed value) with increasing

carbon incorporation. From Fig. 3.18(a), with 0.4 % carbon incorporation, there is

~27 meV drop in ΦBn at a rate of ~6.6 meV/ (0.1 % carbon). ΦB

n extracted via Norde

function (not shown) also drops at the same rate, which is approximately equal to the

rate of decrease in the energy of ΔZ valley of strained Si1-xCx shown by Chang et al.

Norde function is a modified form of the TE model itself [3.40]. This further justifies

the extrapolation of the linear fit to reach 1.3 % carbon concentration (one of the

reported incorporations of carbon in Si1-xCx S/D n-MOSFETs [3.27]) in Fig. 3.18(a),

which leads to a drop in ΦBn of more than 85 meV. Higher substitutional carbon

incorporation in Si1-xCx leads to higher in-plane tensile strain (εxx), and hence the inset

in Fig. 3.18(a) shows the drop in ΦBn with εxx for the 0 %, 0.15 %, 0.28 % and 0.4 %

carbon incorporated samples. εxx is calculated using Kelires’s relation, given by [3.37]

2rel Si 2.439 0.5705a a x x , and (3.4)

Si relxx

rel

( )( )

( )

a a xx

a x

, (3.5)

where arel is relaxed lattice parameter of Si1-xCx, aSi is the lattice parameter of Si (aSi =

5.431 A°), and x is the mole fraction of carbon in Si1-xCx.

Current lowest ΦBn for n-SSDTs is around 0.27 eV for YbSi2-y [3.23]. Thus,

Fig. 3.18(a) has been re-plotted in Fig. 3.18(b) (with 0.27 eV being the ΦBn at 0 %

66

carbon) to give the projected ΦBn for YbSi2-y on Si1-xCx (assuming that ΦM,eff remains

constant with carbon incorporation for the YbSi2-y/ Si1-xCx interface as-well). This

indicates the possibility of engineering an n-SSDT with ΦBn < 0.2 eV (using 1.3 %

carbon Si1-xCx), which is even lower than that of the best case p-SSDT value (with

PtSi) of ~0.22 eV [3.9]. Recently, incorporation of ~2 % carbon in Si1-xCx has been

demonstrated [3.43], [3.44]. With Si0.98C0.02, ~130 meV drop in ΦBn is expected.


This work reports the demonstration of the tuning of ΦBn of NiSi on n-Si using

Si1-xCx bandgap engineering. Increase in carbon content in Si1-xCx leads to ΦBn

reduction at a rate of ~6.6 meV/(0.1 % carbon) due to reduction in the bandgap of Si1-

xCx at a rate of ~6.5 meV/(0.1 % carbon). The study is impactful for both, n-SSDTs

as well as conventional n-MOSFETs (with ion-implanted S/D). Presence of carbon in

the NiSi film increases its thermal stability without any adverse impact on the low

resistivity phase of the thin film.

67

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72

CHAPTER 4

Aluminum Implant Technology for Contact Resistance

Reduction in Strained p-FinFETs with SiGe Source/Drain

4.1 Introduction and Motivation

Multiple-gate field-effect transistors or FinFETs have better control of short-

channel effects (SCE) than planar bulk MOSFETs and ultra-thin body MOSFETs,

thus allowing gate length scaling into the sub-10 nm regime, and could be potentially

adopted in sub-22 nm technology generations [4.1]-[4.13]. By using a low channel

doping concentration, FinFETs suffer less from mobility degradation due to impurity

scattering and variability in device characteristics due to random dopant fluctuation.

Nevertheless, there are challenges associated with the adoption of FinFET or

multiple-gate field-effect transistors for manufacturing. A prominent issue is the high

source/drain (S/D) parasitic series resistance (RSD), wherein the contact resistance (RC)

at the silicide/(heavily-doped S/D) interface is a major contributor to RSD [4.14]. RC is

inversely proportional to the fin width WFIN and increases with device scaling, posing

a bottleneck for the achievement of high drive current in aggressively scaled FinFETs.

RC is an exponential function of the Schottky barrier height (ΦB) at the

silicide/(heavily-doped S/D) interface (Equation 1.9) [4.15]. Hence, various

techniques to reduce ΦB have been proposed and integrated in n-FETs, e.g., novel

silicides (such as nickel-aluminide silicide and nickel-dysprosium silicide), dopant

segregation Schottky (DSS) involving arsenic implant, and sulfur and selenium

73

segregation [4.16]-[4.20]. For p-FETs, DSS contact (involving boron implant) and a

novel silicide (nickel-platinum germano-silicide) contact have been reported [4.21]-

[4.22].

While silicon-germanium (SiGe) S/D stressors and nickel-based germano-

silicide S/D contacts are an integral part of the p-FETs in mainstream CMOS

technology, the Schottky barrier height for holes ΦBp at the germano-silicide/SiGe

interface is still above 0.2 eV. With a need to achieve below 1×10-7 Ω-cm2 contact

resistivity values, extremely low ΦBp values are needed [4.1].

In section 3.2 (chapter 3), the modulation of the effective ΦBp of nickel silicide

(NiSi) on p-Si using aluminum (Al) segregation at the NiSi/p-Si interface is shown to

achieve an extremely low ΦBp value of 0.12 eV. In this work, it is demonstrated that

through Al ion-implantation, and its segregation after metal deposition and

silicidation, the effective ΦBp of nickel germano-silicide (NiSiGe) on SiGe can also be

tuned. One of the lowest reported effective ΦBp on SiGe of 0.068 eV is achieved,

which is extremely promising for application in strained p-MOSFETs with SiGe S/D.

A possible theoretical model explaining the ΦBp modulation is discussed in this work.

Moreover, the effect of the thickness of NiSiGe on the effective ΦBp modulation at the

NiSiGe/SiGe interface is also presented. The Al ion implant into SiGe leads to

amorphization of its top layer and its impact on transistor integration issues is

elucidated.

Furthermore, the integration of the novel Al implant and segregation

technology at the NiSiGe/p+-SiGe S/D contact interface is demonstrated in strained p-

channel FinFETs with SiGe S/D. Detailed device characterization results are

discussed which show RC and RSD reduction due to the Al implant, contributing to

drive current enhancement.

74

4.2 Device Fabrication

A. Fabrication of NiSiGe/SiGe Contact Junctions

200-mm p-type Si (100) wafers (4-8 Ω cm) were used as the starting substrate

in the experiments. 150 nm of SiO2 was grown on the wafers by wet oxidation. The

oxide was patterned using standard lithography and dry etching to define active areas.

100 nm of undoped SiGe was grown epitaxially using ultra-high-vacuum chemical

vapor deposition (UHVCVD), selectively in the oxide windows. Omega/2theta (ω/2θ)

high-resolution x-ray diffraction (HRXRD) rocking curve (shown in Fig. 4.1) was

used to quantify the Germanium content (~26 %) in the SiGe epilayer. Al ions were

then implanted at energy of 10 keV. Three different implant dose values, namely

2×1014, 1×1015 and 2×1015 atoms-cm-2, were used to fabricate the three device splits.

After standard substrate cleaning using hydrofluoric acid (HF) solution, 10 nm of

nickel (Ni) was immediately deposited using an e-beam evaporator. NiSiGe was

formed using rapid thermal annealing (RTA) at 400˚C for 30 s in N2 ambient.

33.5 34.0 34.5 35.0

100

101

102

103

104

105

Si0.74Ge0.26 Epi-layer Peak

Inte

nsi

ty (

cps)

omega/2 theta (degree)

Si Substrate Peak

Fig. 4.1 HRXRD rocking curve of a p-Si (100) wafer with SiGe epilayer. The Ge

concentration in SiGe and the epilayer thickness are extracted to be ~26 % and 100 nm,

respectively.

75

p-SiSiO2

Al+ Implant

V, I

SiGe

NiSiGe

Segregated Al

(a) (b)

Fig. 4.2 (a) Schematic showing the NiSiGe/SiGe device structure just after the SiGe

epilayer growth and undergoing Al implant. (b) Schematic showing the final NiSiGe/SiGe

device structure with Al implant, which is used for I-V characterization. The Al atoms have

been shown to have segregated near the NiSiGe/SiGe interface.

The unreacted Ni was selectively etched away using 4:1 mixture of sulfuric acid and

hydrogen peroxide (SPM) at 120 °C. The fabricated metal-semiconductor junctions

are square-shaped with an area of 85×85 µm2. Finally, 200 nm of Al was deposited

on the backside of the wafer to provide an ohmic contact. Figure 4.2 shows the

schematic of the contact junction during the fabrication process. One p-Si wafer with

the SiGe epilayer that did not go through any Al ion-implantation was used as the

control sample. Blanket NiSiGe films were also prepared on SiGe epilayer grown on

unpatterned p-Si substrate, with and without Al implant, for sheet resistance (RS)

measurement and XRD phase analysis.

B. Fabrication of Strained p-Channel FinFETs

200-mm silicon-on-insulator (SOI) substrates with 70 nm thick (001) silicon

(Si) and 140 nm thick buried silicon oxide (BOX) were used as starting substrates.

Figure 4.3(a) shows the key steps used for fabricating tri-gate p-channel FinFETs with

76

Al segregated NiSiGe/p+-SiGe S/D. The channel orientation, i.e., source-to-drain

direction, is <110>. The Si layer was first thinned down to 40 nm using dry oxidation

followed by dilute HF etch. Threshold voltage adjust implant was performed on all

wafers using Phosphorus (P) ion-implantation at an energy of 22 keV and a dose of

4×1013 atoms/cm2 through 10 nm of sacrificial silicon dioxide (SiO2) layer, which was

deposited using plasma-enhanced chemical vapour deposition (PECVD). Activation

of phosphorus dopants was performed using a 1000 °C, 60 s anneal. A 70 nm thick

PECVD SiO2 hardmask was deposited on the wafers. Using 248 nm lithography,

photoresist lines down to a width of ~170 nm were defined on the hardmask. Resist

trimming using N2-O2 plasma further reduced the photoresist linewidth to ~90 nm.

The photoresist pattern was transferred to the underlying PECVD SiO2 using reactive

ion etching (RIE). After resist removal, isotropic wet etch using diluted hydrofluoric

acid (DHF) was utilized to trim the linewidth of the PECVD SiO2 pattern down to ~50

nm. Finally, the SiO2 hardmask pattern was transferred to the underlying Si active

layer by mesa etching using a highly selective RIE process involving HBr-Cl2-He-O2

plasma. Si fins having a fin height HFin of ~40 nm and fin width WFin of ~50 nm were

thus formed.

After removal of the hard mask on the fins, a 3 nm thick SiO2 gate dielectric

was thermally grown, followed by deposition of a 80 nm thick poly-crystalline Si

(poly-Si) electrode material using low pressure chemical vapour deposition (LPCVD).

This was followed by deposition of sacrificial PECVD SiO2 with a thickness of 10 nm.

Gate pre-doping was done through the PEVCD SiO2 layer using BF2 at energy of 10

keV and a dose of 2.5×1014 atoms/cm2. The implant was performed at a 45° angle to

the normal of the wafers with 8 rotations to ensure that the entire volume of the gate

material gets implanted, considering the three-dimensional topography of the poly-Si

77

layer enveloping the Si fin. Similar to the fin definition process, gate length LG down

to 60 nm was defined using 248 nm lithography, resist trimming, and RIE (with 70

nm of PECVD SiO2 as hard mask). The poly-Si gate etch uses a HBr-Cl2-He-O2

plasma, and an optimized over-etching was performed to remove the poly-Si stringers

from the fin sidewalls. The gate hard mask was not removed at this stage.

Fin Definition

Gate Oxidation (3 nm SiO2)

SDE Implant

Si0.74Ge0.26 Epitaxy on S/D

S/D Implant and Activation

Channel Implant

Poly-Si Deposition and Etching

Ni Deposition

(a) Process Flow

Al+ Implant (21014 atoms/cm2)

Selective Ni Etch

(b) Al+ Implant

Si FinSiO2

SiGe S/DPoly-Si

Strain

(c) Ni Deposition

Si FinSiO2

SiGe

Ni

Strain

(d) Silicidation and Ni Removal

SiGe

NiSiGe

Strain

Starting Substrate: 8-inch SOI

Spacer Formation and Stringer Removal

NiSi Segregated Al

NiSiGe Formation and Al Segregation

Fig. 4.3 (a) Process flow used for fabricating strained p-channel tri-gate FinFETs with Al

implant and segregation at the NiSiGe contact. The Al implant step was skipped for control

p-FinFETs. Critical process steps for the formation of Al segregated NiSiGe/p+-SiGe S/D

contact are also schematically illustrated in (b)-(d). After SiGe epitaxial growth to form

raised S/D stressors in strained p-FinFETs, dopant implant and activation were performed,

followed by the first step in the contact formation process: (b) blanket Al implant at a dose of

2×1014 atoms/cm2 and an energy of 10 keV. This was followed by (c) 10 nm nickel

deposition. Finally, (d) germano-silicidation was performed at 400 °C for 30 s, followed by

SPM clean to remove the unreacted nickel. During NiSiGe formation, Al segregates near the

NiSiGe/p+-SiGe interfacial region.

78

After gate definition, source and drain extension (SDE) implant was

performed through a 10 nm thick spacer liner oxide (PECVD SiO2), involving BF2 at

an energy of 15 keV and a dose of 1×1014 atoms/cm2. Silicon nitride (SiN) with a

thickness of 40 nm was then deposited using LPCVD. SiN spacers were formed by

dry etch, and an optimized over-etch step was used to remove the SiN stringers from

the fin sidewalls. This was followed by the selective growth of SiGe epilayer with a

Ge concentration of 26 % and a thickness of 45 nm on the Si S/D regions. Absence of

SiN spacer stringers around the fin enables SiGe to grow on the fin sidewalls for

enhanced coupling of compressive strain to the transistor channel [4.10]. The gate

hard mask was then removed by DHF, followed by deep S/D implant at an energy of

10 keV and a dose of 4×1015 atoms/cm2. Dopant activation anneal was carried out at

1000 °C for 1 s.

After dopant activation, the first step of the contact formation process was

implantation of Al at energy of 10 keV and dose of 2×1014 atoms/cm2 [Fig. 4.3(b)].

All p-FinFETs (except control devices) in this work received the same Al implant

dose of 2×1014 atoms/cm2 (at energy of 10 keV) unless otherwise mentioned. It is this

additional implant step that leads to the lowering of NiSiGe/p+-SiGe S/D contact

resistance. The control wafer did no go through any Al implant. All wafers received

a standard DHF cleaning before deposition of 10 nm of Ni [Fig. 4.3(c)]. The wafers

were thermally annealed at 400 °C for 30 s to form NiSiGe S/D contact (and NiSi gate

contact). The germanosilicide formation process causes segregation of Al at the

NiSiGe/p+-SiGe, as illustrated in Fig. 4.3(d). Unreacted Ni was selectively etched

using 4:1 SPM solution at 120 °C for 90 s. All devices were electrically characterized

at the silicide level.

79

C. Fabrication of p+/n Drain-to-Body Contact Diodes

For fabrication of p+/n contact diodes to emulate the drain-to-substrate

junction in the fabricated p-FinFETs, 200-mm n-type bulk Si (001) wafers (1-10 Ω

cm) were used as starting substrates. These diodes were fabricated to compare the

junction leakage currents with and without Al implant. 200 nm of SiO2 was grown on

the substrate wafer by wet oxidation, and then patterned and dry-etched to define

square shaped active areas having a dimension of 85 µm × 85 µm. Si0.74Ge0.26

epilayer with a thickness of 45 nm was grown in the active areas using UHVCVD.

This was followed by BF2 implantation at energy of 5 keV and dose of 4×1015

atoms/cm2 to form p+ regions. Dopant activation was performed at 1000 °C for 1 s.

In one wafer, Al was then implanted at energy of 10 keV and at a dose of 2×1014

atoms/cm2. The control wafer did not receive any Al implant. After a DHF clean for

native SiO2 removal, 10 nm of Ni was deposited using an e-beam evaporator and a

germano-silicidation anneal was performed at 400 °C for 30 s to form NiSiGe.

Unreacted Ni was removed using SPM to complete the diode fabrication.

4.3 Results and Discussions

4.3.1 Material Characterization

A. Current-Voltage (I-V) Measurements of NiSiGe/SiGe Contact Junctions

Figure 4.4(a) shows the experimental I-V characteristics of the fabricated

NiSiGe/SiGe contact junctions with and without Al implant. With increasing Al

implant dose, the reverse current increases monotonically and the I-V characteristics

approach that of a pure ohmic contact. This shows that the effective ΦBp of NiSiGe

on SiGe has reduced considerably with Al implant, considering the Thermionic

emission (TE) model for metal-semiconductor junctions [Equation (2.1) and

80

-2 -1 0 1 210-4

10-3

10-2

10-1

100

101

102

p-Si

V, I

SiGe

NiSiGe

SiO2

21015Al/cm211015Al/cm221014Al/cm2 No Al

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 )

(a)

Increasing Reverse Current

Temperature Range

for Bp Extraction

3.0 3.5 4.0 4.5 5.0 5.510-11

10-10

10-9

VF = 0.06V

VF = 0.08V

VF = 0.10V

I F /T

2 (A

/K2 )

1000/T (K-1)

(b)

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6

10-2

10-1

100

101

-0.10 -0.08 -0.06

100

101

Cu

rren

t D

ensi

ty(A

/cm

2 )

Voltage (V)

Voltage (V)

Cu

rren

t D

ensi

ty (

A/c

m2 ) 300K

280K260K

240K230K220K210K200K190K180K

Low Forward Bias Range(0.06V < VF < 0.01V)

(c)

Fig. 4.4 (a) I-V characteristics of NiSiGe/SiGe contact junctions, with and without Al ion-

implantation. 10 nm of Ni is germano-silicided using RTA at 400˚C for 30 seconds to form

the NiSiGe contact on SiGe. The inset shows the schematic of the fabricated device used for

I-V characterization. (b) Activation energy measurements to extract the effective ΦBp for

NiSiGe on SiGe. For this device, the SiGe substrate was implanted with Al at a dose of

2×1014 atoms-cm-2. With the y-axis plotted on log-scale, the slope of the linear fit of the curve

(solid line) in the low temperature part of the plot is used to extract the effective ΦBp. (c)

Series of I-V curves of the same NiSiGe/SiGe junction [as mentioned in (b)] measured at

different temperatures (180 K – 240 K). Inset shows the same set of I-V plots, but in an

extremely small forward bias voltage range (0.06 V ≤ VF ≤ 0.1 V). Data points are fitted

using a best-fit line.

81

Equation (2.2)] [4.23]. The Activation energy method is used to extract the effective

ΦBp for all the samples, with and without Al implant. It uses a rearranged form of the

TE model given by

*F B F2

ln lnI qV

AAT kT

, (4.1)

where A is the diode area, A* is the Richardson constant, q is the electronic charge, ΦB

is the effective Schottky barrier height that includes the contribution due to image-

force barrier lowering, and k is Boltzmann constant [4.23]-[4.25]. Appendix B can be

referred for more details regarding the activation energy method.

Figure 4.4(b) shows a typical plot of IF/T2 versus 1000/T at different VF, where

T is the absolute temperature in Kelvin, for the sample that underwent an Al implant

dose of 2×1014 atoms-cm-2. Figure 4.4(c) shows the series of I-V curves measured at

different temperatures, for the same sample. The inset in Fig. 4.4(c) shows the same

set of data plots, in an extremely low forward bias voltage range (0.06 V ≤ VF ≤ 0.1

V), showing the linearity of I (on log scale) with V. The curves in Fig. 4.4(b) are

extracted from the inset in Fig. 4.4(c), and are fitted using Equation (4.1) to extract

the effective ΦBp and the average value is calculated to be 0.12 eV. In this case, ΦB

p

is same as parameter ΦB in Equation (4.1). Note that the slope of the Arrhenius plot,

from Equation (4.1), is given by (qVF - ΦB)/kT. Thus, the slope and hence the

effective ΦBp is dependent on the bias voltage, as depicted in Fig. 4.4(b). The

junction series resistance is neglected in Equation (4.1) as the curves in Fig. 4.4(b) are

plotted in an extremely low forward bias voltage range (0.06 V ≤ VF ≤ 0.1 V).

Although the slope of the Arrhenius plot should be fixed for a particular bias voltage

[as expected from the Equation (4.1)], it can clearly seen in Fig. 4.4(b) that it varies

from a negative value to a positive value as the temperature is increased. It has been

reported that when the temperature is high enough such that kT is comparable to qVF –

82

ΦB, the slope changes its sign from negative to positive [4.24]. This physically

implies that most carriers have enough thermal energy to surmount the barrier height

and hence, the effective ΦBp cannot be measured using the high temperature part of

the data [4.24]. Thus, the effective ΦBp extraction is done in the low temperature part

of the plot [as shown in Fig. 4.4(b)].

Figure 4.5 plots the effective ΦBp at the NiSiGe/SiGe junction for all the

samples fabricated in this work, with and without Al implant. Error bars are also

drawn to explicitly show the variation in effective ΦBp extracted at different bias

voltages. For all samples, this variation was found to be within ±10 % of the mean

value. For the control sample (without Al implant), the effective ΦBp value of 0.53 eV

is around the SiGe midgap indicating the pinning of the NiSiGe Fermi level. With

0.073 eV 0.068 eV

0.53 eV

0.0

0.1

0.2

0.3

0.4

0.5

0.12 eV

21014

Aluminum Dose (atoms/cm2)

Sch

ottk

y B

arri

er H

eigh

t (e

V)

21015110150

Control Sample (No Al)

77%

86% 87%

Fig. 4.5 The variation of the effective ΦBp of NiSiGe on SiGe, with and without Al

implant, extracted using activation energy method. Error bars are also drawn to show the

variation in the extracted ΦBp at different forward bias voltage VF, about its mean value. 10

nm of Ni is germano-silicided using RTA at 400˚C for 30 seconds to form the NiSiGe contact

on SiGe, for all the samples.

83

subsequently higher Al implant dose, the effective ΦBp drops and starts to saturate at

sub-0.1 eV with an Al implant dose of 1×1015 atoms-cm-2. The lowest effective ΦBp

achieved in these experiments is 0.068 eV, at an Al implant dose of 2×1015 atoms/cm2,

which is a massive 87 % drop from the value of the control sample.

It should be noted that in low Schottky barrier junctions, field emission can

play a critical role in the current transport mechanism, which will render the use of TE

model for effective ΦBp extraction error-prone. It has been reported that at extremely

low bias voltages, TE model coupled to image-force barrier lowering is sufficient to

accurately account for the physics of transport in a low barrier Schottky junction, and

that this would not hold at higher bias voltages [4.26]. In this work, an extremely low

bias voltage (≤ 0.1 V) has been used and so the extracted ΦBp should be reasonably

accurate.

B. Mechanism for Schottky Barrier Height Modulation

Time-of-flight secondary-ion mass spectroscopy (TOF-SIMS) was used to

measure the depth profile of Al in the fabricated NiSiGe/SiGe junctions (with

different Al implant dose), as shown in Fig. 4.6. It is apparent that Al segregates near

the NiSiGe/SiGe interface, with its peak just inside the SiGe side of the interface,

which is similar to the case of NiSi/p-Si junctions, as reported in section 3.2.3.1

(chapter 3). This is also shown schematically in Fig. 4.2(b). From the TOF-SIMS

depth profile of Al in the as-implanted sample (not shown), whose structure is

schematically similar to that shown in Fig. 4.2(a), the implantation peak of Al in SiGe

is extracted to be at ~10 - 13 nm. With 10 nm of Ni used for germano-silicidation, it

will react with ~20 nm of SiGe, easily consuming the as-implanted Al profile [4.27],

[4.28]. Hence, the profile of Al at the NiSiGe/SiGe interface is due to the segregation

84

21014Al/cm2

11015Al/cm2

21015Al/cm2

0 20 40 60 80 100 120 140 160

100

101

102

103

104

SiGe

Inte

nsi

ty (

cou

nts

)

Depth (nm)

NiSiGe/SiGe Interfacial Region

NiSiGe

Fig. 4.6 TOF-SIMS depth profile of Al in NiSiGe/SiGe junctions, with Al implant dose in

the range of 2×1014 - 2×1015 atoms-cm-2. Segregation of Al near the NiSiGe/SiGe interface is

clearly seen. The starting thickness of Ni used to form the NiSiGe contacts is 10 nm.

of Al during germano-silicidation. The first peak of the Al depth profile in

NiSiGe/SiGe is within the bulk NiSiGe film (as shown in Fig. 4.6) and is due to the

as-implanted peak of Al in SiGe.

Al is known to introduce shallow acceptor-type trap level in Si and Ge

bandgap near the valence band (0.069 eV and 0.01 eV above the valence band,

respectively) [4.23]. Thus, it can be assumed that Al will also act in a similar way in

SiGe. These trap levels are acceptor-like, are located well below the Fermi level, will

be filled with electrons, and hence negatively charged. The prerequisite for the traps

to be charged (and hence activated) is that the Al atom should be at substitutional sites

in the SiGe lattice. In this case, Al would act as a dopant. T. Yamauchi et al. have

shown through first principle calculations that for a NiSi/Si interface, the system

would in its lowest energy state (most stable configuration) when the ion-implanted

dopant atoms, after low temperature thermal annealing, occupy substitutional sites in

85

the Si lattice in the first few Si monolayer near the silicide/silicon interface [4.29].

Assuming that the same model is true for a NiSiGe/SiGe interface, Al piling up on the

SiGe side of the NiSiGe/SiGe interface (Fig. 4.6) will introduce negative charge,

which in turn will induce equal and opposite positive charge on the NiSiGe side of the

interface, generating a dipole at the interface. This will further lead to a very sharp

electric field at the interface which thins down the Schottky barrier width, thus

allowing holes to tunnel through it and lowering their effective ΦBp. It should be

noted that this model is essentially the same as that used to explain the lowering of the

ΦBp of NiSi on p-Si, in the section 3.2.3.1 (chapter 3).

M. Y. Ali and M. Tao reported that Al, which is a low work function metal,

has an electron Schottky barrier height (ΦBn) of ~0.56 eV on n-type Si and a ΦB

p of

~0.66 eV on p-type Si [4.30]. Thus, the metal Fermi level seems to be pinned near the

Si midgap. After the surface of Si was passivated by sulfur (S) using a solution of

(NH4)2S, the ΦBn changed to <0.11 eV on n-type Si and the ΦB

p changed to ~0.80 eV

on p-type Si. These Schottky barrier values are much closer to the ideal Schottky

barrier height values of Al on n-Si (~0.01 eV) and p-Si (~1.13 eV), predicted by the

Schottky-Mott model [4.23]. In Ref. 4.30, a simple calculation was done to show that

the surface state density at the Al/Si (100) interface dropped by more than an order of

magnitude by S passivation, possibly leading to the partial de-pinning of the metal

Fermi level. But, in this work, the lowest ΦBp value that we have achieved (~0.068

eV) is far smaller than that predicted by the Schottky-Mott model, if we assume the

workfunction of NiSiGe to be in between that of NiSi (~4.7 eV) and NiGe (~4.57 eV)

and the electron affinity of SiGe to be approximately the same as that of Si (~4.15 eV)

[4.31]-[4.33]. Hence, surface passivation can be safely ruled out as the reason behind

lowering of the ΦBp.

86

30 40 50 60

In

ten

sity

(a.

u.)

2 Theta (degree)

21015Al/cm2

(011

)

(111

)

(112

)

(013

)

(202

)No Al

11015Al/cm2

21014Al/cm2

(a)

0

3

6

9

12

21015

11015

Sh

eet

Res

ista

nce

( /s

q)

21014

Aluminum Dose

(atoms/cm2)

0

(b)

Fig. 4.7 (a) XRD theta/2theta (θ/2θ) phase analysis of NiSiGe on SiGe with and without

Al implant. .Germano-silicidation is done using RTA at 400 ˚C for 30 seconds on 10 nm of Ni.

(b) Sheet resistance of NiSiGe contact formed on SiGe, with and without Al implant.

Germano-silicidation is done using RTA at 400 ˚C for 30 seconds on 10 nm of Ni. Error bars

are also drawn to show the spread in the measured sheet resistance within a set of devices due

to statistical process variation.

Figure 4.7(a) shows the theta/2theta (θ/2θ) XRD phase analysis of the blanket

NiSiGe films with and without Al implant. For all films, the same XRD peaks are

observed, all corresponding to the nickel mono-germano-silicide phase only. Thus,

the bulk properties of the NiSiGe layer (and hence its work function) are unchanged

even with the Al implant. Also, the sheet resistance of all NiSiGe films (determined

from the four-point probe method), with Al implant, is within ±10 % of its value for

the control sample (without Al implant), which is shown in Fig. 4.7(b) to be ~9.6 Ω/sq.

Therefore, it is speculated that the introduction of shallow acceptor-type traps by Al

on the SiGe side of the NiSiGe/SiGe interface is the most probable reason behind

lowering of the effective ΦBp of NiSiGe on SiGe.

87

C. Effect of Nickel Thickness

Figure 4.8(a) shows the I-V characteristics of two NiSiGe/SiGe junctions with

different NiSiGe thicknesses. The starting thicknesses of Ni used to form NiSiGe is

10 nm for the first device (which is the same thickness that was utilized for devices

discussed in the previous sections) and 30 nm for the second device, which will lead

to approximately 22 and 66 nm of NiSiGe, respectively [4.27], [4.28]. It should be

noted that the thickness of NiSiGe is also dependent on the germano-silicidation

temperature because of germanium out-diffusion from NiSiGe and NiSiGe film

agglomeratiom [4.34]. For comparison, a control sample which did not receive any

Al implant is also shown in Fig. 4.8(a). The Al implant dose for the two devices is

2×1014 atoms-cm-2. It can be clearly observed that the reverse current for the Al

implanted NiSiGe/SiGe junction with thicker NiSiGe is lower than the other Al

implanted junction. This points towards an increase in the effective ΦBp for the

NiSiGe/SiGe junction with increase in NiSiGe thickness.

The Activation energy method [as shown before in Fig. 4.4(b)] is used to

extract the effective ΦBp of the NiSiGe/SiGe junction with thicker NiSiGe and the

result is shown in Fig. 4.8(b) [4.25]. Again, the low temperature part of the plot is

used to fit the curve with the TE model. The average value of the ΦBp is extracted to

be ~0.25 eV. As shown in Fig. 4.9(a), the effective ΦBp of NiSiGe/SiGe junction

increases by a significant 108 %, from its earlier value when the Ni thickness used to

form NiSiGe was 10 nm.

To understand this, TOF-SIMS depth profile of Al was measured on three

NiSiGe/SiGe samples (with the same Al implant dose as before, namely 2×1014,

1×1015, and 2×1015 atoms-cm-2) in which the NiSiGe film was prepared from 30 nm

of Ni. The result is plotted in Fig. 4.9(b) and it can be clearly observed that the

88

-2 -1 0 1 210-4

10-3

10-2

10-1

100

101

102

p-Si

V, I

SiGe

NiSiGe

SiO2

Lowering of Reverse Current

No Al

21014Al/cm2

21014Al/cm2Cu

rren

t D

ensi

ty (

A/c

m2 )

Voltage (V)

30 nm Ni

10 nm Ni

Ref. Sample: No Al

(a)

Temperature

Range for B

p

Extraction

3.0 3.5 4.0 4.5 5.0

10-12

10-11

10-10

10-9

VF = 0.06V

VF = 0.08V

VF = 0.10V

1000/T (K-1)

I F /T

2 (A

/K2 )

(b)

Fig. 4.8 (a) I-V characteristics of two NiSiGe/SiGe junctions with Al implant at a dose of

2×1014 atoms-cm-2, formed from 10 nm and 30 nm of Ni. For the NiSiGe contact formed

from 30 nm of Ni, germano-silicidation was done using RTA at 400 ˚C for 1 minute. The

control device without any Al implant is also shown. The inset shows the schematic of the

fabricated device used for I-V characterization. (b) Activation energy measurements to

extract the effective ΦBp for NiSiGe on SiGe, for the device with Al implant at a dose of

2×1014 atoms-cm-2 and formed by germano-silicidation of 30 nm of Ni. With the y-axis

plotted on log-scale, the slope of the linear fit of the curve (solid line) in the low temperature

part of the plot is used to extract the effective ΦBp.

89

0.0

0.1

0.2

0.3

0.4

0.5

0.25 eV

0.12 eV

21014

0.53 eV

Aluminum Dose (atoms/cm2)

Sch

ottk

y B

arri

er H

eigh

t (e

V)

210140

Ref. Sample (No Al)

10nm Ni

30 nm Ni

108 % increase of B

p

(a)

21014Al/cm2

11015Al/cm2

21015Al/cm2

0 20 40 60 80 100 120 140

10-1

100

101

102

103

104

105

0.0

0.2

0.4

0.6

Al Dose (atoms/cm2)

B

p (

eV)

Ni Thickness = 30 nm

0 11015

21014 21015

SiGe

Inte

nsi

ty (

cou

nts

)

Depth (nm)

NiSiGe/SiGe Interfacial Region

NiSiGe (b)

Fig. 4.9 (a) The effective ΦBp of two NiSiGe/SiGe junctions, with Al implant at a dose of

2×1014 atoms-cm-2, and formed from 10 nm and 30 nm of Ni. The ΦBp is extracted using

activation energy method. (b) TOF-SIMS depth profile of Al in NiSiGe/SiGe junctions, with

Al implant dose in the range of 2×1014 - 2×1015 atoms-cm-2. The starting thickness of Ni used

to form the NiSiGe contacts is 30 nm. The inset shows the corresponding effective ΦBp of all

the NiSiGe/SiGe junctions with Al implant in the range of 2×1014 - 2×1015 atoms-cm-2 and

NiSiGe contact formed from 30 nm of Ni. The ΦBp values are much higher than those

extracted for thinner NiSiGe contacts (formed from 10 nm of Ni) with the same Al implant

dose. Error bars are also drawn to show the variation in the extracted ΦBp at different forward

bias voltage, about their mean value.

90

intensity (or counts) of Al atoms at the NiSiGe/SiGe interface is much lower than that

observed for the earlier case in which NiSiGe film was prepared from 10 nm of Ni

(Fig. 4.6). This is expected because it is the concentration of Al, segregated at the

NiSiGe/SiGe interface that is responsible for the lowering of the effective ΦBp (as

explained in section 4.3.1). The effective ΦBp of the three NiSiGe/SiGe junctions

prepared from 30 nm of Ni is shown in the inset of Fig. 4.9(b). As in all the previous

cases, the activation energy method (using low temperature I-V characterization) is

used to extract the effective ΦBp for all the samples [4.25].

D. Effect of Al Implant Dose

Figure 4.10(a) shows the cross-sectional transmission electron microscopy

(xTEM) image of a SiGe layer implanted with Al at dose of 2×1014 atoms-cm-2. It

can be seen that the implant dose amorphizes approximately the top 20 nm of the

SiGe layer. With higher Al implant dose of 1×1015 and 2×1015 atoms-cm-2, the

amorphization depth increases to ~30 nm [Fig. 4.10(b)] and ~35 nm [Fig. 4.10(c)],

respectively. This amorphization of the SiGe film has two issues associated with it,

when integrated into the S/D of a p-MOSFET. Firstly, it will reduce the thickness of

the SiGe S/D that needs to be crystalline to introduce compressive stress in the Si

channel. Thus, the total channel stress would drop, adversely affecting the hole

mobility in the channel. Secondly, the p+/n S/D junction leakage current will increase

due to the presence of defects in the amorphized S/D region. Moreover, since the S/D

dopant activation will be performed before the Al implant, there are no further high

temperature steps to restore the crystallinity of the top SiGe layer. Thus, the nickel

germano-silicidation process step has to consume all of the amorphized SiGe (-SiGe)

thickness.

91

SiO 2

SiGe

p-Si

Amorphized SiGe ≈20 nm

50 nm (a) (b)

(c)

50 nm

Amorphized SiGe ≈ 30 nm

50 nm

Amorphized SiGe ≈ 35 nm

SiGe

p-Si

SiGep-Si

100 nm

SiGe

p-Si

NiSiGe

(d)

80 nm

78 nm

Fig. 4.10 XTEM image of the SiGe film implanted with Al at a dose of (a) 2×1014 atoms-

cm-2 showing amorphization of the top 20 nm, (b) 1×1015 atoms-cm-2 showing amorphization

of the top 30 nm, and (c) 2×1015 atoms-cm-2 showing amorphization of the top 35 nm. (d)

XTEM image of NiSiGe/SiGe junction with Al implant dose of 2×1014 atoms-cm-2, formed

from 10 nm of Ni. A continuous NiSiGe film is formed which consumes all of the α-SiGe.

The XTEM image in Fig. 4.10(d) shows that germano-silicidation of 10 nm of

Ni is just enough to consume the amorphization depth in the SiGe film implanted with

Al at a dose of 2×1014 atoms-cm-2. This is because the thickness of crystalline SiGe

(c-SiGe) left after the NiSiGe formation in Fig. 4.10(d) is ~78 nm which is almost the

same as the thickness of c-SiGe left after Al implant in Fig. 4.10(a) (~80 nm). Also,

there is no -SiGe sandwiched between the metallic NiSiGe and c-SiGe in Fig.

4.10(d). Thus, 10 nm of Ni has consumed ~22 nm of SiGe during complete germano-

silicidation, which is in agreement with published data [4.27], [4.28]. So, for the SiGe

92

films implanted with higher Al implant dose (1×1015 and 2×1015 atoms-cm-2), 10 nm

of Ni will not be enough to consume all of the amorphization depth and hence a

thicker Ni has to be used. But, a thicker NiSiGe increases the effective ΦBp of the

NiSiGe/SiGe junction [as seen in Fig. 4.8 and 4.9]. Thus, a trade-off exists in

choosing the most optimal Ni thickness and Al implant dose, for the formation of

NiSiGe contact on SiGe.

4.3.2 Electrical Results: p-FinFET Integration

A. Morphology and I-V Characteristics of Strained p-FinFETs with Al Segregated

NiSiGe/p+-SiGe S/D Interface

Figure 4.11(a) shows the top-view SEM image (rotated and tilted at 45°) of a

completed strained p-FinFET that underwent Al implant and NiSiGe S/D contact

formation. The NiSiGe film is uniform with no evidence of agglomeration. Figure

4.11(b) shows the cross-sectional TEM image of a fabricated p-FinFET with Al

implant and contact formation. The focused ion beam (FIB) cut in the TEM sample

preparation was not performed at the narrowest portion of the gate electrode which

runs over the fin. The location of the FIB cut is along a line A-A', as illustrated in the

SEM image of Fig. 4.11(a). Due to off-centering of the FIB cut, TEM image shows

the gate stack to be on top of the BOX layer, instead of it being on top of the Si fin.

With 10 nm of Ni used for germano-silicidation, the actual NiSiGe thickness is

obtained to be ~25 nm, close to the expected value of ~22 nm [4.35]. The Al implant

did not affect the NiSiGe film morphology.

Figure 4.12(a) shows the IDS-VGS plot of a pair of p-FinFETs with and without

Al implant. The devices have a LG of 105 nm and a WFin of 50 nm. They also have

similar drain induced barrier lowering (DIBL) of ~45 mV/V, subthreshold swing (SS)

93

of ~95 mV/decade, saturation threshold voltage (VTSAT) of ~-0.125 V, and off-state

current (IOFF) of the order of 10-10 A/µm. Short-channel effects (SCE) are perfectly

matched, indicating comparable effective channel lengths. VTSAT for all p-FinFETs in

this work were extracted using the constant current method [4.25]. VTSAT is defined to

be the VGS at which IDS is 1 μA/μm at a fixed VDS of -1.2 V. In Fig. 4.12(a), IDS

enhancement is visible in both linear and saturation region. Figure 4.12(b) plots the

IDS-VDS characteristics of the same pair of p-FinFETs at various gate overdrives (VGS -

VTSAT) from 0 V to -1.2 V in steps of -0.2 V. At VGS - VTSAT = VDS = -1.2 V, the

saturation drive current (IDSAT) is ~30 % higher in the p-FinFET with Al segregated

NiSiGe/p+-SiGe S/D junction as compared to the control p-FinFET without Al

implant.

500 nmNiSiG

e

NiSiGe

NiSiSiO 2

A

A'

SiN

GateDrain

Source

Buried SiO2Si

NiSi

SiGe S/D

NiSiGe with

Al Segregated

Bottom Interface

125 nm

Poly-SiGate

100 nm

SiN Spacer

Fig. 4.11 (a) Top-view SEM image of a strained p-FinFET device that went through Al

segregated NiSiGe/p+-SiGe S/D contact formation. The introduction of Al does not affect the

NiSiGe film morphology. (b) Cross-sectional TEM image of a strained p-FinFET. Focused

Ion Beam (FIB) cut is done along line A-A' as shown in (a), which is not on the part of the

gate line which runs across the active fin region. The actual physical gate length for this

device is therefore slightly smaller than 125 nm. The NiSiGe film thickness is estimated to be

~25 nm. Bright contrast near the gate sidewalls is due to air hole creation during TEM

sample preparation.

(b)(a) (b)

94

-1.5 -1.0 -0.5 0.0 0.510-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

LG = 105 nm

WFin

= 50 nm

Dra

in C

urr

ent

ID

S (

A/

m)

Gate Voltage VGS

(V)

Al Implant No Al (Control)

VDS

= - 1.2 V

VDS

= - 50 mV

-1.0 -0.5 0.0

0

50

100

150

200

250

300 Al Implant No Al (Control)

Drain Voltage VDS

(V)D

rain

Cu

rren

t I

DS (A

/m

)

VGS

- VTSAT

= -1.2 V

30 %

Fig. 4.12. (a) IDS - VGS characteristics of a pair of strained p-FinFETs with and without Al

implant. The devices have a gate length LG of 105 nm and a fin width WFin of 50 nm, and

have comparable short channel effects. (b) IDS-VDS characteristics of the same pair of p-

FinFETs show that Al implant and segregation contributes to ~30 % higher IDSAT at VDS = VGS

- VTSAT = -1.2 V.

Figure 4.13(a) plots IOFF versus IDSAT for p-FinFETs with and without Al

implant. IOFF and IDSAT were extracted at a VGS of 0 V and -1.2 V, respectively, with

VDS kept at -1.2 V. Each data set (with or without Al implant) comprises 30 to 40

devices with LG ranging from 60 nm to 230 nm. The best-fit lines for the two data

sets were obtained using linear regression. At a fixed IOFF of 100 nA/μm, ~25 %

enhancement in IDSAT is achieved for FinFETs with Al segregated NiSiGe/p+-SiGe

S/D junction over the control FinFETs. For the same two sets of p-FinFET devices, a

(a) (b)

95

0 200 400 600

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

Data Best-Fit

Off

Cu

rren

t I O

FF (

A/

m)

Drive Current IDSAT

(A/m)

25%V

DS = -1.2 V


0 10 20 30 40

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

Linear Drain Current IDLIN

(A/m)

Off

Cu

rren

t I

OF

F (

A/

m)

29%

VDS

= -0.05 V

Data Best-Fit


Fig. 4.13 (a) IDSAT - IOFF plot for strained p-FinFETs with and without Al implant showing a

saturation drain current IDSAT enhancement of ~25 %. (b) IDLIN - IOFF plot shows a linear drain

current enhancement of ~29 % for devices with Al implant over the control FinFETs. The

best-fit lines were obtained using least-square-error fitting.

plot of IOFF versus linear drive current (IDLIN) in Fig. 4.13(b) shows ~29 %

enhancement in IDLIN at a fixed IOFF of 100 nA/μm. IOFF and IDLIN are extracted at a

VGS of 0 V and -1.2 V, respectively, with VDS kept at low voltage of -50 mV.

B. Series Resistance Extraction

Figure 4.14 shows a plot of total resistance (RTotal) versus LG for p-FinFETs

with and without Al segregated NiSiGe/p+-SiGe S/D junction at a linear gate

overdrive (VGS – VTLIN) of -2 V and -1.8 V, where VTLIN is the threshold voltage

obtained from the IDS-VGS curve in the linear region. The same set of devices, used in

Fig. 4.13(a) and 4.13(b), were used for the series resistance extraction. At each gate

(a) (b)

96

0.0 0.1 0.2 0.3

2000

4000

6000

No Al(Control) Al Implant

Al Implant

VGS

- VTLIN

= -2.0 V

T

otla

l Res

ista

nce

RT

otal (

m)

Gate Length LG (m)

VGS

- VTLIN

= -1.8 V

No Al(Control)

LinearRegressionFits

Fig. 4.14 Plot of RTotal versus LG for strained p-FinFETs with and without Al implant in the

linear region at VGS - VTLIN of -1.8 V and -2 V. Linear regression fit of data gives a y-axis

intercept that allows for extraction of RSD. RSD for p-FinFETs with Al segregated NiSiGe/p+-

SiGe S/D junction is lowered by 21 % with respect to control p-FinFETs without Al implant.

length in Fig. 4.14, one RTotal data point is obtained from an average of 8 to10 devices.

With VDS kept at a low value of -50 mV to ensure MOSFET operation in linear region,

and the device maintained under strong inversion by keeping VGS – VTLIN << 0.5VDS,

RTotal is given by [4.25]

DS GTotal CH SD SD

DS ox GS TLIN

,( )

V L LR R R R

I W C V V

(4.2)

where RCH is the FinFET channel resistance, W is the effective channel width, μ is the

effective channel mobility, Cox is the oxide capacitance per unit area, and ∆L is the

difference between the physical gate length (same as LG) and the effective channel

length L. L and LG are especially different for devices with lightly doped drain (LDD)

structures where the channel can extend into LDD at higher gate voltages. Equation

(4.2) can be further written as

97

Total G ,R AL B (4.3)

where A and B are given by

ox GS TLIN1 [ ( )],A W C V V and (4.4)

SD .B R A L (4.5)

Linear regression was used to fit the RTotal versus LG plot for devices with and without

Al implant, at the two different linear gate overdrive (VGS – VTLIN) values of -1.8 V

and -2 V, as shown in Fig. 4.14. The slope and y-intercept of the linear regression fits

are used to extract two sets of A and B using Equation (4.3), both for devices with and

without Al implant. The two (VGS – VTLIN) values are selected close to each other

because, although ∆L and RSD are assumed to be constant in Equation (4.2) – (4.5),

they do have a weak dependency on VGS. The extracted values of A and B are in turn

least-square-error-fitted using Equation (4.5) to quantify ∆L and RSD (not shown).

RSD for control p-FinFETs (without Al implant) and p-FinFETs with Al implant (Al

segregated NiSiGe/p+-SiGe S/D junction) are evaluated to be 783 and 617 Ω-μm,

respectively, giving a drop of ~21 % (with respect to the control devices). With

respect to the Al implanted devices, the drop in RSD is calculated to be ~27 %. This is

in close agreement with the drain current enhancement obtained in the saturation

region [Fig. 4.14(a)] or the linear region [Fig. 4.14(b)], given by (IDSAl - IDS

Ctrl)/IDSCtrl

≈ (RSDCtrl - RSD

Al)/RSDAl. IDS

Ctrl and IDSAl are the drain currents for the control devices

(p-FinFETs without Al implant) and Al segregated FinFETs, respectively and RSDCtrl

and RSDAl are the parasitic series resistances for the control and Al segregated

FinFETs, respectively.

The interfacial contact resistivity, C (and hence RC) at the NiSiGe/p+-SiGe

interface is an exponential function of ΦB at the interface and is given by Equation

(1.9). With ~77 % drop in the hole Schottky barrier height of NiSiGe on SiGe, from

98

0.4 eV (for the control sample without Al) to 0.12 eV (for the sample with Al implant

at dose of 2×1014 atoms/cm2), RC is bound to drop, leading to a drop in RSD. Thus, the

IDSAT enhancement is attributed to the reduction in RSD due to the presence of Al

segregated NiSiGe/p+-SiGe S/D junction. It should be noted here that for any specific

linear gate overdrive voltage (in Fig. 4.14), the gradient of the linear regressions fits

(∆RTotal/∆LG) are the same, for devices with and without Al implant, indicating that

the effective mobility in the channel is not affected by the low dose Al implant of

2×1014 atoms/cm2 [4.36]. Thus, the reduced RSD due to Al segregated NiSiGe/p+-

SiGe junctions is the dominant factor responsible for IDSAT enhancement.

As LG is reduced from 230 nm to 80 nm, IDSAT enhancement increases from 25

% to 35 %, as shown in Fig. 4.15. The impact of RSD reduction on drive current

enhancement is higher for devices with a smaller gate length, which is in good

agreement with published work [4.37], [4.38]. For each of the two device splits (with

and without Al implant), the sample size for evaluation of the mean IDSAT at each LG

is ~15. The measurement of IDSAT was done at VDS = VGS - VTSAT = -1.2 V. The

enhancement in IDSAT with Al implant is further illustrated by plotting IDSAT against

drain induced barrier lowering, DIBL in Fig. 4.16. Devices with LG from 60 to 230

nm were plotted in Fig. 4.16, and these are essentially the same devices that were

illustrated in Fig. 4.13 and Fig. 4.14. Linear regression was performed and plotted in

Fig. 4.16 to show the trends. As expected, FinFETs with a shorter LG have a higher

IDSAT and a poorer SCE control or higher DIBL. At a fixed DIBL of 100 mV/V, ~25

% enhancement in IDSAT is achieved with Al implant.

99

0

50

100

150

200

250

300

35 %

Mea

n I

DS

AT (A

/m

)

Gate Length LG


230 nm 80 nm

25 %

Fig. 4.15 Mean saturation drain current in p-FinFETs with and without Al implant at a gate

length LG of 230 nm and 80 nm. IDSAT enhancement increases with gate length reduction.

0 100 200 3000

100

200

300

400

500V

DS = -1.2 V

Drain Induced Barrier Lowering DIBL (mV/V)

Sat

ura

tion

Dra

in C

urr

ent

25%

I DS

AT (A

/m

)

Data Best-Fit


Fig. 4.16 Plot of saturation drain current IDSAT versus Drain Induced Barrier Lowering

(DIBL) for strained p-FinFETs. All measured data are plotted as circles for p-FinFETs

without Al implant (control) and as solid triangles for p-FinFETs with Al implant. Best-fit

lines were obtained using least-square-error fitting. At a fixed DIBL of 100 mV/V, Al

implant and segregation gives ~25 % enhancement in IDSAT.

100

C. Control of Short Channel Effects

IOFF versus VTSAT is plotted in Fig. 4.17 to examine the matching of SCE in

strained p-FinFETs with and without Al implant. The devices have LG in the range of

60 to 230 nm, and are the same set of devices as those plotted in Fig. 4.16. Due to the

wide range of LG used in Fig. 4.17, IOFF and VTSAT have a relatively large spread. IOFF

is extracted at VGS of 0 V and VDS of -1.2 V. It can be clearly seen that at any fixed

VTSAT, the IOFF for the two splits are very similar, indicating similar subthreshold

swing. The Al implant did not degrade the subthreshold swing (SS) or IOFF. Thus,

SCE are effectively matched for the devices with and without Al implant. Figure 4.18

shows the cumulative probability distribution (in percentage) of (a) VTSAT, (b) DIBL,

and (c) SS, for p-FinFETs with and without Al implant. These three parameters are

extracted for the same set of devices that were used in Fig. 4.17. It is found that the

spread of parameters as well as the cumulative probability coincides for devices with

and without Al implant, showing no degradation of SCE due to the Al implant.

In Fig. 4.19, p+/n junction leakage current is compared in strained p-FinFETs

with and without Al implant. A schematic diagram of the fabricated diode is shown

as an inset in Fig. 4.19. It is essentially a NiSiGe contacted p+-SiGe S/D junction on

n-type Si, which emulates the drain-to-substrate p+/n junction in FinFETs used for this

work. The detailed fabrication process flow is discussed in section 4.2. The junction

leakage current is extracted at a fixed reverse voltage of -1.2 V. It can be clearly

observed that for both set of devices, with and without Al implant, the junction

leakage current is comparable. Thus Al implant does not degrade the junction leakage

characteristics.

101

-0.4 -0.2 0.0 0.2 0.4 0.610-10

10-9

10-8

10-7

10-6

10-5

10-4

Saturation Threshold Voltage VTSAT

(V)

Off

Cu

rren

t I O

FF (

A/

m) Al Implant

No Al (Control)

Fig. 4.17 IOFF extracted at VGS = 0 V is plotted against VTSAT, which shows that the

transistor off-state leakage current is not affected by Al implant at a dose of 2×1014 atoms/cm2.

-0.4 0.0 0.4 0.8

0

20

40

60

80

100

Cu

mu

lati

ve P

rob

abil

ity

(%)

VTSAT

(V)

Al Implant

No Al

0.0 0.2 0.4

0

20

40

60

80

100

DIBL (V/V)

Cu

mu

lati

ve P

rob

abili

ty (

%)

Al Implant

No Al

60 80 100 120 140 160

0

20

40

60

80

100

C

um

ula

tive

Pro

bab

ility

(%

)

SS (mV/decade)

Al Implant

No Al

Fig. 4.18 Cumulative distributions of (a) VTSAT, (b) DIBL, and (c) SS in strained p-FinFETs

with and without Al implant. Both device splits have comparable VTSAT, DIBL and SS,

suggesting that gate control of short-channel effects is unaffected by the Al implant and

segregation process.

(a) (b) (c)

102

10-8 10-7 10-6 10-5 10-4 10-3

0

20

40

60

80

100

n-Si

V, I

p+-SiGe

NiSiGe

SiO

2

SiO

2

p+-Si

Cu

mu

lati

ve P

rob

abil

ity

(%)

Junction Leakage Current (A/cm2)

No Al (Control)Al Implant

Measured at V = -1.2 V

Fig. 4.19 Cumulative distributions of NiSiGe contacted p+(SiGe/Si)/n(Si) diode junction

leakage current, measured at a reverse bias voltage of -1.2 V. The inset shows a schematic of

the fabricated diode used for this measurement. The result suggests that the Al implant and

segregation does not affect the drain-to-substrate junction leakage characteristics.

4.4 Summary and Conclusion

The modulation of the effective ΦBp of NiSiGe on SiGe has been demonstrated

by Al implant and segregation to sub-0.1 eV. Using an implant dose of 2×1015 Al

atoms-cm-2, an extremely low effective ΦBp of 0.068 eV is achieved. This is

extremely promising for p-MOSFETs, especially multiple-gate transistors (or

FinFETs) with narrow fin widths. A possible mechanism to explain the lowering of

the effective ΦBp with increasing Al concentration at the NiSiGe/SiGe interface is

discussed. It is speculated that the thinning of the Schottky barrier width (at the

NiSiGe/SiGe interface) due to the interfacial dipole generated by Al atoms, is

responsible for the lowering of the effective ΦBp. Al implant has been found to have

no adverse effect on the sheet resistance and the low resistivity phase of the NiSiGe

film. But, the increase in thickness of NiSiGe has a negative impact on the effective

103

ΦBp. The increase in implant dose of Al, although reduces the effective ΦB

p, it also

increases the amorphization depth in SiGe. Thus, there is a trade-off in choosing the

thickness of Ni (to form NiSiGe) and the implant dose of Al, to reap the maximum RC

reduction benefits.

Furthermore, segregation of Al introduced by ion-implantation and germano-

silicidation at the NiSiGe/p+-SiGe interface in p-FinFETs resulting in lowering of RC

(and RSD) has also been demonstrated. P-channel strained FinFETs with Al

segregated NiSiGe/p+-SiGe S/D junctions were fabricated and shown to have ~27 %

lower RSD than devices without Al implant. Al implant and segregation enhances

IDSAT by ~25 % for p-FinFETs, without degrading the NiSiGe film morphology or

short-channel effects.

104

4.5 References



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T.-J. King, J. Bokor, and C. Hu, “FinFET: A self-aligned double-gate MOSFET

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Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu,

“Sub-50 nm p-channel FinFET,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp.

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Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, “FinFET scaling to 10

nm gate length,” IEDM Tech. Dig., pp. 251-254, 2002.

[4.6] G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C.-C. Kan, “FinFET design

considerations based on 3-D simulation and analytical modeling,” IEEE Trans.

Electron Devices, vol. 49, no. 8, pp. 1411-1419, Aug. 2002.




C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, “5 nm-gate nanowire






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105

transistor architecture with high-k gate dielectrics, metal gates, and strain

engineering,” VLSI Symp. Tech. Dig., pp. 50-51, 2006.



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vol. 28, no. 10, pp. 905-908, Oct. 2007.

[4.11] J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D.

Fried, and H.-S. P. Wong, “Extension and source/drain design for high-performance

FinFET devices,” IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-958, Apr.

2003.

[4.12] A. Pouydebasque, S. Denorme, N. Loubet, R. Wacquez, J. Bustos, F. Leverd, E.

Deloffre, S. Barnola, D. Dutartre, P. Coronel, and T. Skotnicki, “High-performance

high-k/metal planar self-aligned gate-all-around CMOS devices,” IEEE Trans.

Nanotechnology, vol. 5, no. 7, pp. 551-557, 2008.

[4.13] A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I.

Mizushima, K. Okano, H. Kawasaki, T. Izumida, T. Kanemura, N. Aoki, A.

Kinoshita, J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K.

Eguchi, and Y. Tsunashima, “High-performance FinFET with dopant-segregated

Schottky Source/Drain,” IEDM Tech. Dig., pp. 893-896, 2006.




[4.15] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices, Cambridge, UK,

1998.

[4.16] R. T. P. Lee, T.-Y. Liow, K.-M. Tan, A. E.-J. Lim, A. T.-Y. Koh, M. Zhu, G.-Q. Lo,

G. S. Samudra, D.-Z. Chi, and Y.-C. Yeo, “Achieving conduction band-edge

schottky barrier height for arsenic-segregated nickel aluminide disilicide and

implementation in FinFETs with ultra-narrow fin widths,” IEEE Electron Device

Letters, vol. 29, no. 4, pp. 382-385, Apr. 2008.

[4.17] R. T. P. Lee, A. T.-Y. Koh, F.-Y. Liu, W.-W. Fang, T.-Y. Liow, K.-M. Tan, P.-C.

Lim, A. E.-J. Lim, M. Zhu, K.-M. Hoe, C.-H. Tung, G.-Q. Lo, X. Wang, D. K.-Y.

Low, G. S. Samudra, D.-Z. Chi, and Y.-C. Yeo, “Route to low parasitic resistance in

MuGFETs with silicon-carbon Source/Drain: Integration of novel low barrier

106

Ni(M)Si:C metal silicides and pulsed laser annealing,” IEDM Tech. Dig., pp. 685-

688, 2007.

[4.18] Q. T. Zhao, M. Zhang, J. Knoch, and S. Mantl, “Tuning of Schottky barrier heights

by silicidation induced impurity segregation,” International Workshop on Junction

Tech., pp. 147-152, 2006.

[4.19] H.-S. Wong, L. Chan, G. Samudra, and Y.-C. Yeo, “Effective Schottky barrier

height reduction using sulfur and selenium at the NiSi/n-Si (100) interface for low

resistance contacts,” IEEE Electron Device Letters, vol. 28, no. 12, pp. 1102-1104,

Dec. 2007.

[4.20] H.-S. Wong, F.-Y. Liu, K.-W. Ang, G. S. Samudra, Y.-C. Yeo, “Novel nickel

silicide contact technology using selenium segregation for SOI n-FETs with silicon-

carbon source/drain stressors,” IEEE Electron Device Letters, vol. 29, no. 8, pp. 841-

844, Aug. 2008.

[4.21] Z. Zhang, Z. Qiu, P.-E. Hellstrom, G. Malm, J. Olsson, J. Lu, M. Ostling, S.-L.

Zhang, “SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant

segregation,” IEEE Electron Device Letters, vol. 29, no. 1, pp. 125-127, Jan. 2008.

[4.22] R. T.-P. Lee, K.-M. Tan, A. E.-J. Lim, T.-Y. Liow, G. S. Samudra, D.-Z. Chi, and

Y.-C. Yeo, “P-channel tri-gate FinFETs featuring Ni1-yPtySiGe source/drain contacts

for enhanced drive current performance,” IEEE Electron Device Letters, vol. 29, no.

5, pp. 438-441, May 2008.





2593-2595, Sep. 2003.

[4.25] D. K. Schroder, Semiconductor Material and Device Characterization, 3rd edition,

IEEE Press, 2006.


metallic source/drain metal-oxide-semiconductor field effect transistors ,” J. Appl.

Phys., vol. 96, no. 1, pp. 729-737, July 2004.

[4.27] J. Seger, T. Jarmar, Z.-B. Zhang, H. H. Radamson, F. Ericson, U. Smith, and S.-L.

Zhang, “Morphological instability of NiSi1-uGeu on single-crystal and polycrystalline

Si1-xGex,” J. Appl. Phys., vol. 96, no. 4, pp. 1919-1928, Aug. 2004.

107

[4.28] J. H. Ko, C. H. Jang, S. H. Kim, Y.-J. Song, and N. E. Lee, “Formation of nickel

silicide and germanosilicide layers on Si(001), relaxed SiGe/Si(001), and strained

Si/relaxed SiGe/Si(001) and effect of postthermal annealing,” J. Vac. Sci. Technol. A,

vol. 24, no.4, pp. 1468-1473, Jul/Aug 2006.

[4.29] T. Yamauchi, Y. Nishi, Y. Tsuchiya, A. Kinoshita, J. Koga, and K. Kato, “1 nm

NiSi/Si Junction Design based on First-Principles Calculation for Ultimately Low

Contact Resistance,” IEDM Tech. Dig., pp. 963-966, 2007.

[4.30] M. Y. Ali, and M. Tao, “Effect of sulfur passivation of silicon (100) on Schottky

barrier height: Surface states versus surface dipole,” J. Appl. Phys., vol. 101, 103708,

2007.

[4.31] E. Bucher, S. Schulz, M. Ch. Lux-Steiner, P. Munz, U. Gubler, and F. Greuter,

“Work function and barrier heights of transition metal silicides,” Appl. Phys. A:

Solid Surf., vol. 40, no. 2, pp. 71-76, June 1986.

[4.32] M. K. Niranjan, L. Kleinman, and A. A. Demkov, “Electronic structure, elastic

properties, surface energies, and work functions of NiGe and PtGe within the

framework of density-functional theory for various surface terminations,” Physical

Review B, vol. 75, 085326, 2007.

[4.33] Erich Kasper, and Klara Lyutovich, Properties of Silicon Germanium and

SiGe:Carbon, INSPEC, IEE, UK, 2000.

[4.34] H. B. Zhao, K. L. Pey, W. K. Choi, S. Chattopadhyay, E. A. Fitzgerald, D. A.

Antoniadis, and P. S. Lee, “Interfacial reactions of Ni on Si1-xGex (x=0.2, 0.3) at low

temperature by rapid thermal annealing,” J. Appl. Phys., vol. 92, no. 1, pp. 214-217,

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[4.35] L. J. Chen, Silicide technology for integrated circuits, IEE, London, 2004.

[4.36] G. Niu, J. D. Cressler, S. J. Mathew, and S. Subbanna, “A total resistance slope-

based effective channel mobility extraction method for deep submicrometer CMOS

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108

[4.38] S.-D. Kim, S. Narasimha, and K. Rim, “An integrated methodology for accurate

extraction of S/D series resistance components in nanoscale MOSFETs,” IEDM Tech

Dig., 2006, pp. 149-152.

109

CHAPTER 5

Novel Cost-effective Single Silicide Solutions for

Simultaneous Contact Resistance Reduction in both p- and

n-channel FETs

5.1 Introduction

This chapter is divided into two parts. In part 1, a single silicide contact

technology employing a low workfunction metal alloy [Nickel (Ni) - Dysprosium (Dy)]

silicide is demonstrated, which achieves low contact resistance, RC, for both n- and p-

FETs. A key enabler is the Aluminum (Al) ion implant technology for independent and

effective reduction of RC in strained p-FinFETs with SiGe S/D. For strained p-FinFETs,

Ni-Dy alloy germanosilicide (NiDySiGe) contact with Al implant gives ~20 % drive

current, IDSAT, enhancement over conventional NiSiGe contact without Al implant. For

strained n-FinFETs with Si:C S/D, Ni-Dy alloy silicide (NiDySi:C) S/D contact,

simultaneously formed using the same process conditions, gives an IDSAT enhancement of

~49 % in n-FinFETs against NiSi:C contacts. Extensive material characterization

results as well as the FinFET device electrical data will be presented.

Part 2 of this chapter reports the demonstration of a nickel-silicide (NiSi)

contact technology that achieves dual near-band-edge barrier heights (i.e., a low

electron barrier height ΦBn for n-FETs and a low hole barrier height ΦB

p for p-FETs)

using just one mask and two ion implants. Independent and effective tuning of RC is

achieved in both p- and n- FinFETs. Compensation effects of Al and sulfur (S)

110

implants is studied for the first time, and exploited for process simplification. A novel

cost-effective integration scheme is shown to give 52 % and 35 % IDSAT enhancement

for p- and n- FinFETs, respectively.

5.2 Ni-Dy Metal Alloy based Single-Silicide Solution using Al+

Implant

5.2.1 Motivation

Silicide contact resistance RC is a major bottleneck to achieving high drive

current IDSAT for CMOS FETs at the 22-nm technology node and beyond [5.1], [5.2].

Independent minimization of RC for both n-FETs and p-FETs is needed to reap the

most benefits of strain engineering in nanoscale MOSFETs. In the sub-25 nm gate

length LG regime, multiple-gate transistors or FinFETs is a promising device option

due to its superior control of short channel effects [5.3]-[5.10]. Benefits of silicon-

carbon (Si:C or Si1-xCx) stressor for n-FinFETs and silicon-germanium (SiGe) stressor

for p-FinFETs have been shown [5.6]-[5.9]. Nevertheless, keeping RC low is a

challenge in FinFETs with narrow fins [5.10]. Dual silicides with near band-edge

effective work function m, e.g., YbSi2-y and ErSi2-y for n-FETs, and PtSi or IrSi for

p-FETs, have been proposed to achieve low RC [5.11]. Complex fabrication processes

for incorporating dual silicides, however, may incur high incremental cost.

A single silicide material having a tunable m, adjustable to values near the

conduction band edge or near the valence band edge would be attractive for IDSAT

optimization for n- and p- FETs, respectively. A silicide formed of an alloy of nickel

(Ni) and dysprosium (Dy) [NiDySi:C] formed on Si:C substrate (with 1% carbon

content) has been shown to have a low effective m (38 % lower electron barrier

111

height ΦBn than that of NiSi:C), and has been integrated in strained n-FinFETs with

Si:C source/drain (S/D) to achieve a 30 % IDSAT enhancement over n-FinFETs with

NiSi:C S/D silicide contacts [5.12].

This work demonstrates that the effective m of the germanosilicide of Ni-Dy

alloy [NiDySiGe] formed on SiGe substrate can be tuned towards the valence band,

using a novel Aluminum (Al) implant technology. All silicidation process conditions

[Ni and Dy thickness, and rapid thermal annealing (RTA) temperature and time] were

the same as that for NiDySi:C contact fabrication in n-FinFETs [5.12]. Al implant

reduces the effective Schottky barrier height for holes ΦBp of NiDySiGe on SiGe.

The novel silicide is integrated in strained p-FinFETs with SiGe S/D stressors to

demonstrate series resistance RSD reduction leading to significant IDSAT enhancement.

Furthermore, strained n-FinFETs integrated with NiDySi:C S/D contacts were

also fabricated for a full CMOS integration. A single metal alloy (composed of Ni and

Dy) silicide used for both n- and p- FinFETs enables a cost-effective single-silicide

integration scheme for series resistance reduction in FinFET CMOS technology.


NiDySiGe/SiGe contact junctions were fabricated to extract the ΦBp of

NiDySiGe on SiGe. 200 nm of SiO2 was grown and patterned on p-type Si (100)

wafers (4 – 8 Ω-cm) to define active areas (85 µm × 85 µm squares), in the same way

as described in section 4.2 (for NiSiGe/SiGe contact junctions). 60 nm thick strained

Si0.74Ge0.26 was grown selectively in the active areas using ultra-high vacuum

chemical vapour deposition (UHVCVD). Al ions were then implanted at energy of 10

keV with a dose in the range of 0 – 2×1015 atoms/cm2. The implantation range (Rp)

was extracted to be ~13 nm using secondary-ion mass spectroscopy (SIMS). After

112

wafer cleaning using dilute hydrofluoric acid (HF), the e-beam evaporator was used to

deposit 5 nm of Dy interlayer followed by 15 nm of Ni. This was followed by

germano-silicidation anneal at a temperature of 500 °C for 30 s to form NiDySiGe

contact. Unreacted metal was removed by wet etch using 4:1 mixture of SPM at 120

°C. A backside ohmic contact was formed using 200 nm of Al to complete the

contact junction fabrication process. Blanket NiDySiGe contacts were also formed on

SiGe/p-Si substrate for sheet resistance (RS) and x-ray diffraction (XRD) phase

analysis studies. Control devices did not receive the Al implant and had nickel

germano-silicide (NiSiGe) contacts formed from 15 nm of Ni.


A. Material Characterization: Al Segregated NiDySiGe/SiGe Contact Junctions

Figure 5.1(a) shows the I-V characteristics of NiDySiGe/SiGe contact

junctions. Note that the reverse current of the control device (NiSiGe/SiGe contact

device) and of the NiDySiGe/SiGe contact device without Al implant is very close to

each other, indicating almost equal ΦBp. Increasing the dose of Al implant increases

the reverse current, indicating ΦBp lowering at the NiDySiGe/SiGe interface. The

NiDySiGe/SiGe contacts show ohmic characteristics even at a low Al implant dose of

2×1014 atoms/cm2. Figure 5.1(b) shows that the low resistivity process window of

blanket germano-silicide film is shifted by ~50 °C due to the presence of Dy, from

400 – 550 °C for pure NiSiGe to 450 – 600 °C for NiDySiGe film. The minimum

sheet resistivity values are not significantly different for the two films. Figure 5.1(c)

shows that the NiDySiGe film comprises nickel mono-germanosilicide phase only

when formed at 450 – 700 °C, although the sheet resistivity increases at temperatures

above 600 °C due to agglomeration. This phenomenon is similar to the agglomeration

113

-2 -1 0 1 2

10-3

10-2

10-1

100

101

p-Si

V, I

SiGe

NiDySiGe

SiO

2

SiO

2

NiDySiGe

0(a)

11015

21014

(atoms/cm2)

Cu

rren

t D

ensi

ty (

A/c

m2 )

Voltage V (V)

21015

Al Dose

NiSiGe -

Ref

(No A

l)

30 40 50 60

(c)

2 theta (degree)

NiS

iGe(

112)

NiS

iGe(

202)

NiS

iGe(

103)

NiS

iGe(

013)

Inte

nsi

ty (

a.u

.)

NiDySiGe: 500C

NiDySiGe: 450C

NiSiGe: 450C - No Al

NiDySiGe: 700C

NiS

iGe(

011)

NiS

iGe(

111)

NiS

iGe(

210)

300 400 500 600 700

0

100

200

300

400

500

(b)

Res

isti

vity

(

-cm

)

Temperature (C)

NiSiGe - Ref NiDySiGe

0 20 40 60 80 100100

101102

103

104

105106 Si

(d)

In

ten

sity

(a.

u.)

Average Depth (nm)

Silicide SiGe

Dy

Si

NiGe

Al

Fig. 5.1 (a) I-V characteristics of NiDySiGe/SiGe contact junctions with Al implant in the

range of 0 to 2×1015 atoms/cm2 and formed at 500 °C. The control NiSiGe/SiGe contact

junction formed at 450 °C is also shown for comparison. Inset shows the schematic of the

fabricated contact devices. (b) Comparison of the sheet resistivity of blanket NiDySiGe film

(with Al implant of 1×1015 atoms/cm2) with that of the NiSiGe control film (without any Al).

A germano-silicidation temperature in the range of 350 – 700 °C for 30 s, at intervals of 50°C

is used for the analysis. (c) XRD theta/2theta (θ/2θ) phase analysis of blanket NiDySiGe film

(with Al implant of 1×1015 atoms/cm2), formed at a temperature in the range of 450 °C – 700

°C. NiSiGe control film (formed at 450 °C) is also shown for comparison. (d) SIMS depth

profile of Al in NiDySiGe/SiGe contact junctions (with Al implant at dose of 1×1015

atoms/cm2).

of nickel mono-germanosilicide films at high temperatures (≥ 600 °C) [5.13]. From

Figs. 5.1(b) and 5.1(c), 500 °C is chosen as the germano-silicidation temperature for

p-Si

114

NiDySiGe contact formation in strained p-FinFETs with SiGe S/D. This temperature

lies within the low resistivity process window of the NiDySiGe film. The presence of

Al at the NiDySiGe/SiGe interface after germano-silicidation is observed using

secondary-ion mass spectroscopy (SIMS) [Fig. 5.1(d)]. The mechanism of ΦBp

reduction in NiDySiGe/SiGe contact devices (with Al implant) is postulated to be the

same as the modulation of ΦBp of NiSiGe on SiGe using Al implant (section 4.3.1).

Al introduces negatively charged acceptor-type trap levels in the SiGe band-gap,

forming a dipole at the NiDySiGe/SiGe interface that leads to ΦBp lowering.

Arrhenius plot based on the thermionic emission (TE) model is used to extract

the ΦBp

of NiDySiGe on SiGe for all contact junctions shown in Fig. 5.1(a) [5.14].

Equation (4.1) is used for this purpose. Appendix B can be referred for more details

regarding the Arrhenius plot method. Figure 5.2(a) plots IF/T2 versus 1000/T at

different VF for the NiDySiGe/SiGe contact device (with Al implant of 2×1014

atoms/cm2), and data-fitting gives an average ΦBp of ~0.18 eV. An extremely low VF

(0.06 V ≤ VF ≤ 0.1 V) is used to minimize the effect of junction series resistance (RJ).

Note that the fitting is only done in the low temperature part of Arrhenius plot so as to

minimize the effect of RJ over junction RC [5.15]. Figure 5.1(b) shows the extracted

ΦBp for all contact devices.

Increasing the Al implant dose from 0 to 2×1015 atoms/cm2 causes ΦBp to drop

from ~0.5 eV to ~0.12 eV for NiDySiGe/SiGe contact junctions, which is ~77 %

lower than that of the control NiSiGe/SiGe contact junction ΦBp of ~0.53 eV [Fig. 5.2

(b)]. The ΦBp of the NiDySiGe/SiGe contact device without any Al implant is ~0.5

eV, which is close to that of the control NiSiGe/SiGe contact junction, indicating

Fermi level pinning of the novel germano-silicide (similar to that of NiSiGe on SiGe),

at the silicide/SiGe interface near the mid-gap of SiGe. This is possibly due to the

115

diffusion of Dy in the NiDySiGe film towards the top surface, rather than being

present at the NiDySiGe/SiGe interface [Fig. 5.1(d)]. Note that the contact devices

did not go through the S/D implant and anneal process used for FinFETs.

Cross-sectional transmission electron microscopy (TEM) image of the

NiDySiGe/SiGe stack (formed at 500 °C) shows a uniform NiDySiGe film with a

thickness of ~25 nm. The morphology of the silicide film is not affected by the presence

of Dy and Al.

Low Temperature part

3 4 5 6

10-9

10-8

(a)VF = 0.06VVF = 0.08V

Average Bp = 0.18 eV

I F

/T2 (

A/K

2 )

1000/T (K-1)

VF = 0.10V

used for Bpextraction

0 5 10 15 20

0.1

0.2

0.3

0.4

0.5

-2 -1 0 1 210-2

10-1

100

101

102

NiDySiGe(b)

S

chot

tky

Bar

rier

Hei

ght

Bp (

eV)

Al Dose (1014atoms/cm

2)

NiSiGe - Ref: No Al

Step = 10K

T = 300K

Cu

rren

t D

ensi

ty (

A/c

m2 )

Voltage V (V)

T = 160K

Fig. 5.2 (a) Arrhenius plot to extract the ΦBp of NiDySiGe on SiGe, for the

NiDySiGe/SiGe contact device with Al implant at dose of 2×1014 atoms/cm2. IF on the y-axis

is the forward bias current measured at a particular forward bias voltage VF at temperature T.

(b) Lowering of ΦBp of NiDySiGe on SiGe, with increase in Al implant dose. All data points

are extracted by using the Arrhenius plot method [5.14]. The ΦBp of NiSiGe on SiGe (without

any Al implant, and formed at 450°C) is also shown for reference, at 0.53 eV. Inset shows

the I-V curves measured at different T for the contact device used in Fig. 5.2(a).

116

NiDySiGe

SiGe

p-Si

25 nm

Fig. 5.3 Cross-sectional TEM image of a NiDySiGe/SiGe contact device with Al implant

at dose of 1×1015 atoms/cm2.

B. Electrical Results: CMOS FinFET Integration

To integrate the NiDySiGe S/D contact (with Al implant) into tri-gate

strained p-FinFETs with raised SiGe S/D, 200-mm (100) SOI substrates with 40 nm

thick Si (fin height HFin = 40 nm) were used. Extensive details of the strained p-

FinFET fabrication process flow can be found in section 4.2 (chapter 4). Fin width

(WFin) down to 40 nm was defined using 248-nm lithography, resist trimming and

reactive-ion etching. Gate stack comprising poly-Si on 2.6 nm SiO2 was formed,

followed by S/D extension implant and silicon-nitride spacer formation with stringer

removal. After 45 nm of Si0.74Ge0.26 deposition selectively on S/D region, deep S/D

implant using BF2 was performed which was activated by RTA at 950 °C for 20 s.

Then Al ions were implanted at energy of 10 keV with a dose of 2×1014 atoms/cm2.

This was followed by the NiDySiGe contact formation. 5 nm of Dy was deposited

followed by 15 nm of Ni. Germano-silicidation was done at 500 °C for 30 s and then

the unreacted metal was removed using SPM. Control devices did not receive the Al

117

implant and had nickel germano-silicide (NiSiGe) contacts formed from 15 nm of Ni

at 450 °C.

The cross-sectional TEM image of a fabricated p-FinFET after Al implant and

NiDySiGe contact formation is shown in Fig. 5.4. Figure 5.5 shows the output and

transfer characteristics of two p-FinFETs, one with NiDySiGe contacts (with Al

implant of 2×1014 atoms/cm2) and the second one with conventional NiSiGe contacts

(without Al). The two devices are perfectly matched in terms of short channel effects,

with similar drain-induced barrier lowering (DIBL) of ~0.03 V/V, subthreshold swing

(SS) of ~90 mV/decade, and saturation threshold voltage (VT) of ~0.2 V, and have a

comparable off-state leakage current. NiDySiGe S/D contact (with Al implant) leads

to ~24 % IDSAT enhancement against conventional NiSiGe contact at a gate overdrive

of -1.2 V, in the pair of transistors shown in Fig. 5.5(a).

BOX

Si

Gate

SiGe S/D

Ni(Dy)SiGe

SiGe S/D

LG = 115 nm

SiN Spacer

A

A'

S/D

S/DGate

100 nm

Fig. 5.4 Cross-sectional TEM of a p-FinFET with 115 nm gate length. FIB cut along A-

A' (shown in the SEM image of the device in the inset of the figure) does not run over the

centre of the gate enveloping the fin and hence overestimates the LG slightly.

118

-1.2 -0.8 -0.4 0.0

0

50

100

150

200

250

300

350

400

450 Step = -0.2 V

Drain Voltage VDS

(V)

Dra

in C

urr

ent

|ID

S| (A

/m

)

24 %

VGS

- VT = -1.2 V


(a)

-3 -2 -1 0 110-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

0

2

4

6

VDS

= -1.2 V

LG = 115 nm

Gate Voltage VGS

(V)

Dra

in C

urr

ent

|ID

S| (

A/

m)

VDS

= -0.05 V

WFin

= 40 nm

RSD

= -24%


(b)R

Total =

50 mV

/ ID

S,lin (k

m

)

Fig. 5.5 (a) IDS-VDS characteristics of a matched pair of p-FinFETs with LG = 115 nm and

WFin = 40 nm, one with NiDySiGe S/D contact (with Al implant at dose of 2×1014 atoms/cm2),

and the other one being that of the reference device with NiSiGe S/D contact (without any Al

implant). (b) Y-axis on the left shows IDS-VGS characteristics of the same pair of FinFETs

used in Fig. 5.5(a). Y-axis on the right shows a graph of RTotal versus VGS for the same pair of

devices. RTotal = |VDS|/IDS,lin, where VDS = -50 mV and IDS,lin is the linear drain region.

Hyphened line shows the first order exponential fit used to extract RSD at VGS = -10 V [5.10].

Y-axis on the right in Fig. 5.5(b) shows the total resistance (RTotal) versus VGS

plot at a VDS of -50 mV, for the two FinFETs shown in Fig. 5.5(a). RTotal = VDS/IDS =

RCH + RSD, where RCH is the channel resistance. RSD is extracted using a first order

exponential fit, to be ~883 Ω-μm and ~1096 Ω-μm for p-FinFETs with NiDySiGe

contact (with Al implant) and NiSiGe S/D contacts, respectively [5.10]. There is a

~24 % drop in RSD for p-FinFETs with NiDySiGe contacts (with Al implant) which

relates directly to the IDSAT enhancement.

119

0 50 1000

100

200

300

400

500

VDS

= -1.2 V

DIBL (mV/V)

I

DS

AT @

VG

S -

VT =

-1.

2 V

(A

/m

)

NiDySiGe Best Fit

NiSiGe - Ref Best Fit

14 %

(a)

80 100 1200

100

200

300

400

500

VDS

= -1.2 V

Subthreshold Swing (mV/decade)

I D

SA

T @

VG

S -

VT =

-1.

2 V

(A

/m

)

NiDySiGe Best Fit


24 %

(b)

Fig. 5.6 (a) Plot of drive current IDSAT versus DIBL for p-FinFETs with NiDySiGe S/D

silicide (with 2×1014 Al/cm2) and for p-FinFETs with NiSiGe S/D silicide, each with a set of

30-40 devices. (b) Plot of drive current IDSAT versus Subthreshold swing SS for p-FinFETs

with NiDySiGe S/D silicide (with 2×1014 Al/cm2) and for p-FinFETs with NiSiGe S/D

silicide [for the same set of devices used in Fig. 5.6(a)].

Statistically, for a group of 30-40 devices, device performance compared at a

fixed DIBL of 65 mV/V shows IDSAT enhancement of ~14 % for p-FinFETs with

NiDySiGe S/D silicide (with Al implant at dose of 2×1014 atoms/cm2) over p-FinFETs

120

with conventional NiSiGe contacts (without Al implant) [Fig. 5.6(a)]. On the average, at

a fixed subthreshold swing SS of 110 mV/decade, ~24 % enhancement in IDSAT is

achieved with the novel NiDySiGe S/D silicide contact [Fig. 5.6(b)].

0.06 0.08 0.10 0.12 0.14

200

250

300

VDS

= -1.2 VM

ean

I D

SA

T (A

/m

)

Gate Length LG (m)

NiSiGe - RefNiDySiGe

20 %V

GS - V

T = -1.2 V

0.00 0.05 0.10 0.150

500

1000

1500

2000

2500

3000

Gate Length LG (m)

RT

otal

(

m)

20 %

NiDySiGe Best Fit


Fig. 5.7 (a) Plot of drive current as a function of LG. Each data point corresponds to an

average of 5-7 devices. P-FinFETs with NiDySiGe S/D silicide (with 2×1014 Al/cm2)

demonstrate higher IDSAT compared to p-FinFETs with NiSiGe S/D silicide. (b) Plot of RTotal

versus LG for p-FinFETs with novel NiDySiGe contacts (with Al implant of 2×1014 atoms/cm2)

and p-FinFETs with conventional NiSiGe contacts, at a linear gate overdrive of -3 V, and VDS

= -50 mV. The drop in RSD is calculated with respect to the RSD of p-FinFETs with NiDySiGe

S/D contacts (with Al implant).

(a)

(b)

121

Figure 5.7(a) plots the drive current as a function of LG and records an average

IDSAT enhancement of ~20 % for NiDySiGe p-FinFETs with Al implant (at a dose of

2×1014 atoms/cm2) compared to NiSiGe p-FinFETs. Extraction of RSD in these strained

p-FinFETs shows a 20 % drop in RSD for NiDySiGe p-FinFETs [Fig. 5.7(b)]. Linear

regression fit of data gives a y-axis intercept that allows the extraction of RSD [5.14].

The contact resistivity ρC (and hence the contact resistance RC) at the

silicide/semiconductor interface is proportional to B Ne , where ΦB is the Schottky

barrier height at the interface and N is the doping density in the semiconductor (also

discussed in section 1.2.2). With RC being a major component of RSD in FinFETs, the

low ΦBp (< 0.2 eV) at the NiDySiGe/SiGe interface (with Al implant) with respect to

that at the NiSiGe/SiGe interface of ~0.53 eV [as seen in Fig. 5.2(b)] significantly

reduces RC and increases IDSAT.

Figure 5.8 shows the cumulative distribution of p+/n drain-to-substrate junction

leakage (extracted at -1 V) for two sets of diodes, one with NiDySiGe silicided contacts

(with Al implant at dose of 2×1014 atoms/cm2) and the other one with NiSiGe contact.

Presence of Dy and Al does not degrade the drain-to-substrate junction leakage current.

The top 20 nm of SiGe is amorphized by Al implant at a dose of 2×1014 atoms/cm2

with an implant energy at 10 keV, leading to an RP of ~13 nm (Fig. 4.10). This

thickness (SiGe region with possible EOR defects) is completely consumed by 15 nm

of Ni and hence, the leakage current is not degraded by the Al implant [5.16]. The

details of the fabrication process flow of these diodes can be found in section 4.2 (chapter

4) and the metal silicidation process has been discussed in section 5.2.2.

The proposed single silicide integration scheme is ellucidated in Fig. 5.9. It is

simple and cost effective and allows for independent control of RC for both p- and n-FETs.

122

10-7 10-6 10-5 10-4

0

20

40

60

80

100

n-Si

V, I

p+-SiGe

Silicide

SiO

2

SiO

2

p+-Si

Cu

mu

lati

ve P

rob

abil

ity

(%)

Junction Leakage (A/cm2)

NiSiGe - RefNiDySiGe

Measured @ -1 V

Fig. 5.8 Junction leakage in p-FinFETs with NiDySiGe S/D silicide (with 2×1014 Al/cm2)

and p-FinFETs with NiSiGe S/D silicide is compared. Inset shows the schematic of the

fabricated diode.

BOXSi Fin

SiGe S/D Si:C S/D Si:C S/DSi Fin

SiGe S/DGate Gate

p-FinFET n-FinFET

Masking LayerAl+

Dy Deposition Followed by Ni

BOX

Si FinGateGate

NiDy

Implant

(a)

(b)

SiGe S/D SiGe S/D Si:C S/D Si:C S/DSi Fin Si Fin

BOX

Si Fin

Silicidation Anneal

BOX

Si Fin

Selective Metal Etch

(c)

(d)

Si Fin Si Fin

Gate Gate

Si Fin Si Fin

Gate Gate

NiDySiGe

NiDySiGe

NiDySi:C

NiDySi:C

Fig. 5.9 Schematics of the proposed single silicide integration solution. (a) A masking

layer is deposited on the n-FETs followed by Al+ ion implant on the entire wafer. (b) 5 nm Dy

is deposited on the entire wafer followed by 15 nm Ni deposition (c) A 500 °C anneal is

performed to form NiDySiGe for p-FET S/D contact (with Al implant) and NiDySi:C for n-

FET S/D contact (without Al implant). (d) Unreacted metal is etched away selectively using

SPM.

In addition, strained n-FinFETs (with Si:C S/D containing 1 % carbon content)

with NiDySi:C silicide contacts and NiSi:C silicide contacts were also fabricated.

123

Silicide formation process conditions, including Ni and Dy thickness, temperature, and

time, are kept exactly the same as those used for the p-FinFETs. IDS-VGS characteristics

of a pair of n-FinFETs with NiDySi:C and NiSi:C S/D silicide contact are shown in Fig.

5.10(a). The two devices (with LG of 120 nm and WFIN of 40 nm) have similar short

channel effects since the DIBL, SS and OFF Current are matched. IDS-VDS characteristics

of the same pair of n-FETs are shown in Fig. 5.10(b). The n-FinFET with NiDySi:C S/D

silicide contact demonstrates an IDSAT enhancement of ~40 % over the device with NiSi:C

contacts. The IDSAT enhancement is attributed to the reduced RC at the silicide/n+-Si:C

S/D interface due to 38 % lower ΦBn of NiDySi:C than that of NiSi:C, on Si:C [5.12].

Figure 5.11 plots IDSAT as a function of IOFF and records an average IDSAT enhancement of

~49 % for NiDySi:C n-FinFETs over NiSi:C n-FinFETs at a fixed IOFF of 100 nA/μm.

-0.5 0.0 0.5 1.0 1.5 2.010-11

10-9

10-7

10-5

10-3

VDS

= 50 mV

Gate Overdrive VGS

- VT

NiSi:C NiDySi:CD

rain

Cu

rren

t I D

S (

A/

m)

LG = 120 nm

WFin

= 40 nm

VDS

= 1.2 V (a)

0.0 0.4 0.8 1.2

0

100

200

300

400 (b) NiSi:C NiDySi:C

VGS

- VT = 1.2V

Dra

in C

urr

ent

I DS (A

/m

)

Drain Voltage VDS

(V)

Step = 0.2 V

40 %

Fig. 5.10 (a) IDS-VGS characteristic of a NiDySi:C contacted strained n-FinFET and a

NiSi:C contacted strained n-FinFET, having similar DIBL, SS and IOFF. (b) IDS-VDS

characteristic of the same pair of devices show 40 % IDSAT enhancement with NiDySi:C S/D

contacts.

124

0 100 200 300 40010-10

10-9

10-8

10-7

10-6

NiSi:C NiDySi:C

I OF

F (

A/

m)

@ V

GS =

0.2

V

IDSAT

(A/m) @ VGS

= 1.4 V

49 %

Fig. 5.11 Plot of ON current (IDSAT extracted at VGS = 1.4 V) versus OFF current (IOFF

extracted at VGS = 0.2 V) for strained n-FinFETs with NiDySi:C S/D contact against devices

with NiSi:C S/D contacts. A VDS of 1.2 V is used for the data extraction.


Ni-Dy alloy silicide has been demonstrated as a possible candidate for single

silicide CMOS integration scheme. ΦBp modulation of novel NiDySiGe on SiGe using

Al implant is shown to achieve a low RC silicide contact on strained p-FinFETs,

leading to an IDSAT enhancement of ~20 % against p-FinFETs with conventional NiSiGe

contacts (without Al implant). For strained n-FinFETs (without Al implant), NiDySi:C

S/D contacts, formed simultaneously, lead to an average IDSAT enhancement of ~49 %

over n-FinFETs with NiSi:C silicide contacts.

125

5.3 NiSi based Single-Silicide Contact Technology using Al+ and S+

Double Implant

5.3.1 Motivation

High series resistance RSD is a major technology roadblock to the continual

CMOS performance scaling [5.1], [5.2]. The silicide contact resistance RC is a major

component of RSD and needs to be minimized for both p- and n-FETs. However,

simultaneous achievement of greatly reduced RC for p- and n-FETs is not possible using

the conventional nickel silicide (NiSi) process. The high RC issue is aggravated in

multiple gate transistors or FinFETs, which may be introduced in sub-22 nm logic

technology node [5.10]. Use of new materials, e.g. nickel-dysprosium alloy silicide with

Al implant has been explored (section 5.2). However, the electron barrier height ΦBn

achieved (ΦBn = 0.43 eV [5.12]) was not band-edge, leaving plenty of room for further

improvement. Another option which is the integration of dual silicide materials using

multiple metals/anneals and two additional lithographic steps is costly and may not

achieve band-edge barrier heights.

In this work, the demonstration of a dual near-band-edge NiSi using aluminum

(Al) and sulfur (S) implants for RC minimization in both p- and n- FinFETs is reported

using just one mask. Al is implanted in strained p-FinFETs (with SiGe S/D) only (one

mask); S is implanted in both p- and n- FinFETs (no mask). The compensation effects of

Al and S implants are investigated for the first time. The new observation is then

exploited for process simplification. By choosing a higher dose for Al than S in p-

FinFETs, its effect overwhelms that of S, thus effectively lowering the hole barrier height

ΦBp by interfacial dipole mechanism [discussed in section 4.3.1]. S in n-FinFETs lowers

the ΦBn, consistent with other reports [5.17]. This leads to a simple and cost-effective

integration scheme.

126

5.3.2 Contact Technology: Implant Interactions

A. Fabrication of Contact Structures and Implant Conditions

To prepare NiSiGe/SiGe contact junctions to extract ΦBp (for p-FETs), 200-mm

p-Si wafers with SiO2 isolation regions were patterned. Strained Si0.75Ge0.25 with a

thickness of 60 nm was deposited selectively on S/D regions using UHVCVD. The

wafers received Al implant at energy of 10 keV with dose splits of 2×1014 and 1×1015

atoms/cm2. This was followed by S implant at energy of 10 keV with dose splits of

5×1013 and 1×1014 atoms/cm2, giving a total of 4 double-implant splits. Silicidation was

done at 450 °C for 30 s using 15 nm of Ni. The reference silicide films did not go through

any implant. Wafers without SiGe growth were used for ΦBn extraction (for n-FETs)

using NiSi/Si contact junctions and underwent S implant only, giving a total of 2 implant

splits. Blanket silicide films were used for sheet resistance RS and x-ray diffraction (XRD)

phase analysis studies.

B. Material Characterization

NiSiGe/SiGe contact devices with Al and S double-implant show ohmic behavior,

regardless of the implant dose split (Fig. 5.12). Reverse current of NiSiGe/SiGe contact

device increases with the double-implant of Al and S, pointing towards a much lower

ΦBp. ΦB

p is extracted using the Arrhenius plot and is shown in Fig. 5.13(a) for the sample

with Al implant dose of 1×1015 atoms/cm2 and S implant dose of 5×1013 atoms/cm2 [5.14].

All the four NiSiGe/SiGe contact devices with double-implant split have approximately

the same ΦBp as their reverse currents are the same (Fig. 5.12). Low temperature part of

the plot is used for ΦBp extraction [5.15]. ΦB

p drops from 0.53 eV to 0.16 eV (ΔΦBp =

0.37 eV or 70%) [Fig. 5.13(b)]. Hence, near-band-edge ΦBp is achieved for p-FinFETs.

127

-2 -1 0 1 2

10-2

10-1

100

101

102NiSiGe/SiGe/p-Si

S: 1

S: 5

Cu

rren

t (A

/cm

2 )

Voltage (V)

Al: 2

Al: 2

Al: 1

Al: 1S: 1

S: 5

NiSiGe Ref: No I/I

Dose (atoms/cm2)

Reverse CurrentIncrease in

with Al+S I/I

Fig. 5.12 I-V characteristics of NiSiGe/SiGe contact junctions with Al and S double-

implant. Al is implanted first, followed by S. The control NiSiGe/SiGe contact junction is

also shown for comparison.

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

10-9

10-8

10-7(atoms/cm2)

S: 51013Al: 11015

Low Temperature part

of the plot used for Bp

extraction

I F

/T 2

(A

/K2 )

1000/T (K-1)

VF = 0.06 V

VF = 0.08 V

VF = 0.10 V

I/I Dose

(a)

p-Si

V, I

SiGe

NiSiGe

SiO

2

SiO

2

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Al + S I/I

0.16 eV

0.53 eV

Hol

e B

arri

er H

eigh

t

Bp (

eV)

Ref: No I/I

NiSiGe/SiGe/p-Si

Bp = 0.37 eV

(b)

Fig. 5.13 (a) Arrhenius plot to extract the ΦBp of NiSiGe on SiGe, for the NiSiGe/SiGe

contact device with Al implant at dose of 1×1015 atoms/cm2 and S implant at dose of 5×1013

atoms/cm2. IF on the y-axis is the forward bias current measured at a particular forward bias

voltage VF at temperature T. Schematic of the fabricated contact devices is shown in the inset.

(b) Lowering of ΦBp of NiSiGe on SiGe with the Al and S double-implant. The ΦB

p of

NiSiGe on SiGe (without the double-implant) is also shown for reference, at 0.53 eV.

128

Note that for the reference contact device without Al and S implant, ΦBp is extracted to be

~0.53 eV [also shown in Fig. 5.2(b)].

SIMS depth profile shows that S does not pile up at the NiSiGe/SiGe interface

(Fig. 5.14). S is thus overwhelmed by Al atoms at the interface by virtue of the fact that

the S implant dose is lower than that of Al. Note that the implantation range (RP) of both

Al and S is the same (~13 nm) at implantation energy of 10 keV. Sheet resistance RS of

the NiSiGe film is not appreciably affected by the double-implant technology [Fig.

5.15(a)]. Figure 5.15(b) shows that the low resistivity phase of the germano-silicide film

is also not affected by the implant species, which can be generalized for the four double

implant splits, since the rest of the two splits [not shown in Fig. 5.15(b)] have lower

implant dose.

0 20 40 60 80 100 120 140100

101

102

103

104

105

106

Al: 2S: 1

Al: 2S: 5

Al: 1S: 1

Inte

nsi

ty (

a.u

.)

Depth (nm)

Al

NiSiGe SiGe Si

S

Al: 1S: 5

Implant Dose (atoms/cm2)

Fig. 5.14 SIMS depth profile of Al and S in the four NiSiGe/SiGe contact junction splits

with the double-implant of Al and S ions.

129

6

8

10

12

14

16

+

+

+

Al: 11015

S: 11014

Al: 11015

S: 51013

Al: 21014

S: 11014

Al: 21014

S: 51013

Sh

eet

Res

ista

nce

RS (

/sq

)

Ref:No I/I

Implant Dose (atoms/cm2)

+

NiSiGe/SiGe/p-Si

(a)

20 30 40 50 60

(atoms/cm2)+ S: 1

NiS

iGe

(013

)

NiS

iGe(

202)

NiS

iGe

(112

)

NiS

iGe

(102

)

Inte

nsi

ty (

a.u

.)

2 Theta (degree)

NiS

iGe

(002

)

Ref: No I/I

Al: 2

+ S: 1Al: 1

(atoms/cm2)

NiSiGe

(b)

Fig. 5.15 (a) Comparison of sheet resistance RS of the four blanket NiSiGe films

(corresponding to the four Al + S double-implant splits) with that of the NiSiGe control film

(without any implant). (b) XRD theta/2theta (θ/2θ) phase analysis of blanket NiSiGe film

(with Al and S double-implant). NiSiGe control film is shown for comparison.

NiSi/p-Si contact devices with and without S implant, formed simultaneously (for

extraction of ΦBn for n-FETs), show an increase in ΦB

p with S implant, as shown in Fig.

5.16 and Fig. 5.17. The reverse current in NiSi/p-Si contact devices decreases with the

130

-2 -1 0 1 2

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

p-Si

V, INiSi

SiO2SiO2

Voltage (V)

Cu

rren

t (A

/cm

2 )

NiSi/p-Si Ref: No I/I

S: 1 S: 5

Dose (atoms/cm2)

Reverse CurrentDecrease in

with S I/I

Fig. 5.16 I-V characteristics of NiSi/p-Si contact junctions with S implant in the range of 0

to 1×1014 atoms/cm2 and formed at 450 °C. The reference NiSi/p-Si contact junction without

S implant is shown for comparison purposes. Inset shows the schematic of the fabricated

device.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8(

B

n) [5.17](B

p)

15 0

NiSi/n-Si

Sch

ottk

y B

arri

er H

eigh

t (e

V)

0

NiSi/p-Si

S Implant Dose (atoms/cm2)

15

Increasein

B

p

B

n =0.44 eV

B

n =0.53 eV

Fig. 5.17 Extracted ΦBp of NiSi contact on p-Si with and without S implant. With increase

in S implant dose, ΦBp increases leading to a corresponding drop in ΦB

n since the sum of ΦBp

and ΦBn is the bandgap of Si.

131

0 20 40 60 80 100 120 140

101

102

103

104

3

4

5

6

(a)

Sh

eet

Res

ista

nce

( /s

q)

Depth (nm)

Inte

nsi

ty (

a.u

.)

NiSi Si

S: 1 S: 5

Dose (atoms/cm2)

0 51013 11014

S Implant Dose(atoms/cm2)

20 30 40 50 60

(b)

NiSi

Ref: NoS I/I

NiS

i (01

3)

NiS

i (10

3)

NiS

i (20

2)

NiS

i (11

2)

NiS

i (10

2)

Inte

nsi

ty (

a.u

.)

2 Theta (degree)

NiS

i (00

2)

(atoms/cm2)S: 1

Fig. 5.18 (a) SIMS depth profile of S in the two NiSi/p-Si contact devices implanted with S.

There is clear evidence of S segregation at the NiSi/p-Si interface. Inset shows the sheet

resistance RS of the blanket NiSi films with and without S implant. (b) XRD theta/2theta

(θ/2θ) phase analysis of blanket NiSi films (formed on p-Si substrate) with and without S

implant dose of 1×1014 atoms/cm2. Only mono-silicide peaks are observed for both the films,

with exactly the same orientation as that of the ref. device.

introduction of S implant, indicating an increase in ΦBp. ΦB

p is extracted using the

Thermionic emission (TE) model [using Equation (2.1) and Equation (2.2)], and it

increases with the S implant dose, as shown in Fig. 5.17. Correspondingly, ΦBn

becomes smaller (i.e., the silicide Fermi level moves towards the conduction band-

edge) with S implant. Sub-0.2 eV ΦBn can be obtained at S dose of 5×1013 and above,

for NiSi/n-Si contacts (Fig. 5.17) [5.17]. S segregates at the NiSi/p-Si interface [Fig.

5.18(a)] leading to lowering of ΦBn, which is consistent with other reports [5.17]. Higher

S implant dose leads to a higher concentration of S at the interface, as shown in Fig.

5.18(a), thus leading to a larger Schottky barrier modulation (Fig. 5.17). The inset of Fig.

5.18(a) shows that S implant does not affect the sheet resistance RS of the thin NiSi film.

Furthermore, the low resistivity nickel mono-silicide phase of the NiSi film is also not

affected by the S implant step [Fig. 5.18(b)].

132

(a)

SiGe

p-Si20 nm (b)

Amorphized Top Layer

33 nm

(20 nm)

(d)(c)

SiGe

p-Si

p-Si

p-Si

NiSiNiSiGe40 nm

20 nm

20 nm20 nm

(10 nm)

Silicidation consumedamorphized region

Fig. 5.19 Cross-sectional TEM images of contact devices before and after silicidation. (a)

Double-implant (Al at dose of 2×1014 atoms/cm2 and S at dose of 1×1014 atoms/cm2) into

SiGe amorphizes top 20 nm. (b) S implant at dose of 1×1014 atoms/cm2 in Si amorphizes top

10 nm. (c), (d) Silicide formed consumes the amorphized region.

Top 20 nm of SiGe epilayer is amorphized during the double-implant split

consisting of Al implant at dose of 2×1014 atoms/cm2 and S implant at dose of 1×104

atoms/cm2 (corresponding to the NiSiGe/SiGe contact device split for p-FETs), as

shown in Fig. 5.19(a). NiSiGe formed subsequently consumes the amorphized part of

SiGe [Fig. 5.19(b)]. Similarly, top 10 nm of Si is amorphized during S implant at dose

of 1×104 atoms/cm2 (corresponding to the NiSi/p-Si contact device split for n-FETs)

[Fig. 5.19(c)], which gets consumed during subsequent nickel silicidation [Fig.

5.19(d)]. Thus the silicide morphology is unaffected by the presence of implant species

(Al and S double-implant for NiSiGe, and S implant for NiSi) [Fig. 5.19]. This may not

be true for the double-implant split consisting of Al implant at the higher dose of 1×1015

atoms/cm2 (corresponding to the NiSiGe/SiGe contact device split for p-FETs). But,

133

the ΦBp corresponding to the four double-implant splits (for p-FETs) is the same [Fig.

5.13(b)]. Thus, a lower double-implant dose (consisting of Al implant dose of 2×1014

atoms/cm2, followed by S implant dose of 5×1013 atoms/cm2) is used for p-FinFET

integration. Correspondingly, n-FinFETs were integrated with S implant at dose of

5×1013 atoms/cm2. Details of the CMOS integration scheme will discussed in the next

section.

5.3.3 FinFET Integration and Electrical Results

Key process steps for forming strained p-channel SOI FinFETs (fin height HFin =

40 nm) with raised SiGe S/D stressors are shown in Fig. 5.20(a). Extensive details of the

strained p-FinFET fabrication process flow can be found in section 4.2 (chapter 4).

Fin width WFin down to 40 nm was defined using 248-nm lithography, resist trimming

and reactive ion etching (RIE). Gate stack comprising poly-Si on 2.6 nm SiO2 was

formed followed by SDE implant and spacer formation. 45 nm of Si0.75Ge0.25 epilayer

was grown selectively on S/D regions using UHVCVD to generate uniaxial

compressive strain in the channel for hole mobility enhancement. This was followed

by deep S/D implant and activation.

The contact silicide (with low contact resistance) formation process started

with the ion-implantation of Al (at dose of 2×1014 atoms/cm2), followed by the ion-

implantation of S (at dose of 5×1013 atoms/cm2). Both implants were done at energy

of 10 keV. Following which, 15 nm of Ni was deposited and germano-silicidation

was done at 450 °C to complete the FinFET fabrication process. Figure 5.20(b)

shows the cross-sectional TEM image of a completed p-FinFET after Al + S double-

implant and NiSiGe contact formation.

134

Channel ImplantFin DefinitionSiO2 Gate Oxidation (2.6 nm)Poly-Si Gate DefinitionSpacer Formation with Stringer RemovalSi0.75Ge0.25 Epilayer Growth on S/DDeep S/D Implant and ActivationAl+ I/I @ 2×1014 atoms-cm-2

S+ I/I @ 5×1013 atoms-cm-2

NiSiGe formation @ 450 °CSelective Metal Etch

BOXSi

Gate

SiGe S/D

NiSiGe

SiGe S/D

LG = 85 nm

SiN Spacer

100 nm

NiSi

A

A'

S/D

S/D

Gate

G

Fig. 5.20 (a) Key Process steps for the fabrication of p-FinFETs with NiSiGe silicided S/D

contacts, and integrated with the double-implant of with Al and S for contact resistance

reduction. Control devices did not receive the double-implant. (b) Cross-sectional TEM

image of a fabricated p-FinFET. Inset shows the top-view SEM of the device. FIB is done

along the line A-A' which overestimates LG.

IDS-VGS characteristics (transfer characteristics) and IDS-VDS characteristics (output

characteristics) of a pair of p-FinFETs, with and without the double-implant, are shown in

Fig. 5.21(a) and 5.21(b), respectively. The two devices have comparable SS (~85

mV/decade), DIBL (~55 mV/V), VT (~ -0.2 V), and OFF state leakage current, and hence

are perfectly matched in terms of their effective channel length L. The device that

received Al + S double-implant has a 27 % higher IDSAT than the one without [Fig.

5.21(b)]. Figure 5.22 shows the plot of total resistance RTotal versus gate voltage VGS for

the same pair of transistors shown in Fig. 5.21. A first order exponential fit is used to

extract RSD at a high VGS of -10 V [5.10]. The double-implant reduced RSD by 28 %. This

drop in RSD is directly proportional to the 27 % increase in drive current shown in Fig.

5.21(b).

(a) (b)(b)

135

-3 -2 -1 0 110-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

(a)

Gate Voltage VGS (V)

Dra

in C

urr

ent

|ID

S| (

A/

m)

DIBL = 55 mV/VSS = 85 mV/decade

VDS = - 50 mV

VDS = - 1.2 V

NiSiGe - Al + S I/I NiSiGe - Ref

LG = 75 nmWFin = 40 nm

-1.2 -0.8 -0.4 0.0

0

50

100

150

200

250

300

350

400

Drain Voltage VDS (V)

Dra

in C

urr

ent

|ID

S| (A

/m

) NiSiGe - Al + S I/I NiSiGe - Ref

Step = 0.2 V

VGS - VT = -1.2 V

27%

(b)

Fig. 5.21 (a) IDS-VGS characteristics of a pair of p-FinFETs with and without the double-

implant (Al and S) and having comparable short channel effects. (b) IDS-VDS characteristics of

the same set of p-FinFETs, showing 27 % higher IDSAT for the device with double-implant (Al

and S).

-10 -8 -6 -4 -2 0500

1000

1500

2000

2500

3000

3500

4000

Tot

al R

esis

tan

ce

Gate Voltage VGS

(V)

RT

otal =

50

mV

/ID

S,li

n (

m)

RSD = 28 %

NiSiGe - Ref NiSiGe - Al + S I/I

Fig. 5.22 Plot of total resistance RTotal versus VGS for the pair of p-FinFETs used in Fig.

5.21. RTotal = |VDS|/IDS,lin, where VDS = -50 mV and IDS,lin is the drain current in the linear

region. RSD is extracted at a high gate voltage of -10 V using a first order exponential fit

[5.10]. The drop in RSD is measured with respect to the RSD of the p-FinFET that went

through the double-implant.

136

0 50 100 150 200 250 3000

100

200

300

400

500

VDS

= -1.2 V

DIBL (mV/V)

I D

SA

T @

VG

S -

VT =

-1.

2 V

(A

/m

)37 %

NiSiGe - Al + S I/I NiSiGe - Ref

60 80 100 120 1400

100

200

300

400

500

VDS

= -1.2 V

Subthreshold Swing (mV/decade)

I D

SA

T @

VG

S -

VT =

-1.

2 V

(A

/m

)

35%

NiSiGe - Al + S I/INiSiGe - Ref

Fig. 5.23 (a) Plot of drive current IDSAT as a function of DIBL, both for p-FinFETs with and

without the double-implant of Al + S. (b) Plot of IDSAT versus subthreshold swing SS, both

for p-FinFETs with and without the double-implant. In both the plots [5.23(a) and 5.23(b)],

best-fit lines (solid line for the devices with the double-implant and dashed line for the control

devices) are drawn using linear regression. IDSAT for all devices is extracted at a fixed gate

overdrive of -1.2 V, with drain voltage kept at -1.2 V.

0.05 0.10 0.15 0.20 0.25

100

150

200

250

300

350

10-7 10-6

020406080

100P

rob

abil

ity

(%)

Cu

mu

lati

ve

(A/cm2)Junction Leakage

VDS

= -1.2 V

Mea

n I

DS

AT (A

/m

)

Gate Length LG (m)

52 %

VGS

- VT = -1.2 V

NiSiGe - Al + S I/INiSiGe - Ref

Fig. 5.24 Plot of mean IDSAT as a function of LG for devices with and without the double-

implant (Al and S). Both, IDSAT (for both sets of devices) and ∆IDSAT (increase in IDSAT for

devices with double-implant over control devices) increase with LG scaling. Each data point

is an average of ~5-7 devices. P+\n drain-to-body junction leakage is shown in the inset, and

is unaffected by the double-implant technology. Best-fit lines (solid line for the devices with

the double-implant and dashed line for the control devices) are drawn using linear regression.

(a) (b)

137

Statistical data show a significant performance enhancement when IDSAT is

compared against short channel effects. At a DIBL of 100 mV/V, p-FinFETs with the

double-implant (Al and S) show 37 % higher IDSAT against the control devices [Fig.

5.23(a)]. Again, at a fixed SS of 100 mV/decade, 35 % enhancement in IDSAT is

achieved with the double-implant [Fig. 5.23(b)]. On the average, the mean IDSAT

increases by 52 % for devices with the double implant (Fig. 5.24). This enhancement in

drive current is achieved as a result of RC reduction related to the substantial lowering of

the hole Schottky barrier height at the NiSiGe/(p+-SiGe S/D) interface due to the double-

implant of Al and S. RC reduction leads to 58 % reduction in RSD, which is extracted

from the RTotal versus LG plot shown in Fig. 5.25.

0.00 0.05 0.10 0.15 0.20 0.250

2000

4000

6000

8000

Gate Length LG (m)

Tot

al R

esis

tan

ce R

Tot

al (

m)

58 %

NiSiGe - Ref NiSiGe - Al + S I/I

VDS

= -50 mV

Same Slope

Fig. 5.25 Plot of RTotal versus LG showing reduction in RSD by 58 % (calculated with respect

to the control devices) for p-FinFETs with the double implant of Al and S ions. Best-fit lines

for the two sets of devices, with and without the double-implant are drawn using linear

regression. Solid line is for the devices with the double-implant and dashed line is for the

control devices. RSD is extracted by extrapolation of the best-fit lines to zero gate length LG.

No mobility variation is observed in the two set of devices due to the same slope of the best-

fit lines. RTotal is calculated at a linear gate overdrive of -3 V for every data point.

138

The proposed cost-effective single-silicide integration scheme is shown in Fig.

5.26. It utilizes only one additional mask and two ion-implant steps for independent

contact resistance minimization in both p- and n- FETs. N-FinFETs, fabricated

simultaneously with p-FinFETs, received S implant for RC reduction on n+ contacts.

BOXSi Fin

SiGe S/DSi Fin

SiGe S/DG G

p-FET n-FETAl+ Implant(a)

Si S/D Si S/D

Masking Layer

S+ Implant (No Mask)(b)

BOXSi Fin

SiGe S/DSi Fin

SiGe S/DG G

Si S/D Si S/D

Blanket Ni Deposition(c)

BOX

Si Fin

Silicidation Anneal and Selective Metal Etch

(d)

Si Fin Si Fin

G G

NiSiGe NiSi

BOXSi Fin

GSi S/D Si S/D

Si Fin

GSiGe S/D SiGe S/D

Fig. 5.26 Schematics of the proposed single silicide integration solution. (a) A masking

layer is deposited on the n-FETs followed by Al ion-implant. (b) Blanket S implant is done

afterwards. (c) Ni is deposited on the entire wafer. (d) A 450 °C anneal is performed to form

NiSiGe for p-FET S/D contact and NiSi for n-FET S/D contact, followed by unreacted metal

removal using SPM.

139

-1 0 1 210-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Gate Voltage VGS

(V)

Dra

in C

urr

ent

|ID

S| (

A/

m)

DIBL = 52 mV/VSS = 88 mV/decade

VDS

= 50 mVV

DS = 1.2 V

NiSi - S I/I NiSi - Ref

LG = 75 nmWFin = 30 nm

0.0 0.4 0.8 1.2

0

50

100

150

200

250

300

350

400

Drain Voltage VDS

(V)

Dra

in C

urr

ent

|ID

S| (A

/m

) NiSi - S I/I NiSi - Ref

VGS

- VT = 1.2 V 29 %

Step = 0.2 V

Fig. 5.27 (a) IDS-VGS characteristic of a pair of n-FinFETs (LG = 75 nm, WFin = 30 nm) with

and without S implant. Both the devices have comparable short channel effects, due to

similar DIBL (~52 mV/V), SS (~88 mV/decade), VT (~0.1 V) and OFF state current. (b) IDS-

VDS characteristics of the same pair of devices show 29 % IDSAT enhancement for the device

with S implant, at a gate overdrive of 1.2 V, with VDS also at 1.2 V.

0 100 200 300 40010-11

10-10

10-9

10-8

10-7

10-6

10-5

I OF

F (

A/

m)

@ V

GS =

0 V

IDSAT

(A/m) @ VGS

= 1.2 V

35%

NiSi - S I/INiSi - Ref

Fig. 5.28 Plot of ON current (IDSAT extracted at VGS = 1.2 V) versus OFF current (IOFF

extracted at VGS = 0 V) for n-FinFETs with and without S implant. VDS is kept at 1.2 V. 30-

40 devices each are used for the statistical plot.

(a) (b)

140

IDS-VGS and IDS-VDS characteristics of a matched pair of devices (in terms of short channel

effect) show an IDSAT enhancement of 29 % [Fig. 5.27(a) and 5.27(b)]. At a fixed IOFF of

100 nA/um, devices with S implant show an IDSAT enhancement of 35 %. This is due to a

lower effective ΦBn (ΔΦB

p = 0.44 eV, or 66%) of NiSi on n-Si contributed by the S

implant (Fig. 5.17).


A novel single-silicide single mask integration scheme is demonstrated for achieving

dual near-band-edge barrier height and RC reduction in both p- and n- FinFETs. The

approach in this work relies on new observations related to the interaction of Al and S

implants and their impact on ΦBp. For p-FinFETs, both Al and S were implanted (Al dose

is higher than S dose) prior to NiSiGe formation on SiGe to give 0.37 eV lower ΦBp and

52 % higher IDSAT compared to an un-implanted control. The n-FinFETs, formed

simultaneously, received only S implant and have 35 % higher IDSAT and 0.44 eV lower

ΦBn compared to un-implanted control.

141

5.4 References







1259-1264, May 2008.

[5.2] S.-D. Kim, S. Narasimha, and K. Rim, “An integrated methodology for accurate

extraction of S/D series resistance components in nanoscale MOSFETs,” IEDM Tech

Dig., pp. 149-152, 2005.



[5.4] H. Shang, L. Chang, X. Wang, M. Rooks, Y. Zhang, B. To, K. Babich, G. Totir, Y.

Sun, E. Kiewra, M. Ieong, and W. Haensch, “Investigation of FinFET devices for 32

nm technologies and beyond,” VLSI Symp. Tech. Dig., pp. 66-67, 2006.

[5.5] N. Collaert, R. Rooyackers, A. Hikavyy, A. Dixit, F. Leys, P. Verheyen, R. Loo, M.

Jurczak, and S. Biesemans, “Multi-gate devices for the 32 nm technology node and

beyond: Challenges for selective epitaxial growth,” Thin Solid Films, vol. 517, pp.

101-104, 2008.

[5.6] T.-Y. Liow, K.-M. Tan, D. Weeks, R. T. P. Lee, M. Zhu, K.-M. Hoe, C.-H. Tung, M.

Bauer, J. Spear, S. G. Thomas, G. S. Samudra, N. Balasubramanian, and Y.-C. Yeo,

“Strained n-channel FinFETs featuring in-situ doped silicon-carbon (Si1-yCy) source

and drain stressors with high carbon content,” IEEE Trans. Electron Devices, vol. 55,

no. 9, pp. 2475-2483, Sep. 2008.





the source and drain regions,” in VLSI Symp. Tech. Dig., pp. 194-195, 2005.



142

transistor architecture with high-k gate dielectrics, metal gates and strain

engineering, ” in VLSI Symp. Tech. Dig., pp. 62-63, 2006.



shaped silicon-germanium source and drain stressors,” IEEE Electron Device Letters,

vol. 28, no. 10, pp. 905-908, Oct. 2007.



Electron Devices, vol. 52, no. 6, pp. 1132-1140, June 2005.

[5.11] K. Maex, and M. Van Rossum, Properties of Metal Silicides, IEE-INSPEC, London,

1995.





Ni(M)Si:C metal silicides and pulsed laser annealing,” IEDM Tech Dig., pp. 685-688,

2007.

[5.13] S.-L. Zhang, “Nickel-based contact metallization for SiGe MOSFETs: progress and

challenges,” Microelectronic Engineering, vol. 70, pp. 174-185, 2003.

[5.14] D. K. Schroder, Semiconductor material and device characterization, third edition,

IEEE, New York, 2006.


metallic source drain metal–oxide–semiconductor field effect transistors,” J. Appl.

Phys., vol. 96, no. 1, pp. 729-737, 2004.

[5.16] L. J. Chen, Silicide technology for integrated circuits, IEE, London, 2004.


barrier heights by sulfur segregation during Ni silicidation” Appl. Phys. Lett., vol. 86,

062108, 2005.

143

CHAPTER 6

Summary and Future Work

6.1 Summary

The main focus of this thesis is to develop techniques to lower Schottky

barrier height ΦB at the interface between metal-silicide and heavily-doped

Source/Drain (S/D) region of CMOS FETs. New materials and process are explored

to achieve the desired result. Lowering of ΦB ultimately leads to reduction in

parasitic series resistance RSD, which is a major bottleneck for achieving performance

targets in CMOS transistors for sub-22 nm technology nodes [6.1], [6.2].

In particular, through ion-implantation of impurity elements at the interface

between metal-silicide and the S/D material of MOSFETs, tailoring of ΦB has been

performed. Furthermore, lowering of ΦB through substrate engineering is also

investigated. Only nickel (Ni)-based silicides (either pure nickel silicide or a silicide

formed of an alloy of nickel and a rare-earth metal) are used in this work for their ease

of adoption by the semiconductor industry with minimal process and cost overheads

[6.3]. Extensive material characterization is done to develop processes for

ΦB modulation and then they are integrated in p- and n-channel FETs (strained and/

unstrained) to achieve drive current enhancement through series resistance reduction.

The FinFET device architecture is projected to be introduced at the sub-22 nm

technology node. FinFETs suffer less from mobility degradation and random dopant

fluctuation, and have better short channel effect control than planar transistors [6.4],

[6.5]. Nevertheless, there are challenges associated with the adoption of FinFETs or

multiple-gate field-effect transistors (MuGFETs) for manufacturing. A prominent

144

issue is the high RSD, which is an even bigger issue in the FinFET architecture than in

planar FETs [6.6]. The ΦB-lowering modules developed in this thesis have been

integrated on tri-gate SOI FinFETs. Extensive device fabrication and electrical data

analysis is performed. In summary, the main contributions of this thesis are listed in

Table 6.1 and elucidated in the sub-sections to follow.

Table 6.1 A summary of effective Schottky barrier height and drive current enhancement

achieved by the various Schottky barrier engineering technologies demonstrated in this thesis,

except for two entries taken from [6.7] and [6.8]. Note that ΦBp + ΦB

n ≈ bandgap of

semiconductor.

Schottky Barrier Engineering

Technology

ΦBp

(eV)

ΦBn

(eV)

IDSAT Enhancement

(%)

A. p-FinFETs with Si S/D

1. NiSi

2. NiSi with Al+ I/I

3. NiSi with Co+ I/I

4. NiSi with Cd+ I/I

5. NiSi with Zn+ I/I

6. NiSi with Mg+ I/I

0.40 [6.9]

0.12 [6.10]

0.59

0.59

0.59

0.67

0.67 [6.9]

–

–

–

–

–

–

15 [6.11]

–

–

–

–

B. n-FinFETs with Si S/D

1. NiSi with S+ I/I

–

0.14 [6.7]

35

C. Strained p-FinFETs with SiGe S/D

1. NiSiGe

2. NiSiGe with Al+ I/I

3. NiDySiGe with Al+ I/I

4. NiSiGe with (Al+) + (S+) I/I

0.53 [6.12]

0.068 [6.12]

0.12 [6.14]

0.16

–

–

–

–

–

25 [6.13]

20 [6.15]

52

D. Strained n-FinFETs with Si1-xCx S/D

1. NiSi1-xCx (x = 0.02)

2. NiSi1-xCx (x = 0.01)

3. NiDySi1-xCx (x = 0.01)

–

–

–

0.54 [6.16]

0.61 [6.16]

0.43 [6.8]

–

–

49

145

6.1.1 Material Screening for Modulation of Hole Schottky Barrier

Height of NiSi on p-Si

In this work a range of materials were screened to investigate their possible

application in lowering of the effective hole Schottky barrier height ΦBp of nickel

silicide (NiSi) on p-Si. These materials (impurity elements) were ion-implanted in the

Si active region before nickel deposition and silicidation, and the whole process was

tuned to make sure that enough concentration of the implanted species is present at

the NiSi/p-Si interface after silicidation. The materials that were experimented with

in this work are aluminum (Al), cobalt (Co), cadmium (Cd), zinc (Zn), and

magnesium (Mg). These materials were handpicked by studying the trap levels that

they introduce in the silicon bandgap. The central idea was to select the elements that

introduce acceptor-type trap level in the silicon bandgap near its valence band. This

would result in a dipole moment at the NiSi/p-Si interface pointing towards the NiSi

side, leading to downward band banding of the valence and conduction band of Si.

This would eventually lead to thinning down of the Schottky barrier width at the

NiSi/p-Si interface causing significant hole tunneling through it, and the lowering of

the effective ΦBp. Mg atom introduces only donor-type trap levels near the

conduction band of Si and was selected to check for the complementary effect of

increase in ΦBp due to a dipole moment pointing in the reverse direction (i.e., towards

the Si side of the interface).

Extensive I-V characterization and SIMS results were presented. Most

implanted impurities segregate at the NiSi/p-Si interface after silicidation leading to

modulation of ΦBp. The effect of the thickness of silicide on ΦB

p was also

investigated. It was shown that Al implant into p-Si before Ni deposition and

silicidation leads to lowering of ΦBp and an ohmic contact is thus formed. Mg implant

146

was shown to have a complementary effect of increase in ΦBp (or a reduction in

effective electron Schottky barrier height ΦBn), which is beneficial for contact

resistance reduction in n-FETs. Approximately 270 meV lowering of ΦBn is achieved

with Mg implant.

For the case of Co, Cd and Zn, an increase in ΦBp was observed, which is

again directly related to the reduction in ΦBn. Approximately 190 meV lowering in

ΦBn is achieved with the optimized implant technology involving either one of Co, Cd,

and Zn.

6.1.2 Hole Schottky Barrier Height Tuning of NiSi on p-Si using

Aluminum Implant and Segregation

In this work, we reported the tuning of ΦBp at the NiSi/p-Si junction by the

introduction of aluminum (Al) using ion-implantation and its segregation after nickel

deposition and silicidation. The ΦBp was found to decrease with increasing

concentration of Al at the NiSi/p-Si interface. We demonstrated the achievement of

one of the lowest reported ΦBp of 0.12 eV, with less than 0.1 atomic percent Al in

NiSi, without any degradation of the resistivity and the thermodynamic phase of the

thin NiSi film. This is extremely promising for application in p-FETs. Detailed

material characterization results were presented. The impact of Al implant dose and

the silicide thickness on ΦBp was also investigated. TOF-SIMS profile of Al in the

NiSi/p-Si material stack was extracted in an effort to understand the mechanism

behind lowering of the barrier height.

Furthermore, Al implant parameters and the metal silicidation process

conditions were optimized to integrate this novel implant technology at the NiSi/p+-Si

interface in the S/D of p-channel FinFETs to reduce contact resistance through

147

lowering of the effective Schottky barrier height of holes at the NiSi/p+-Si interface.

It was shown that the addition of a low dose (2×1014 atoms/cm2) Al ion implant step

in the Si S/D of p-channel FinFETs could achieve ~15 % enhancement in drive

current. A 13 % reduction in series resistance is observed which is directly related to

reduction in contact resistance and the enhancement in drive current achieved with Al

implant. The Al implant technology does not degrade short channel effects in the

transistors.

6.1.3 Study of Modulation of Electron Schottky Barrier Height of

NiSi on Si1-xCx using Substrate Engineering

In this work, we demonstrated the modulation of the effective electron

Schottky barrier height ΦBn of nickel silicide on silicon-carbon (Si1-xCx or Si:C) by

varying the carbon mole fraction, x. ΦBn was found to decrease with carbon

concentration at a rate of ~6.6 meV/ (0.1 % carbon). This is directly related to drop in

the bandgap of Si with increase in carbon concentration [at a rate of ~6.5 meV/ (0.1 %

carbon)]. We achieved ~27 meV drop in ΦBn with 0.4 % carbon incorporation in Si1-

xCx and showed that a Si1-xCx substrate with 2 % carbon could lead to more than 130

meV lowering of ΦBn. Increase in carbon content within the NiSi film increases its

thermal stability without any degradation of the low resistivity phase of the thin film,

although the sheet resistance does increase. The results of this study are useful in the

integration of low barrier NiSi contacts on n-FETs with Si1-xCx S/D.

148

6.1.4 Aluminum Implant Technology for Contact Resistance

Reduction in Strained p-FinFETs with SiGe Source/Drain

In this work, nickel germano-silicide (NiSiGe) contacts was formed on

silicon-germanium (Si1-xGex or SiGe) epilayer with 26 % Ge concentration, grown on

a p-Si (100) substrate. We reported the tuning of the effective Schottky barrier height

of holes ΦBp at the NiSiGe/SiGe junction to sub-0.1 eV by the introduction of

aluminum (Al) using ion-implantation and its segregation at NiSiGe/SiGe interface

after germano-silicidation. The effective ΦBp decreased with increasing concentration

of Al at the NiSiGe/SiGe interface. We demonstrated the achievement of one of the

lowest reported ΦBp for NiSiGe on SiGe of 0.068 eV, which is extremely promising

for application in strained p-FETs with SiGe S/D. The presence of Al does not affect

the sheet resistance or the low resistivity nickel mono-germano-silicide phase of the

NiSiGe film. The results indicate the possibility of an electric dipole at the

NiSiGe/SiGe interface, introduced by Al atoms, which is responsible for the ΦBp

modulation. Increase in thickness of nickel used for germano-silicidation increases

the effective ΦBp. On the other hand, increase in the Al implant dose reduces the

effective ΦBp but degrades the SiGe epilayer by amorphizing it to a greater depth.

Thus, a trade-off exists in choosing the Al implant dose and the nickel thickness

needed to consume the amorphized SiGe, for maximum device performance.

Furthermore, integration of the Al implant technology in strained p-FinFETs

with SiGe S/D, resulting in lowering of contact resistance RC (and parasitic series

resistance RSD) at the NiSiGe/p+-SiGe interface was also demonstrated. Al was

implanted into the p+-SiGe S/D region at energy of 10 keV and dose of 2×1014

atoms/cm2, followed by its segregation at the NiSiGe/p+-SiGe S/D interface during

germano-silicidation. The presence of Al at this interface leads to lowering of the

149

effective Schottky barrier height for holes, which in essence lowers the RC. It was

demonstrated that the RSD gets lowered by ~27 % which led to an enhancement in the

saturation drive current by ~25 % and in the linear drive current by ~29 %. The novel

Al segregated NiSiGe/p+-SiGe S/D contact technology for strained p-FinFETs does

not degrade the device short channel effects and the silicide thin film morphology is

unaffected.

6.1.5 Novel Cost-effective Single Silicide Solutions for Simultaneous

Contact Resistance Reduction in both p- and n-channel FETs

In this work, two novel single-silicide integration schemes were developed for

independent and simultaneous contact resistance reduction in p- and n- channel FETs. In

the first approach, a silicide formed of an alloy of nickel (Ni) and dysprosium (Dy) was

demonstrated as a possible candidate for single-silicide CMOS integration. Aluminum

(Al) implant technology is a key enabler in this approach. Using one additional

lithography step, n-FETs were blocked off during the Al implant step. This was followed

by the metal silicidation process flow, involving a blanket metal deposition (15 nm thick

layer of Ni on top of a 5 nm thick Dy interlayer) and silicidation anneal to form contact

silicides on both, p- and n- FETs. For strained tri-gate p-FinFETs with raised SiGe S/D

(containing 26 % Ge concentration), a novel Ni-Dy alloy germanosilicide (NiDySiGe)

S/D contact was formed. The effective ΦBp of NiDySiGe on SiGe was modulated

using Al implant to achieve an extremely small value of 0.12 eV. Various dose splits

of Al were experimented with to optimize the metal-silicidation process for integration of

Al implanted NiDySiGe/p+-SiGe S/D contact technology in p-FinFETs. This led to an

IDSAT enhancement of ~20 % against p-FinFETs with conventional NiSiGe contacts

150

(without Al implant). The enhancement in drive current is attributed to the presence of

silicide contacts with low RC.

For strained n-FinFETs (with Si:C S/D containing 1 % carbon), Ni-Dy alloy

silicide (NiDySi:C) S/D contacts, formed simultaneously led to an average IDSAT

enhancement of ~49 % over n-FinFETs with NiSi:C silicide contacts. This is due to the

38 % lower ΦBn of NiDySi:C on Si:C as compared to that of NiSi:C on Si:C [6.8].

In addition, a second novel single-silicide single-mask integration scheme was

also demonstrated for achieving dual near-band-edge barrier height and RC reduction in

both p- and n- channel FinFETs. The approach in this work relied on new observations

related to the interaction of Al and S implants and their impact on ΦBp. For p-FinFETs,

both Al and S were implanted on SiGe (Al dose is higher than the S dose) prior to NiSiGe

formation to give 0.37 eV lower ΦBp and 52 % higher IDSAT compared to an un-implanted

control. The n-FinFETs, formed simultaneously, received only S implant and achieved

35 % higher IDSAT and 0.44 eV lower ΦBn (of NiSi on n-Si) compared to un-implanted

control.

The second integration scheme (involving a double-implant technology of Al and

S) is even more promising than the first one. It involves tuning of the Schottky barrier

height ΦB of a silicide material (i.e., nickel-silicide) that is currently used by most

semiconductor manufacturers [6.3]. Thus, minimal cost and process overheads are

involved in adopting this technique. Furthermore, the electron barrier height ΦBn

achieved in the first approach was not band-edge. The ΦBn that was achieved with the

novel Ni-Dy alloy silicide was 0.43 eV [6.8], leaving plenty of room for further

improvement. On the other hand, the double-implant technology of Al and S (second

approach) can easily achieve band-edge ΦBn by tuning the S implant dose.

151

6.2 Future Work

A. Further Insights into the Mechanism for ΦBp Modulation at NiSi/p-Si Interface

In chapter 2, the interfacial dipole mechanism was proposed to explain the

modulation of the effective Schottky barrier height for holes ΦBp at the NiSi/p-Si

interface by Al, as well as Mg implant and segregation. Nevertheless, it may not be

the only reason responsible for barrier height modulation. Further work needs to be

done to ascertain the detailed mechanism. As mentioned in section 2.5, three-

dimensional atom-probe tomographic studies may permit the actual reconstruction of

atoms near the NiSi/p-Si interface in three dimensions [6.17]. This direction may be

pursued to increase our understanding of the NiSi/p-Si interface in presence of the

novel implant species (Al, and Mg). Furthermore, first principle simulation studies

involving density of states (DOS) calculations could be another avenue towards

dissecting the interaction of the novel implant species (Al, Mg, Zn, Cd, and Co) on

the energy band structure of the (metal-silicide)/semiconductor junctions studied in

this thesis [6.18], [6.19].

B. Plasma immersion ion-implantation of Aluminum for Contact Resistance

Reduction in FinFETs

Plasma immersion ion-implantation (PIII) is a novel doping technique which

is a promising candidate for sub-22 nm technology node [6.20], [6.21]. In PIII, the

wafer is placed on a conducting sample holder which is immersed in a uniform

plasma containing the implant ion species. Negative voltage pulses applied to the

wafer result in the creation of a plasma sheath around the wafer and the positive

implant ions get accelerated through it towards the wafer. This results in an

implanted flux to all the exposed surfaces of the wafer. Some of the key advantages

152

of this technique over conventional beam-line ion-implantation approach are shallow

junction formation with depths as low as 10 nm, doping of deep trenches, and high

dose rate and ion current. In the FinFET device architecture, conduction of charge

carriers take place along the vertical side walls of the fin also. With the sub-22 nm

technology node (where FinFETs are slated to be introduced) design rules limiting the

fin pitch, conformal doping of the fin (top surface as well as the side-walls) to reduce

parasitic series resistance becomes increasingly challenging using conventional ion-

implanters. This is where the PIII technology finds an exciting application because of

its ability to dope all of the exposed surfaces, even at high aspect ratio [6.22]. The

aluminum (Al) implant technology development reported in this thesis (chapter 3 and

chapter 4) has focused on conventional ion-implanters which did not implant Al at the

fin side-walls. The silicide contacts are formed on all the fin surfaces. Thus, the PIII

technology can be investigated for possible reduction of RC at the silicide/(heavily-

doped S/D) interface on the fin side-walls as well, leading to a much higher

enhancement in drive current than that shown in this thesis.

C. Contact Resistivity Measurements

In this thesis, exhaustive study of the Schottky barrier height ΦB at the

interface between metal-silicide and the S/D material in CMOS FETs (for e.g., SiGe,

Si:C, p-Si, and n-Si) has been performed. It needs to be mentioned here that the

contact devices used for ΦB measurements did not go through the deep S/D implant

step, which was present in the corresponding transistors when the developed ΦB

lowering technique was integrated into them. Thus the actual ΦB at the

silicide/(heavily-doped S/D region) interface may be different. A more direct study

would be to extract the contact resistivity ρC and contact resistance RC itself, at the

153

silicide/(heavily-doped S/D region) in the MOSFETs integrated with the novel ΦB

lowering techniques. Cross-kelvin bridge or transmission line model (TLM)

structures can be utilized for this purpose [6.23].

D. Development of Aluminum Implant Technology for Strained p-FETs with

[Ge] > 40 %

In chapter 4, a novel aluminum implant and segregation technology is

developed for p-FETs with uniaxial compressively strained SiGe S/D. These

transistors have Ge content in the S/D region of ~26 %. Other contact resistance

reduction RC techniques developed in chapter 5 were also experimentally tested on p-

FETs which had a similar Ge content. Leading semiconductor companies have been

continuously increasing the Ge content in the embedded S/D region of their state-of-

the-art p-FETs with each progressive technology node since they first introduced it at

the 90-nm technology node ([Ge] = 16 % at 90-nm [6.24], 23 % at 65-nm [6.25], and

30 % at 45-nm [6.3]). Higher [Ge] used in the S/D of p-FETs (with SiGe S/D) leads

to higher compressive strain in the channel, leading to enhanced hole mobility. If this

trend of strain engineering continues, at sub-22 nm technology node, [Ge] may be 40

% - 50 % Ge in the embedded S/D region. The hole Schottky barrier height ΦBp

lowering effects of Al implant developed in this work needs to be experimentally

verified on SiGe with higher Ge content (>40 %). Extensive optimization of the

metal-silicidation process would also be required for fabrication of silicides (with low

contact resistance) on S/D materials with higher compressive stress.

154

E. Compensation Effect of Aluminum and Sulfur Implants

In section 5.3, the implant interaction between Al and S ions was

experimentally studied for hole Schottky barrier height ΦBp reduction at the

NiSiGe/SiGe interface. The compensation effect of Al on S was demonstrated by

choosing a higher dose of Al than that of S (keeping the same implantation range RP

for both), leading to a ΔΦBp of 0.37 eV. Nevertheless, further work can be done for an

exhaustive study of this compensation effect of Al and S implants. In this work

(demonstrated in section 5.3), Al was implanted first followed by S. It remains to be

seen whether S implantation before Al would make any difference. Also, it needs to

be experimented investigated whether a higher dose of S implant (than that of Al) can

overwhelm the effect of Al and reduce the electron Schottky barrier height ΦBn at the

NiSi/n-Si interface for application in reducing RC for n-FETs.

F. Contacts to III-V MOSFETs with Low Contact Resistance

Recently, III-V MOSFETs have received a renewed interest by researchers

due to the theoretical limit of traditional device scaling being within sight [6.26],

[6.27]. N-channel InxGa1-xAs MOSFETs are extremely promising due to the high

electron mobility of the III-V channel material (at least an order of magnitude higher

that of Si) [6.28]. Nevertheless, there are several challenges faced by the III-V

technology. It needs to be integrated on the existing silicon platform to be

economically viable. Contacts to III-V MOSFETs are traditionally fabricated from

metal alloys consisting of gold (Au) which is a heavy metal contaminant in silicon

integrated circuits (IC). Moreover, the contact formation is not self aligned, which is

a basic norm in the state-of-the-art silicon-based CMOS technology. Non-self aligned

contact formation scheme increases cost overheads. Thus work is needed to develop

155

Au-free self aligned contacts to III-V MOSFETs. Dopant segregation based approach

may be utilized to achieve low contact resistance.

156

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160

Appendix A

List of Publications

Journal Publications

[1] M. Sinha, C. F. Tan, and E. F. Chor, “Schottky barrier height tuning of

silicide on Si1−xCx,” Applied Physics Letters, vol. 91, 242108, Dec. 2007.

[2] M. Sinha, E. F. Chor, and Y.-C. Yeo, “Tuning the Schottky barrier height of

nickel silicide on p-silicon by aluminum segregation,” Applied Physics Letters,

vol. 92, 222114, Jun. 2008.

[3] M. Sinha, R. T. P. Lee, K.-M. Tan, G.-Q. Lo, E. F. Chor, and Y.-C. Yeo,

“Novel aluminum segregation at NiSi/p+-Si source/drain contact for drive

current enhancement in p-Channel FinFETs,” IEEE Electron Device Letters,

vol. 30, no. 1, pp. 85-87, Jan. 2009.

[4] M. Sinha, R. T. P. Lee, A. Lohani, S. Mhaisalkar, E. F. Chor, and Y.-C. Yeo,

“Achieving sub-0.1 eV hole Schottky barrier height for NiSiGe on SiGe by

aluminum segregation,” Journal of The Electrochemical Society, vol. 156, no.

4, pp. H233-H238, Apr. 2009.

[5] M. Sinha, R. T. P. Lee, E. F. Chor, and Y.-C. Yeo, “Schottky barrier height

modulation of nickel-dysprosium alloy germano-silicide contacts for strained

161

P-FinFETs,” IEEE Electron Device Letters, vol. 30, no. 12, pp. 1278-1280,

Dec. 2009.

[6] M. Sinha, R. T. P. Lee, E. F. Chor, and Y.-C. Yeo, “Contact resistance

reduction technology using aluminum implant and segregation for strained p-

FinFETs with silicon-germanium source/drain,” to be published in IEEE Trans.

Electron Devices, vol. 57, 2010.

[7] M. Sinha, E. F. Chor, and Y.-C. Yeo, “Nickel-silicide contact technology with

dual near-band-edge barrier heights and integration in CMOS FinFETs with

single mask,” under review in IEEE Electron Devices Letters.

Conference Publications

[8] M. Sinha, R. T. P. Lee, S. N. Devi, G.-Q. Lo, E. F. Chor, and Y.-C. Yeo, “P-

FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series

resistance reduction,” International Symposium on VLSI Technology, Systems

and Applications, pp. 74-75, 2009.

[9] M. Sinha, R. T. P. Lee, S. N. Devi, G.-Q. Lo, E. F. Chor and Y.-C. Yeo,

“Integration of Al segregated NiSiGe/SiGe source/drain contact technology in

p-FinFETs for drive current enhancement,” ECS Trans., vol. 19, pp. 323-330,

May 2009.

[10] M. Sinha, R. T. P. Lee, S. N. Devi, G.-Q. Lo, E. F. Chor, and Y.-C. Yeo,

“Single silicide comprising nickel-dysprosium alloy for integration in p- and

162

n- FinFETs with independent control of contact resistance by aluminum

implant,” VLSI Symp. Tech. Dig., pp. 106-107, 2009.

Other Publications

[11] P. S. Y. Lim, R. T. P. Lee, A. E.-J. Lim, A. T. Y. Koh, M. Sinha, D. Z. Chi,

and Y.-C. Yeo, “Schottky-barrier height tuning of nickel silicide on epitaxial

silicon-carbon films with high substitutional carbon content,” Solid State

Device and Materials Conf. Ext. Abst., pp. 692-693, 2008.

[12] P. S. Y. Lim, R. T. P. Lee, M. Sinha, D. Z. Chi, and Y.-C. Yeo, “Effect of

substitutional carbon concentration on Schottky-barrier height of nickel

silicide formed on epitaxial silicon-carbon films,” J. Appl. Phys., vol. 106,

043703, Aug. 2009.

[13] S.-M. Koh, W.-J. Zhou, R. T. P. Lee, M. Sinha, C.-M. Ng, Z. Zhao, H.

Maynard, N. Variam, Y. Erokhin, G. Samudra, and Y.-C. Yeo,

"Silicon:carbon source/drain stressors: Integration of a novel nickel aluminide-

silicide and post-solid-phase-epitaxy anneal for reduced Schottky-barrier and

leakage," 216th Electrochemical Society Meeting, Oct. 2009.

[14] S.-M. Koh, M. Sinha, Y. Tong, H.-C. Chin, W.-W. Fang, X. Zhang, C.-M. Ng,

G. Samudra, and Y.-C. Yeo, “Sulfur implant for reducing nickel silicide

contact resistance in FinFETs with silicon-carbon source/drain,” International

Semiconductor Device Research Symposium, Dec. 2009.

163

Appendix B

Measurement of Schottky Barrier Height – Activation

Energy Method

In the activation energy method for extraction of Schottky barrier height at the

interface between a metal (or metal-silicide) and a semiconductor, the Thermionic

Emission (TE) model is used. This method requires 2-terminal current-voltage (I-V)

measurement of the metal/semiconductor contact device at different temperatures.

The Simplified form of the TE model is given by [3.11]

* 2 BΦexp exp 1

q qVI AA T

kT kT

, (1)

where A is the diode area, A* is the Richardson constant, T is the temperature in

Kelvin, ΦB is the Schottky barrier height to be extracted, k is the Boltzmann constant,

and q is the electronic charge. The junction series resistance is neglected in equation

(1) by keeping the bias voltage, V small. More details regarding fabrication of the

contact devices (test structures) can be found in section 4.2 (A). Under the

assumption that V >> kT/q, equation (1) can be rewritten as

*F B F2

Φln ln

I qVAA

T kT

, (2)

where IF is the forward-bias current at a corresponding forward-bias voltage VF. Thus,

using equation (2), for a fixed forward bias VF, the slope of a plot of ln(IF/T2) versus

1/T yields the barrier height ΦB and the ordinate intercept at 1/T = 0 yields the product

of the electrically active area A and the Richardson constant A*.

The main benefit of Schottky barrier height determination by means of an

activation energy measurement is that an assumption of the electrically active area is

164

not required. This feature is particularly important in the experimental investigation

of novel metal-silicide/semiconductor interfaces which may be incompletely reacted,

and hence have an electrically active area different from that of the geometrical area.

Note that the activation energy method is also known as the Arrhenius plot or the

Richardson plot method.

In this thesis, unless otherwise mentioned, the activation energy method is

always used to extract ΦB at the interface between a metal-silicide and semiconductor.

Low temperature (T < room temperature) I-V measurement is utilized for drawing the

Arrhenius plot which is especially beneficial for extraction of extremely low ΦB,

achievement of which is the main focus of this thesis. It has been reported that when

the temperature is high enough such that kT is comparable to qVF – ΦB, carriers may

have enough thermal energy to surmount the barrier height and hence, the effective

ΦBp cannot be accurately measured [3.17].

schottky barrier engineering for contact resistance ... · 2.5 summary and conclusion 34 2.6...

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