sdh basics (marconi 2000)

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SDH Basics

AN00091831 (62.1013.105.11-A001)Edition e, 03.2000

M a r c o n i C o m m u n ic a t io n s G m b HD - 7 1 5 2 0 B a c k n a n gT e le f o n ( 0 7 1 9 1 ) 1 3 -0 T e l e f a x ( 0 7 1 9 1 ) 1 3 - 3 2 1 2h t t p : / /w w w .m a r c o n i . c o mC o p y r ig h t 2 0 0 0 b y M a r c o n i C o m m u n i c a t i o n s G m b H ( h ie r i n b e z e ic h n e t a ls M a r c o n i )Ä n d e r u n g e n v o r b e h a l t e n é G e d r u c k t i n D e u t s c h la n d

M a r c o n i , M a r c o n i C o m m u n ic a t i o n s , d a s M a r c o n i L o g o , d a s g e s c h w u n g e n e 'M ' ,S k y b a n d , M D R S , M D M S u n d S e r v i c e O n A c c e s s s i n d e in g e t r a g e n e M a r k e n z e ic h e nv o n M a r c o n i C o m m u n ic a t i o n s G m b H .W i n d o w s is t e i n e i n g e t r a g e n e s M a r k e n z e i c h e n d e r M i c r o s o f t C o r p o r a t io n , R e d m o n d .

M a r c o n i C o m m u n ic a t io n s G m b HD - 7 1 5 2 0 B a c k n a n gT e le p h o n e + 4 9 (7 1 9 1 ) 1 3 -0 T e l e f a x + 4 9 (7 1 9 1 ) 1 3 - 3 2 1 2h t t p : / /w w w .m a r c o n i . c o mC o p y r ig h t 2 0 0 0 b y M a r c o n i C o m m u n i c a t i o n s G m b H ( h e r e in r e f e r r e d t o a s M a r c o n i )S p e c i f i c a t io n s s u b j e c t t o c h a n g e é P r in t e d in G e r m a n y

M a r c o n i , M a r c o n i C o m m u n ic a t i o n s , t h e M a r c o n i l o g o , t h e s w a s h 'M ', S k y b a n d , M D R S , M D M S a n d S e r v i c e O n A c c e s s a r e t r a d e m a r k s o fM a r c o n i C o m m u n ic a t io n s G m b H .W i n d o w s is a t r a d e m a r k o f M i c r o s o f t C o r p o r a t i o n , R e d m o n d .

62.1013.105.11-A001 3

NotesThis “Introduction to the Synchronous Digital Hierarchy“ is a company-inter-nal brochure. Marconi Communications GmbH takes no responsibility for the correctness of its contents!

Have you detected any faults or deficiencies? Do you have any new ideas? Please let us know them!

Marconi Communications GmbH, Department: Customer documentation.

Attention:

The ordering no. has changed with edition “e“. The new ordering no. is: 62.1013.105.11-A001

Ordering no. of previous editions: 62.1013.109.00-A001.

4 62.1013.105.11-A001

Table of contents

62.1013.105.11-A001 -5-

Table of contents

1 Introduction1.1 SDH functional model ............................................................................................................. 1-1

1.2 From the source signal to the transport frame........................................................................ 1-2

1.3 Transport frame ...................................................................................................................... 1-7

1.4 Section Overhead ................................................................................................................... 1-9

2 Structures2.1 Synchronous Transport Module Level 1 (STM-1)................................................................... 2-1

2.2 Structure of the synchronous STM-1 frame............................................................................ 2-1

2.3 SDH multiplex elements ......................................................................................................... 2-42.3.1 Container C .................................................................................................................... 2-42.3.2 Virtual container.............................................................................................................. 2-52.3.3 Administrative Unit.......................................................................................................... 2-62.3.4 Tributary Unit .................................................................................................................. 2-62.3.5 Tributary Unit Group ....................................................................................................... 2-82.3.6 Administrative Unit Group............................................................................................... 2-8

2.4 Concatenation....................................................................................................................... 2-13

2.5 Synchronous multiplexing..................................................................................................... 2-14

2.6 Multiframe generation ........................................................................................................... 2-15

2.7 Error monitoring using BIP-X ................................................................................................ 2-17

2.8 SDH transmission sections................................................................................................... 2-18

3 Multiplex paths in the SDH3.1 SDH multiplex scheme ........................................................................................................... 3-1

3.2 C-4 to STM-N.......................................................................................................................... 3-2

3.3 C-3 to STM-N.......................................................................................................................... 3-4

3.4 Two-step multiplexing of C-3 into STM-N ............................................................................... 3-6

3.5 C11, C12 and C2 to TUG-2 .................................................................................................... 3-8

3.6 TUG-2 to TUG-3 ................................................................................................................... 3-11

3.7 TUG-2 to VC-3...................................................................................................................... 3-12

4 Mapping procedures4.1 Asynchronous mapping of 140 Mbit/s signals into VC-4 ........................................................ 4-1

4.2 Asynchronous mapping of 34 Mbit/s signals into VC-3 .......................................................... 4-4

4.3 Asynchronous mapping of 2 Mbit/s signals into VC-12 .......................................................... 4-6

4.4 Asynchronous mapping of 1.5 Mbit/s signals into VC-11 ....................................................... 4-7

4.5 Mapping 1.5 Mbit/s signals into VC-12 ................................................................................... 4-8

5 Overhead5.1 Section Overhead ................................................................................................................... 5-1

5.1.1 Regenerator Section Overhead (RSOH) ........................................................................ 5-25.1.2 Multiplex Section Overhead (MSOH) ............................................................................. 5-2

5.2 Path Overhead........................................................................................................................ 5-35.2.1 Higher-order POH (VC-3/VC-4) ...................................................................................... 5-35.2.2 Lower-order POH (VC-1x/VC-2) ..................................................................................... 5-6

6 Pointers6.1 Pointer value modification....................................................................................................... 6-1

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-6- 62.1013.105.11-A001

6.1.1 Setting a new pointer value ............................................................................................ 6-16.1.2 Frequency matching ....................................................................................................... 6-1

6.2 Pointer types........................................................................................................................... 6-46.2.1 AU-3 pointer ................................................................................................................... 6-46.2.2 AU-4 pointer ................................................................................................................... 6-6

6.3 TU-3 pointer............................................................................................................................ 6-8

6.4 TU-2 pointer.......................................................................................................................... 6-10

6.5 TU-11 pointer........................................................................................................................ 6-12

6.6 TU-12 pointer........................................................................................................................ 6-14

7 Reference model7.1 Lower-order path functions ..................................................................................................... 7-2

7.2 Higher-order path functions .................................................................................................... 7-2

7.3 Transport terminal functions ................................................................................................... 7-2

8 Applications8.1 Synchronous line equipment .................................................................................................. 8-1

8.1.1 Synchronous line multiplexer.......................................................................................... 8-18.1.2 Synchronous line regenerator ........................................................................................ 8-2

8.2 Multiplexers............................................................................................................................. 8-48.2.1 Terminal Multiplexer ....................................................................................................... 8-48.2.2 Add/Drop Multiplexer ...................................................................................................... 8-68.2.3 Cross-connect Multiplexer .............................................................................................. 8-8

8.3 Networks............................................................................................................................... 8-108.3.1 Ring networks............................................................................................................... 8-118.3.2 Double rings ................................................................................................................. 8-11

9 Protection switching9.1 Overview................................................................................................................................. 9-1

9.2 Definitions ............................................................................................................................... 9-1

9.3 Protection switching................................................................................................................ 9-19.3.1 MS 1+1 protection .......................................................................................................... 9-39.3.2 MS 1:n protection ........................................................................................................... 9-49.3.3 MS shared protection ring .............................................................................................. 9-49.3.4 MS dedicated protection ring.......................................................................................... 9-69.3.5 Path/subnetwork protection ............................................................................................ 9-69.3.6 Protocols......................................................................................................................... 9-7

9.4 Network topologies ................................................................................................................. 9-8

9.5 Equipment protection............................................................................................................ 9-15

10 Literature

Index

List of figures

62.1013.105.11-A001 -7-

List of figures

Fig. 1-1 Transmitter/receiver model ................................................................................................ 1-1Fig. 1-2 Conversion of a serial source signal into a block structure................................................ 1-2Fig. 1-3 Container ........................................................................................................................... 1-3Fig. 1-4 Container with label ........................................................................................................... 1-3Fig. 1-5 Transport frame ................................................................................................................. 1-4Fig. 1-6 Combining containers to a container group ....................................................................... 1-5Fig. 1-7 Concatenated containers................................................................................................... 1-6Fig. 1-8 Transport frame of the 1st hierarchy level ......................................................................... 1-7Fig. 1-9 Overhead with pointer........................................................................................................ 1-9Fig. 2-1 STM-1 frame...................................................................................................................... 2-1Fig. 2-2 Pointer ............................................................................................................................... 2-3Fig. 2-3 Containers ......................................................................................................................... 2-4Fig. 2-4 Virtual containers ............................................................................................................... 2-5Fig. 2-5 Administrative Unit............................................................................................................. 2-6Fig. 2-6 Tributary Unit ..................................................................................................................... 2-7Fig. 2-7 Tributary Unit Group .......................................................................................................... 2-8Fig. 2-8 Administrative Unit Group.................................................................................................. 2-8Fig. 2-9 Generation of an STM-1 signal from a 140 Mbit/s signal................................................... 2-9Fig. 2-10 Generation of an STM-1 signal in compliance with ETSI ................................................ 2-10Fig. 2-11 Generation of an STM-1 signal from a 2.048 Mbit/s signal.............................................. 2-11Fig. 2-12 Terminal Multiplexer 63 x 2.048 Mbit/s ............................................................................ 2-12Fig. 2-13 SDH multiplexing procedure ............................................................................................ 2-14Fig. 2-14 TU-1x/TU-2 Multiframe identification by the H4 byte ....................................................... 2-16Fig. 2-15 BIP-8 monitoring process ................................................................................................ 2-17Fig. 2-16 SDH digital signal sections .............................................................................................. 2-18Fig. 3-1 Synchronous multiplex structure in compliance with ITU-T Recommendation G.707 ....... 3-1Fig. 3-2 Multiplexing of AU-4 to AUG.............................................................................................. 3-2Fig. 3-3 Multiplexing N x AUGs into STM-N.................................................................................... 3-3Fig. 3-4 Multiplexing of three AU-3s into AUG ................................................................................ 3-4Fig. 3-5 Multiplexing of one TUG-3 into one VC-4 .......................................................................... 3-6Fig. 3-6 TU-3 pointer....................................................................................................................... 3-7Fig. 3-7 TU-11 Tributary Unit ......................................................................................................... 3-8Fig. 3-8 TU-12 Tributary Unit .......................................................................................................... 3-9Fig. 3-9 TU-2 Tributary Unit ............................................................................................................ 3-9Fig. 3-10 Multiplexing TU-11, TU-12 and TU-2 into TUG-2 ............................................................ 3-10Fig. 3-11 Multiplexing seven TUG-2s into one TUG-3 .................................................................... 3-11Fig. 3-12 Multiplexing seven TUG-2s into one VC-3....................................................................... 3-12Fig. 4-1 Splitting up VC-4 into 13-byte blocks................................................................................. 4-1Fig. 4-2 Asynchronous mapping of 140 Mbit/s signals into VC-4 ................................................... 4-2Fig. 4-3 VC-3 divided up into three partial frames .......................................................................... 4-4Fig. 4-4 Asynchronous mapping of 34 Mbit/s signals into VC-3 ..................................................... 4-4Fig. 4-5 Asynchronous mapping of 2 Mbit/s signals into VC-12 ..................................................... 4-6Fig. 4-6 Asynchronous mapping of 1.5 Mbit/s signals into VC-11 .................................................. 4-7Fig. 4-7 Conversion of a VC-11 into a VC-12 (1.5 Mbit/s in VC-12) ............................................... 4-8Fig. 5-1 Overhead bytes ................................................................................................................. 5-1Fig. 5-2 Higher-order POH.............................................................................................................. 5-3Fig. 5-3 VC3/VC4 path status (G1) ................................................................................................. 5-4Fig. 5-4 TU multiframe indicator H4 ................................................................................................ 5-5Fig. 5-5 Lower Order POH.............................................................................................................. 5-6Fig. 5-6 Bit assignment of the V5 byte ............................................................................................ 5-6Fig. 5-7 V5[5-7] Mapping Code....................................................................................................... 5-7Fig. 6-1 Pointer modification (positive justification)......................................................................... 6-2Fig. 6-2 Pointer modification (negative justification) ....................................................................... 6-3Fig. 6-3 AU-3 pointer....................................................................................................................... 6-4

List of figures

-8- 62.1013.105.11-A001

Fig. 6-4 AU-4 pointer....................................................................................................................... 6-6Fig. 6-5 Multiplexing a VC-3 into a TUG-3 ...................................................................................... 6-8Fig. 6-6 TU-3 pointer....................................................................................................................... 6-9Fig. 6-7 TU-2 pointer..................................................................................................................... 6-10Fig. 6-8 TU-11 pointer................................................................................................................... 6-12Fig. 6-9 TU-12 pointer................................................................................................................... 6-14Fig. 7-1 Reference model for the design of SDH units ................................................................... 7-1Fig. 8-1 SLA4 and SLA16 synchronous line equipment (Example) ................................................ 8-1Fig. 8-2 Multiplex scheme in compliance with ITU G.707 ............................................................... 8-2Fig. 8-3 FlexPlex MS1/4 used as Terminal Multiplexer in an SDH network.................................... 8-4Fig. 8-4 Functioning of a Terminal Multiplexer................................................................................ 8-5Fig. 8-5 FlexPlex MS1/4 used as an Add/Drop Multiplexer in an SDH network ............................. 8-6Fig. 8-6 Functioning of an Add/Drop Multiplexer............................................................................. 8-7Fig. 8-7 FlexPlex MS1/4 used as Cross-connect Multiplexer in an SDH network .......................... 8-8Fig. 8-8 Functioning of a Cross-connect Multiplexer....................................................................... 8-9Fig. 8-9 Synchronous networks .................................................................................................... 8-10Fig. 8-10 Single ring network .......................................................................................................... 8-11Fig. 8-11 Double ring network......................................................................................................... 8-12Fig. 8-12 Interrupted double ring..................................................................................................... 8-12Fig. 8-13 Double ring connection of two ring networks ................................................................... 8-13Fig. 9-1 MSP 1+1 Multiplex Section Protection .............................................................................. 9-3Fig. 9-2 MS 1:n Protection Switch................................................................................................... 9-4Fig. 9-3 Example of the traffic flow in an MS shared protection ring............................................... 9-5Fig. 9-4 Example for the traffic flow in an MS dedicated protection ring......................................... 9-6Fig. 9-5 Path und subnetwork protection ........................................................................................ 9-7Fig. 9-6 Linear multiplexer chain with redundancy.......................................................................... 9-9Fig. 9-7 Path protection in a multiplexer chain................................................................................ 9-9Fig. 9-8 Examples for multiplexer rings with two and four connecting lines.................................. 9-11Fig. 9-9 Example for protection switching in interconnected rings................................................ 9-12Fig. 9-10 Interconnection of two rings with path protection............................................................. 9-13Fig. 9-11 Interconnection of two rings with MS shared protection .................................................. 9-14

Introduction

62.1013.105.11-A001 1-1

1 Introduction The Synchronous Digital Hierarchy (SDH) supersedes the previous Plesio-chronous Digital Hierarchy (PDH) and provides a worldwide uniform multi-plex hierarchy. Besides standardization, SDH systems offer further advantages for the setup and operation of modern network topologies:

♦ Simple multiplex process (no positive/negative justification)

♦ Network-wide standardized reference clock

♦ Direct access to individual channels

♦ High bit rates for broadband applications

♦ High transmission capacity for network monitoring and network control

♦ Control by highly efficient network management systems

♦ Integration of the previous plesiochronous multiplex hierarchy.

1.1 SDH functional model

The following transmitter/receiver model shows the transmission of source signals. The transmitter converts the incoming source signals into a SDH-conforming structure. In doing this, the signals are assembled in defined transport frames. These frames are then transmitted to the receiver. The receiver extracts again the individual signals from the frame. The source signals can be both plesiochronous or synchronous.

Fig. 1-1 Transmitter/receiver model

Transmitter2 Mbit/s

140 Mbit/s

2 Mbit/s

140 Mbit/s

Receiver2 Mbit/s

140 Mbit/s

2 Mbit/s

140 Mbit/s

Transport frame

TransmitterReceiver

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1-2 62.1013.105.11-A001

1.2 From the source signal to the transport frame

The serial source signal (e.g. 140 Mbit/s) is at first converted into a byte-ori-ented block structure. In this block structure, the bytes are arranged in columns and rows. In the Synchronous Digital Hierarchy, the block structures are defined and have a certain size. The number of blocks per second is also specified.

Example: Block size: 260 columns with 9 rows each consisting of 1 byte = 2340 ByteNumber of blocks per second: 8000

This results in a transmission capacity of 260 columns x 9 rows x 8000 blocks per second = 18,720 kbyte/s or 149,760 kbit/s.

The above calculation shows that the transmission capacity of the blocks is larger than the bit rate of the source signal. In order to compensate this diffe-rence, each block must contain a certain amount of justification, i.e. stuffing information.

Fig. 1-2 Conversion of a serial source signal into a block structure

9 C 72 33 A4 ... ...

... ... ... ... ... ...

... ... ... ... ... ...

... ... ... ... ... ...

... ... ... ... ... ...

... ... ... ... ... ...

... ... ... ... ... ...

... ... ... ... ... ...

... ... ... ... ... ...

Serial bit stream, e.g. 140 Mbit/s + stuffing information

9C

1 byte1 0 0 1 1 1 0 1 0 1 1 1 ...

9CH

1 260 260 2601

Introduction

62.1013.105.11-A001 1-3

Containers

The transmission of SDH signals can be compared with the transmission of containers on a conveyor belt.

The payload is transported in containers of certain sizes. Since the payloads have different volumes, containers with different capacities have been defi-ned. If the payload is too small, it is filled up with stuffing information.

For transporting the information, the container needs a label. The latter inclu-des information on the container contents, monitoring data etc. The receiver evaluates this information.

The complete containers are then put on a kind of conveyor belt. This con-veyor belt is divided up into several frames of identical size. They are used to transport the containers.

Fig. 1-3 Container

Container

Fig. 1-4 Container with label

Container

Label

Payload

Blind information

Introduction

1-4 62.1013.105.11-A001

The position of the containers in the frame is arbitrary, i.e. a container does not have to start at the beginning of the frame. A container can be located on two adjacent frames.

Fig. 1-5 Transport frame

Empty frame

Container

Container

Direction of transmission

Start of frame

Introduction

62.1013.105.11-A001 1-5

Groups of containers

The type of payload in the containers is unimportant for transportation. The stuffing information can therefore be regarded as part of the payload. Before transportation, several small containers can be combined to form a group. This group is then packed into a larger container. Each of these containers includes a label which is evaluated by the receiver. Whenever necessary, stuffing information is added.

The individual containers are assigned a certain position within the group. The position no. determines the start of the respective container.

Fig. 1-6 Combining containers to a container group

Position within the container

Stuffing information

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1-6 62.1013.105.11-A001

Concatenation

The above description was based on the assumption that the payload is smaller than the container available. If the payload to be transported is larger than the container available for it, several containers can be concatenated. They then form a continuous container chain. In this case, the payload is dis-tributed on this container chain.

Example: The source signal is 599.04 Mbit/s (broadband ISDN). Since the largest con-tainer defined can transport only a signal up to 140 Mbit/s, four such contai-ners have to be concatenated. The position of the container chain on the conveyor belt is defined for the first container. The position of all other contai-ners 2, 3 and 4 is determined by the first one.

Fig. 1-7 Concatenated containers

1st container 2nd container 3rd container 4th container

ConcatenationPosition

Start of frame

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62.1013.105.11-A001 1-7

1.3 Transport frame

The transport frame represents the transmission medium for the containers. It has a block structure similiar to that of a container, i.e. it is composed of N columns and M rows (N= 270, M=9). In order to meet the different capacity requirements, different sizes of transport frames have been defined. These subdivisions are referred to as hierarchy levels.

Example: Transport frame of the 1st hierarchy level

It is composed of 270 columns and 9 rows. The first 9 columns are reserved for special transport functions. The other 261 columns are used to transport payload signals. 8000 frames are transported per second. This corresponds to a frame duration of 125 µs.

The “Additional transport capacity” has a transmission capacity of

9 (columns) x 9 (rows) x 8 (bits) x 8000 (frames per second) =5.184 Mbit/s. This area is referred to as “Section Overhead”.

In addition to the payload (which can be arbitrarily structured), additional pay-load-independent information is transmitted. The Section Overhead is trans-mitted even when there is no payload.

Fig. 1-8 Transport frame of the 1st hierarchy level

270 columns

9 rows Payload area

9 columns

Additional transport capacity

261 columns

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1-8 62.1013.105.11-A001

Hierarchy levels

The transport frame of the higher hierarchy levels differ from each other only with respect to the number of columns. The following hierarchy levels have been defined:

Hierarchy level

Number of columns

Number of rows

Transport capacity

1 270 9 155.520 Mbit/s

4 1080 (4 x 270) 9 622.080 Mbit/s

16 4320 (16 x 270) 9 2488.320 Mbit/s

Table 1-1 Hierarchy levels

Introduction

62.1013.105.11-A001 1-9

1.4 Section Overhead

The Section Overhead is a minicontainer containing various information required for transmission. The Section Overhead offers free capacity which can be used for additional information. The Section Overhead always starts at the beginning of the transport frame.

The Section Overhead also includes a pointer defining the position of the containers in the payload area. The pointer value, also referred to as offset, indicates the offset of the container with respect to a reference point of the frame. The pointer, however, is not part of the Section Overhead!

Before a container is placed on the conveyor belt (add function), the pointer value is calculated and the container is placed e.g. in position 30, calculated from the end of the fixed pointer position. On taking the container from the conveyor belt (drop function), the pointer is evaluated and the position of the container determined.

The pointer also permits a dynamic adaptation of the container to the trans-port frame. This means that the container can be moved on the conveyor belt in both directions by changing the offset value. If a container is to be shifted to another conveyor belt (cross-connect), this is also done by means of the pointer.

Fig. 1-9 Overhead with pointer

30

70Section Overhead

Pointer

Pointer

Pointer

Pointer

Reference point

Direction of transmission

40

60

Pointer

Pointer

Pointer

Add/Drop

Cross-connect

Position of pointer in the Section Overhead

Introduction

1-10 62.1013.105.11-A001

Structures

62.1013.105.11-A001 2-1

2 Structures

2.1 Synchronous Transport Module Level 1 (STM-1)

The Synchronous Digital Hierarchy (SDH) defines the Synchronous Trans-port Module Level 1 (STM-1) as multiplex signal of the lowest level. It has a transmission rate of 155.520 Mbit/s. The STM-N bit rates of the standardized higher hierarchy level (N= 4 and 16) are always higher by factor 4.

An STM-N multiplex signal is formed by interleaving the individual STM-1 fra-mes byte by byte.

2.2 Structure of the synchronous STM-1 frame

The following diagram shows the structure of the byte-oriented STM-1 frame. The frame is composed of 270 columns and 9 rows. An STM-4-(16) frame has 4 (16) * 270 columns and also 9 rows.

Synchronous Transport Module

Hierarchy level

Transport capacity in kbit/s

Interface

Electrical Optical

STM-1 1 155 520 G.703 G.957

STM-4 4 622 020 - G.957

STM-16 16 2 488 320 - G.957

Table 2-1 Allocation of transmission capacity to transport modules

Fig. 2-1 STM-1 frame

270 Bytes

9 rows

1 9

1

9

19440 bits or 2430 bytes/frame

Bit length: 6.4300411 nsTransmission bit rate: 155.520 Mbit/s

Frame length: 125 µs

Payload

SOH

SOH

Pointer

Structures

2-2 62.1013.105.11-A001

The first 9 columns include the Section Overhead (SOH) and the Pointer of the Administrative Unit (AU pointer). The remaining 261 columns are used for transporting the payload. It consists of packed and multiplexed payload signals (tributaries) and an accompanying Path Overhead (POH).

The repetition frequency of the STM-1 frame is 8 kHz, i.e. one STM-1 frame has a length of 125 µs. The transmission capacity of one byte in an STM-N frame is thus 64 kbit/s.

With STM-1, an Overhead capacity of 5184 kbit/s is transported in addition to the traffic bit rate of 150,336 kbit/s.

Bit rates of the STM-1 frame

Columns x rows x 64 kbit/s Bit rate

STM-1 frame 270 x 9 x 64 kbit/s 155,520 kbit/s

Section-Over-head

9 x 9 x 64 kbit/s 5,184 kbit/s

Payload 261 x 9 x 64 kbit/s 150,336 kbit/s

Table 2-2 Bit rates in the STM-1 frame

Structures

62.1013.105.11-A001 2-3

The payload has no fixed phase relation to the STM-N frame. In order to be able to access the payload, the Section Overhead block contains a pointer. It is located in the 4th row of the STM-N frame.

The pointer indicates the beginning of the payload frame and permits the payload to be directly accessed. The first byte of the payload frame (byte 0) follows the last pointer byte. Bytes 522 to 782 are located in front of the poin-ter. Pointer values higher than 521 are thus pointing at the next STM frame!

Fig. 2-2 Pointer

STM-1

SOH Payload

310

Pointer

Pointer

310

-0 -

-522

-1 - ...

...

-310

...

310

-0 -

-522

-1 - ...

...

-310

...

782

782

522

-

- -

- ...

-

- -

...-

Structures

2-4 62.1013.105.11-A001

2.3 SDH multiplex elements

In the SDH, only synchronous signals with an STM-N structure are transmit-ted. However, tributary signals, i.e. signals received by synchronous multiple-xers, are currently still plesiochronous. For this reason, they have to be converted into the clock-synchronous block structure of the payload before being transmitted.

A block structure is a frame with a certain number of columns and rows.

2.3.1 Container C

The transmission capacity of the incoming source signal is smaller than the capacity of the block structure. The source signal is therefore filled up by adding stuffing information (positive justification).

The process of filling up the incoming information to obtain the defined block structure is referred to as mapping. The complete block structure is called Container C. Different container sizes (e.g. C-11, C-12, C-2, C-3, C-4) are available for the different source signal bit rates.

The digit in the container designation indicates the hierarchy level of the ple-siochronous signal (e.g. C-4 for 140 Mbit/s). If several containers for different bit rates are available within one hierarchy level, a second digit defines the bit rate assignment (C-11=1,5 Mbit/s, C-12=2 Mbit/s).

Fig. 2-3 Containers

C-4

1 260

C-3

1 84

1 12 1 4 1 3

1.5 Mbit/s + stuffing bits � C-112 Mbit/s + stuffing bits � C-126 Mbit/s + stuffing bits � C-245 (34) Mbit/s + stuffing bits � C-3140 Mbit/s + stuffing bits � C-4

Hierarchy Bit rate assignment

C-12 C-11C-2

Structures

62.1013.105.11-A001 2-5

2.3.2 Virtual container

Each container is completed with a Path Overhead (POH) which is used to monitor and control the correct addressing as well as to identify the container contents. The POH + C-n entity is referred to as Virtual Container (VC-n) and is transported within the synchronous network from the source to the sink, i.e. over the complete path. The name convention is identical with that of normal containers.

Note: The POH of VC-11, VC-12 or VC-2 is composed of four bytes (V5/J2/N2/K4). One byte of this POH is transmitted per VC-n, thus leading to the generation of a multiframe.

Fig. 2-4 Virtual containers

C-4

1 261

C-3

1 85

1 12 1 4 1 3

POH POH

POH POH POH

C-11 + POH � VC-11C-12 + POH � VC-12C-2 + POH � VC-2C-3 + POH � VC-3C-4 + POH � VC-4

C-12C-2 C-11

VC-4 VC-3

VC-2 VC-12 VC-11

Structures

2-6 62.1013.105.11-A001

2.3.3 Administrative Unit

The AU pointer provides the phase relation between the start of VC-3 or VC-4 and the reference point of the STM-1 frame. By adding the pointer value, the VC-3/VC-4 becomes an Administrative Unit (AU-3/AU-4). The pay-load of an STM-1 signal consists of one AU-4 or three AU-3s.

2.3.4 Tributary Unit

The Virtual Containers VC-11, VC-12 and VC-2 are completed to a Tributary Unit by adding the pointer. This results in the following TU structures of the individual columns and rows:

TU-11: 9 rows x 3 columnsTU-12: 9 rows x 4 columns TU-2: 9 rows x 12 columnsTU-3: 9 row x 86 columns

In TU-11, TU-12 and TU-2, there is only space for one pointer byte. However, three bytes are required for the pointer operations. In order to be able to transport these bytes, a multiframe has been defined (see “Multiframe gene-ration” on page 16). The position of the pointer bytes is depicted in the alternative illustration (see next figure). The V1 and V2 bytes form the TU pointer. Byte V3 is available for a dynamic increase in the payload (stuffing).

VC-3 can also be completed to form a TU-3 instead of an AU-3.

Fig. 2-5 Administrative Unit

VC-4

10 270

AU-4 pointer

VC-3

4 90

AU-3 pointer

VC-4 + AU-4 pointer � AU-4VC-3 + AU-3 pointer � AU-3

AU-4

AU-3

1 9

123

Structures

62.1013.105.11-A001 2-7

Fig. 2-6 Tributary Unit

1 12

1 4

1 3

TU-11

TU-12

TU-2

VC-3

1 86

Pointer

V1 321 322 ... 426 427 V2 0 1 ... 105 106 V3 107 108 ... 212 213 V4 214 215 ... 319 320

V1 105 106 ... 138 139 V2 0 1 ... 33 34 V3 35 36 ... 68 69 V4 70 71 ... 103 104

V1 78 79 ... 102 103 V2 0 1 ... 24 25 V3 26 27 ... 50 51 V4 52 53 ... 76 77

Pointer bytes

VC-2 + TU-2 pointer � TU-2VC-12 + TU-12 pointer � TU-12VC-11 + TU-11 pointer � TU-11 orVC-11 + stuff. info + TU-12 pointer � TU-12VC-3 + TU-3 pointer � TU-3

TU-2 TU-2 TU-2 TU-2

TU-12 TU-12 TU-12 TU-12

TU-11 TU-11 TU-11 TU-11

in frame #1 in frame #2 in frame #3 in frame #4



bytes

Pointer bytes

Pointer bytes

H1H2H3

TU-3

V

V

V

H1 595 596 ... H2 ... 763 764 H3 0 1 ...

Structures

2-8 62.1013.105.11-A001

2.3.5 Tributary Unit Group

The Tributary Units are multiplexed to so-called Tributary Unit Groups (TUGs). These Tributary Unit Groups represent an arrangement of block-structured signals with a frame length of 125 µs.

2.3.6 Administrative Unit Group

On multiplexing the AU-N into STM-N, an Administrative Unit Group (AUG) is formed by three AU-3s or one AU-4. The three AU-3s are interleaved byte by byte.

The Administrative Unit Group (AUG) represents an information structure composed of 9 rows each consisting of 261 columns plus 9 bytes in row 4 for the AU pointers.

Fig. 2-7 Tributary Unit Group

1 12

TUG-2 TU-3

1 86

Stuffinginformation

4 x TU-11 � TUG-23 x TU-12 � TUG-21 x TU-2 � TUG-27 x TUG-2 + stuff. info � TUG-31 x TU-3 + stuff. info � TUG-3

TUG-3

Fig. 2-8 Administrative Unit Group

10 270

1x AU-4 � AUG3x AU-3 � AUG

Space for3 AU-3 or1 AU-4 pointers

AUG

Structures

62.1013.105.11-A001 2-9

Examples

With 140 Mbit/s signals, the generation of an STM-1 signal can be described as follows:

1. Filling up the 140 Mbit/s signal with stuffing bits -> C-42. Adding the Path Overhead (POH)-> VC-43. Calculating and adding the pointer -> AU-44. Adding the Section Overhead (SOH) -> STM-1

In this case, AUG and AU-4 are identical, i.e. the AUG does not have to be separately illustrated in the following figure.

Fig. 2-9 Generation of an STM-1 signal from a 140 Mbit/s signal

C

Payload

POH

PTRPOH

STM-1 AU-4 VC-4 C-4

270 bytes

9 1

3

1

5

POH

PTR

SOH

SOH

140 Mbit/s signal

Structures

2-10 62.1013.105.11-A001

Bit rate < 140 Mbit/s At bit rates lower than 140 Mbit/s, the plesiochronous signals are converted into an STM-1 signal via a 2-step procedure. .

Fig. 2-10 Generation of an STM-1 signal in compliance with ETSI

C

POH

C

PTR

VC

<34

TUG-2

TUG-3

POH

PTR

SOH

C-4

VC-4

AU-4

Filling up the tributary bit rate with stuffing bits

<140

Adding the Path

Calculating and adding the pointer

<34No

No

Generating TUG-2

Generating TUG-3

Adding the Path

Calculating and adding the pointer

Adding the SectionOverhead

<140No

No

Overhead

Overhead

Mbit/s

Mbit/s

STM-1

Structures

62.1013.105.11-A001 2-11

The following diagram shows how a 2.048 Mbit/s signal is converted into an STM-1 signal via the different multiplex steps.

The maximum number of 2.048 Mbit/s signals can be calculated as follows:

3 (TU-12) x 7 (TUG-2) x 3 (TUG-3) x 1 (VC-4) = 63 x 2.048 Mbit/s

A maximum of 63 x 2.048 Mbit/s signals can thus be assembled in one STM-1 signal. This is shown in the next figure.

The individual 2.048 Mbit/s signals are subjected to the same multiplex pro-cedure in both the transmit and receive direction, however, in the opposite order. For this reason, the two directions are not separately depicted.

For further simplification, tributary signals of the same type (e.g. 2.048 Mbit/s) are shown only one time. All intermediate steps of the same type (e.g. TUG-2) are also illustrated only once. The application of this prin-ciple to all tributary signals defined results in the SDH multiplex scheme des-cribed in chapter 3 below.

Fig. 2-11 Generation of an STM-1 signal from a 2.048 Mbit/s signal

Pointer

270 bytes9 bytes

SOH

SOH

TUG-3

Pointer

TUG-2

AU-4

VC-4

TUG-3

stuff. info

VC-4 POH stuff. info

TU-12 f

TU-12 pointer

TUG-2

TU-12

VC-12 POH

9

VC-12

C-12

Payload

bytes

2.048 Mbit/s + stuffing info

C-12 2.048 Mbit/sVC-12TU-12TUG-2TUG-3VC-4AU-4STM-1

x 3x 7x 3x 1

STM-1

Structures

2-12 62.1013.105.11-A001

Fig. 2-12 Terminal Multiplexer 63 x 2.048 Mbit/s

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

TUG-2

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

TUG-2

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

TUG-2

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

TUG-2

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

TUG-2

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

TUG-2

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

C-12 2.048 Mbit/sVC-12TU-12

TUG-2

TUG-3

TUG-3

TUG-3

21 x 2.048 Mbit/s

21 x 2.048 Mbit/s

VC-4

7 x

7 x

AU-4STM-1

Structures

62.1013.105.11-A001 2-13

2.4 Concatenation

If the payload is larger than the container available for it, it can be distributed to several consecutive containers. The individual containers are concatena-ted by means of a special pointer value. This pointer value is referred to as Concatenation Indication.

Example of a VC-4 con-catenation

A number of four VC-4 containers are required for an ATM cell stream of the broadband ISDN with a bit rate of 599.04 Mbit/s. In the first VC-4, a valid POH is generated. The other three VC-4s are only filled up with payload and are assembled to form one VC-4-4c Virtual Container.

By adding the pointer, the VC-4-4c is converted into the AU-4-4c group. The first AU-4 of the AU-4-4c group is provided with a pointer. All other AUs con-tained in the AU-4-4c group receive the pointer value which indicates the concatenation of the containers. All following AUs within the AU-4-4c group receive the Concatenation Indication (CI) instead of the pointer value. The CI is composed as follows:

1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1

The CI value indicates that this AU-4 belongs to the previous AU-4 and that all pointer operations of the first AU-4 shall be executed on all AU-4 units contained in the AU-4-4c group.

� A VC-4 concatenation is possible only in STM-N frames with N > 1, e.g. STM-4 frames.

Structures

2-14 62.1013.105.11-A001

2.5 Synchronous multiplexing

The STM-N multiplex signal is generated by interleaving the individual STM-1 frames byte by byte. The STM-1 frames are numbered in the sequence in which they appear in the STM-N frame. The third STM-1 frame (STM-1#3) starts, for example, in the 3rd column of the STM-N frame.

In this connection, it is pointed out that the Section Overheads (SOH) of the individual STM-1 signals are not interleaved.

The multiplex procedure used for generating lower-order multiplex elements (TUG-2, TUG-3 etc.) is identical with the one used for generating STM-N signals.

The demultiplexing procedure (disassembling the multiplex signal into the individual STM-1 frames, TUG-3, TUG-2) is performed in the same way, however, in the opposite order.

Fig. 2-13 SDH multiplexing procedure

1 109 270

STM-1#1

1010

1010

1111

1111

270270

270270

125µs 125µs 125µs 125µs

125µs

4 x 9 4 x 261

Byte interleaving

STM-4 frame

SOH Payload

11

Pointer

12 13

SOH

SOH

1212

1212

1313

1313

Pointer

4 x 9

1 109 270

STM-1#2

11

Pointer

12 13

SOH

SOH

1 109 270

STM-1#3

11

Pointer

12 13

SOH

SOH

1 109 270

STM-1#4

11

Pointer

12 13

SOH

SOH

SOH

SOH

1 1 1 19 9 9 9

SOH is newly inserted,not interleaved!

Structures

62.1013.105.11-A001 2-15

2.6 Multiframe generation

The TU-11, TU-12 and TU-2 frames offer space for only one pointer byte. However, three bytes are required for the pointer operations, i.e. two bytes for addressing and one byte for the negative justification process. A fourth byte is to be provided as spare byte.

For this reason, several TU frames are combined to form a multiframe. The pointer bytes are then distributed to these consecutive TU frames. The still separate TU frames are arranged in a TUG-2 unit. In compliance with the multiplex structure, they can be accommodated in a VC-3 or via TUG-3 in a VC-4. This VC-3 /VC-4 is finally converted into an STM-1 frame.

In order to ensure that the receiver knows that the VC-3/VC-4 includes Tribu-tary Units with a multiframe, a so-called multiframe indicator (H4) is set and transmitted in the POH of VC-3/VC-4. The receiver evaluates this indicator and interprets the pointer bytes in the individual TUs correspondingly.

The relevant ITU-T Recommendations currently only define the 500 µs multi-frame:

♦ 500 µs (4 frames) for byte-asynchronous payloads in VC-11, VC-12 and VC-2 (floating mode).

Example: The system generates a TU multiframe composed of four TU-2 frames. The TU-2 Tributary Units are converted via TUG-2 into a VC-3. The TU pointer bytes V1 to V4 are distributed to four consecutive VC-3s. By means of a counting process, the H4 byte determines the VC-3 frames containing the individual pointer bytes.

H4 = x x x x x x 0 0 indicates that the next VC-3/VC-4 frame includes the V1 pointer byte.

.

Structures

2-16 62.1013.105.11-A001

Fig. 2-14 TU-1x/TU-2 Multiframe identification by the H4 byte

H4 (00)

V4

VC-3/VC-4 Payload

H4 (01)

V1

VC-3/VC-4 Payload

H4 (10)

V2

VC-3/VC-4 Payload

H4 (11)

V3

VC-3/VC-4 Payload

H4 (00)

V4

VC-3/VC-4 Payload

VC-3/VC-4 POH

9 ro

ws

Structures

62.1013.105.11-A001 2-17

2.7 Error monitoring using BIP-X

Bit Interleaved Parity X (BIP-X) is a method used for monitoring a signal for bit errors. This method consists in adding an additional information of X bits to a defined length of the signal to be monitored (e.g. one frame). In the SDH, X can assume the values 2, 8 and 24.

Example: BIP-8 Starting from the first bit of the signal to be monitored, every eighth bit is ana-lyzed in order to determine the number of logic “ones”. Then the first bit of the BIP-8 value is defined so that together with this bit, there is an even number of logic “ones”.

Then the same process is executed starting from the second bit of the signal to be monitored, i.e. every eighth bit is analyzed and the second bit of the BIP-8 value is defined by applying the same rule.

This calculation is performed for all eight bits of the BIP-8 value. The result is then transmitted together with the signal to the opposite station. There the same calculation is performed. Possible deviations of the calculated value from the transmitted BIP-8 value permit transmission errors to be detected. A maximum of 8 parity violations can be identified by means of one BIP-8 value on condition that these parity violations are statistically distributed.

The BIP-2 and BIP-24 monitoring process is based on the same principle. The BIP-2 value to be transmitted is composed of two bits, the BIP-24 value of three bytes.

Before being transmitted, the signals are scrambled. On reception, they are descrambled. The BIP value is calculated in front of the scrambler and inser-ted in the next frame also in front of the scrambler.

Fig. 2-15 BIP-8 monitoring process

1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1

+ + + +1

1

0

1

0

0

1

1

1

1

0

1

0

0

1

1

+ + + +

+ + + +

+ + +

+ + +

+ + +

+ + +

+ + +

BIP-8 value Result from signal

Signal

1st bit

1 9 17 25

CBH <-

Structures

2-18 62.1013.105.11-A001

2.8 SDH transmission sections

From its assembly to its disassembly, a container passes the transmission sections shown in the diagram below. The C3 container can either be injec-ted directly into the higher-order path or via an upstream stage into the lower-order path (also see multiplex structure).

The Multiplex Section represents the section between two multiplexers. A Regenerator Section is located between a multiplexer and a regenerator or between two regenerators.

The overheads are generated or terminated in accordance with these sec-tions. The SOH of a Regenerator Section (RSOH) is disassembled and newly inserted at each regenerator. The MSOH is transmitted between two multiplexers. The Path Overhead (POH) accompanies the container all over the paths. In accordance with the two paths available, they are referred to as lower-order POH or higher-order POH.

Fig. 2-16 SDH digital signal sections

C-3

C-11,

Multiplex Section

Higher-order path

Lower-order path

SOH = Section Overhead (assigned to the transmission section) POH = Path Overhead (assigned to the virtual container)

STM-N RSOH

STM-N MSOH

VC-3, VC-4 POH

VC-11, VC-12-, VC-2-, VC-3POH

ST

M-N

Mul

tiple

xer

VC

-4A

ssem

bler

RegeneratorSectionVC-3

Assem-bler

Regenerator Regenerator

C-12,C-2

VC-11, VC-12, VC-2Assem-bler

VC

-3,

VC

4A

ssem

bler

C-3,C-4

C-3

C-11,

ST

M-N

Mul

tiple

xer

VC

-4A

ssem

bler VC-3

Assem-bler

C-12,C-2

VC-11, VC-12, VC-2Assem-bler

VC

-3,

VC

4A

ssem

bler

C-3,C-4

Multiplex paths in the SDH

62.1013.105.11-A001 3-1

3 Multiplex paths in the SDH

3.1 SDH multiplex scheme

The source signals received are assembled in the corresponding containers, provided with the POH and pointer and converted into a STM-1 signal via the different multiplex steps. Source signals with bit rates higher than 139.264 Mbit/s are multiplexed into the STM-1 frame in one step, those with lower bit rates in two steps. The multiplex paths (demultiplex paths) for the individual source signals are combined to a multiplex scheme.

This multiplex scheme complies with ITU-T G.707 and includes optional mul-tiplex paths. The VC-3 can e.g. be multiplexed via TU-3 into VC-4 or the AU-3 path can be selected.

A distinction is made between the lower-order and higher-order path. For SDH signals there are two levels which are used to set up the phase relation using pointers: TU-11, TU-12, TU-2 and TU-3 being the lower level and AU-3, AU-4 being the higher level.

The following chapter contains a detailed description of the individual sec-tions and elements of the multiplex structure. The assembly of payload signals in containers is explained in a separate chapter.

Fig. 3-1 Synchronous multiplex structure in compliance with ITU-T Recommendation G.707

xN x1

x3

x7

x1

x1

VC-3

C-4AU-4AUGSTM-N

TUG-3

TUG-2x4

x3

see note

8 Mbit/s and non-hierarchical bit rates can Note

44.736

34.368

6.312

2.048

1.544

139.264

Pointer processing

VC-4

TU-2

TU-12

TU-11

VC-2

VC-12

VC-11

TU-3

C-12

C-2

C-11

C-3

N = 1, 4

VC-3

be mapped into concatenated VC-2 virtual containers.

TUG-3

Mbit/s

Mbit/s

Mbit/s

Mbit/s

Mbit/s

Mbit/s

AU-3 VC-3

x7

x3


3-2 62.1013.105.11-A001

3.2 C-4 to STM-N

C-4 to AU-4

The 139.264 Mbit/s signal is assembled in a C-4 container. Then the VC-5 is generated by adding the POH. It is composed of 261 columns, each consisting of 9 rows.

By adding the AU-4 pointer, the VC-4 is converted into an AU-4. The AU pointer indicates the relative offset between the frame start of the VC and the STM-1 frame.

AU-4 to AUG

The AU-4 Administrative Unit is converted into an AUG arrangement. The AUG represents an information structure composed of 9 rows consisting of 261 columns plus 9 additional bytes in row 4 for the AU pointers. In the example depicted below, the AUG consists of one VC-4 and one AU-4 poin-ter. The AU-4 and AUG are identical.

xN x1C-4AU-4AUGSTM-N

139,264VC-4

N=1, 4

Mbit/s

Fig. 3-2 Multiplexing of AU-4 to AUG

J1

B3

C2

G1

F2

H4

F3

K3

N1

VC-4-POH

H1 Y Y H2 1* 1* H3 H3 H3

VC-4

AU-4

AUG

no fixed phase

fixed phase

C-4

1 261


62.1013.105.11-A001 3-3

AUG to STM-N

The AUGs generated this way can now be either assembled in a STM-1 frame by mapping in an AUG directly or in an STM-N frame by multiplexing N x AUGs byte by byte.

Phase relation

The phase of the VC-4 has no fixed relation to the STM-N frame. The AU-4 pointer indicates the frame start of VC-4. This pointer is transmitted in the STM-N signal and establishes thus the phase relation to the STM-N frame.

The AU-4 pointer has a defined phase relation to the AUG and thus to the STM-N frame.

Fig. 3-3 Multiplexing N x AUGs into STM-N

1 9

10 261

1 9

10 261

123...N123...N

SOH

N x 9

123...N123...N

N x 261STM-N

# 1 # 2

SOH

AUG AUG


3-4 62.1013.105.11-A001

3.3 C-3 to STM-N

.

The 34.368 Mbit/s signal (44.736 Mbit/s) is assembled in a C-3 container. Then the VC-3 is generated by adding the POH. This virtual container is composed of 85 columns with 9 rows each.

For mapping three VC-3s into a AUG, two columns with fixed stuffing infor-mation must at first be inserted in VC-3 (3 x (85 +2) = 261).

In order to achieve a relatively uniform distribution of this stuffing information, it is inserted in columns 30 and 59. These extended VC-3s obtain their phase relation to the STM-N signal by adding an AU-3 pointer. The three AU-3s generated have the same fixed phase relation to the STM-N signal. The structure of the AUG is filled by multiplexing the three AU-3s byte by byte.

xN x3C-3AU-3AUGSTM-N VC-3

N=1, 4

44,736

34,368

Mbit/s

Mbit/s

Fig. 3-4 Multiplexing of three AU-3s into AUG

J1

B3

C2

G1

F2

H4

F3

K3

N1

VC-3-POH

1 30 59 87

J1

B3

C2

G1

F2

H4

F3

K3

N1

VC-3-POH

1 30 59 87

J1

B3

C2

G1

F2

H4

F3

K3

N1

VC-3-POH

1 30 59 87

H1 H2 H3

A

H1 H2 H3

B

H1 H2 H3

C

A B C A B C A B C

AB

C

AB

C

AU-3 AU-3 AU-3

VC-3 VC-3 VC-3

AUGA

BC

no fixed phase no fixed phase no fixed phase


62.1013.105.11-A001 3-5

The AUGs thus generated can now be assembled in an STM-1 frame by mapping in an AUG directly or in a STM-N frame by multiplexing N x AUGs byte by byte. In this connection, it is of no importance whether the AUGs con-tain AU-3s or AU-4s, since the structure (261 columns each with 9 rows + 9 bytes for pointer) is always the same.

Phase relation

The phase of the VC-3 has no fixed relation to the STM-N frame. The AU-3 pointer indicates the frame start of the VC-3. This pointer is transmitted in the STM-N signal and establishes thus the phase relation to the STM frame.

For each VC-3, the STM-N transmits one pointer, i.e. it contains a total of three pointers.

The AU-3 pointer has a defined phase relation to the AUG and thus to the STM-N frame.


3-6 62.1013.105.11-A001

3.4 Two-step multiplexing of C-3 into STM-N

The 34.368 Mbit/s signal (44.736 Mbit/s) is assembled in a C-3 container. Then the VC-3 is generated by adding the POH. This virtual container is composed of 85 columns, each consisting of 9 rows.

By providing the VC-3 with a pointer, the TU-3 Tributary Unit is generated. This TU-3 is then converted into a TUG-3 arrangement by adding stuffing information.

A TUG-3 is composed of 86 columns. Up to three TUG-3s can be multiplexed into one VC-4.

A VC-4 has a POH and is composed of 261 columns. Behind the POH of the VC-4, two columns with fixed stuffing information (pos. justification bits) are inserted. In the remaining 258 columns, the three TUG-3s are multiplexed by turns into the VC-3 byte by byte. This process results in a total of 3 x 86 + 2 + 1 = 261 columns.

x N x1

x3

x1VC-3

AU-4AUGSTM-N

TUG-3

44.736

34.368

VC-4

TU-3 C-3

N=1, 4

VC-3TUG-3Mbit/s

Mbit/s

Fig. 3-5 Multiplexing of one TUG-3 into one VC-4

TUG-3(A)

1 86

TUG-3(B)

TUG-3(C)

A B C A B C A B C A B CA B C

1 2 3 4 5 6 7 8 9 10 1112 261

POH

Stuffing information

VC-4

1 86 1 86


62.1013.105.11-A001 3-7

Phase relation

In the first three bytes of the first column, the TU-3 pointer sets up the phase relation between VC-3 and TUG-3.

TUG-3 has a fixed phase relation to VC-4. AU-4 sets up the phase relation to the STM-N signal.

Fig. 3-6 TU-3 pointer

J1

B3

C2

G1

F2

H4

F3

K3

N1

VC-3-POH

C-3VC-3

H2

H3TUG-3

85 columns

H1

86 columns

Stu

ffing

bits

TU-3pointer


3-8 62.1013.105.11-A001

3.5 C11, C12 and C2 to TUG-2

Depending on their bit rate, the payload signals are assembled in containers C-n of appropriate size. The Virtual Containers (VC-n) are generated by adding the POHs. By providing these VC-n containers with their pointers, the TU-n Tributary Units are generated.

Since all SDH stuctures are based on a structure composed of 9 rows, the TUs can be described as a structure with a certain number of columns and nine rows.

TU-11

The capacity of a TU-11 is 1,728 kbit/s = 27 bytes per 125 µs. A TU-11 can be described as a structure composed of three columns and nine rows.

TU-12

The capacity of a TU-12 is 2,304 kbit/s = 36 bytes per 125 µs. A TU-12 can be described as a structure composed of four columns and nine rows.

x1

TUG-2x4

x3

6.312

2.048

1.544

TU-2

TU-12

TU-11

VC-2

VC-12

VC-11

C-12

C-2

C-11 Mbit/s

Mbit/s

Mbit/s

Fig. 3-7 TU-11 Tributary Unit

1

2

27

TU-1127

bytes

125 µs

1 2 3

27

9 r

ows

3 columns

1,728 kbit/s


62.1013.105.11-A001 3-9

TU-2

The capacity of a TU-2 is 6,912 kbit/s = 108 bytes per 125 µs. A TU-2 can be described as a structure composed of 12 columns and nine rows.


1

2

36

TU-1236

bytes

125 µs

1 2 3

9 ro

ws

4 columns

2,304 kbit/s

4

36


1

2

108

TU-2108

bytes

125 µs

1 2 3

9 ro

ws

12 columns

6912 kbit/s

4

108

5 6 7 8 9 10 11 12


3-10 62.1013.105.11-A001

TUG-2

A TUG-2 is generated by multiplexing

4 x TU-11 or3 x TU-12 or1 x TU-2

column by column. Thus, the TUG-2 frame represents an arrangement in which each byte of a TU has its fixed position.

Fig. 3-10 Multiplexing TU-11, TU-12 and TU-2 into TUG-2

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

1

2

3

1

2

3

1

2

3

TU-11 TU-12 TU-2

TUG-2

4 x 3 x 1 x


62.1013.105.11-A001 3-11

3.6 TUG-2 to TUG-3

A TUG-3 frame can be filled by multiplexing seven TUG-2 frames byte by byte. The first two columns are contain stuffing information.

Phase relation

The TU-11, TU-12 and TU-2 Tributary Units and the TUG-2 and TUG-3 Tri-butary Unit Groups have a fixed phase relation to each other. A direct multi-plexing process without pointer matching is therefore possible.

x1

TUG-2x4

x3

6.312

2.048

1.544

TU-2

TU-12

TU-11

VC-2

VC-12

VC-11

C-12

C-2

C-11 Mbit/s

Mbit/s

Mbit/s

TUG-3

x7

Fig. 3-11 Multiplexing seven TUG-2s into one TUG-3

12

34

12

34

12

34

12

3

12

3

12

3

12

3

TU-11 TU-12 TU-2

12

34

56

7

12

34

56

7

12

34

56

7

12

34

56

7

12

34

56

7

1 234 . . . 868482

(1) (2) (3) (7)

Stu

ffing

info

TUG-2

TUG-3


3-12 62.1013.105.11-A001

3.7 TUG-2 to VC-3

A VC-3 Virtual Container can be filled by multiplexing seven TUG-2 frames byte by byte. In doing this, seven TUG-2s are multiplexed into columns 2 to 85. The VC-3 POH occupies column 1 of the VC-3.

x1

TUG-2x4

x3

6.312

2.048

1.544

TU-2

TU-12

TU-11

VC-2

VC-12

VC-11

C-12

C-2

C-11 Mbit/s

Mbit/s

Mbit/sx7VC-3

Fig. 3-12 Multiplexing seven TUG-2s into one VC-3

12

34

12

34

12

34

12

3

12

3

12

3

12

3

TU-11 TU-12 TU-2

12

34

56

7

12

34

56

7

12

34

56

7

12

34

56

7

12

34

56

7

1 23 4 . . . 858381

(1) (2) (3) (7)

VC-3

TUG-2

POH

VC-3

Mapping procedures

62.1013.105.11-A001 4-1

4 Mapping proceduresFor all defined PDH bit rates there are mapping procedures which permit the plesiochonous bit rates to be assembled in the corresponding containers.

These mapping procedures are always based on a positive justification pro-cess, i.e. the transmission capacity of the container is larger than the maxi-mum amount of information received.

In order to compensate the difference between the information received and transmitted, useful information or stuffing information must be inserted at defined points.

In the following sections, the mapping procedures available for signals with bit rates normally used in Europe are described.

4.1 Asynchronous mapping of 140 Mbit/s signals into VC-4

A VC-4 is composed of 261 columns, each consisting of 9 rows. The first column is occupied by the VC-4 POH. Each row is split up into 20 blocks of 13 bytes each. With nine rows, this results in a total number of 20 x 9 = 180 blocks (see marks in figure below). The overhead bytes are not taken into account here.

The first byte of each block is a special byte, the following 12 bytes contain (12 x 8) = 96 information bits.

The special bytes are referred to as W, X, Y and Z and have the following order:

W is a normal information byte. Y is a stuffing byte, i.e. its contents are not defined. The bits of the X byte are assigned as follows:

C R R R R R O O

The O bits can be used as overhead bits for the PDH. Five R bits are filled

Fig. 4-1 Splitting up VC-4 into 13-byte blocks

1 2 3 4 5 5 6 7 8 9 10 11 12 13 14 ... 256 257 258 259 260 261J1B3C2G1F2H4F3K3N1

Block 2 Block 20Block 1

VC-4POH

Block 180

Mapping procedures

4-2 62.1013.105.11-A001

with undefined stuffing information. The C bit is a stuffing check bit which includes the information as to whether this row contains traffic or justification information in the stuffing position. If the C bit is “0”, the stuffing bits are real traffic bits. If it is “1”, the stuffing information consists of justification bits only.

Since the X byte is transmitted 5 times per row, five stuffing check bits are available. On the Rx side, a majority decision prevents transmission errors from leading to a false interpretation of the stuffing bit contents.

The Z byte is occupied as follows:

I I I I I I S R

It contains six information bits (I), one fixed stuff bit (R) as well as the justifi-cation bit (S) that can be used for real or stuffing information.

The following figure shows the first row of VC-20 divided up into 20 blocks.

Fig. 4-2 Asynchronous mapping of 140 Mbit/s signals into VC-4

WJ1 96 I X 96 I Y 96 I Y 96 I Y 96 I

X 96 I Y 96 I Y 96 I Y 96 I X 96 I

Y 96 I Y 96 I Y 96 I X 96 I Y 96 I

Y 96 I Y 96 I X 96 I Y 96 I Z 96 I

1 12 bytes

POH byte

Mapping procedures

62.1013.105.11-A001 4-3

An evaluation of this assignment leads to the following result:

VC-4 sum bit rate = 149,760 kbit/s

Nominal bi trate fs 139,264 kbit/s

Bit rate w/o stuffing positions 139,248 kbit/s = fs - 1 x 10-4

Bit with stuffing positions 139,320 kbit/s = fs + 4 x 10-4

The nominal bit rate is achieved on transmission of 2 x information and 7 x justification bits in the nine possible stuffing positions.

Bytes Information bits

Fixed stuffing bits

Stuffing check bits

Possible justifi-cation bits

Overhead bits

240 x Inf1 x W13 x Y

5 x X1 x Z

1.9208

6

10425

15

110

260x 9 2340

1.93417.406

1301.170

545

19

1090

Bit rate[kbit/s] 139,248 9,360 360 72 720


Mapping procedures

4-4 62.1013.105.11-A001


The VC-3 is composed of 85 columns of 9 rows each. The first row is occu-pied by the VC-3 POH. For the mapping process, all other rows are combi-ned so that always three of them form one partial frame.

The assignment of these partial frames is depicted in the following diagram. Columns 39 and 82 contain the C bytes which include the stuffing check bits C1 and C2. The A and B bytes (columns 83, 84) contain the stuffing positions S1 and S2. All partial frames are occupied in the same way.

In contrast to the VC-4 mapping procedure, two stuffing positions, i.e. S1 and S2, with the associated five stuffing check bits C1 and C2 are transmitted here. Additional overhead bytes are not provided.

Fig. 4-3 VC-3 divided up into three partial frames

1 2 3 4 5 5 6 7 8 ... 80 81 82 83 84 85J1 ...B3 ...C2 ...G1 ...F2 ...H4 ...F3 ...K3 ...N1 ...

VC-3POH

Partial frame 1

Partial frame 2

Partial frame 3


2 3 4 5 5 6 7 8 9 ... 17 18 ... 39 ... 58 59 60 61 ... 81 82 83 84 85... ... C ... ... C... ... C ... ... C... ... C ... ... A B

Byte C

Bytes A, B S2 I I I I I I IR R R R R R R S1

R R R R R R C1 C2R: Fixed stuffing bitsC1, C2: Stuffing check bitS1, S2: Possible stuffing bitsI: Information bit

R R R R R R R R

I I I I I I I I

Mapping procedures

62.1013.105.11-A001 4-5

The evaluation of the information transmitted in each partial frame leads to the following result:


Nominal bit rate fs 34.368 kbit/s

Bit rate w/o stuffing positions 34.344 kbit/s = fs - 7 x 10-4

Bit rate with stuffing positions 34.392 kbit/s = fs + 7 x 10-4

The nominal bit rate is achieved on transmission of 1 x information and 1 x justification bit in the two possible stuffing positions.

Information bits

Fixed stuffing bits

Stuffing check bits


Overhead bits

1.431 573 10 2 0

x 34.293 1.719 30 6 0

Bit rate[kbit/s] 34,344 13,752 240 48 0

VC-3 sum bit rate = 48,384kbit/s

Mapping procedures

4-6 62.1013.105.11-A001


The VC-12 consists of 140 bytes per 500 µs multiframe (4 x 125 µs frames). They are used as shown in the following diagram.

The VC-12 has two stuffing positions (S1, S2). They are controlled by the two stuffing bits (C1, C2). On evaluation of the stuffing check bits C1 and C2, a majority decision is performed on the receive side. The evaluation of the information transmitted in each multiframe leads to the following result:

Nominal bit rate fs 2.048 kbit/sBit rate w/o stuffing positions 2.046 kbit/s = fs - 1 x 10-3

Bit rate with stuffing positions 2.050 kbit/s = fs + 1 x 10-3



C1 C2 O O O O R R

V5R

32 bytes

RJ2

C1 C2 O O O O R R

32 bytes

RN2

C1 C2 R R R R R S1

32 bytes

RK4

S2 I I I I I I I

31 bytes

R

140bytes

500 µs

R: Fixed stuffing bits (info)O: Overhead bitsC1, C2: Stuffing check bitS1, S2: Possible stuffing bitsI: Information bit

Information bits

Fixed stuffing bits

Stuffing check bits


Overhead bits

1.0167

649

6 2 8

Bits/500 µs Bit rate[kbit/s]

1.023

2.046

73

146

6

12

2

4

8

16

VC-12 sum bit rate = 2.224 kbit/s

Mapping procedures

62.1013.105.11-A001 4-7

4.4 Asynchronous mapping of 1.5 Mbit/s signals into VC-11

The VC-11 consists of 104 bytes per 500 µs multiframe. They are used as shown in the following diagram.

The two stuffing positions S1 and S2 are controlled by three stuffing check bits C1 and C2 each.

A majority decision performed on the receive side with regard to the three check bits determines as to whether the associated stuffing position S is interpreted as information bit or as justification bit. The evaluation of the infor-mation transmitted leads to the following result:

Nominal bit rate fs 1.544 kbit/s

Bit rate w/o stuffing positions 1.542 kbit/s = fs - 1.3 x 10-3

Bit rate with stuffing positions 1.546 kbit/s = fs + 1.3 x 10-3


Fig. 4-6 Asynchronous mapping of 1.5 Mbit/s signals into VC-11

C1 C2 O O O O I R

V5

24 bytes

J2

C1 C2 O O O O R R

24 bytes

N2

C1 C2 R R R S1 S2 R

24 bytes

K4

24 bytes

140 bytes

500 µs

R: Fixed stuffing bitsO: Overhead bitsC1, C2: Stuffing check bitS1, S2: Possible stuffing bitsI: Information bit

R R R R R R I R

Information bits

Fixed stuffing bits

Stuffing check-bits


Overhead bits

7683

2413

6 2 8

Bits/500 µs Bit rate[kbit/s]

771

1.542

37

74

6

12

2

4

8

16

VC-12 sum bit rate = .,648 kbit/s

Mapping procedures

4-8 62.1013.105.11-A001

4.5 Mapping 1.5 Mbit/s signals into VC-12

In order to be able to process 1.5 Mbit/s signals in SDH environments just like 2 Mbit/s signals, it is possible to transport both VC-11 and VC-12 Virtual Containers as TU-12.

For this purpose, a VC-11 is generated first of all. This VC-11 consists of 104 bytes which are located in 36 rows (4 basic frames) with 3 columns each. In each row, the 9th byte of the third column is missing. On providing a column with fixed stuffing bytes (with even parity!) between column 2 and 3, the 140 bytes of a VC-12 are obtained.

In the entire network, the VC-12 generated this way cannot be distinguished from a ’normal’ VC-12. Only in the receiver, the initial VC-11 is recovered by extracting the stuffing information.

Fig. 4-7 Conversion of a VC-11 into a VC-12 (1.5 Mbit/s in VC-12)

V5

J2

N2

K4

V5

J2

N2

K4

Fixed stuffing information with even parity

500 µs

Overhead

62.1013.105.11-A001 5-1

5 OverheadFor monitoring and controlling the SDH network, additional information is transmitted together with the traffic data (payload). This additional informa-tion, called Overhead, is divided up into two main groups, i.e. the Section Overhead and the Path Overhead.

5.1 Section Overhead

Together with the payload, the Section Overhead (SOH) forms an STM-N frame. This frame contains all information required for frame synchronization, maintenance, performance monitoring and various other functions.

The SOH is composed of a block consisting of nine rows of N x 9 columns each (N = 1, 4, 16). For operation, a distinction is made between the Rege-nerator Section Overhead (RSOH) composed of rows 1 to 3 and the Multi-plex Section Overhead (MSOH) consisting of rows 5 to 9. Row 4 of the SOH contains the AU pointer bytes.

While the RSOH is terminated (i.e. disassembled, evaluated and newly gene-rated) at each regenerator point, the MSOH passes the regenerator without being modified and is only terminated at the multiplexers (where the payload is assembled or disassembled).

On generation of STM-4 and STM-16, the number of SOH columns increa-ses by 4 and 16, respectively.

Fig. 5-1 Overhead bytes

Spare channels

AU-4

STM-1

261 bytes

Connection check

Ident. of VC contents

Path status

User channel

J1

B3

C2

G1

F2

H4

F3

K3

K4

VC-4

C-4Payload

D.. Data transmission

Future purposes

B1 E1

D1 D2

D4

D7

D5

D8

S1 Z1 Z1 Z2 M1 E2

D9

D6

K2

D3

F1

A2 J0/A1 A1 A1 A2 A2

B2 B2 B2 K1

H3H1 H3 H3H2

D10 D11 D12

User channel

STM identifier

Multiframe indic.

RSOH

MSOH

Service channel

BER monitoring

Voice

Section REI

Frame alignment

BER moni-toring

Synchronization status

Autom. prot. switch. sign.

Voice

Pointer

Z2

Autom. prot. switching

Managem. purposes

signal

C1

Overhead

5-2 62.1013.105.11-A001

5.1.1 Regenerator Section Overhead (RSOH)

A1, A2 Frame align-ment signal

Assignment:A1 = 1111 0110A2 = 0010 1000

C1 STM-N identifier

The C1 byte can be used to check an STM-N connection between two multi-plexers (old meaning, new see J0).

J0 Path Trace

16 byte telegram for connection check

B1 BIP-8 monito-ring

Only defined in STM-1 no. 1. This byte is used for error monitoring on the Regenerator Section. The BIP-8 value is calculated over all bits of the current STM-N frame to receive an even parity and is inserted in the next frame.

E1 Regenera-tor ser-vice channel

Only defined in STM-1 no. 1. This byte can be used to generate a 64 kbit/s voice channel for service chan-nel purposes. This channel is accessible at all regenerators and the associa-ted multiplexers.

F1 User channel

Only defined in STM-1 no. 1.This byte is reserved for network operator purposes. This channel is accessi-ble at all regenerators and the associated multiplexers.

D1, D2, D3 Data Commu-nication Channel (DCC)

Only defined in STM-1 no. 1.These three bytes form a common DCCR data channel with a capacity of 192 kbit/s for the regenerator section. This channel is used to exchange management information.

5.1.2 Multiplex Section Overhead (MSOH)

B2 BIP-N x 24 monitoring

N x 3 bytes for bit error monitoring of the multiplex section. The BIP-Nx24 value is calculated to obtain an even parity over all bits of the current STM-N frame with the exception of the RSOH rows (row 1 to 3) and is inserted in the next frame.

K1, K2 Autom. pro-tection swit-ching

Only defined in STM-1 no. 1.These two bytes can be used to control automatic protection switching pro-cesses. The assignment of these bytes is defined for different protection swit-ching configurations (1+1, 1:n). Bits 6, 7 and 8 of the K2 byte are reserved for future applications. The following assignments have been defined:

’111’ for Multiplex Section AIS MS-AIS,

’110’ for Multiplex Section Remote Defect Indication MS-RDI.

D4...D12 Data Com-munication Channel (DCC)

Only defined in STM-1 no. 1.These eight bytes form a common data channel ( DCCM) with 576 kbit/s for the Multiplex Section.

Overhead

62.1013.105.11-A001 5-3

S1 Synchroniza-tion status (Synchroni-zation Sta-tus Message (SSM))

Only defined in STM-1 no. 1.The SSM informs the operator on the performance of the clocks used in the unit.

Z1,Z2 Spare bytes These N x 4 bytes are reserved for future applications.

M1 Section REI Remote Error Indication for the Multiplex Section.

E2 Multiplexer service chan-nel

Only defined in STM-1 no. 1.This byte can be used to form a 64 kbit/s voice channel for service channel purposes. This channel is accessible only at multiplexers.

5.2 Path Overhead

Together with Container C, the Path Overhead (POH) forms the Virtual Con-tainer VC. The POH capacity depends on the path level. While the higher-order POH is composed of 9 bytes (1 row), only four bytes are available for the lower-order POH.

5.2.1 Higher-order POH (VC-3/VC-4)

The higher-order POH is located in the first column (9 bytes) of VC-3 or VC-4. It is formed on generation of the VC-3 (VC-4) and remains unchanged (exception: N1 byte) until the Virtual Container is disassembled in order to be able to monitor the complete path.

The following bytes have been defined:

Fig. 5-2 Higher-order POH

Connection check

Identif. of VC contents

Path status

User channel

J1

B3

C2

G1

F2

H4

F3

K3

N1

C-4Payload

Autom. prot. switch.

Multiframe indicator

BER monitoring

User channel

Managem. purposes

Overhead

5-4 62.1013.105.11-A001

J1 Path Trace This is the first byte in the VC-3/VC-4. Its position is indicated by the pointer and represents thus the reference point of the VC-3/VC-4 structure. This byte can be used to transmit either a repetitive telegram with a length of 64 bytes in any format or a 16-byte telegram in the so-called E.164 format. The Path Trace permits the link to be checked over the complete path.

E.164 format:

The first byte marks the beginning of the frame. It includes the result of a CRC-7 calculation performed for the previous frame. The following 15 bytes are used to transmit the ASCII signs. If the 16-byte format shall be transmit-ted in a 64-byte format, it must be repeated four times.

B3 BIP-8 monitoring This byte is used for error monitoring over the complete path. The BIP-8 value is calculated over all bits of the current VC3/VC-4 to obtain an even parity and is inserted into the next VC3/VC-4.

C2 Contents identifier This byte is used as identifier for the VC contents. The following table gives an overview of the defined codings of the C2 byte.

G1 Path status Via this byte, the transmission performance data are reported by the path end to the VC source. Thus, it is possible to monitor the complete path from any point or from any of the two ends.

The following information is transmitted:

MSB1 2 3 4

LSB1 2 3 4

Hex. code

Explication

0 0 0 0 0 0 0 0 00 Unequipped

0 0 0 0 0 0 0 1 01 Equipped - non specific

0 0 0 0 0 0 1 0 02 TUG structure

0 0 0 0 0 0 1 1 03 Locked TU

0 0 0 0 0 1 0 0 04 Asynchronous mapping of 34,368 kbit/s or 44,736 kbit/s into Container-3

0 0 0 1 0 0 1 0 12 Asynchronous mapping of 139,264 kbit/s into Container-4

0 0 0 1 0 0 1 1 13 ATM mapping

0 0 0 1 0 1 0 0 14 MAN (DQDB) mapping

0 0 0 1 0 1 0 1 15 FDDI mapping

MAN: Metropolitan Area NetworkDQDB: Dual Queue Dual BusFDDI: Fibre Distributed Data Interface

Table 5-1 C2 byte mapping code

Fig. 5-3 VC3/VC4 path status (G1)

1 2 3 4 5 6 7 8

REI RDI (not used)

Overhead

62.1013.105.11-A001 5-5

Bit 1..4 VC Path Remote Error Indication (REI).

The binary value transmitted corresponds to the number of parity violations detected on comparison of B3 with BIP-8. Numbers higher than 8 are evalua-ted as 0 errors, since the BIP-8 error monitoring method does not permit errors > 8 to be detected.

Bit 5 VC Path Remote Defect Indication (RDI)

This signal is returned whenever the VC-3/VC-4 assembler does not receive a valid signal. The following conditions have been defined:

a) Path AISb) Loss of signalc) Wrong path trace (J1 byte)

In each of these cases, bit 5 is set to logic ’1’, otherwise it is ’0’.

Bit 6...8 not yet defined.

F2 User channel This 64 kbit/s channel is available for communication between the path start and path end for user purposes.

H4 Multiframe indicator On generation of a payload multiframe, this byte is used in the lower-order VC for multiframe synchronization. It is therefore payload-specific.

F3 User channel This 64 kbit/s channel is available for communication between the path start and path end for user purposes.

K3 Autom. protection switching

Bits 1 to 4 are provided for controlling automatic protection switching proces-ses at the higher-order level. Bits 5 to 8 are reserved for future applications.

N1 Network operator byte

This byte is provided for management purposes, e.g. Tandem Connection Maintenance.

Fig. 5-4 TU multiframe indicator H4

1 2 3 4 5 6 7 8

P1 P1 SL2 SL1 C3 C2 C1 T

500 µs TU multiframe

Overhead

5-6 62.1013.105.11-A001

5.2.2 Lower-order POH (VC-1x/VC-2)

The lower-order POH is composed of the V5, J2, N2 and K4 bytes. These are transmitted in four consecutive frames forming a 500 µs multiframe.

V5 V5 is the first byte in VC-1x/VC-2. The TU-1x/TU-2 pointer ’points’ at this byte and represents thus the reference point of the lower-order VC. V5 is used for transmitting the following information:

Definitions:

Bit 1, 2 BIP-2 moni-toring

These two bits are used for error monitoring over the complete lower-order path. The result is calculated to obtain an even parity. The calculation is per-formed for the complete VC-1/VC-2 including the POH bytes, however, without bytes V1 to V4 of the TU-1/TU-2 pointer. If information is transmitted in byte V3 in negative justification processes, this byte is included in the cal-culation.

Bit 3 Remote Error Indication (REI)

By setting this bit to logic ’1’, the VC source is informed that one or several parity violations were detected in the BIP-2 calculation. If there are no errors, this bit is logic ’0’.

Bit 4 Remote Failure Indi-cation (RFI)

On detection of a fault or failure, this bit is set to logic ’1’. RFI is sent back to the VC source.

Fig. 5-5 Lower Order POH

V5

J2

N2

K4

500 µs

POH

Frame 1

Frame 2

Frame 3

Frame 4

Fig. 5-6 Bit assignment of the V5 byte

1 2 3 4 5 6 7 8

BIP-2 Signal LabelREI RDIRFI

Overhead

62.1013.105.11-A001 5-7

Bit 5, 6, 7 Contents identifier

These three bits correspond with the C2 byte of the higher-order POH. The use of the three special mapping indicators 010, 011 and 100 is optional. However, these values must not be used for other purposes.

Bit 8 VC-Path Remote Defect Indi-cation (RDI)

This bit is sent back to the VC source. In normal operation, it is logic ’0’. On reception of TU1x/TU2 Path AIS or detection of LOS or wrong path trace (J2), it is set to logic ’1’.

J2 Path Trace The function of this byte is identical with that of byte J1 of the higher-order POH. This byte can be used to transmit a 16 byte telegram in the E.164 for-mat. Using the Path Trace, it is possible to check the link over the complete path.

K4 Autom. pro-tecting swit-ching

Bits 1 to 4 are provided for controlling automatic protection switching proces-ses at the lower-order level. Bits 5 to 8 are reserved for future applications.

N2 Network ope-rator byte

This byte is provided for management purposes, e.g. Tandem Connection Maintenance.

b5 b6 b7 Meaning

0 0 0 Unequipped

0 0 1 Equipped - non specific

0 1 0 Asynchronous

0 1 1 Bit-synchronous

1 0 0 Byte-synchronous

1 0 1

equipped - unused1 1 0

1 1 1

Fig. 5-7 V5[5-7] Mapping Code

Overhead

5-8 62.1013.105.11-A001

Pointers

62.1013.105.10-A001 6-1

6 PointersA worldwide synchronous network represents an ideal condition that can in practise not always be achieved. In synchronous networks, failures can lead to islands without clock connection. In this case, a free-running oscillator must supply these islands with the required clock information.

The introduction of pointers in the SDH created the possibity to maintain the synchronous character of the transported information in a not clock-synchro-nous environment. The information sent to such an island can thus be pro-cessed without any loss of information and can be passed on although the clock bit rates are not identical.

The payload has no fixed phase relation to the frame. In order to be able to access the payload, a pointer is transmitted in the overhead block. It permits the dynamic adaptation of the phase of the Virtual Container to the frame. In this connection, dynamic means:

1. The phase of the Virtual Container can differ from that of the frame. 2. At different frequencies, the phase position can continuously vary without

causing any loss of information.

6.1 Pointer value modification

There are two possibilities of modifying the pointer value:

a) Setting a new pointer valueb) Frequency matching.

6.1.1 Setting a new pointer value

In case of modifications of the payload, it may be necessary to set a new pointer value. In order to indicate this change, the so-called “New Data Flag (NDF)“ is set. Then the new pointer value is transmitted.

On the receive side, the NDF is evaluated. The new pointer value received indicates the new position of the Virtual Container.

The NDF with the new pointer value is transmitted only once, i.e. in the first frame. There must not be any further pointer operations within the next three frames.

6.1.2 Frequency matching

If the frequency of the STM-N frame is not exactly identical with the one of the VC frame, the pointer value is increased or decreased by 1 at regular intervals, while frame matching is simultaneously performed by a positive or negative justification process.

After each pointer correction, at least three frames must be transmittedwithout pointer modification.

The frequency matching process for AU pointers is explained in the following section. The process for the TU pointers is identical.

Pointers

6-2 62.1013.105.10-A001

Positive justification

If the frame frequency of the VC is lower than that of the STM-N frame, stuf-fing bytes must be inserted and the pointer value must be increased by 1 at regular intervals.

The stuffing bytes are inserted directly behind the last H3 byte. For an AU-3 one stuffing byte, for an AU-4 three stuffing bytes are inserted. The new poin-ter (P+1) is then transmitted starting at the next frame.

The next VC starts at the position indicated by the new pointer.

Fig. 6-1 Pointer modification (positive justification)

H1 H2 H3

H1 H2

H1 H2

Beginning of

STM-1 frame

2701 9

Frame n

Frame n+1

Frame n+2

Frame n+3

125 µs

250 µs

375 µs

500 µs

H1 H2 H3Pointer (P)

Pointer (P)

Pointer (P)

Pos. stuffing

New pointer (P+1)

H3

H3

byte(s)

VC-4

Pointers

62.1013.105.10-A001 6-3

Negative justification

If the frame frequency of the VC is higher than that of the STM-N frame, addi-tional information of the VC must be transmitted in the H3 bytes and the poin-ter value must be decreased by 1 at regular intervals.

The following three H3 bytes are filled with information. With AU-3, only the H3 byte belonging to the VC to be stuffed is filled with information. The new pointer (P-1) is transmitted starting at the next frame.

The next VC starts at the position indicated by the new pointer.

Fig. 6-2 Pointer modification (negative justification)

H1 H2

H1 H2 H3

H1 H2

Beginning of

STM-1 frame

2701 9

Frame n

Frame n+1

Frame n+2

Frame n+3

125 µs

250 µs

375 µs

500 µs

H1 H2 H3

Neg. justification(data)

Pointer

Pointer (P)

Pointer (P)

New poin-ter (P-1)

H3

VC-4

bytes

Pointers

6-4 62.1013.105.10-A001

6.2 Pointer types

In the Synchronous Digital Hierarchy (SDH), there are two pointer types: the AU pointer and the TU pointer:

♦ AU pointer: AU-3, AU-4 pointer♦ TU pointer: TU-3, TU-2, TU-11, TU-12 pointer

6.2.1 AU-3 pointer

The AU-3 pointer permits a dynamic adaptation of the phase of a VC-3 to the frame of the Administrative Unit AU (and thus to the STM frame). In this con-nection, dynamic means:

1. The phase of VC-3 can differ from that of the STM frame. 2. At different frequencies, the phase position can continuously vary without


The AU-3 pointer is located in the 4rth row of the SOH. It is composed of three bytes referred to as H1, H2 and H3.

The three bytes with number “0” start to the right of the last pointer byte (H3). The byte nos. 522 to 782 are located in front of the pointer. Consequently, pointer values higher than 521 point to the next STM-1 frame.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 . . . . ... . . . . 269 270

1 522 522 522 523 523 523 524 524 524 ... 607 607 607 608 608 608

2 609 609 609 610 610 610 611 611 611 ... 694 694 694 695 695 695

3 696 696 696 697 697 697 698 698 698 ... 781 781 781 782 782 782

4 H1 H1 H1 H2 H2 H2 H3 H3 H3 0 0 0 1 1 1 2 2 2 ... 85 85 85 86 86 86

5 87 87 87 88 88 88 89 89 89 ... 172 172 172 173 173 173

6 174 174 174 175 175 175 176 176 176 ... 259 259 259 260 260 260

7 261 261 261 262 262 262 263 263 263 ... 346 346 346 347 347 347

8 348 348 348 349 349 349 350 350 350 ... 433 433 433 434 434 434

9 435 435 435 436 436 436 437 437 437 ... 520 520 520 521 521 521

1 522 522 522 523 523 523 524 524 524 ... 607 607 607 608 608 608

2 609 609 609 610 610 610 611 611 611 ... 694 694 694 695 695 695

3 696 696 696 697 697 697 698 698 698 ... 781 781 781 782 782 782

4 H1 H1 H1 H2 H2 H2 H3 H3 H3 0 0 0 1 1 1 2 2 2 ... 85 85 85 86 86 86

5 87 87 87 88 88 88 89 89 89 ... 172 172 172 173 173 173

Fig. 6-3 AU-3 pointer

Pointers

62.1013.105.10-A001 6-5

The three AU-3 pointers are interleaved byte by byte and arranged as fol-lows:

The three pointers are independent of each other and indicate the beginning of the corresponding VC, only the bytes of this VC being counted and those of all others being skipped.

H1, H2 H1 and H2 are read as a 16-bit data word. Bits 1 to 4 form the so-called New Data Flag NDF. The NDF indicates as to whether a new pointer value has to be set. Two values have been defined:

NDF 0110 = disabled Maintain pointer value NDF 1001 = enabled Set new pointer value

Bits 5 and 6 are referred to as S S. They are set to S S = 10.

Bits 7 to 16 represent the pointer value. As a binary value, the pointer value indicates the offset between the VC start and the reference point expressed in bytes.

The bits are by turns referred to as I bit and D bitt (Increment and Decre-ment). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).

On the decoder side, an inversion of the I bits is followed by a majority deci-sion, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the cur-rent VC are ignored.

In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated and the informa-tion contained in H3 is inserted into the payload of the current VC.

H3 H3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC frame frequency higher than STM frame frequency). In all other cases of application, the content of this byte is not defined.

H1(a) H1(b) H1(c) H2(a) H2(b) H2(c) H3(a) H3(b) H3(c)

Pointer a

Pointer b

Pointer c

N N N N S S I D I D I D I D I D

New Data Flag Pointer value

Pointers

6-6 62.1013.105.10-A001

6.2.2 AU-4 pointer

In the AU-4, only every third byte is provided with a counting no.. The three bytes with number “0” start to the right of the last pointer byte (H3). The byte nos. 522 to 782 are located in front of the pointer in rows 1 to 3. Conse-quently, pointer values higher than 521 point to the next STM-1 frame.

H1, H2 H1 and H2 are read as a 16-bit data word. It includes the New Data Flag NDF and the pointer value.

NDF 0110 = disabled Maintain pointer valueNDF 1001 = enabled Set new pointer value

The bits S S are set to ’1 0’.

Bits 7 to 16 represent the pointer value. As a binary value, the pointer value indicates the offset between the VC-4 start (J1 byte) and the reference point in 3-byte increments.

The bits are by turns referred to as I bit and D bit (Increment and Decrement). If the pointer value is to be increased by a positive justification process, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).

On the decoder side, an inversion of I bits is followed by a majority decision, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the cur-rent VC-4 are ignored.

In negative justification processes, the five D bits (bit 8, 10, 12,14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and

1 2 3 4 5 6 7 8 9 10 11 12 13 14 . . . . ... . . . . 269 270

1 522 - - 523 - - 524 - - ... 607 - - 608 - -

2 609 - - 610 - - 611 - - ... 694 - - 695 - -

3 696 - - 697 - - 698 - - ... 781 - - 695 - -

4 H1 Y Y H2 1* 1* H3 H3 H3 0 - - 1 - - 2 - - ... 85 - - 86 - -

5 87 - - 88 - - 89 - - ... 172 - - 173 - -

6 174 - - 175 - - 176 - - ... 259 - - 260 - -

7 261 - - 262 - - 263 - - ... 346 - - 347 - -

8 348 - - 349 - - 350 - - ... 433 - - 434 - -

9 435 - - 436 - - 437 - - ... 520 - - 521 - -

1 522 - - 523 - - 524 - - ... 607 - - 608 - -

2 609 - - 610 - - 611 - - ... 694 - - 695 - -

3 696 - - 697 - - 698 - - ... 781 - - 695 - -

4 H1 Y Y H2 1* 1* H3 H3 H3 0 - - 1 - - 2 - - ... 85 - - 86 - -

5 87 - - 88 - - 89 - - ... 172 - - 173 - -

Fig. 6-4 AU-4 pointer

Pointers

62.1013.105.10-A001 6-7

the information contained in H3 is inserted into the payload of the current VC-4.

H3 H3 is the Pointer action byte. In negative justification processes, it is used for transmitting the additional information byte. In all other cases of application, the content of this byte is not defined.

The H1 and H2 bytes not required have been defined as follows:

H1 1 0 0 1 S S 1 1 (S bits not defined, in Fig. „AU-4 pointer“ on page 6 referred to as “Y“)

H2 1 1 1 1 1 1 1 1 (in Fig. „AU-4 pointer“ on page 6 referred to as “1*“)

The bit combination H1 and H2 thus corresponds with the Concatenation Indication CI, i.e. an AU-4 is treated just like three concatenated AU-3s.

If the pointer value is 0, it indicates that the VC starts with the byte directly fol-lowing the last H3 byte.

AU-4 concatenation In case of large payload amounts, several AU-4 Administrative Units are con-catenated. The first AU-4 contains a normal pointer. The associated following AU-4s include the CI instead of the pointer value. This CI indicates that these AU-4s are to be treated in the same way as the previous ones.



1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1

Concatenation Indication CI

Pointers

6-8 62.1013.105.10-A001

6.3 TU-3 pointer

The TU-3 pointer permits a dynamic adaptation of the phase of a VC-3 to the TUG-3 frame. In this connection, dynamic means:

1. The phase of VC-3 can differ from that of the TUG-3 frame. 2. At different frequencies, the phase position can continuously vary without


The TU-3 pointer is located in the first column of the TUG-3 frame. It is com-posed of three bytes referred to as H1, H2 and H3.

H1, H2 H1 and H2 are read as a 16-bit data word. Bits 1 to 4 represent the New Data Flag NDF. The NDF indicates as to whether a new pointer value must be set or not. The following two values have been defined:

NDF 0110 = disabled Maintain pointer valueNDF 1001 = enabled Set new pointer value

Bits 5 and 6 are referred to as S S. They are set to S S = 10.

Bits 7 to 16 represent the pointer value. As binary value, the pointer value indicates the offset between the VC-3 start (J1 byte) and the reference point expressed in bytes.

The bits are by turns referred to as I bit and D bitt (Increment and Decre-ment). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).

On the decoder side, an inversion of the I bits is followed by a majority deci-sion, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the cur-rent VC-3 are ignored.

Fig. 6-5 Multiplexing a VC-3 into a TUG-3

J1

G1

B3

C2

F2

H4

F3

K3

N1

H1

H2

H3

STUFFING

VC-3

TUG-386 columns

TU-3 pointer

VC-3 POH

85 columns

C - 3

Pointers

62.1013.105.10-A001 6-9

In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in H3 is inserted into the payload of the current VC-3.

H3 H3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC-3 frame frequency higher than STM frame frequency). In all other cases of application, the content of this byte is not defined.

If the pointer value is 0, it indicates that the VC-3 starts with the byte directly following the H3 byte. The values for the TU-3 pointer range from 0 to 764.

Pointer values between 595 and 764 point to the next TUG-3 frame!



1 2 3 4 5 6 ... 82 83 84 85 86

1 H1 595 596 597 598 599 ... 675 676 677 678 679

2 H2 680 681 682 683 684 ... 760 761 762 763 764

3 H3 0 1 2 3 4 ... 80 81 82 83 84

4STUFFING

85 86 87 88 89 ... 165 166 167 168 169

5 170 171 172 173 174 ... 250 251 252 253 254

6 255 256 257 258 259 335 336 337 338 339

7 340 341 342 343 344 ... 420 421 422 423 424

8 425 426 427 428 429 ... 505 506 507 508 509

9 510 511 512 513 514 ... 590 591 592 593 594

1 H1 595 596 597 598 599 ... 675 676 677 678 679

2 H2 680 681 682 683 684 ... 760 761 762 763 764

3 H3 0 1 2 3 4 ... 80 81 82 83 84

4 0 - - 1 - ... - - 86 - -

5 85 86 87 88 89 ... 165 166 167 168 169


Pointers

6-10 62.1013.105.10-A001

6.4 TU-2 pointer




The bytes required for the pointer operations are referred to as V1, V2, and V3. These bytes are located in the first byte position of four consecutive TU-2s. The definition of the byte available in the current TU-2 is performed by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.

V1, V2 V1 and V2 can be read as a 16-bit data word. Bits 1 to 4 represent the New Data Flag NDF. The following two values have been defined:

NDF 0110 = disabledNDF 1001 = enabled

Bits 5 and 6 are referred to as S S and indicate the type of the TU. TU-2: S S = 0 0

Bits 7 to 16 represent a 10-bit word, the so-called pointer value. As a binary value, the pointer value indicates the offset between the VC-2 start and the reference point in bytes. The bits are by turns referred to as I and D bit (Incre-ment and Decrement). If the pointer value is to be increased by positive justi-fication, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).


In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in V3 is inserted into the payload of the current


V1 321 322 ... 426 427 V2 0 1 ... 105 106 V3 107 108 ... 212 213 V4 214 215 ... 319 320

V1, V2= Pointer byteV3= Pointer action byteV4= Spare byte

Pointers

62.1013.105.10-A001 6-11

VC-2.

V3 V3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC-2 frame frequency higher than TU-2 frame frequency). In all other cases of application, the content of this byte is not defined.

If the pointer value is 0, it indicates that the VC-2 starts with the byte directly following the V2 byte. The values for the TU-2 pointer range from 0 to 427.


V4 V4 not yet defined.

TU-2 concatenation

In order to be able to transport bit rates not defined by ITU-T within the Syn-chronous Digital Hierarchy (SDH), several TU-2 Tributary Units can be con-catenated to TU-2-mc. Thus, it is possible to transport information in multiples of VC-2 within a VC-2-mc.

Three different concatenation types are possible:

a. Concatenation of consecutive TU-2s in one higher-order VC-3 (conti-guous concatenation).

b. Sequential concatenation of several TU-2s in one higher-order VC-3 (sequential concatenation).

c. Virtual concatenation of TU-2s in one higher-order VC-4 (virtual conca-tenation).

In case of a contiguous concatenation, the first TU-2 receives a valid pointer. All other TU-2s contained in the TU-2-mc receive the Concatenation Indicator (CI) instead of the pointer. The CI indicates that all pointer operations of the first TU-2 are to be perfor-med in the same way in all other TU-2s. The VC-2-mc includes a VC-2 POH which is located in the first VC-2 of the VC-2-mc.

The sequential concatenation permits the simultaneous transport of both TU-2-mc and TU-3 in one VC-4.

In case of a virtual concatenation, all VC-2s of a VC-2-mc receive the same pointer at the beginning of the path. The control circuit ensures that all VC-2s belonging together are accommodated in the same VC-4.



1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1

Concatenation Indication CI

Pointers

6-12 62.1013.105.10-A001

6.5 TU-11 pointer




The bytes required for the pointer operations are referred to as V1, V2 and V3. These bytes are located in the first byte position of four consecutive TU-11s. The definition of the byte available in the current TU-11 is performed by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.



Bits 5 and 6 are referred to as S S and indicate the Type of the TU. TU-11: S S = 1 1

Bits 7 to 16 represent a 10-bit word, the so-called pointer value. As a binary value, the pointer value indicates the offset between the VC-11 start and the reference point expressed in bytes. The bits are by turns referred to as I and D bit (Increment and Decrement). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).


In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in V3 is inserted into the payload of the current VC-11.


V1 78 79 ... 102 103 V2 0 1 ... 24 25 V3 26 27 ... 50 51 V4 52 53 ... 76 77




Pointers

62.1013.105.10-A001 6-13

V3 V3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC-11 frame frequency higher than TU-11 frame frequency). In all other cases of application, the content of this byte is not defined.




Pointers

6-14 62.1013.105.10-A001

6.6 TU-12 pointer




The bytes required for the pointer operations are referred to as V1, V2 and V3. These bytes are located in the first byte position of four consecutive TU-12s. The definition of the byte available in the current TU-12 is performed by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.



Bits 5 and 6 are referred to as S S and indicate the type of the TU. TU-12: S S = 1 0

Bits 7 to 16 represent a 10-bit word, the so-called pointer value. As a binary value, the pointer value indicates the offset between the VC-12 start and the reference point expressed in bytes. The bits are by turns referred to as I and D bit (Increment and Decrement). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15).


In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in V3 is inserted into the payload of the current VC-12.


V1 105 106 ... 138 139 V2 0 1 ... 33 34 V3 35 36 ... 68 69 V4 70 71 ... 103 104


Pointers

62.1013.105.10-A001 6-15

V3 V3 is the Pointer action byte. It is used to transmit an additional information byte in negative justification processes (VC-12 frame frequency higher than TU-12 frame frequency). In all other cases of application, the content of this byte is not defined.






Pointers

6-16 62.1013.105.10-A001

Reference model

62.1013.105.11-A001 7-1

7 Reference model International standards set up for the Synchronous Digital Hierarchy (SDH) and the associated equipment units ensure that networks can be established using equipment from different manufacturers. This is achieved thanks to the introduction of application-independent reference models.

The general reference model (acc. G.783) specifies both the physical charac-teristics (bit rates, optical/electrical level, impedances) and definitions regar-ding the contents of each byte and even bit. These specifications cover the following aspects:

• Frame structure • Identification • Scrambling • Coding/decoding • Mapping procedures • Service channel utilization • Monitoring and control signals.

The essential parts of signal processing are defined as “functions”. Regar-ding external interfaces, previous recommendations were maintained. The reference model is composed of 16 different basic functions. They have an internal function and logic reference points via which the individual blocks communicate with each other. These reference points are no internal test or measuring points and in many cases physically not even obvious. The exter-nal interfaces (inputs and outputs), however, are physically defined.

The SDH definitions used in the reference model such as section, lower-

Fig. 7-1 Reference model for the design of SDH units

STM-M

SPI

T

S

RST MST MSP MSA

G.703

PPI LPA LPT

T

S

T

S

T

S

T

S

T

S

T

S

T

S

LPC HPA

T

S

T

S

HPT HPC

T

S

T

S

T

S

T

S

T

S

T

S

MSA MSP MST RST

T

S

SPI

STM-N

T

S

T

S

G.703

PPI LPA

DCCDCCM R

S SEMF MCFQ interface

F interface

External synchronization

T SETS SETPI

S S

Lower-order path

Transport terminal function

Higher-order path Transport terminal function

Higher-order path

Reference model

7-2 62.1013.105.11-A001

order path, higher-order path, overhead etc. are generally applicable to both transmission directions. All functional blocks have a clock reference point “T” and a management reference point “S”. The reference point “T” communica-tes with the functional block referred to as SETS, the reference point “S” with functional block SEMF.

7.1 Lower-order path functions

PPI PDH Physical Interface

This function represents the interface for the information transfer to other transmission systems as defined in ITU-T Rec. G.703 for the PDH. Essential tasks include the electrical isolation, overvoltage protection, exchange cable equalization, line coding/decoding as well as clock recovery and monitoring of the incoming signal.

LPA Lower-Order Path Adaption

This function defines how plesiochronous signals are mapped into C-n con-tainers (n=11, 12, 2, 3) and the justification procedures necessary for this purpose.

LPT Lower-Order Path Termination

This function generates and/or evaluates the VC-Path Overhead. The Path Overhead is carried in the container from its assembly up to its disassembly.

LPC Lower-Order Path Connection

This function permits a flexible arrangement of VC-11s, VC-12s, VC-2s and VC-3s within a VC-4 or of VC-11s, VC-12s, VC-2s within a VC-3 via a so-cal-led “connection matrix”. This function is required only if the time allocation of the VC to the STM signal shall not be defined by the card slot.

7.2 Higher-order path functions

HPA Higher-Order Path Adaption

Here the VC-m contents are assembled (m = 3, 4); in addition, the TU poin-ters are generated or modified. These pointers set up the phase relation bet-ween VC-n (n = 11, 12, 2, 3) and VC-m (m = 3, 4).

HPT Higher-Order Path Termination

Here the VC-m POH (m = 3, 4) is generated and/or evaluated in accordance with the LPT function.

HPC Higher-Order Path Connection

This function permits the flexible arrangement of the VC-m Virtual Containers (m = 3, 4) within an STM-N frame.

7.3 Transport terminal functions

MSA Multiplex Section Adaption

Here the AU pointers are generated and/or modified. The AU Groups (AUG) thus generated are interleaved byte by byte to obtain the STM-N frame (wit-hout Section Overhead SOH).

MSP Multiplex Section Protection

This function includes all aspects necessary to ensure that switchover to pro-tection paths is possible in case of failures on the line side. MSP communica-tion with the opposite station takes place via the K bytes of the Section Overhead.

MST Multiplex Section Termination

This function generates the MSOH (row 5 to 9 of the SOH) and/or evaluates it on the receive side.

Reference model

62.1013.105.11-A001 7-3

RST Regenerator Sec-tion Termination

This function generates the RSOH (row 1 to 3 of the SOH) and/or evaluates it on the receive side. In addition, the STM-N signal is scrambled in the trans-mit direction. Frame alignment and descrambling take place in the receive direction.

SPI SDH Physical Interface

The logic signal is normally converted into an optical STM-N signal appro-priate for the transmission medium available. Both signal conversion and clock recovery are performed in the receive direction.

SETSSynchronous Equipment Timing Source

This function provides all clocks required by the network element (NE). All functions mentioned above receive the necessary clock signals via the refe-rence points T from the SETS.

SETPI Synchronous Equipment Timing Physical Interface

This is the interface between an external synchronization source and SETS.

SEMF Synchronous Equipment Management Function

Here the monitoring data (performance data and hardware-specific messa-ges) are converted into object-oriented messages which can be transmitted via the DCC or the Q or F interface to a management system or an Operator Terminal. In the opposite direction, messages from the management system are converted into hardware-specific control signals. The connections to the individual functional blocks are set up via logic reference points S.

MCF Message Com-munication Function

This function covers all tasks to be fulfilled in conjunction with the transport of TMN messages to or from the management system via DCC channels or via the Q or F interface.

Reference model

7-4 62.1013.105.11-A001

Applications

62.1013.105.11-A001 8-1

8 Applications

8.1 Synchronous line equipment

In the SDH, no distinction is made between multiplexers and line terminating units. The “synchronous line equipment“ includes both synchronous multiple-xers with integrated optical transmitters and receivers and the associated regenerators.

8.1.1 Synchronous line multiplexer

The SLX1/4 synchronous line multiplexer is described here as an example. This multiplexer combines four STM-1 signals to one STM-4 signal.

On the multiplex side, the Section Overheads (SOH) of the individual STM-1 signals are terminated (disassembled and evaluated). The payload signals are multiplexed column by column and a new STM-4 SOH is generated.

On the demultiplex side, the STM-4 SOH is terminated, while the payload signals are distributed column by column onto the four STM-1 channels. In addition, a new STM-1 SOH is generated for each STM-1 signal.

Besides pointer matching, the different SOH bytes are evaluated:

• B1 and B2 signal monitoring bytes• D1 to D3 management information bytes• F1 user channel byte• E1 and E2 service channel bytes

Fig. 8-1 SLA4 and SLA16 synchronous line equipment (Example)

SLR16

Fin1

Fout4

SLR16

Fin1

Fout4

Fout2

Fin3

Fout2

Fin3

2488 Mbit/s

622 Mbit/s

SLX1/4

F2in

F2out

F1out

F1in

SLR4

Fin1

Fout4

Fout2

Fin3

SLR4

Fin1

Fout4

Fout2

Fin3

SLX1/4

F2out

F2in

F1in

F1out

SLX1/16

F2in

F2out

F1out

F1in

SLX1/16

F2out

F2in

F1in

F1out

16

16

16

16

4

4

4

4

140/155 Mbit/s 140/155 Mbit/s

140/155 Mbit/s 140/155 Mbit/s

Applications

8-2 62.1013.105.11-A001

Alternatively, 140 Mbit/s signals can be applied to the synchronous line multi-plexer instead of STM-1 signals.

In the transmit direction, the asynchronous 140 Mbit/s signals are converted into an STM-1 signal. In the receive direction, the initial 140 Mbit/s signals are extracted from the STM-1 signal.

As opposed to the PDH, the conversion of STM-4 signals to STM-16 signals is not performed by a 4 x STM-4 multiplexing process, but 16 STM-1 signals are directly combined to form the STM-16 signal.

8.1.2 Synchronous line regenerator

In the PDH, the line regenerator fulfills the function of regenerating the line signal with respect to time and amplitude. In addition, it is responsible for the coding rule check (transmission performance feature) and must support fault location processes. A service channel can be additionally provided for maintenance purposes. The signal contents are transparently switched through without taking into account eventually available signal structures or frames.

In the SDH, the tasks of a regenerator are by far more extensive. The signals are descrambled and the STM-N frame structure is analyzed.

Since a regenerator section is ending, part of the SOH (RSOH, rows 1 to 3) is terminated, i.e. the transmission quality is determined by means of the B1 byte, the management information contained in bytes D1 to D2 is evaluated,

Fig. 8-2 Multiplex scheme in compliance with ITU G.707

AU-4 VC-4 C-4

139.264 Mbit/s

155.520 Mbit/s2448 Mbit/s

AUG

STM-16

16

16

AU-4 VC-4 C-4

139.264 Mbit/s

155.520 Mbit/s622 Mbit/s

AUG

STM-4

4

4

Applications

62.1013.105.11-A001 8-3

the user channel is made available via byte F1 and the service channel via byte E1. Then the SOH is completed again by forming a new RSOH. Here the new Regenerator Section begins.

Fault location is generally performed by a management system using the information supplied by all equipment units available in the network. A spe-cial system-internal fault-locating device is therefore not necessary here.

The difference between SLA-4 and SLA-16 consists only in the different regenerator bit rates.

Applications

8-4 62.1013.105.11-A001

8.2 Multiplexers

Regarding their functions, multiplexers can be divided up into the following three basic types:

♦Terminal Multiplexers

♦Add/Drop Multiplexers

♦Cross-connect Multiplexers

8.2.1 Terminal Multiplexer

Application of a Termi-nal Multiplexer in the network topology

One of the FlexPlex MS1/4 applications is its use as a Terminal Multiplexer. This multiplexer type is required at the end of linear links in SDH networks. It combines the tributary signals supplied by lower-order network elements to an aggregate signal which is passed on to the network. Fig. 8-3 shows a section of a network topology with FlexPlex MS1/4 used as Terminal Multiplexer.

Fig. 8-3 FlexPlex MS1/4 used as Terminal Multiplexer in an SDH network

TMS

MS1/4MS1/4: FlexPlex MS1/4TMS: Terminal Multiplexer (SDH)

STM-4

STM-1

STM-4

TMS

MS1/4

STM-1

e.g.:2 Mbit/s34 Mbit/s140 Mbit/s


Applications

62.1013.105.11-A001 8-5

Functioning of a Terminal Multiplexer

The Terminal Multiplexer can split up the signal available at an aggregate interface into the subsignals contained. These are then passed on to the associated tributary interfaces. In the opposite direction, the Terminal Multi-plexer combines the signals received at the tributary interfaces to one signal which is routed to the aggregate interface. Fig. 8-4 shows the functioning of a Terminal Multiplexer with regard to the traffic data to be transmitted.

On splitup of the signal available at the aggregate interface, the multiplexer extracts the associated Overhead information and routes parts of it accessi-ble to the user and appropriate e.g. for operating a service channel system to the corresponding interfaces. In the outgoing direction, the Terminal Multiple-xer generates the Overhead data for the signal sent out at the aggregate interface.

Fig. 8-4 Functioning of a Terminal Multiplexer

Tributary signals1 n

Aggregate signal

(e.g. STM-1, STM-4)

(e.g. 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, (STM-1))

Applications

8-6 62.1013.105.11-A001

8.2.2 Add/Drop Multiplexer

Application of an Add/Drop Multiplexer in the network topology

One of the FlexPlex MS1/4 applications in SDH networks is its use as an Add/Drop Multiplexer. The Add/Drop Multiplexer is used as network element in linear transmission links or in ring network configurations. It extracts one or several subsignals from the aggregate-side signals (STM-1 or STM-4) and routes them to the tributary interfaces (drop function). From there they are passed on to lower-order network elements of the net-work hierarchy. In the opposite direction, the Add/Drop Multiplexer inserts tri-butary signals supplied by lower-order network elements into the aggregate signals in the form of subsignals (add function) from where they are passed on to the network via the aggregate-side interfaces.

Fig. 8-5 shows a section of a network topology with a FlexPlex MS1/4 system functioning as an Add/Drop Multiplexer.

Fig. 8-5 FlexPlex MS1/4 used as an Add/Drop Multiplexer in an SDH network

MS1/4: FlexPlex MS1/4AMS: Add/Drop Multiplexer (SDH)

STM-4

STM-1

STM-4

STM-1




AMS

MS1/4

Applications

62.1013.105.11-A001 8-7

Functioning of anAdd/Drop Multiplexer

The Add/Drop Multiplexer is an expansion of the Terminal Multiplexer. In contrast to the Terminal Multiplexer, it is equipped with two aggregate-side interfaces for signals of the same hierarchical level. It can split up the signals of the two aggregate interfaces (referred to as "West" and "East") into the subsignals contained and can route individual subsignals to the associated tributary interfaces (drop function). In the opposite direction, it inserts the signals received at the tributary interfaces into the aggregate signals instead of the subsignals extracted (add function).

Subsignals not affected by the add/drop functions are switched through from one aggregate interface to the other. On through-connection, the subsignals can be switched at TU-12 level.

Fig. 8-6 shows the functioning of an Add/Drop Multiplexer with regard to the traffic data to be transmitted.

Fig. 8-6 Functioning of an Add/Drop Multiplexer

Tributary signals

Aggregate signal

1 n

Aggregate signalEastWest

(e.g. STM-1, STM-4)


(e.g. STM-1, STM-4)

TU-12

Applications

8-8 62.1013.105.11-A001

8.2.3 Cross-connect Multiplexer

Application of a Cross-connect Multiplexer in the network topology

One of the FlexPlex MS1/4 applications is its use as a Cross-connect Multi-plexer. Within SDH networks, the Cross-connect Multiplexer is used at nodes, in which several signals of the same hierarchy level have to be cross-connected. This cross-connect function is possible for both signals available on the aggregate side and signals available on the tributary side of the multi-plexer. The Cross-connect Multiplexer is ideally suited for network nodes located on a linear SDH link to which further SDH signals of the same hierar-chy are routed (star topology) or for network nodes representing the interface between two SDH rings. Fig. 8-7 shows the example of a network section with such nodes.

Fig. 8-7 FlexPlex MS1/4 used as Cross-connect Multiplexer in an SDH network

MS1/4: FlexPlex MS1/4XMS1: Cross-connect Multiplexer (STM-1)XMS4: Cross-connect Multiplexer (STM-4)

STM-4

STM-1

STM-4

XMS4

MS1/4

STM-1

XMS1

MS1/4

STM-1

Applications

62.1013.105.11-A001 8-9

Functioning of the Cross-connect Multiple-xer

The Cross-connect Multiplexer is an expansion of the Add/Drop Multiplexer or Terminal Multiplexer. In contrast to these, it is equipped with up to four aggregate interfaces. They can be referred to as "West1/East1" and "West2/East2", if e.g. the multiplexer is used as network node at the interface between two SDH rings. These interfaces do not have to be used in pairs. In case of a star-shape network node, it is possible to occupy e.g. three of them.

The aggregate and tributary interfaces are identical with regard to their cross-connecting capabilities. A FlexPlex MS1/4 configured as Cross-connect Mul-tiplexer is also capable of cross-connecting the individual tributary signals. Thus, it offers maximum flexibility when setting up network structures.

Fig. 8-8 shows the functioning of a Cross-connect Multiplexer with respect to the traffic data (payload) to be transmitted.

Fig. 8-8 Functioning of a Cross-connect Multiplexer

Tributary signals

Aggregate signal

1 n

Aggregate signalEast 2West 2

(e.g. STM-1, STM-4)


(e.g. STM-1, STM-4)

Aggregate signalAggregate signalEast 1West 1

(e.g. STM-1, STM-4) (e.g. STM-1, STM-4)

TU-12

Applications

8-10 62.1013.105.11-A001

8.3 Networks

If a telecommunications network, e.g. the DBP Telekom network, is divided up into three levels, i.e. the local area network, the regional long-distance network and the supraregional long-distance network (see Fig. 8-6), all three levels can be equipped with SDH units. However, in order to be able to opti-mally exploit all possiblilities offered by the Synchronous Digital Hierarchy, different equipment types have to be provided for the different network topo-logies.

The synchronous line equipment (SLA) available for the transmission capaci-ties of 622 Mbit/s and 2.5 Gbit/s (SLA 4, SLA 16) is appropriate for the long-distance network levels where the networks are in most cases implemented as line networks with point-to-point connections.

The local area network level mostly consists of ring networks implemented using add/drop multiplexers (ADM). Cross-connect systems can be used at all network levels.

Fig. 8-9 Synchronous networks

SLA4, SLA16Network nodes

Long-distance

Long-distance

Local area

Network nodes

SLA4, SLA16

ADM

FMUXADM

network 1

network 2

network

Applications

62.1013.105.11-A001 8-11

8.3.1 Ring networks

In local area networks, the existing requirements cannot be satisfactorily met by conventional star networks. Especially in this area, the danger of cable breaks and interruptions caused by digging works is considerable. For this reason, the links to the individual stations have to be doubled and routed via different paths.

On interconnection of the stations as depicted in Fig. 8-7, a ring network is set up.

The stations have access to all information available in the ring. Thus, each station can set up a connection to any other station. Furthermore, each sta-tion included in the ring can enter the long-distance network. A central station is no longer required for these tasks.

Connections within the ring are set up by informing the corresponding stati-ons on which part of the STM-N signal (i.e. time slot) is to be used for the connection.

8.3.2 Double rings

The problem of cable breaks can be solved by setting up a second ring. The same information passes through the second ring in the opposite direction.

Since in such configurations, each station transmits and receives the same information into/from two directions (hot standby), the stations affected by a cable break must only switch over to the other receive path.

This can be effected automatically and very quickly so that the full operability of the ring is maintained.

Since the effects of such failures (cable breaks) are eliminated automatically, these rings are also referred to as self-healing rings.

Such self-healing ring toplogies can also be implemented at the long-

Fig. 8-10 Single ring network

to the long-distance network

Applications

8-12 62.1013.105.11-A001

distance network level.

Fig. 8-11 Double ring network

to the long-distance network

Fig. 8-12 Interrupted double ring

to the long-distance

Interruption/

self-healing

self-healing

cable break

network

Applications

62.1013.105.11-A001 8-13

By a double connection of the two rings via two stations, the reliability can be further increased.

Fig. 8-13 Double ring connection of two ring networks

Long-dist. netw. Local area netw.

Applications

8-14 62.1013.105.11-A001

Protection switching

62.1013.105.11-A001 9-1

9 Protection switching

9.1 Overview

The reliability and maintenance of transmission networks are two important aspects to be taken into account on installation of SDH multiplexers. In this connection, redundancy plays an important role. Redundancy means that additional functions are made available on a standby basis. Redundancy should be provided for both the transmission channels of the network and the multiplexer modules.

If a transmission channel is faulty or disturbed, the data traffic is switched over to an appropriate protection channel (protection switching).

If the function of a multiplexer fails, the system switches over to the redun-dant function available (equipment protection).

9.2 Definitions1. Single-ended operation (unidirectional operation)

On failure of only one direction of transmission, only the protection switches of this direction are switched over.

2. Dual-ended operation (bidirectional operation)

On failure of only one direction of transmission, the protection switches of both directions are switched over.

3. Extra traffic

Extra traffic occupies redundant transmission channels. In the case of a fault, this traffic is interrupted.

4. Normal traffic

Normal traffic is routed via the redundant transmission channels.

9.3 Protection switching

With protection switching, additional, i.e. redundant transmission channels are provided on a standby basis for the transmission channels to be protec-ted. In the event of a failure, the traffic is automatically switched over to a red-undant transmission channel.

Important aspects for protection switching:

1. Monitoring

The traffic must be monitored so that faults and failures are immediately detected.

2. Protection switch


9-2 62.1013.105.11-A001

The traffic must be switched over by appropriate protection switches.

3. Protocol

In many protection switching procedures, a protocol is exchanged between the multiplexers.

4. Control

The protection switches have to be controlled in an appropriate way. Any fault detected must be signalled by an alarm. For maintenance purposes, it must be possible to switch over traffic even if there is no fault or failure.

There are different protection switching procedures. All these procedures are highly reliable and appropriate for saving the complete traffic protected in case of a single fault. With multiple faults, this is not always possible.

For some protection switching procedures there are several variants which differ from each other with regard to the following characteristics:

1. Extra traffic

Redundant transmission channels can be occupied by low-priority traffic. In the event of a fault, this traffic is interrupted.

2. Revertive/non-revertive operation

This option permits the operator to decide whether the system shall switch back to the original transmission channel on elimination of the fault.

3. Single-ended/dual-ended operation

This option permits the operator to decide whether both directions of trans-mission shall be switched over in common.


62.1013.105.11-A001 9-3

The following table gives an overview of the protection switching procedures currently available.

9.3.1 MS 1+1 protection

The transmitter doubles the traffic and sends it out on two lines. The receiver selects one of these two lines. Extra traffic is not possible here.

In the most simple case, operation is single-ended and non-revertive. Dual-ended and/or revertive operation is optionally possible.

Designation Operation Protocol in Extra traffic

MS 1+1 Pro-tection

Single-ended/dual-endedrevertive/non-revertive

K1/K2 bytes not possible

MS 1:n Pro-tection

Single-ended/dual-endedrevertive/non-revertive

K1/K2 bytes possible

MS Shared Protection Ring

Dual-endedrevertive/non-revertive


MS Dedicated Protection Ring



Path/Subnet-work Protec-tion

Single-endedrevertive/non-revertive

not necessary not possible


K3/K4 bytes not possible

Table 9-1 Overview of protection switching procedures

Fig. 9-1 MSP 1+1 Multiplex Section Protection

Operating path

Protection path

Multiplex Section

Doubling Selector


9-4 62.1013.105.11-A001

9.3.2 MS 1:n protection

A number of n operating channels (n = 1,...,14) are sharing a so-called Pro-tection Section. The protection switches of the transmitter and receiver must operate in the same way, however, in the opposite order. Extra traffic is pos-sible on the Protection Section.

Operation can be revertive or non-revertive and single- or dual-ended.

9.3.3 MS shared protection ring

MS shared protection rings can consist of two or four fibres. Connections are set up in both directions of transmission using the same ring segment. The advantage consists in a higher transmission capacity, which is, however, only available if the traffic is not routed to a certain multiplexer in a star-shape configuration.

The transmission capacity of the MS shared protection ring is divided up into two halfs at the AU level. One half is occupied by normal traffic, while the other is provided for protection purposes. Optionally, the latter can also be used for extra traffic. Two-fibre rings on the STM-1 basis are not provided.

Fig. 9-2 MS 1:n Protection Switch

Zero

channel

(0)

0

0

Operating

section

1

Operating

channel

1

1

1

Operating

section

2

Operating

channel

2

2

2

Protection

section

(0)

Extra

traffic

channel

(15)

15

15

Bridge Selector


62.1013.105.11-A001 9-5

In the event of a fault, the adjacent multiplexers switch over the normal traffic at the AU level to the half provided for protection. Operation is dual-ended and revertive or non-revertive.

In four-fibre rings, there are two protection switching levels. At first the system tries to protect each section of the ring by an own MS 1:1 protection. If the fault cannot be eliminated this way, a loop is switched.

Fig. 9-3 Example of the traffic flow in an MS shared protection ring

N N

NN

E E

E E

N N

NN

N N

NN

N

E

Add/drop function for normal traffic

Add/drop function for extra traffic

Node 1 Node 2

Node 3Node 4

Node 1 Node 2

Node 4 Node 3

Node 1 Node 2

Node 4 Node 3

No failure Failure on section betweennode 1 and 2

Failure of node 2


9-6 62.1013.105.11-A001

9.3.4 MS dedicated protection ring

MS dedicated protection rings are composed of two fibres. One of them is used for transmitting the normal traffic, the other remains free. Optionally, the free fibre can be used for transmitting extra traffic.

Each connection occupies only one ring line, however, over the entire ring. In the event of a fault or failure, the adjacent multiplexers switch over the nor-mal traffic to the ring line provided for protection purposes. Operation is dual-ended and optionally revertive or non-revertive.

9.3.5 Path/subnetwork protection

With path/subnetwork protection, the payload to be protected is doubled and - assembled in a VC - transmitted via two different interfaces and transmis-sion paths to the receiver. The receiver monitors both VCs and selects one of them. The criteria taken into consideration for this selection are Path AIS, LOP and, optionally, degraded signal.

A distinction is made between the following variants of path/subnetwork pro-tection:

Path protection The payload is available in the form of a container and is doubled. Then each container is separately assembled in a VC. Thus, there are two independent VCs which are transmitted via separate paths.

Subnetwork protection The payload is available in the form of a VC and is doubled. Thus, there is only one VC which is transmitted two times via separate paths.

In the relevant literature, sometimes no distinction is made between the two protection types, i.e. both variants are meant by path protection. Only ETSI differentiates between these two types of protection.

Fig. 9-4 Example for the traffic flow in an MS dedicated protection ring

N N

NN

E E

E E

N N

NN

N N

NN

N

E

Add/drop function for normal traffic

Add/drop function for extra traffic

Node 1 Node 2

Node 3Node 4

Node 1 Node 2

Node 4 Node 3

Node 1 Node 2

Node 4 Node 3

No failure Failure on section betweennode 1 and 2

Failure of node 2


62.1013.105.11-A001 9-7

Operation is normally single-ended and non-revertive. In dual-ended opera-tion, a protocol is necessary.

The advantages of path/subnetwork protection are (1) the low technical com-plexity, (2) the possibility of application in any network topology and (3) the flexibility regarding the decision on which connections are to be protected. The disadvantages are (1) the relatively high expenditure resulting from the high number of protection switches and (2) the missing possiblity of extra traffic, since the normal traffic to be protected is always transmitted redun-dantly.

9.3.6 Protocols

Protocols exchanged between the multiplexers are used to control the pro-tection switching processes.

Appropriate channels are required for transmitting these protocols. In the Section Overhead, there are the K1/K2 bytes. They are used for the proto-cols of the following protection types:

• MS 1+1 protection,

• MS 1:n protection,

• MS shared protection ring,

• MS dedicated protection ring.

For path protection, a separate protocol is required for each virtual container (VC). For this reason, path protection protocols can be appropriately trans-mitted in the Path Overhead only (bytes K3, K4).

Fig. 9-5 Path und subnetwork protection

C-xy C-xy

VC-xy #1

VC-xy #2Path

termination

Permanentbridge

Pathtermination

Pathselector

Path Protection:

C-xy C-xy

VC-xy

VC-xyPath

terminationPermanent

bridge

Pathtermination

Pathselector

Subnetwork Protection:

VC-xy VC-xy

C-xy

C-xy

C-xy

C-xy


9-8 62.1013.105.11-A001

9.4 Network topologies

The following sections describe different network topologies appropriate for protection switching.

Linear chain

In a linear chain, the multiplexers are connected in series via Aggregate Interfaces. The multiplexers at both ends of the chain are Terminal Multiple-xers, those in between are Add/Drop Multiplexers.

In order to increase reliability, the transmission lines between two neigbou-ring multiplexers are doubled. The transmission lines are operated as MS 1:1, MS 1+1 protection (or path protection). The chain is thus protected against faults occurring on individual transmission lines or Aggregate Inter-faces.

However, there is no protection against an interruption (cut) of all connection cables between two multiplexers or a total failure of a multiplexer in such a chain configuration. Ring configuration offers better protection features.

With path protection in a chain configuration of multiplexers, the following two variants can be implemented:

Variant 1 - The protection switches are located only in the multiplexers drop-ping the path to be protected (see Fig. 9-6).

Variant 2 - Each multiplexer through which the path to be protected is running is equipped with protection switches (see Fig. 9-7).

Variant 1 can be implemented in each multiplexer which supports path pro-tection for signals available at the Tributary Interfaces. For variant 2, the mul-tiplexer must also support path protection at the Aggregate Interfaces.

The reliability of variant 2 is higher, since it also copes with multiple faults on condition that only one single fault occurs on each section.


62.1013.105.11-A001 9-9

Fig. 9-6 Linear multiplexer chain with redundancy

TM #1 ADM #2 ADM #3 TM #4

TR TR TR TR

4 x STM-N

TR ... Tributaries

TM ... Terminal multiplexer

ADM ... Add/drop muliplexer

Fig. 9-7 Path protection in a multiplexer chain

ADM #1 (path switched through)ADM #2 (path dropped)

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC

-xy

VC

-xyAggregate

InterfaceAggregateInterface

TributaryInterface


9-10 62.1013.105.11-A001

Rings

Add/drop multiplexers can be operated in a ring (see Fig. 9-8). Between each multiplexer pair located in a ring, there are two separate transmission paths. For this reason, rings are especially appropriate for setting up reliable sub-networks. These rings can include two or four fibres.

Interconnected rings

Rings can be connected with each other so that (1) the connecting lines are protected and (2) protection switching can be performed independently for both rings (see Fig. 9-9). The two multiplexers serving one connecting line form a so-called Serving Node. It is possible to combine the two multiplexers and their connecting line to one multiplexer.

All ring types available can be interconnected (see Fig. 9-10 and 9-11). Even connections between different ring types are possible.

A complete recovery of the traffic signals failed is possible, if not more than one single fault occurs in each ring and with only one single fault in the Ser-ving Nodes.


62.1013.105.11-A001 9-11

Fig. 9-8 Examples for multiplexer rings with two and four connecting lines

Two-fiber ring

Four-fiber ring

ADM #1

ADM #3

ADM #4ADM #2

ADM #1

ADM #4

ADM #3

ADM #2

TR

TRTR

TR

TRTR

TR

TR

ADM ... Add/drop multiplexer

TR ... Tributaries


9-12 62.1013.105.11-A001

Fig. 9-9 Example for protection switching in interconnected rings

ADM

ADM ADM

ADM ADM

ADM

ADM ADM

ADM

ADM

Serving nodes


62.1013.105.11-A001 9-13

Fig. 9-10 Interconnection of two rings with path protection

Path protection ring

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC

-xy

VC

-xy

VC

-xy

VC

-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

ADM #1 ADM #3

ADM #2 ADM #4

ADM: Add/drop multiplexer

Path protection ring


9-14 62.1013.105.11-A001

Fig. 9-11 Interconnection of two rings with MS shared protection

MS shared protection ring

ADM: Add/drop multiplexerMS: Multiplex section

MS shared protection ring

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xyVC-xy

VC-xy

VC

-xy

VC

-xy

VC

-xy

VC

-xy

ADM #1 ADM #3

ADM #4ADM #2


62.1013.105.11-A001 9-15

9.5 Equipment protection

With Equipment Protection, multiplexers are equipped with additional (redun-dant) functions which are made available on a standby basis for the functions to be protected. The redundant function can assume the task of a disturbed function. This results in an increase in reliability.

Aspects to be considered for Equipment Protection:

1. Monitoring

The functions have to be monitored so that faults or failures are immediately detected. This also applies to functions which are currently not required.

2. Protection Switch

It must be possible to enable or disable the functions via appropriate protec-tion switches.

3. Control

The protection switches have to be appropriately controlled. Any failure must be signalled by an alarm. In addition, it must be possible to localize any faulty function. For maintenance purposes it must be possible to disable individual functions even if there is no fault or failure.

Most of the Equipment Protection procedures offer several variants. These differ from each other to respect to the following features:

• Revertive/non-revertive operation

This option permits the operator to decide whether the system shall switch back to the original function on elimination of the fault.

The following table gives an overview of Equipment Protection procedures available:

Designation Operation

Equipment 2+1 protection Majority decision

Equipment 1+1 protection Revertive/non-revertive

Equipment 1:1 protection Revertive/non-revertive

Equipment 1:n protection Revertive/non-revertive

Table 9-2 Overview of equipment protection procedures


9-16 62.1013.105.11-A001

Literature

62.1013.105.11-A001 10-1

10 Literature[1] ITU-T Recommendation G.702: Digital Hierarchy Bit Rates (Blue Book)

[2] ITU-T Recommendation G.703: Physical/Electrical Characteristics of Hierarchical Digital Interfaces (Blue Book)

[5] ITU-T Recommendation G.707: Network Node Interface fo rthe SDH

[6] ITU-T Recommendation G.773: Protocol Suites for Q Interfaces for Management of Transmission Systems

[7] ITU-T Recommendation G.781: Structure of Recommendations on Mul-tiplexing Equipment for the Synchronous Digital Hierarchy (SDH)

[8] ITU-T Recommendation G.782: Types and General Characteristics of Synchronous Digital Hierarchy (SDH) Multiplexing Equipment

[9] ITU-T Recommendation G.783: Characteristics of Synchronous Digital Hierarchy (SDH) Multiplexing Equipment Functional Blocks

[10] ITU-T Recommendation G.784: Synchronous Digital Hierarchy (SDH) Management

Literature

10-2 62.1013.105.11-A001

Index

62.1011.105.11-A001 I-1

Index

AA byte 4-4A1 byte (RSOH) 5-2A2 byte (RSOH) 5-2Administrative Unit (AU) 2-6Administrative Unit Group (AUG) 2-8AU 2-6AU pointer 2-6AU-3 pointer 6-4

D bit 6-5, 6-8H1, H2 pointer bytes 6-5H3 pointer action byte 6-5I bit 6-5, 6-8NDF 6-5

AU-4 concatenation 6-7AU-4 pointer 6-6

Concatenation 6-7D bit 6-6H1, H2 pointer bytes 6-6I bit 6-6NDF 6-6

AUG 2-8Autom. protection switching (K4 byte) 5-7Autom. protection switching bytes K1, K2 5-2Automatic protection switching at the higher-order

path 5-5

BB byte 4-4B1 byte 5-2B2 byte (MSOH) 5-2B3 byte (higher-order POH) 5-4BIP 2-17BIP values 2-17BIP-2 monitoring (lower-order POH) 5-6BIP-8 monitoring 5-2BIP-8 monitoring (higher-order POH) 5-4BIP-N x 24 monitoring 5-2Bit errors 2-17Bit Interleaved Parity 2-17Bit rates of the STM-1 frame 2-2Block structure 2-4

CC bit 4-2C1 bit 4-4, 4-6, 4-7C1 byte (RSOH) 5-2C2 bit 4-4, 4-6, 4-7C2 byte (higher-order POH) 5-4

CI 2-13, 6-7Concatenation 2-13, 6-11

Continuous concatenation 6-11Sequential concatenation 6-11Virtual concatenation 6-11

Concatenation Indication 2-13, 6-7Concatenation of containers 1-6Container C

Container sizes 2-4Container chain 1-6Containers 1-3Contents identifier (higher-order POH) 5-4Contents identifier (lower-order POH) 5-7Conveyor belt 1-3Cross-connect Multiplexer XMS 8-8

DD bit (Decrement) 6-5, 6-8D1...D3 byte (RSOH) 5-2D4...D12 byte (MSOH) 5-2Data Communication Channel 5-2DCC 5-2DCCM 5-2DCCR 5-2Descrambling 2-17Double ring connection 8-13Double rings 8-11Dual-ended operation 9-1

EE.164 format 5-4E1 byte (RSOH) 5-2E2 byte (MSOH) 5-3Equipment protection 9-15Error monitoring byte B3 5-4Error monitoring byte V5 (Bit 1, 2) 5-6Error monitoring using BIP-X 2-17Extra traffic 9-1, 9-2

FF1 byte (RSOH) 5-2F2 byte (higher-order POH) 5-5Floating mode 2-15Frame alignment signal 5-2

GG1 byte (higher-order POH) 5-4

HH1, H2 byte 6-5, 6-6, 6-8H3 byte 6-5, 6-7, 6-9H4 byte 2-15, 5-5

Index

I-2 62.1013.105.11-A001

Hierarchy level 1-7Higher-order path 3-1

HPA 7-2HPC 7-2HPT 7-2

Higher-order path functions (reference model)7-2

Higher-order POH 5-3

B3 byte (BIP-8 monitoring) 5-4C2 byte (contents identifier) 5-4F2 byte (user channel) 5-5F3 bytes (User Channel) 5-5G1 byte (path status) 5-4H4 byte (multiframe indicator) 5-5J1 byte (Path Trace) 5-4

II bit 4-2

JJ0 byte 5-2J1 byte (higher-order POH) 5-4J2 byte 5-7Justification information 1-2, 4-2

KK1, K2 byte (MSOH) 5-2K3 byte 5-5K4 byte (lower-order POH) 5-7

LLabel 1-3Local area network 8-10, 8-11Long-distance network 8-10, 8-11Loss of signal 5-5Lower-order path 3-1

LPA 7-2LPC 7-2LPT 7-2PPI 7-2

Lower-order path functions (reference model)7-2

Lower-order POH 5-6J2 byte 5-7V5 byte

Bit 1, 2 (BIP-2 monitoring) 5-6Bit 3 (REI) 5-6Bit 4 (RFI) 5-6Bit 8 (RDI) 5-7

V5 byte Bit 5, 6, 7 (contents identifier)

5-7

MM1 byte (MSOH) 5-3Mapping 2-4Mapping procedures 4-1– 4-8

Asynchronous mapping of 1.5 Mbit/s si-gnals into VC-11 4-7

Asynchronous mapping of 140 Mbit/sinto VC-4 4-1

Asynchronous mapping of 2 Mbit/s si-gnals into VC-12 4-6

Asynchronous mapping of 34 Mbit/s si-gnals into VC-3 4-4

Mapping of 1.5 Mbit/s signals into VC124-8

MS 1

n protection 9-4MS 1+1 protection 9-3MS dedicated protection ring 9-6MS shared protection ring 9-4MSOH 5-2Multiframe 4-6, 4-7Multiframe generation 2-15Multiframe indicator (H4) 2-15, 5-5Multiplex paths 3-1

AU-4 to AUG 3-2AUG to STM-N 3-3C11, C12 and C2 to TUG-2 3-8C-3 to STM-N 3-4, 3-6C-4 to STM-N 3-2TUG-2 to TUG-3 3-11TUG-2 to VC-3 3-12

Multiplex scheme 3-1Multiplex scheme in compliance with ITU-T G.709

3-1Multiplex Section Overhead 5-2Multiplexer

Cross-connect Multiplexer XMS 8-8Multiplexer service channel 5-3

NN1 byte 5-5N2 byte (lower-order POH) 5-7NDF 6-1, 6-5Negative justification 6-3Network operator byte 5-5Networks, synchronous 8-10New Data Flag 6-1, 6-5Normal traffic 9-1

Index

62.1011.105.11-A001 I-3

OO bit 4-1, 4-6, 4-7Offset 1-9Overhead 5-1– 5-7

Path Overhead (POH) 5-1Section Overhead (SOH) 5-1

Overhead bit 4-1, 4-6, 4-7Overhead capacity 2-2

PParitätsverletzung 2-17Parity violations 2-17Path AIS (P AIS) 5-5Path monitoring 5-4Path Overhead 2-2, 2-5, 5-3– 5-7Path status 5-4Path Trace 5-2Path Trace J1 (higher-order POH) 5-4Path Trace J2 (lower-order POH) 5-7Path/subnetwork protection 9-6Payload 1-3, 2-2POH 2-5Pointer action byte 6-5Pointer modification 6-1

Frequency matching 6-1H3 byte 6-2, 6-3Negative justification 6-3Positive justification 6-2Setting a new pointer 6-1

Pointer types 6-4

AU pointer 6-4TU pointer 6-4

Pointers 6-1– 6-15

AU pointerAU-3 pointer 6-4AU-4 pointer 6-6

TU pointerTU-11 pointer 6-12TU-12 pointer 6-14TU-2 pointer 6-10TU-3 pointer 6-8

Point-to-point connections 8-10Positive justification procedure 6-2Protection switching 9-1Protection switching in interconnected rings 9-10Protection switching in linear chains 9-8Protocols for protection switching 9-7

RR bit 4-2RDI 5-5

RDI (lower-order POH) 5-7Reference model 7-1Reference points 7-1Regenerator Section Overhead 5-2Regenerator service channel 5-2REI 5-3, 5-5REI (lower-order POH) 5-6Remote Defect Indication (RDI) 5-5Remote Defect Indication (VC path) 5-7Remote Error Indication (REI) 5-3, 5-5Remote Error Indication (REI) (lower-order POH)

5-6Remote Failure Indication (RFI) 5-6Revertive/non-revertive operation 9-2RFI 5-6Ring network 8-11Rings, self-healing 8-11RSOH 5-2

SS bit 4-2S1 bit 4-4, 4-6, 4-7S1 byte (MSOH) 5-3S2 bit 4-4, 4-6, 4-7Scrambler 2-17Scrambling 2-17SDH multiplex elements 2-4– 2-8Section Overhead 1-7, 5-1Section REI 5-3Setting a new pointer value 6-1Setting the pointer by frequency matching 6-1Single ring 8-11Single-ended operation 9-1Single-ended/dual-ended operation 9-2SOH 5-1

MSOHB2 byte (BIP-N x 24 monitoring) 5-2D4 to D12 (DCCM) 5-2E2 byte (multiplex service channel)

5-3K1, K2 byte (automatic protection

switching) 5-2M1byte (section FEBE) 5-3S1 byte (timing marker) 5-3Z1, Z2 byte (spare bytes) 5-3

RSOHA1, A2 byte (frame alignment signal)

5-2B1 byte (BIP-8 monitoring) 5-2D1 to D3 (DCCR) 5-2E1 byte (regenerator service channel)

Index

I-4 62.1013.105.11-A001

5-2F1 byte (user channel) 5-2J0 byte (STM-N identifier) 5-2

Spare bytes 5-3SSM 5-3STM-1

Frame 2-1Structure 2-1

STM-N 2-1STM-N identifier 5-2Stuffing byte 4-1Stuffing check bit 4-4, 4-6, 4-7Stuffing check bit (C bit) 4-2Stuffing position 4-2, 4-6, 4-7Synchronization status 5-3Synchronization Status Message (SSM) 5-3Synchronous line equipment 8-1Synchronous line multiplexer 8-1Synchronous line regenerator 8-2Synchronous multiplexing 2-14Synchronous Tranport Module STM-1 2-1

TTerminal Multiplexer (TMS) 8-4Transport frame 1-7Transport terminal functions

MCF 7-3MSA 7-2MSP 7-2MST 7-2RST 7-3SEMF 7-3SETPI 7-3SETS 7-3SPI 7-3

Transport terminal functions (reference model)7-2

Tributary Unit (TU) 2-6Tributary Unit Group (TUG) 2-8TU pointer 2-6TU size 6-10, 6-12, 6-14TU-11 pointer 6-12

D bit 6-12I bit 6-12NDF 6-12V1, V2 pointer bytes 6-12, 6-14V3 pointer action byte 6-13V4 byte 6-13

TU-12 pointer 6-14

D bit 6-14I bit 6-14

NDF 6-14V3 pointer action byte 6-15

TU-14 pointer

V4 byte 6-15TU-2 concatenation 6-11TU-2 pointer 6-10

D bit 6-10I bit 6-10NDF 6-10V1, V2 pointer bytes 6-10V3 byte 6-11V3 pointer action byte 6-11

TU-3 pointer 6-8

D bit 6-9H1, H2 pointer bytes 6-8H3 pointer action byte 6-9NDF 6-8

TUG 2-8

UUser channel 5-2

VV1, V2 byte 6-10, 6-12, 6-14V3 byte 6-11, 6-13, 6-15V4 byte 6-11, 6-13, 6-15V5 5-6VC-12 4-6VC-3 4-4VC-3 POH 4-4VC-3/VC-4 assembler 5-5VC-4 4-1VC-4 POH 4-1Virtual Container (VC)

Formats 2-5Voice channel 5-3

WW byte 4-1

XX byte 4-1

YY byte 4-1

ZZ byte 4-2Z1, Z2 byte (MSOH) 5-3

sdh basics (marconi 2000)

Documents

1st hierarchy level

bit rate assignment

synchronous digital hierarchy

order path functions

serial source signal

additional transport capacity

administrative unit group

pointer bytes 1v