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SDS Foil no 1 SDL – Inheritance

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Page 1: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 1

SDL –Inheritance

Page 2: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 2

Controller behaviour

toCentral

Validation

Idle

Code(cid,PIN)

Code(cid,PIN) via U

Validation

virtual OK

OKto cur_panel

cur_panel :=sender

NOK

NOKto cur_panel

Idle

process type Controller

dcl cur_panel PId ; /* current panel whose Code will be validated */dcl cid, PIN integer ; /* temporary variables for the data attributes of 'Code' */

1(2)

[Code]

[(validity)]

[opened,closed]

[open,close]

[(validity)]

[Code]P D U

Opening

Open /* to Door */

Page 3: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 3

Behaviour inheritance

process type BlockingControllerinherits Controller

1(1)

*

Disable

BlockDoor

blocked

blocked

Enable

Idle

U[Disable,Enable]

*

BlockDoor

For all states

Add transition

To new state

Add signals

«process»controller

«process» BlockingController

Page 4: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 4

Inherited behaviour

toCentral

Validation

Idle

Code(cid,PIN)

Code(cid,PIN) via U

Validation

virtual OK

OKto cur_panel

cur_panel :=sender

NOK

NOKto cur_panel

Idle

process type Controller

dcl cur_panel PId ; /* current panel whose Code will be validated */dcl cid, PIN integer ; /* temporary variables for the data attributes of 'Code' */

1(2)

[Code]

[(validity)]

[opened,closed]

[open,close]

[(validity)]

[Code]P D U

Opening

Open /* to Door */

Page 5: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 5

Who can interwork correctly?

a:controller u

b:blockingcontroller u

c:validation

d:blockingvalidation

Page 6: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 6

code OK NOK opened closed

Idle

Validation

Controller

blockingController

code OK NOK opened closed Disable Enable

Validation

Idle ControllerBlocked

Subtyping for states and transitions

Page 7: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 7

e [(inp)]

[(outp)]

block type BlockingAccessPoint 1(1)

Door

[(validity)][code] [opened,

closed][open,close]

[(inp)]

[(outp)]

[(validity)] [Code]

P1

signal opened,closed ; /* Door -> Controller */signal open, close ; /* Controller -> Door */

CE

CU

D

C

[(validity)]

[Code]apc: Blocking

Controller

P DU

Panel

[unlock,lock] d

[unlock,lock]

[isOpen,isClosed]

[isOpen,isClosed]

BlockingController

Using the Blocking controller –the BlockingAccessPoint

could we define this by inheriting from AccessPoint?

Page 8: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 8

«block»AccessPoint

«block» BlockingAccessPoint

«block» LoggingAccessPoint

Inheritance: pure extension

«process»controller

«process» BlockingController

«process» LoggingController

Note that this is valid SDL-2000 notation!

Page 9: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 9

«block»AccessPoint

«block» BlockingAccessPoint

«block» LoggingAccessPoint

Inheritance: virtual to enable changes

«process»controller{virtual}

«process» Controller

{redefined}

«process» Controller{finalised}

Page 10: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 10

Virtual process in modified AccessPoint

e

[(outp)]

block type AccessPoint 1(1)

Door

[(validity)]

[code] [opened,

closed][open,close]

[(inp)]

[(outp)]

[(validity)] [Code]

P1

signal open, close ; /* Controller -> Door */signal opened, closed ; /* Door -> Controller */

CE

CU

D

C

[(validity)]

[Code]

apc:Controller

P DU

Panel

[unlock,lock] d

[unlock,lock]

[isOpen,isClosed]

[isOpened,isClosed]

VirtualController

[(inp)]

Page 11: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 11

Virtual process

Validation

Code(cid,PIN)

Code(cid,PIN) via U

Validation

OKto cur_panel

Idle

cur_panel :=sender

unlockDoor

unlockDoor

NOKto cur_panel

Idle

virtual process type Controller

dcl cur_panel PId ; /* current panel whose Code will be validated */dcl cid, PIN integer ; /* temporary variables for the data attributes of 'Code' */

1(1)

[Code]

[(validity)]

[opened,closed]

[open,close]

[(validity)]

[Code]P D U

Idle

OK NOK

Page 12: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 12

redefined

C

[Enable,Disable]

block type blockingAccessPoint inherits AccessPoint

Controller

existing gate

addedsignals

Inheriting AccessPoint: BlockingAccessPoint

Note that the full structure of AccessPoint is inherited here!Note that the full structure of AccessPoint is inherited here!

Page 13: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 13

Inherited structure

e

[(outp)]

block type AccessPoint 1(1)

Door

[(validity)][code] [opened,

closed][open,close]

[(inp)]

[(outp)]

[(validity)] [Code]

P1

signal open, close ; /* Controller -> Door */signal opened, closed ; /* Door -> Controller */

CE

CU

D

C

[(validity)]

[Code]

apc:Controller

P DU

Panel

[unlock,lock] d

[unlock,lock]

[isOpen,isClosed]

[isOpened,isClosed]

VirtualController

[(inp)]

Page 14: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 14

Redefined process type:Controller in blocking AccessPoint

redefined process type Controller 1(1)

*

Disable

BlockDoor

BlockDoor

blocked

blocked

Enable

Idle

U[Disable,Enable]

*

Page 15: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 15

blocktype loggingAccessPointinherits AccessPoint

1(1)

finalised Controller

apc: Controller

LogDevice

[(validity),Code]

L

LD

existing instance

addedsignalroute

Inheriting structure: LoggingAccessPoint

addedprocess

«block»AccessPoint

«block» LoggingAccessPoint

Page 16: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 16

Virtual process with virtual transitions

Validation

Code(cid,PIN)

Code(cid,PIN) via U

Validation

OKto cur_panel

Idle

cur_panel :=sender

unlockDoor

unlockDoor

NOKto cur_panel

Idle

virtual process type Controller

dcl cur_panel PId ; /* current panel whose Code will be validated */dcl cid, PIN integer ; /* temporary variables for the data attributes of 'Code' */

1(1)

[Code]

[(validity)]

[opened,closed]

[open,close]

[(validity)]

[Code]P D U

Idle

OK NOKvirtualvirtual

Page 17: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 17

OK

OKto cur_panelvia P

Idle

unlockDoor

NOKto cur_panelvia P

Idle

NOK

finalised process type controller 1(1)

[Code, (validity)]

L

Validation

Redefined and finalized transitions

redefined finalized

OK,Code(cid,PIN)via L

NOK,Code(cid,PIN)via L

«process»controller{virtual}

«process» controller

{finalised}

Page 18: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 18

Virtual Procedures

virtualwhenOK

virtualwhenNotOK

unlockDoor

Validation

Idle

Code(cid,PIN)

Code(cid,PIN)via U

Validation

OK

cur_panel :=sender

NOK

process type Controller

dcl cur_panel PId ; /* current panel whose Code will be validated */dcl cid, PIN integer ; /* temporary variables for the data attributes of 'Code' */

1(1)

[Code]

[(validity)]

[opened,closed]

[open,close]

[(validity)]

[Code]P D U

Idle

unlockDoor

Idle

whenOK whenNotOK

Page 19: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 19

process type loggingControllerinherits Controller

L[Code,OK,NOK]

redefinedWhenOK

redefinedWhenNOK

Redefining virtual procedures

Page 20: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 20

CentralUnit

Building a system from components

system type AccessControl

use AccessPointLib

ap(100):AccessPoint

ce

d

bp(10):BlockingAccessPoint

ce

d

lp(20):LoggingAccessPoint

ce

d

[(inp)][(outp)]

unlock,lock

isOpen,isClosed

[(validity)] [Code]

[(inp)][(outp)]

unlock,lock

isOpen,isClosed

[(validity),Disable, Enable]

[Code]

[(validity)] [Code][(inp)][(outp)]

unlock,lock

isOpen,isClosed

Page 21: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 21

package AccessPointLib

AccessPoint BlockingAccessPoint

use SignalLib ;

LoggingAccessPoint

The Block types in the AccessPointLib Package

Page 22: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 22

signal opened,closed ; /* Door to Controller */signal open, close ; /* Controller to Door */

package SignalLib

signal eject-card, lock, unlockinput-card, isOpen, isCloseddisplay,keys;signal Code(integer,integer);signal OK,NOK,ERR ;

signallist validity = OK, NOK, ERR ;signallist outp = EjectCard, display;signallist inp = InputCard, keys ;

/* AccessPoint/* ENV/* Display/* ENV/* AccessPoint/* CentralUnit

to ENV */to AccessPoint*/to ENV */to Keyboard */to CentralUnit */to AccessPoint */

signalDisable,

Enable/* CentralUnit to/* CentralUnit to

BlockingAccessPoint */BlockingAccessPoint */

Page 23: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 23

system type GeneralAccessControl

use SignalLib ; use PanelLib / PanelInterface;use DoorLib / DoorInterface;

virtual process type Panel atleast PanelInterface

virtual process type Door atleast DoorInterface

virtual Door virtual Panel

ls(10):AccessPoint

CentralUnitCE C

[(validity)] [Code]

e c[(inp)][(out)]

package SystemTypes

AccessPoint

Specialisation of system types

d

Page 24: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 24

Redefined process type Panel inherits PanelInterface

Redefined process type Door inherits DoorInterface

redefined Door redefined Panel

system type MyAccessControl inherits GeneralAccessControl

package SpecialSystemTypes

use SystemTypes

Page 25: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 25

system MAC: MyAccessControl

use SpecialSystemTypes;

System Instance

Page 26: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 26

<SIGNAL OK,NOK,ERR,Code(integer,integer), ejectCard, inputCard, display, keys>

[Code]

e [(inp)]

[(outp)]

virtualController

block type AccessPoint 1(1)

Door

[(validity)]

[code] [opened,

closed][open,close]

[(inp)]

[(outp)]

[(validity)] [Code]

P1

signal opened,closed ; /* Door -> Controller */signal open, close ; /* Controller -> Door */

CE

CU

D

C

[(validity)]apc:Controller

P DU

Panel

[unlock,lock] d

[unlock,lock]

[isOpen,isClosed]

[isOpen,isClosed]

signallist validity = OK, NOK, ERR ;signallist outp = eject-card, display;signallist inp = input-card, keys ;

Context parameters

Page 27: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 27

system AccessControl 1(1)

CE

C[(inp)][(outp)]

[(validity)] [Code]

ap(100):AccessPoint<Ja,Nei,Feil,Kode,KortUt, KortIn, Skjerm, Taster>

Ce

CentralUnit

Actualcontext parameters

use AccessPointLib/AccessPoint;

Actual context parameter

Page 28: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 28

system AccessControl

1(1)

CE

C[(inp)][(outp)]

[(validity)] [Code]

CF

[(validity),Enable,Disable]

[Code]

CB

ap(apn ):AccessPoint

C

bap(bapn):BlockingAccessPoint

e C[(inp)][(outp)]

e

CentralUnit

CGCL

lap(lapn):LoggingAccessPoint

e C [(validity)] [Code]

[(inp)][(outp)]

<SYNONYM apn Integer, bapn Integer, lapn Integer>

Context parameters for dimensioning

d

d

d

L Logger[Code,(validity)]LL

Page 29: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 29

Variability in system families (Product lines)

• Is inheritance sufficient?

• Additional composition will be needed in many cases!

• Is inheritance sufficient?

• Additional composition will be needed in many cases!

Package system lib

ProcesstypesProcesstypes

BlocktypesBlocktypes

SystemtypesSystemtypes

SystemInstallation33:SystemType5

SystemInstallation45

Page 30: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 30

Summary 1 (Inheritance)

Specialization of process, state types and procedures

• Simple inheritance, adding properties

• Virtual procedures

• Virtual transitions

Specialization of block types

• Simple inheritance, adding properties

• Virtual block types

• Virtual process types

• Virtual procedure types

Specialization of data and signal types

• Simple inheritance, adding properties

Specialization of process, state types and procedures

• Simple inheritance, adding properties

• Virtual procedures

• Virtual transitions

Specialization of block types

• Simple inheritance, adding properties

• Virtual block types

• Virtual process types

• Virtual procedure types

Specialization of data and signal types

• Simple inheritance, adding properties

Page 31: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 31

Summary 2 (Virtual, redefined, finalized)

•Virtual types may have virtuality constraints given by an atleast-clause which specifies a minimum type which the analysis of the enclosing type may take for granted. When no atleast-clause is given, the default is that the original virtual type itself is the constraint type.

•A redefined type is a type which is specified as virtual in a supertype of the type enclosing the redefined type. A redefined type must be a specialization of the virtuality constraint. A redefined type may be further redefined in specializations of its encloser.

•A finalized type is a type which is specified as virtual in a supertype of the encloser. A finalized type must be a specialization of the virtuality constraint. A finalized type may not be defined again in specializations of its encloser.

•Virtual, redefined and finalized can also be used for individual transitions in processes. The virtuality specification can occur in input symbols, start symbols and save symbols.

•Virtual types may have virtuality constraints given by an atleast-clause which specifies a minimum type which the analysis of the enclosing type may take for granted. When no atleast-clause is given, the default is that the original virtual type itself is the constraint type.

•A redefined type is a type which is specified as virtual in a supertype of the type enclosing the redefined type. A redefined type must be a specialization of the virtuality constraint. A redefined type may be further redefined in specializations of its encloser.

•A finalized type is a type which is specified as virtual in a supertype of the encloser. A finalized type must be a specialization of the virtuality constraint. A finalized type may not be defined again in specializations of its encloser.

•Virtual, redefined and finalized can also be used for individual transitions in processes. The virtuality specification can occur in input symbols, start symbols and save symbols.

Page 32: SDS Foil no 1 SDL – Inheritance. SDS Foil no 2 Controller behaviour to Central Validation Idle Code (cid,PIN) Code(cid, PIN) via U Validation virtual

SDSFoil no 32

Summary 3 (analyzability)

• Specifying a type as virtual decreases the degree of analysis which can be performed on its encloser (since the instances of the virtual type may be of a type which is actually not known at the analysis of the encloser). However, it increases the flexibility of specializations.

• Finalizing a type increases the degree of analysis which can be performed on the encloser.

• Specifying a type as virtual decreases the degree of analysis which can be performed on its encloser (since the instances of the virtual type may be of a type which is actually not known at the analysis of the encloser). However, it increases the flexibility of specializations.

• Finalizing a type increases the degree of analysis which can be performed on the encloser.