session 25 overview: rf frequency generation from ghz to thz

436 • 2015 IEEE International Solid-State Circuits Conference 978-1-4799-6224-2/15/$31.00 ©2015 IEEE

ISSCC 2015 / SESSION 25 / RF FREQUENCY GENERATION FROM GHz TO THz / OVERVIEW

Session 25 Overview: RF Frequency Generation from GHz to THzRF SUBCOMMITTEE

25.1 A Highly-Digital Frequency Synthesizer Using Ring-Oscillator 1:30 PMFrequency-to-Digital Conversion and Noise CancellationC. Weltin-Wu, Analog Devices, San Jose, CA and University of California, San Diego, CA

Paper 25.1 presents a highly-digital 3.5GHz fractional-N PLL with dual-mode ring oscillator frequency-to-digital conversion and quantization noise cancellation. Its phase noise is -93, -126, and -151dBc/Hz at 100kHz, 1MHz, and 20MHzoffsets, respectively, its largest in-band spurious tone is -60dBc, and its power dissipation is 15.6mW.

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL Using Digital Sub-Sampling Architecture 2:00 PMT. Siriburanon, Tokyo Institute of Technology, Tokyo, Japan

In Paper 25.2, Tokyo Institute of Technology presents an all-digital PLL that employs a voltage-domain digitization realizedusing an ADC. The PLL achieves an in-band phase noise of -112dBc/Hz and an rms jitter of 380fsec at 2.2GHz.

25.3 A VCO with Implicit Common-Mode Resonance 2:30 PMD. Murphy, Broadcom, Irvine, CA

In Paper 25.3, Broadcom presents an LC VCO that uses a common-mode resonance at twice the oscillation frequency toreduce the impact of flicker noise. A 3GHz prototype VCO exhibits -139.7dBc/Hz at 1MHz offset.

Frequency generation circuits are ubiquitous building blocks in communication, sensing, and imaging systems. This session covers the latestadvances in frequency generation, targetting reduction of noise, chip area, and power consumption in frequency synthesizers and VCOs. The session includes an E-band phase-locked-based frequency synthesizer that employs passive scaling to increase loop-filter capacitance, a phase-locked-based transmission array at 320GHz frequency, and a highly stable thin-film-based acoustic resonator achieving a stability of ±3ppm from 0 to 90°C. Two papers describe techniques for reducing the effects of flicker noise in oscillators, another describes quantization noisecancellation in a fractional-N PLL, and another reduces PLL noise by manipulating impulse sensitivity and noise modulating functions of transistors. One paper addresses all-digital PLL design using voltage-mode digitization, and another describes inductorless PLL design to reducepower consumption.

Session Chair: Payam Heydari,University of California, Irvine, CA

Session Co-Chair: Taizo Yamawaki, Hitachi, Tokyo, Japan

437DIGEST OF TECHNICAL PAPERS •

ISSCC 2015 / February 25, 2015 / 1:30 PM

25.4 A 1/f Noise Upconversion Reduction Technique Applied 2:45 PMto Class-D and Class-F OscillatorsM. Shahmohammadi, Delft University of Technology, Delft, The Netherlands

In Paper 25.4, Delft University of Technology presents another technique based on setting up a trap for higher harmonicsto lower the flicker noise contribution on the oscillator phase noise. The 4GHz VCO prototype achieves -123.4dBc/Hz at1MHz offset.

25.5 A 320GHz Phase-Locked Transmitter with 3.3mW Radiated Power and 22.5dBm 3:15 PMEIRP for Heterodyne THz Imaging SystemsR. Han, Cornell University, Ithaca, NY

and Massachusetts Institute of Technology, Cambridge, MA

In Paper 25.5, Cornell University, MIT and STMicroelectronics present a 320GHz phase-locked-based 16-transmitter arrayin a 0.13μm SiGe process. The radiator achieves DC-to-RF efficiency of 0.54% and an EIRP of 22.5dBm.

25.6 A 70.5-to-85.5GHz 65nm Phase-Locked Loop with Passive Scaling of Loop Filter 3:45 PMZ. Huang, Hong Kong University of Science and Technology, Hong Kong, China

In Paper 25.6, HKUST and Tsinghua University present a CMOS E-band PLL with passive scaling of the loop filter toincrease the filter’s effective capacitance. The core PLL occupies 0.6mm2 of chip area with its loop filter taking 0.12mm2

of this area. It exhibits better than -91.7dBc/Hz of phase noise at 1MHz offset.

25.7 A 2.4GHz 4mW Inductorless RF Synthesizer 4:15 PML. Kong, University of California, Los Angeles, CA

In Paper 25.7, UCLA presents a CMOS inductorless 2.4GHz frequency synthesizer that can achieve locked phase noise of-114dBc/Hz at 1MHz offset with 4mW of power consumption.

25.8 A 2.4GHz VCO with FOM of 190dBc/Hz at 10kHz-to-2MHz Offset Frequencies in 0.13μm 4:30 PMCMOS Using an ISF Manipulation TechniqueA. Mostajeran, Sharif University of Technology, Tehran, Iran

and Cornell University, Ithaca, NY

In Paper 25.8, Sharif University of Technology and Cornell University present a CMOS 2.4GHz VCO that achieves low phasenoise by manipulating the ISF and NMF of transistors. The VCO achieves -128.4dBc/Hz phase noise at 1MHz offset.

25.9 A ±3ppm 1.1mW FBAR Frequency Reference with 750MHz Output and 750mV Supply 4:45 PMK. A. Sankaragomathi, University of Washington, Seattle, WA

In Paper 25.9, the University of Washington presents a CMOS 750MHz thin-film bulk acoustic resonator (FBAR) thatachieves a stability of ±3 ppm from 0 to 90°C. A new temperature sensor is implemented that achieves 1.75mK resolutionat 100msec sensing. 25

438 • 2015 IEEE International Solid-State Circuits Conference

ISSCC 2015 / SESSION 25 / RF FREQUENCY GENERATION FROM GHz TO THz / 25.1

25.1 A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation

Colin Weltin-Wu1,2, Guobi Zhao2, Ian Galton2

1Analog Devices, San Jose, CA, 2University of California, San Diego, CA

Digital fractional-N PLLs are increasingly used in place of analog fractional-NPLLs as frequency synthesizers in wireless applications, because they avoidlarge analog loop filters and can tolerate device leakage and low supply voltages,which makes them better-suited to highly-scaled CMOS technology [1-6].However, the phase noise and spurious tone performance of previously published digital PLLs is inferior to that of the best analog PLLs. This is becauseall fractional-N PLLs introduce quantization noise, and in prior digital PLLs thisnoise has higher power or spurious tones than in comparable analog PLLs.Digital PLLs based on ΔΣ frequency-to-digital conversion (FDC-PLLs) offer apotential solution to this problem in that their quantization noise ideally is equivalent to that of analog PLLs, but prior FDC-PLLs incorporate charge pumpsand ADCs that have so far limited their performance and minimum supply voltages [7,8]. This paper presents an FDC-PLL that avoids these limitations byimplementing the functionality of a charge pump and ADC with a simple dual-mode ring oscillator (DMRO) and digital logic. Also demonstrated is a newquantization noise cancellation (QNC) technique that relaxes the fundamentalbandwidth versus quantization noise tradeoff inherent to most fractional-N PLLs.The new techniques enable state-of-the-art spurious tone performance and verylow phase noise with a lower power dissipation and supply voltage than previously published state-of-the-art PLLs in the same class shown in Fig.25.1.6.

The FDC-PLL output frequency is fPLL=(N+α)fref, where N is an integer, α is afractional value between −½ and ½, and fref = 26MHz is the reference frequency.Its core (Figs. 25.1.1 and 25.1.2) consists of a ΔΣ FDC, a digital loop controller(DLC), and a digitally controlled oscillator (DCO). The ΔΣ FDC’s DMRO (Fig.25.1.3) switches between two frequencies, flow and fhigh, depending on the stateof the top PFD output, u(t). An analysis shows that for the correct choice of flowand fhigh the ΔΣ FDC is exactly equivalent to the 2nd-order ΔΣ modulator shownin Fig. 25.1.1, where ePLL[n] is the average frequency error of the PLL output overthe nth reference period. As such, the ΔΣ FDC has the self-dithering advantageof a 2nd-order ΔΣ modulator [8]. In contrast, previously published ring-oscillator-based time-to-digital converters are only equivalent to 1st-order ΔΣmodulators, which are notorious for having large spurious tones and input-dependent quantization noise [2].

The 1st and 2nd accumulators in the FDC-PLL’s equivalent 2nd-order ΔΣ modulatorderive from the frequency-to-phase integrating behaviors of the multi-modulusdivider and DMRO, respectively, and both ΔΣ modulator feedback loops derivefrom the ΔΣ FDC’s 2−z−1 local feedback. The divider and 2−z−1 block are digital,so the ΔΣ modulator’s first accumulator and outer feedback path are numericallyideal. The ΔΣ modulator’s second accumulator is not inherently ideal, but it issurprisingly insensitive to non-ideal DMRO behavior. This can be understood byan analogy to charge pumps in analog PLLs. It is well known that non-idealcharge pump switching transients do not degrade analog PLL performance provided each current source has time to settle whenever it is turned on or off,and provided the rising and falling transient shapes are independent of the timesat which the current source is turned on and off, respectively. For the same reasons, non-ideal DMRO frequency switching transients do not degrade theFDC-PLL performance provided the high and low durations of u(t) each reference period are long enough for the transients to settle out, and the risingand falling transient shapes are independent of the times at which u(t) goes highand low, respectively. Simulations indicate that these conditions occur to a highdegree of accuracy provided the average high-duration of u(t) per reference period is within a relatively wide range of acceptable values.

Ideally, fhigh – flow = fPLL, but deviations from this ideal only change the gain of thesecond ΔΣ modulator accumulator, so the PLL performance is not highly sensitive to such deviations. The value of flow sets the average high-duration ofu(t) each reference period so its value is not critical. Both flow and fhigh are set viaserial port interface (SPI) control to values within 0.4 to 3.4GHz and 1.8 to5.1GHz, respectively, with resolutions of approximately 5% whenever the PLLoutput frequency is changed.

If the average DMRO frequency were incommensurate with the reference frequency, its presence would likely cause fractional spurs. However, it can beverified that the ΔΣ FDC naturally locks the DMRO to an average frequency ofMfref where M is a positive integer in the ring phase calculator (Fig. 25.1.2)

between 40 and 80 set via the SPI. Therefore, any spurious tones from theDMRO are indistinguishable from reference spurs, which, as indicated in Fig.25.1.6, are very low.

The y[n] output of the ring phase calculator (Fig. 25.1.1) is a 5-level 26MHzsequence with a mean of –α when the PLL is locked. The digital logic that generates y[n] (Fig. 25.1.2) is a practical means of implementing the equivalentof counting DMRO cycles with an infinite-range counter, subtracting nM fromthe counter output each reference period where n = 0, 1, 2, …, and clipping thecounter value as necessary (which only happens before the PLL locks) to keepy[n] in the range {−2,−1,…, 2}. It can be verified that this exactly implements thebehavior of the charge pump and 5-level ADC in the FDC-PLL described in [8].

The goal of QNC is to cancel most of the quantization noise in y[n] prior to theloop filter so the PLL bandwidth can be increased significantly without increasing the PLL phase noise. To this end the phase decoder in Fig.25.1.2 uses the 13 DMRO inverter outputs to obtain −ê[n], which is an estimateof the DMRO’s quantization error quantized to 1/26th of a DMRO cycle, i.e.,1/26th of the quantization step-size of y[n]. The DLC logic does the equivalent ofadding −ê[n]+2ê[n−1]−ê[n−2] to y[n], which, given the above-mentioned ΔΣmodulator equivalence (Fig. 25.1.1), cancels most of its quantization noise.

The multi-modulus divider generates a ⅛fPLL clock in addition to the outputshown in Fig. 25.1.1. All the digital I/O and switching is retimed to this fast clock,to minimize reference spur coupling. Extensive clock gating minimizes the associated power dissipation. The DLC loop filter consists of a fixed-point multiplier, four IIR filters and a PI controller, configurable for type-I or II operation with a 1-to-300kHz bandwidth. The 8 LSBs of the 14b DLC outputdrive a 2nd-order digital ΔΣ modulator clocked at ⅛fPLL; the ΔΣ modulated LSBsin conjunction with the 6 MSBs drive the fine control port of the LC-DCO, whosetopology is similar to that presented in [1].

Figures 25.1.4 to 25.1.6 present measured results for fPLL≅3.5GHz and a 140kHzbandwidth. Figure 25.1.4 shows the measured phase noise with QNC enabledand disabled. QNC relies on the ΔΣ modulator equivalence described above, sothe significant reduction in phase noise that occurs when QNC is enabled indicates that the ΔΣ FDC works as expected. Figure 25.1.5 shows a plot of thelargest measured fractional spur over an extensive sweep of α. The fractionalspurs are largest within the loop bandwidth, with a worst-case of −60dBc, anddrop quickly out of band. The measured performance is summarized in Fig.25.1.6 along with that of the best comparable PLLs. As indicated, the FDC-PLLhas state-of-the-art spurious tone performance, excellent phase noise performance, and the lowest supply voltage and power dissipation among thoseshown in the table. This is enabled by the FDC-PLL’s unique combination of ahighly digital architecture and quantization noise equivalent to that of an analogPLL.

Acknowledgements:The authors are grateful to STMicroelectronics for IC fabrication and fruitful discussions, Integrand Software for EMX access, NSF (Award 1343389) andAnalog Devices for financial support, and Chris Mangelsdorf for helpful advice.

References:[1] R. B. Staszewski, et al., “All-Digital PLL and GSM/EDGE Transmitter in 90nmCMOS,” ISSCC Dig. Tech. Papers, pp. 316-317, Feb. 2005.[2] C. Hsu, et. al., “A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-NFrequency Synthesizer with a Noise-Shaping Time-to-Digital Converter andQuantization Noise Cancellation,” ISSCC Dig. Tech. Papers, pp. 340-341, Feb.2008.[3] H. H. Chang, et. al., “A Fractional Spur-Free ADPLL with Loop-GainCalibration and Phase-Noise Cancellation for GSM/GPRS/EDGE,” ISSCC Dig.Tech. Papers, pp. 200-201, Feb. 2008.[4] C. Weltin-Wu, et. al., “A 3.5GHz Wideband ADPLL With Fractional SpurSuppression Through TDC Dithering and Feedforward Compensation,” ISSCCDig. Tech. Papers, pp. 468-469, Feb. 2010.[5] K. Takinami, et. al., “A Rotary-Traveling-Wave-Oscillator-Based All-DigitalPLL with a 32-Phase Embedded Phase-to-Digital Converter in 65nm CMOS,”ISSCC Dig. Tech. Papers, pp. 100-101, Feb. 2011.[6] L. Vercesi, et. al., “A Dither-Less All Digital PLL for Cellular Transmitters,”IEEE Custom Integrated Circuits Conf., pp. 1-8, Sept. 2011.[7] W. T. Bax, M. A. Copeland, “A GMSK Modulator Using a ΔΣ FrequencyDiscriminator-Based Synthesizer,” IEEE J. Solid-State Circuits, pp. 1218-1227,Aug. 2001.[8] C. Venerus, I. Galton, “Delta-Sigma FDC Based Fractional-N PLLs,” IEEETrans. Circuits and Systems-I, pp. 1274-1285, May 2013.

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Figure 25.1.1: High-level block diagram of the FDC-PLL and equivalent signalprocessing behavior of the ΔΣ FDC.

Figure 25.1.2: Functional details of the dual-mode ring oscillator (DMRO) andring phase calculator.

Figure 25.1.3: Circuit details of the dual-mode ring oscillator (DMRO).

Figure 25.1.5: The largest measured fractional spurious tone as a function ofthe PLL’s fractional frequency setting. Figure 25.1.6: Performance summary and comparison table.

Figure 25.1.4: Measured FDC-PLL phase noise with and without quantizationnoise cancellation (QNC) for a bandwidth of 140kHz.

25

• 2015 IEEE International Solid-State Circuits Conference 978-1-4799-6224-2/15/$31.00 ©2015 IEEE

ISSCC 2015 PAPER CONTINUATIONS

Figure 25.1.7: Die micrograph. Note Corgi in lower-right-hand corner.



25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL Using Digital Sub-Sampling Architecture

Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Tokyo Institute of Technology, Tokyo, Japan

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). Itconsists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator,digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nmCMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RMS jitter of 380fs at 2.2GHz oscillation frequency. An FOMof -242dB has been achieved with a power consumption of only 4.2 mW.

Figure 25.2.1 shows a conceptual diagram of the proposed ADC-based all-digitalPLL (ADC-PLL), which is based on a voltage-domain digitization rather than atime-domain counterpart. TDCs or PFD/CPs in conventional PLLs are replacedby an ADC, which has advantages in terms of a finer resolution and lower powerconsumption. The bang-bang PLL (BB-PLL) [1] is one of the simplest architectures for digital PLLs but it suffers from the degradation of in-bandphase noise. The TDC-based all-digital PLL (TDC-PLL), based on the time-domain digitization, has been widely explored [2]-[6]. However, the jitterperformance, i.e., in-band phase noise, of recently-published TDC-PLLs still suffers from the limited TDC resolution. This paper demonstrates that the volt-age-domain digitization used in the proposed ADC-PLL is more feasible for adigital PLL, at least, in the present CMOS technology to achieve lower in-bandphase noise while consuming low power.

Figure 25.2.2 shows an ADC-based phase detector (ADC-PD), which consists ofan isolation buffer, sample-and-hold circuits, a pre-amplifier, and a 4b flashADC. Only the isolation buffer works at the oscillation frequency of the DCO whilethe other blocks operate at the reference clock. Comparing to the time-domaindigitization, the voltage-domain operation is advantageous due to capabilities of(1) sample-and-hold, (2) amplification, and (3) sub-ranging. This helps thephase detection to achieve finer resolution and wider dynamic range with lowpower consumption. Since the voltage-domain signal can be easily sampled-and-held, the proposed digital conversion has only to operate at a reference frequency as it is operating in sub-sampling operation. To obtain a finer resolution, the hold signal can be easily amplified by a linear operational amplifier unlike a linear time amplification which is not easily realized. In addition, the digital conversion can be parallelized and sliced in the voltage-domain. This gives an advantage to achieve a shorter delay and a finerresolution. In this implementation, the 4b flash ADC with resistive averaging hasa 10mV minimum resolution, and each dynamic comparator achieves a 2.5mVrmsoffset without any offset calibration according to the transient-noise simulation[7]. The voltage resolution can be magnified by the preamplifier to furtherimprove the equivalent time resolution (Δt), which can be calculated by the following equation:

where Vrange is the full input reference voltage range of an ADC, VDCO is the oscillation amplitude, N is the number of bits of the ADC, fDCO is the oscillationfrequency, and G is the gain of a preamplifier. In the case of 2.2GHz oscillation,the equivalent time resolution can be as fine as 0.23ps assuming oscillationamplitude of 1V, preamplifier gain of 20 and ADC resolution of 50mV. In addition, a re-conversion can be applied with a smaller gain in case of over-range. This means that a very fine time resolution with a wide range can beachieved by using an ordinary ADC.

Figure 25.2.3 shows the circuit schematic of an 18b push-pull Class-C DCO [8],where 8 bits are assigned for the frequency-locked loop (FLL) as the coarse tuning, 7 bits are assigned for the medium tuning, and 3 bits are used for thefine tuning with a delta-sigma modulation (MASH 1-1-1). To achieve a low powerwhile maintaining low phase noise, an LC push-pull Class-C topology isemployed even though a ring-type DCO can also be used in the proposed ADC-PLL. The push-pull Class-C VCO has an issue of the amplitude imbalance[8,9], so a replica-bias circuit is proposed for the amplitude balancing as well asthe start-up compensation. At the oscillation start-up of conventional push-pullclass-C VCOs [8], the voltage amplitude is small, and the gate biases could staylower than the threshold voltage due to the Class-C biasing. By using the replica-bias circuit, the gate bias voltages for PMOS and NMOS cross-coupledpairs are both enhanced at the oscillation start-up and adaptively changed as itenters the Class-C operation. The voltage imbalance caused by gm mismatch isalso improved by the proposed replica biasing scheme.

Figure 25.2.4 shows the entire block diagram of the proposed ADC-PLL. It iscomposed of an FLL for frequency acquisition [10] and the core phase-lockingloop using an ADC-PD, which can be understood as a digital version of a sub-sampling PLL. The ADC-PD samples and digitizes the oscillation signal atevery rising edge of the reference clock so that the crossing point of differentialoscillation signals meets the reference clock edge as shown in Fig. 25.2.2. Thesub-sampling loop can lock at every integer multiple of the reference clock. Inaddition, a dead zone in the FLL loop filter (LF) has been implemented so as notto disturb the phase locking of the core ADC-PD loop. The DCO has an 8b capacitor bank for the FLL coarse tuning which is controlled by the 12b frequency control word. The frequency resolution of FLL bits is designed to beless than the reference frequency, which is 10MHz for 40MHz reference. The 12bcounter is used for the frequency detection. In the phase-locked loop, the loopfilter in the phase-locking path generates a 7b acquisition code and a 6b trackingcode. The tracking code controls 3 delta-sigma modulated bits for fine-tuningthe DCO. In the proposed architecture, only a DCO and an ADC-PD require analog design while other building blocks are digital circuits that have been synthesized with a standard cell library.

Figure 25.2.5 shows the measured phase noise plots and the frequency spectrum at 2.2GHz evaluated by a signal source analyzer (Agilent E5052B), anda spectrum analyzer (Agilent E4407B), respectively. The measured in-bandphase noise is -112dBc/Hz at 300kHz offset, and the integrated jitter (10 kHz to40 MHz) is 0.38ps. The frequency tuning range of the DCO is 2.15 to 2.35 GHz.The reference clock is 100MHz, and the reference spur is -74dBc. The powerconsumption of the DCO is 1.5mW from a 1.0V supply. The isolation buffer andpreamplifier consume 0.5mW, and the 4b flash ADC consumes 1.2mW. The digital blocks consumes 1.0mW, including the digital loop filters, frequencycounter, and delta-sigma modulator.

Figure 25.3.6 shows a comparison table for the state-of-the-art TDC-based digital PLLs. The proposed ADC-PLL achieves the lowest in-band phase noiseperformance while consuming only 4.2mW. The figure of merit (FOM) is -242dB at 2.2GHz output frequency, where the FOM is defined as10log[(σt/1s)2•(PDC/1mW)], σt is the integrated jitter, and PDC is the DC powerconsumption. Figure 25.2.7 shows the die micrograph. The ADC-PLL is fabricated in 65nm CMOS technology. The areas for DCO, ADC-PD, and digitalblocks are 0.13mm2, 0.01mm2, and 0.01mm2, respectively.

Acknowledgments:This work was partially supported by STARC, MIC, SCOPE, STAR, VDEC in collaboration with Cadence Design Systems, Inc., Mentor Graphics, Inc., andAgilent Technologies Japan, Ltd.

References:[1] D. Tasca, et al., “A 2.9-to-4.0GHz Fractional-N Digital PLL with BBPD and560fsrms Integrated Jitter at 4.5mW Power,” ISSCC Dig. Tech. Papers, pp. 88-89,Feb. 2011.[2] C. Hsu, et al., “A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-NFrequency Synthesizer with a Noise-Shaping Time-to-Digital Converter andQuantization Noise Cancellation,” IEEE J. Solid-State Circuits, Vol. 43, No. 12,pp. 2776-2786, Dec. 2008.[3] N. Pavlovic, and J. Bergervoet, “A 5.3GHz Digital-to-Time-Converter-BasedFractional-N All-Digital PLL,” ISSCC Dig. Tech. Papers, pp. 54-55, Feb. 2011.[4] C.-W. Yao, and A. N. Willson, “A 2.8-3.2-GHz Fractional-N Digital PLL WithADC-Assisted TDC and Inductively Coupled Fine Tuning DCO,” IEEE J. Solid-State Circuits, Vol. 48, No. 3, pp. 698-710, Mar. 2013.[5] V. K. Chillara, et al., “An 860μW 2.1-to-2.7GHz All-Digital PLL-BasedFrequency Modulator with a DTC-Assisted Snapshot TDC for WPAN (BluetoothSmart and Zigbee) Applications,” ISSCC Dig. Tech. Papers, pp.172-173, Feb.2014.[6] M. He, et al., “A 40nm Dual-Band 3-Stream 802.11a/b/g/n/ac MIMO WLANSoC with 1.1Gb/s Over-the-Air Throughput,” ISSCC Dig. Tech. Papers, pp. 350-351, Feb. 2014. [7] M. Miyahara, et al., “A 2.2Gb/s 7b 27.4mW Time-Based Folding-Flash ADCwith Resistively Averaged Voltage-to-Time Amplifiers,” ISSCC Dig. Tech. Papers,pp. 388-389, Feb. 2014.[8] A. Mazzanti, and P. Andreani, “A Push-Pull Class-C CMOS VCO,” IEEE J.Solid-State Circuits, Vol. 48, No. 3, pp. 724-732, Mar. 2013.[9] L. Farnori, and P. Andreani, “A High-Swing Complementary Class-C VCO,”European Solid-State Circuits Conf., pp. 407-410, Sept. 2013.[10] Z. Ru, et al., “A 12GHz 210fs 6mW Digital PLL with Sub-sampling BinaryPhase Detector and Voltage-Time Modulated DCO,” IEEE Symp. VLSI Circuits,pp. 194-195, June 2013.

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Figure 25.2.1: Conceptual diagram of proposed ADC-PLL. Figure 25.2.2: Phase detector using analog-to-digital converter (ADC-PD).

Figure 25.2.3: Schematic of Class-C push-pull DCO with its relevant wave-forms.

Figure 25.2.5: Measured phase noise and frequency spectrum at 2.2GHz. Figure 25.2.6: Performance comparison with the state-of-the-art digital PLLs.

Figure 25.2.4: Block diagram of the proposed ADC-PLL.

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Figure 25.2.7: Die micrograph.



25.3 A VCO with Implicit Common-Mode Resonance

David Murphy, Hooman Darabi, Hao Wu

Broadcom, Irvine, CA

CMOS VCO performance metrics have not improved significantly over the lastdecade. Indeed, the best VCO Figure of Merit (FOM) currently reported was published by Hegazi back in 2001 [1]. That topology, shown in Fig. 25.3.1(a),employs a second resonant tank at the source terminals of the differential pairthat is tuned to twice the LO frequency (FLO). The additional tank provides a highcommon-mode impedance at 2×FLO, which prevents the differential pair transistors from conducting in triode and thus prevents the degradation of theoscillator’s quality factor (Q). As a consequence, the topology can achieve anoscillator noise factor (F) – defined as the ratio of the total oscillator noise to thenoise contributed by the tank – of just below 2, which is equal to the fundamentallimit of a cross-coupled LC CMOS oscillator [2]. There are, however, a few drawbacks of Hegazi’s VCO: (1) the additional area required for the tail inductor,(2) the routing complexity demanded of the tail inductor, which can degrade itsQ and limit its effectiveness, and (3) for oscillators with wide tuning ranges, theneed to independently tune the second inductor, which again can degrade its Q.Moreover, it can be shown that the common-mode impedance of the main tankat 2×FLO also has a significant effect on the oscillator’s performance, which if notproperly modeled can lead to disagreement between simulation and measurement, particularly in terms of the flicker noise corner. To mitigate theseissues, this work introduces a new oscillator topology that resonates the common-mode of the circuit at 2×FLO, but does not require an additional inductor.

The proposed VCO is shown in Fig. 25.3.1(b). Whereas Hegazi’s VCO makes useof an additional tank to realize a large common-mode impedance at 2×FLO, theproposed VCO tunes the common-mode resonant point of the primary tank to2×FLO, which can be tuned independently of the differential resonant frequency.Typically the tank is composed of a differential spiral inductor with series inductance (LS) and some positive coupling coefficient (k) and a combination ofcommon-mode (CCM) and differential (CDM) capacitance. Therefore, the differential resonance (or oscillation frequency) is given by

and the common-mode resonant frequency is given by:

By selecting k, CCM and CDM such that FCM = 2×FLO, the common-mode of the circuit resonates at 2×FLO without the need for an additional tank.

To gain insight into the performance of the proposed VCO, it is helpful to rewritethe expression for FOM in terms of oscillator efficiency (η) and oscillator noisefactor (F):

where η = PTANK/PDC, the total power consumption is PDC, the power dissipated inthe tank is PTANK = A2/(2RP), the oscillation amplitude is A, and the equivalent tankloss is given by RP. This means that an oscillator’s FOM depends on only threevariables: quality factor, efficiency, and noise factor. Since Q is largely set for agiven process and desired tuning range, a circuit designer can only optimize ηand F. Bank’s general result [3-5] explains that when the energy-restoring circuitis connected across the entire tank, the minimum possible noise contribution ofthe energy-restoring circuit is directly related to RP through some proportionalconstant, which in the case of a CMOS design cannot be lower than γ = 2/3, giving a minimum achievable noise factor of FMIN = 1+γ. The other variable is effi-ciency, which by definition cannot exceed 1 (or 100%). Figure 25.3.2 shows theproposed topology complete with an idealized inductance with Q = 12 and anarbitrary arrangement of ideal differential and common-mode capacitors, whoseratio is defined by the variable X. The variable X was then swept, which movedthe capacitors from fully common-mode to fully differential. At the optimumpoint of X = 0.65, the common-mode impedance at 2×FLO is maximized and the

noise factor reaches the theoretically minimum value of 1.67, efficiency reaches75%, and, therefore, FOM is also maximized. Indeed, for the given Q, the achievable FOM of the proposed VCO is only 1.5 dB less than any theoreticallyconceivable LC CMOS oscillator. Interestingly, at this optimum point, the flickernoise contribution of the differential pair transistors is also nulled (as noted bythe fact that the FOM at 50kHz is equal to the FOM at 10MHz).

A wideband, practical realization of this topology that was fabricated in 28nmCMOS is shown in Fig. 25.3.3. The ratio of common-mode to differential capacitance is set by the coupling coefficient of the inductor through the expression:

A higher k requires less differential capacitance, but results in a reduced common-mode Q. By contrast, choosing a low or negative k maintains a largecommon-mode Q but requires a very small amount of common-mode capacitance, which is difficult to achieve in a practical design. As a compromise,the fabricated design used an inductor with k ≈ 0.33, which therefore requiresCDM/CCM ≈ 1. To keep k small, a two-turn inductor was employed and the radiusof the inner turn was purposely reduced. Additionally, in order to allow the supply rail to be solidly AC-shorted to ground with minimal common-mode Qdegradation due to routing, the inductor was flipped inside out and the common-mode terminals were routed on the outside (highlighted on the top ofFig. 25.3.3). The differential inductance was simulated as 1.5nH. The tunable differential switched-capacitor bank and the tunable common-mode bank arehighlighted in Fig. 25.3.3. Both capacitors banks were composed of 32 identicalunit cells that were controlled using an interleaved thermometer code. When theswitches are off, a common-mode path is presented to ground through the digital inverter controlling the switch. Therefore, it is important to make theseinverters large enough that they don’t degrade the common-mode Q. The measured tuning range of the fabricated VCO was 2.85 GHz to 3.75 GHz. Figure25.3.4 shows the measured phase noise profile and FOM profile versus carrieroffset for three frequency settings. Note that the FOM (in the thermal noiseregion) is always better than 192, and the flicker noise corner is around 200kHz.Figure 25.3.5 shows the phase noise, FOM, current consumption and flickernoise corner (measured as the frequency at which FOM degrades by 3dB fromthe FOM at 5MHz) versus oscillation frequency. Note that the good FOM and lowflicker noise corner is maintained across the band. As the VCO is voltage-biased,by monitoring the current and assuming an efficiency of around 65%, we cancalculate the Q of the tank as approximately 11.5. Figure 25.3.6 compares ourwork to the current state-of-the-art VCOs. The FOM is within 2.5dB of Hegazi’sVCO [1], but requires no additional inductor, has a wider tuning range (18% versus 27%) and operates from a much lower supply voltage (0.9V versus 2.5V).Compared to other recent low-voltage, low-noise designs [6,7], the proposeddesign has a comparable or better FOM, and has a significantly lower flickernoise corner (200kHz versus 750kHz to 2000kHz).

References:[1] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.[2] J.J Rael and A.A. Abidi, “Physical processes of phase noise in differential LCoscillators,” IEEE Custom Integrated Circuits Conf., pp. 569-572, 2000.[3] J. Bank, “A harmonic-oscillator design methodology based on describingfunctions,” Ph.D. dissertation, Chalmers University of Technology, Sweden,2006.[4] A. Mazzanti and P. Andreani, “Class-C harmonic CMOS VCOs, with a generalresult on phase noise,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716–2729, Dec. 2008.[5] D. Murphy, J. Rael, and A. Abidi, “Phase noise in LC oscillators: A phasor-based analysis of a general result and of loaded Q,” IEEE Trans. Circuitsand Systems-I, vol. 57, no. 6, pp. 1187–1203, 2010.[6] L. Fanori and P. Andreani, “A 2.5-to-3.3GHz CMOS Class-D VCO,” ISSCC Dig.Tech. Papers, pp. 346-347, Feb. 2013.[7] M. Babaie and R. B. Staszewski, “Third-Harmonic Injection TechniqueApplied to a 5.87-to-7.56GHz 65nm CMOS Class-F Oscillator with 192 dBc/HzFOM,” ISSCC Dig. Tech. Papers, pp. 348-349, Feb. 2013.

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Figure 25.3.1: Hegazi’s VCO, and the proposed VCO topology that does notrequire an additional LC tank.

Figure 25.3.2: Proposed VCO with idealized LC Tank. For a given inductor coupling coefficient, there is an optimum ratio of common-mode to differentialcapacitance that simultaneously maximizes FOM and efficiency, minimizes Fand nulls flicker noise.

Figure 25.3.3: Schematic of fabricated 28nm design.

Figure 25.3.5: Performance metrics versus oscillation frequency. Figure 25.3.6: Table of comparison.

Figure 25.3.4: Measured phase noise and FOM versus carrier offset.

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25.4 A 1/f Noise Upconversion Reduction Technique Applied to Class-D and Class-F Oscillators

Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski

Delft University of Technology, Delft, The Netherlands

The 1/f (flicker) noise upconversion degrades the close-in spectrum of CMOS RFoscillators. The resulting 1/f3 phase noise (PN) can be an issue in PLLs with aloop bandwidth of <1MHz, which practically implies all cellular phones. A previously published noise-filtering technique [1] and adding resistors in serieswith gm-device drains [2] have shown significant reduction of the 1/f3 oscillatorPN corner. However, the former needs an additional tunable inductor and the latter degrades PN in the 20dB/dec region.

The flicker noise can upconvert via two major phenomena. First, tail current flicker noise can modulate the oscillating waveform amplitude, which can convert to PN through a nonlinear C-V characteristic of varactors and activedevices. The second mechanism is the Groszkowski effect [3]: The presence ofharmonic components of the active gm device current can cause a frequency driftof the tank resonance (see Fig. 25.4.1-top). The fundamental drain current IH1

flows into Rp (equivalent parallel resistance of the tank), while its 2nd- and 3rd-harmonic components, IH2 and IH3, mainly take the capacitance path due to itslower impedance. Consequently, the reactive energy stored in the inductanceand capacitance is perturbed, shifting the oscillation frequency Δω lower to satisfy the resonance condition. This shift is static but any variation in the IH2(orIH3)-to-IH1 ratio due to the 1/f noise can modulate Δω and show itself as the 1/f3

PN, see Fig. 25.4.1(top-left). This phenomenon is clearly visible and now dominant in oscillators with the customary tail current source transistorremoved, which is the trend in nanoscale CMOS.

Suppose the tank input impedance Zin demonstrates other peaks at the strongharmonics of the fundamental frequency ω0. These harmonics would mainlyflow into their relative equivalent resistance of Zin instead of its capacitive part,as is shown in Fig. 25.4.1-bottom. Consequently, Groszkowski’s effect on the 1/fnoise up-conversion will reduce significantly. Specifically core transistor flickernoise modulates the 2nd harmonic of the oscillator’s virtual ground. This modulation generates 2nd-harmonic current in the parasitic Cgs capacitors andgets injected to the tank. Consequently, the IH2 component is usually the maincontributor to the frequency shift. In this work we introduce a tank topology thateffectively traps IH2 in its resistive part without the cost of an extra area. The tankderives this characteristic from the different behavior of inductors and transformers in differential (DM) and common mode (CM) excitations.

Figure 25.4.2 shows a 2-turn inductor in DM and CM excitations. In DM, the currents in each turn are in the same direction resulting in an additive flux, whilein CM, the opposite currents cancel each other’s magnetic flux. Due to this cancellation, the effective CM inductance is very low. The “F2 inductor” isdesigned with appropriate spacing between the windings and demonstrates a 4xsmaller effective inductance for CM inputs than for DM inputs. The CM input signals cannot see the differential capacitances, hence to be able to set a CM resonance, the capacitors across the tank have to be single-ended. The inputimpedance of the F2 tank, Zin, demonstrates two resonant frequencies, ωDM=ω0,and ωCM=2ω0. The precise inductor geometry controlled by lithography maintains LDM/LCM≈4 and hence ωCM/ωDM ≈2 over the full tuning range, TR. Thelower and broader CM impedance, compared to that of DM, guarantees the 2nd-harmonic current flowing mainly to the additional resistive part, even if CMresonant frequency is mis-tuned by 10%.

Figure 25.4.3 shows a 1:2 turns ratio transformer excited by DM and CM inputsignals at its primary. In DM excitation, the induced currents at the secondarycirculate in the same direction leading to a strong coupling factor, km. On theother hand, in CM excitation, the induced currents cancel each other, resultingin a weak km. The “F2,3 tank” employs the F2,3 transformer, single-ended primaryand differential secondary capacitors. This tank has two DM and one CM resonant frequencies. For resistive traps at 2nd and 3rd harmonics, ωCM=2ω0,DM

and ω1,DM=3ω0,DM, resulting in LsCs=3LpCp and km=0.72 [4]. In reality, Lpc>Lpd dueto the metal track inductance LT connecting the center tap to the supply, thuslower km is needed to satisfy both F2 and F3 operations. Unlike the F2 tank, in theF2,3 tank, the ωCM/ω0,DM and ω1,DM/ω0,DM ratio is no longer only dependent on theinductive parts. Careful design of the tunable single-ended primary and differential secondary capacitor banks maintains ωCM/ω0,DM≈2 and ω1,DM/ω0,DM≈3over the full TR.

To demonstrate how this technique can reduce the flicker noise upconversion,we employ the F2-tank to a Class-D [5], and F2,3-tank to a Class-F [4] oscillator.These classes of oscillator are chosen for their strong amount of IH2.

The original Class-D oscillator shows promising performance in the 1/f2 regionbut it suffers from the strong 1/f noise upconversion and frequency supply pushing. All known mitigation techniques (e.g., [6]) seem either ineffective orunsuitable. As shown in Fig. 25.4.4-top, the Class-D/F2 oscillator adopts the F2

tank. The gm-devices M1 and M2 inject a large IH2 current into the tank due to theground-clipping of signals. Figure 25.4.4 also compares Class-D and D/F2

waveforms. Clearly the rise/fall times are more symmetric in the Class-D/F2

oscillator, which translates to lower DC value of the gm-transistor ISF functionand thus lowers the 1/f noise up-conversion. The Class-D oscillator shows 0.8to 2.5MHz 1/f3 corner frequency. A version of Class-D with a tail-filter technique[6] was also designed in [5]. A resonator at 2ω0 is interposed between the common source of the transistors and ground. This method is only partiallyeffective, lowering the 1/f3 PN corner to 0.6 to 1MHz, since it only linearizes thegm device and partially reduces the IH2 amount. Our method traps IH2 in the tankand simulations predict the 1/f3 PN corner of <50 kHz.

The Class-F3 oscillator has a pseudo square-wave oscillation waveform bydesigning ω1,DM=3ω0,DM, and avoiding filtering of IH3 in the tank. The special ISFfunction of square waveform oscillation leads to a better PN performance.Simulations show that in this oscillator IH2 can be as high as IH3. The Class-F2,3

oscillator replaces the Class-F3 tank with the F2,3 one, as shown in Fig. 25.4.4-bottom. Simulations show that the pseudo square wave of Class-F is preservedand the 1/f3 PN corner can be reduced from 300 to 700 kHz to <30 kHz.

The Class-D/F2 oscillator was prototyped in a 40nm 1P8M CMOS process without ultra-thick metal layers. The chip micrograph is shown in Fig. 25.4.7-left.The tank employs a 1.5nH inductor with simulated Q-factor of 12 at 3GHz. M1,2

are (200/0.04)μm low-Vt devices which guarantee start-up and Class-D operation over PVT. The oscillator is tunable between 3.3 and 4.5GHz (31% TR)with a 6b MOM capacitor bank. Figure 25.4.5-top shows the PN plots at fmax andfmin oscillation frequencies, with VDD=0.5V. The 1/f3 PN corner is ~100kHz at fmax

and reduces to 60kHz when all switches are on at fmin.

The Class-F2,3 oscillator was prototyped in a 40nm 1P7M CMOS process with anultra-thick metal layer (see Fig. 25.4.7-right). The tank primary and secondaryare 0.58nH and 1.5nH, respectively, and km=0.67. The simulated Q-factors of theprimary and secondary windings are 13 and 19 at 5GHz. M1,2 are (64/0.27)μmthick-oxide devices to tolerate large gate voltage swings. The oscillator is tunablebetween 5.4 and 7 GHz (25% TR) with two 6b MOM capacitor banks. Figure25.4.5-bottom shows the PN plots at fmax and fmin oscillation frequencies, withVDD of 1V. The 1/f3 PN corner is ~130kHz at fmax and reduces to 60kHz when allswitches are on at fmin.

In both oscillators the PN in the 1/f2 region fits well with the simulations.However, the 1/f3 PN corner is at least ~2x higher than expected mainly due to a2ω0 disturbance on the supply rail created by the oscillator output buffer. Fig.25.4.6 summarizes the oscillator performances and compares them with theircounterpart reference designs. Even with the performance degradation due tothe unavoidable supply sharing, this technique demonstrates >10–to-15ximprovement in the 1/f3 PN corner in Class-D and 5x improvement in Class-Fwith no extra area penalty. It also significantly improves supply pushing.

Acknowledgments:We thank the RF Dept. of HiSilicon and EU ERC Starting Grant 307624.

References:[1] A. Ismail and A. A. Abidi, “CMOS differential LC oscillator with suppressedup-converted flicker noise,” ISSCC Dig. Tech. Papers, pp. 98-99, Feb. 2003.[2] S. Levantino, et al., “Suppression of flicker noise up-conversion in a 65nmCMOS VCO in the 3.0-to-3.6GHz band,” ISSCC Dig. Tech. Papers, pp. 50-51,Feb. 2010.[3] J. Groszkowski, “The interdependence of frequency variation and harmonic content, and the problem of constant-frequency oscillator,” Proc. IRE, vol. 21,pp. 958-981, 1933.[4] M. Babaie et al., “A Class-F CMOS oscillator,” IEEE J. Solid-State Circuits,vol. 48, no12, pp. 3120-3133, Dec. 2013.[5 L. Fanori et al., “Class-D CMOS oscillators,” IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3105-3119, Dec. 2013.[6] E. Hegazi et al., “A filtering technique to lower LC oscillator phase noise,”IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.

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Figure 25.4.1: Current harmonic paths and frequency drift. Figure 25.4.2: F2 inductor, F2 tank and tank Zin.

Figure 25.4.3: F2,3 transformer, F2,3 tank and tank Zin.

Figure 25.4.5: Measured oscillator PNs. Figure 25.4.6: Comparison with relevant oscillators.

Figure 25.4.4: Oscillator schematics and waveforms.

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Figure 25.4.7: Die micrographs.



25.5 A 320GHz Phase-Locked Transmitter with 3.3mW Radiated Power and 22.5dBm EIRP for Heterodyne THz Imaging Systems

Ruonan Han1,2, Chen Jiang1, Ali Mostajeran1, Mohammad Emadi1, Hamidreza Aghasi1, Hani Sherry3, Andreia Cathelin3, Ehsan Afshari1

1Cornell University, Ithaca, NY, 2Massachusetts Institute of Technology, Cambridge, MA, 3STMicroelectronics, Crolles, France

Non-ionizing terahertz imaging using solid-state integrated electronics has beengaining increasing attention over the past few years. However, there are currently several factors that deter the implementations of fully-integrated imaging systems. Due to the lack of low-noise amplification above fmax, the sen-sitivity of THz pixels on silicon cannot match that of its mm-Wave or light-wavecounterparts. This, combined with the focal-plane array configuration adoptedby previous sensors, requires exceedingly large power for the illuminationsources. Previous works on silicon have demonstrated 1mW radiation [1,3]; buthigher power, as well as energy efficiency, are needed for a practical imagingsystem. In addition, heterodyne imaging scheme was demonstrated to be veryeffective in enhancing detection sensitivity [4]. Due to the preservation of phaseinformation, it also enables digital beam forming with a small number of receiverunits. This however requires phase locking between the THz source and receiverLO with a small frequency offset (IF<1GHz). In [5], a 300GHz PLL is reportedwith probed output. In this paper, a 320GHz transmitter using SiGe HBTs is presented (Fig. 25.5.1). Combining 16 coherent radiators, this work achieves3.3mW radiated power with 0.54% DC-RF efficiency, which are the highestamong state-of-the-art silicon THz radiators shown in the comparison table inFig. 25.5.6. Meanwhile, the output beam is phase-locked by a fully-integratedPLL, which enables high-performance heterodyne imaging systems.

Generally, to maximize the harmonic (2f0) output power inside a radiating oscillator, it is critical to (i) achieve the optimum voltage gain of the transistor atf0 to maximize the oscillation activity, (ii) isolate the base and collector at the harmonic to eliminate the self-power-cancelation/loading effects [1], (iii) de-couple the base and collector at DC for optimum biasing, and (iv) efficiently radiate the harmonic signal without long, lossy feed lines (used for resonance atf0 in previous works). Unfortunately, none of the previous topologies can simultaneously meet these conditions. In this paper, this is achieved in a harmonic radiator structure, which utilizes multimode wave synthesis. The radiated power and DC-to-RF efficiency are therefore fully optimized.

The radiator structure (Fig. 25.5.2) consists of two self-feeding oscillator units[1] coupled by a return-path gap (RPG). The RPG has four ports. Each two portsat top and bottom are connected in the forward current paths while separated bya metal gap in the return current paths. We will show that the RPG permits thetransmission of unbalanced (differential) mode wave, while fully blocks the balanced (common) mode wave. The former case is illustrated in the left part ofFig. 25.5.3, where a pair of differential signals is injected into P1 and P2. The forward current on the microstrip signal trace flows into the virtual ground “a”.Meanwhile, the differential return current, in the form of a quasi-TEM travelingwave, propagates through the central metal gap and then induces differentialreturn (as well as forward) currents in P3 and P4. This means the RPG is transparent to the differential signal along P1-to-P3 and P2-to-P4 paths. To blockthe wave at the top/bottom boundaries of the RPG, two λf0/4 slot pairs transforming short (or virtual ground “c”) to open are used. HFSS simulationsindicate that for differential signals, the RPG has a transmission loss of only0.6dB at f0 (160GHz). Such broadband transparency forms the feedback paths ofthe two self-feeding oscillator units (Fig. 25.5.2), which provide optimum gaincondition (hence maximum oscillation power) for the HBTs with proper impedance and length of the self-feeding lines [1]. Note that the RPG also separates the DC bias of the base and collector of the HBTs.

Next, for the common-mode excitation (right part of Fig. 25.5.3), the centralmetal gap is like a CPW without signal trace. Propagation of the symmetric waveinduced by the in-phase return currents is therefore not supported. Excellent isolation between the two port pairs, shown in the simulation, is obtained. Ouroscillator utilizes this behavior for three purposes: (i) at f0, the two HBTs cannotoscillate with the undesired in-phase mode; (ii) the generated common-mode 2f0

signal is fully isolated between the base and collector; (iii) the slots on the top(λ/4 at f0) now form a folded-slot antenna at 2f0, which instantly radiates the harmonic signal to the chip backside without feed lines. This greatly reduces thesignal loss and chip area. The simulated radiation pattern of each radiator isshown in Fig. 25.5.3. The estimated radiation efficiency (including the reflectionat silicon-to-air interface) is ~50%. It is also noteworthy that the 2f0 signal isgenerated by the nonlinear heterojunction at the base of the HBT. Such techniquerecycles the fundamental oscillation power dissipated at the base, and efficientlyupconverts it to 2f0. From the above analysis, it can be seen that through the synthesis and guidance of different electromagnetic wave modes, we have optimized the fundamental oscillation, harmonic generation and radiation with avery compact passive structure.

In the transmitter, 16 radiators combine their power in free space. For coherency, they are injection-locked by 4 mutual-coupled VCOs (Fig. 25.5.1).Based on differential Colpitts topology, the VCOs oscillate at 80GHz with second-harmonic extraction to drive 4 160GHz buffers. One VCO also connectsto a divider chain inside a PLL. It is noteworthy that the PLL has a controllablefractional-N capability. When the transmitter pairs with a heterodyne receiver,where an identical PLL (with fractional-N disabled) is built-in to generate LO,desired RF-to-LO frequency offset (~100MHz) is obtained. In such imaging system, only one low-frequency reference clock (~312MHz) is needed.

The transmitter is implemented using a 0.13μm SiGe:C BiCMOS process(fT/fmax=220GHz/280GHz [6]). The measurement setup is shown in Fig. 25.5.4,where the radiation spectra are measured by a WR-3 horn antenna cascadedwith a VDI Even-Harmonic Mixer (EHM). It can be seen that the radiators aresynchronized by the on-chip PLL. The measured output frequency is 317GHz. Toeliminate the substrate wave caused by the silicon substrate, a hemispheric(radius=5mm), high-resistivity Si lens is attached on the chip backside. Themeasured radiation patterns with and without the lens are shown in Fig. 25.5.5,which have a directivity of 17.3dBi and 13.0dBi, respectively. The difference isdue to the refraction at the silicon-to-air interface (without lens). Using anErickson PM4 calorimeter, the radiated power/EIRP (with silicon lens) are measured at varying distances and radiator DC supplies. Shown in Fig. 25.5.5,the measurement is consistent with the Friis equation in far-field range above5cm. The peak EIRP and total radiated power are 22.5dBm and 5.2dBm(3.3mW). Without the silicon lens, the EIRP is 13.9dBm, and the radiated poweronly drops to 0.9dBm (1.23mW), which is still higher than [1,2,7] and [8].Finally, the micrograph of the die and a performance comparison with the state-of-the-art are given in Fig. 25.5.6. This work demonstrates fully-integratedphase-locking capability, and the highest output power and DC-to-RF efficiencyamong the silicon THz radiators listed in the Table.

Acknowledgements:The authors acknowledge the Army Research Lab and National ScienceFoundation for their support and STMicroelectronics for silicon donation.

References:[1] R. Han and E. Afshari, “A 260GHz Broadband Source with 1.1mWContinuous-Wave Radiated Power and EIRP of 15.7dBm in 65nm CMOS,” ISSCCDig. Tech. Papers, pp. 138-139, Feb. 2013.[2] U. Pfeiffer, et al, “A 0.53THz Reconfigurable Source Array with up to 1mWRadiated Power for Terahertz Imaging Applications in 0.13μm SiGe BiCMOS,”ISSCC Dig. Tech. Papers, pp. 256-257, Feb. 2014.[3] K. Schmalz, et al, “245GHz SiGe Transmitter with Integrated Antenna andExternal PLL,” IEEE International Microwave Symp. Dig., pp. 1-3, June 2013.[4] F. Friederich, et al, “THz Active Imaging Systems with Real-TimeCapabilities,” IEEE Trans. THz Science & Technology, vol. 1, no. 1, pp. 183-200,Sept. 2011.[5] P. Chiang, et al, “A 300GHz Frequency Synthesizer with 7.9% Locking Rangein 90nm SiGe BiCMOS,” ISSCC Dig. Tech. Papers, pp. 260-261, Feb. 2014.[6] P. Chevalier, et al, “Scaling of SiGe BiCMOS Technologies for Applicationsabove 100GHz,” IEEE Compound Semiconductor IC Symp., Oct. 2012.[7] K. Sengupta and A. Hajimiri, “A 0.28THz 4x4 Power-Generation and Beam-Steering Array,” ISSCC Dig. Tech. Papers, pp. 256-257, Feb. 2012.[8] Y. Tousi and E. Afshari, “A Scalable THz 2D Phased Array with +17dBm ofEIRP at 338GHz in 65nm Bulk CMOS,” ISSCC Dig. Tech. Papers, pp. 258-259,Feb. 2014.

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Figure 25.5.1: Architecture of the 320GHz transmitter for heterodyne imagingsystems.

Figure 25.5.2: Return-path gap radiator and its operations at f0 (as two self-feeding oscillators) and 2f0 (as a harmonic radiator). The simulated optimum phase of the transistor (plus half RPG) at f0 is also shown.

Figure 25.5.3: The EM field distribution and simulated insertion loss of theRPG structure for (left) differential oscillation at f0 and (right) common-modeharmonic generation/radiation at 2f0.

Figure 25.5.5: (Top) Measured radiation pattern, (bottom left) received radiation power versus distance, and (bottom right) total radiated power andDC-to-RF efficiencies at different power supplies.

Figure 25.5.6: Chip micrograph and performance comparison with other state-of-the-art silicon-based radiators in sub-THz/THz range.

Figure 25.5.4: Measurement setup and the measured spectra of the downconverted radiation (with and without radiator synchronization).

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Figure 25.5.7: Die micrograph of the 320GHz SiGe Transmitter.



25.6 A 70.5-to-85.5GHz 65nm Phase-Locked Loop with Passive Scaling of Loop Filter

Zhiqiang Huang1, Howard Cam Luong1, Baoyong Chi2, Zhihua Wang2, Haikun Jia2

1Hong Kong University of Science and Technology, Hong Kong, China, 2Tsinghua University, Beijing, China

To support 16-QAM modulation in E-band applications, phase-locked loops(PLLs) are required to have wide a frequency tuning range from 71 to 86GHz andlow phase noise of -90dBc/Hz @1MHz [1], which are still very challenging evenwith aggressive CMOS scaling [2]. Another issue associated with PLLs is the difficulty to integrate on-chip loop filters. Active loop filters are employed toscale down the loop filter capacitors and enable them to be fully integrated on-chip [3]. However, this method suffers from large active noise induced by theop-amp. Moreover, as the capacitance is reduced, the resistor value has to beincreased to maintain the same zero frequency, leading to higher thermal noiseand limiting achievable scaling factor. Another method is to integrate digital loopfilters in all-digital PLLs (ADPLLs) [4]. Unfortunately, the quantization noise ofdigitally-controlled oscillators (DCOs) becomes a bottleneck to achieve goodphase noise due to their limited frequency resolution. Furthermore, E-band DCOoscillation frequency is more sensitive to capacitor variation, making it evenmore difficult to achieve high frequency resolution. To address these issues, thispaper proposes a 70.5-to-85.5GHz PLL with an injection-locked frequency tripler(ILFM3) and passive scaling to increase the effective capacitor for the loop filterby 100 times.

Figure 25.6.1 shows a block diagram of the proposed E-band integer-N PLL witha fully integrated loop filter. A fundamental 26GHz VCO is followed by a balanceddifferential-input quadrature-output ILFM3 to generate quadrature output signalsfrom 71.5GHz to 85.5GHz. With this topology, the fundamental VCO does notneed to provide quadrature outputs and can save half of its power as comparedto a QVCO. A divide-by-4 CML divider is inserted between VCO and programmable divider to divide down the frequency. With the ILFM3 and divide-by-4 CML divider, the minimum step of frequency multiplication ratio is12. Employing a 41.67MHz reference and a programmable divider with divisionratio from 143 to 171, the PLL achieves 0.5GHz frequency resolution and isreconfigurable for both 5GHz and 1GHz channels from 71 to 86GHz. The fundamental VCO frequency is controlled and stabilized by a PLL with a passive-scaling dual-path loop filter with a DC control circuit for saturation prevention.

In PLLs, the most difficult part to be integrated on-chip is the integration capacitor, which needs to be extremely large to filter out charge-pump noise andreference spur with sufficient margins. Since a larger capacitor would introducea smaller voltage with a fixed current flowing through it, a large effective capacitor can be realized with passive scaling using a capacitive voltage divideras depicted in Fig. 25.6.2. The capacitors Cb and C2 form a voltage divider todivide down the voltage across C1 and increase the effective integration capacitorfrom (C1+ C2+ Cb) to C1 (Cb + C2)/ Cb ~ C1 C2/ Cb for the case Cb « C2 and Cb « C1,which corresponds to a scaling factor of C1 C2/( Cb (C1+ C2)). In this design,C1=C2=50pF, and Cb=0.25pF, which results in a scaling factor of 100 and aneffective capacitor of 10nF with only 100pF capacitors.

In addition, a dual-path loop filter topology is adopted not only to further reducethe capacitors but also to enable integration capacitor scaling without affectingthe zero frequency and the phase margin. Two parallel varactors are incorporated into VCO to combine the dual paths. Figure 25.6.1 shows the PLLopen-loop transfer function and the combined dual-path loop filter transfer function. Unlike active loop filters whose noise contribution from active devicesincreases with the scaling factor [3], the proposed passive scaling technique haslower noise and achieves larger scaling factor.

For the proposed passive scaling, since Cb blocks the DC current, if there is anyleakage current flowing through node VVCO1, the output voltage VCP of the chargepump would keep increasing or decreasing and finally become saturated, makingthe PLL unstable. To solve the problem, a DC control circuit is implemented asshown in Fig. 25.6.2, which consists of two comparators to detect the chargepump output voltage VCP, two D flip-flops with the PLL reference as the clock toload the comparator outputs, and two current sources ICP and IVCO1 to set VCP. Theworking mechanism of the DC control circuit is shown in Fig. 25.6.2. When VCP

<VL, the DC control current source ICP is turned on to charge C1 during time duration td, and VCP is increased to V1 to prevent the charge pump from being

saturated. Another current source IVCO1 is added to compensate the charging current to keep the control voltage VVCO1 unchanged. After td, the DC control circuit is turned off, and VCP and VVCO1 remain constant. When VL<VCP<VH, the DCcontrol circuit is turned off for normal operation and does not affect the PLL output phase noise. Finally, for VCP>VH, ICP is turned on to discharge C1 duringtime duration td, and VCP is decreased to V3. At the same time, IVCO1 is enabled tocompensate the discharging current to maintain the same control voltage VVCO1.After td, the DC control circuit is turned off, and VCP and VVCO1 stay constant.Since the control voltage VVCO1 is kept constant for all values of VCP, the PLLtransfer function would not be affected by the DC control circuit. For the DC control circuit to work well, it is necessary that the ratio of the two currents ICP

and IVCO1 is designed to be the same as the scaling factor, which is limited dueto the matching requirement and thus limits the maximum achievable scalingfactor for the loop filter’s capacitor.

Figure 25.6.3 shows the proposed mixer-based balanced differential-in quadrature-out injection-locked frequency tripler (ILFM3). A push-push injection-locked frequency doubler (ILFM2) with balun is implemented to generate differential outputs at double frequency, which are divided down byinjection-locked frequency dividers (ILFDs) to obtain quadrature signals. Thetriple frequency is generated by mixing the ILFD output with the ILFM2 outputand fed into injection-locked oscillators (ILOs). Because of process variation andinaccurate modeling, the locking range of ILFM3 has to be wide enough to coverthe desired frequencies with sufficient margins. Compared to the conventionalsolution with a hard limiter whose maximum 3rd-harmonic generation efficiencyis only 4/(3π) (~42%), the mixer-based scheme can achieve efficiency of 8/π2

(~81%) and thus larger locking range. Moreover, the hard limiter not only needsquadrature input but also has an output IQ mismatch at 3fo being triple that ofthe input I/Q mismatch at fo. In contrast, the proposed technique avoids a needfor a quadrature VCO and enables the output IQ mismatches at 3fo to be almostthe same with the IQ mismatches at the ILFD output at fo. Unlike the injection-locked frequency tripler in [1], which only provides differential injectionto a quadrature oscillator, this scheme has small frequency-independent phaseerror because the injection to the frequency tripler ILFM3 is symmetrical for bothI and Q paths. As shown in Fig. 25.6.3, the switched transformer is employed inthe ILFM2 and ILO to further extend the locking range by creating multiple frequency bands.

The PLL was fabricated in a CMOS 65nm GP process and consumes 54.5mW.The fundamental PLL consumes 31.2mW at 1.2V (24mW for VCO, 2.4mW forCML, 0.5mW for programmable divider, and 4.2mW for charge pump and DCcontrol circuit) while the ILFM3 consumes 23.3mW at 1V. The fundamental PLLfrequency tuning range is measured from 23.5GHz to 30.5GHz. The ILFM3 locking range is measured from 59.25GHz to 85.5GHz with 0dBm input power.With a frequency tuning step of 0.5GHz, the PLL covers the whole frequencyrange from 71 to 86GHz for ten 1GHz channels and two 5GHz channels. Asshown in Fig. 25.6.4, the PLL output phase noise at 1MHz offset is measured tobe -94.6dBc/Hz at 73.5GHz. Figure 25.6.5 shows the measured PLL frequencyspectrum with a 50KHz effective loop bandwidth. The sideband rejection ratiocontributed by the IQ amplitude and phase errors is -35dBc, and the fundamentalPLL reference spur is around -45dBc. Figure 25.6.6 summarizes and comparesthe performance with existing state-of-the-art PLLs. The proposed passive scaling technique increases the effective capacitor in the loop filter by 100 timeswhile the active scaling technique only achieves 4 times scaling. Moreover,thanks to the proposed ILFM3, the proposed PLL has wider frequency tuningrange than [2] and can satisfy the frequency tuning range requirement for 71-to-86GHz E-band applications. Figure 25.6.7 shows the PLL die micrograph. ThePLL occupies 0.6mm2 core chip area with only 0.12mm2 for the loop filter evenwith 50kHz loop bandwidth and 10nF effective integrator capacitor.

Acknowledgments:This work was supported in part by the Hong Kong Innovation and TechnologyFund (ITF) under the Project No. ITS/119/13FP.

References: [1] A. Musa, et al., “A Low Phase Noise Quadrature Injection Locked FrequencySynthesizer for mm-Wave Applications,” IEEE J. Solid-State Circuits, vol. 46, pp.2635-2649, Nov. 2011.[2] J. Lee, et al., “A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology,”IEEE J. Solid-State Circuits, vol. 43, pp. 1414-1426, June 2008.[3] B. Catli, et al., “A Sub-200 fs RMS Jitter Capacitor Multiplier Loop FilterBased PLL in 28nm CMOS for High-Speed Serial Communication Applications,”IEEE Custom Integrated Circuits Conf., Sept. 2013.[4] W. Wu, et al., “A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLLin 65nm CMOS,” ISSCC Dig. Tech. Papers, pp. 352-353, Feb. 2013.

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Figure 25.6.1: Block diagram of the proposed E-band PLL with a dual-pathloop filter and capacitor passive scaling.

Figure 25.6.2: Block diagram and working mechanism of the proposed DC control circuit for the passive-scaling dual-path loop filter

Figure 25.6.3: The implementation of the proposed balanced differential-inputquadrature-output frequency-tripler ILFM3.

Figure 25.6.5: Measured PLL output spectrum at 73.5GHz.Figure 25.6.6: Measurement summary and comparison with existing state-of-the-art PLLs.

Figure 25.6.4: Measured output phase noise at 1MHz offset vs frequency.

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25.7 A 2.4GHz 4mW Inductorless RF Synthesizer

Long Kong, Behzad Razavi

University of California, Los Angeles, CA

Recent developments in RF receiver design have eliminated all on-chip inductorsexcept for that used in the local oscillator. This paper addresses this “last inductor” problem and proposes an integer-N synthesizer architecture thatachieves a phase noise and a figure of merit (FOM) comparable to those of LC-VCO-based realizations.

The use of ring oscillators instead of LC implementations offers numerousadvantages: smaller area, much less coupling to and from other circuits, a muchwider tuning range, straightforward generation of multiple phases, and the abilityto multiplex several small rings so as to cover multiple bands with minimal areapenalty. However, the far inferior FOM of rings has discouraged their use in RFsynthesis. The loop bandwidth of traditional type-II PLLs is bounded by“Gardner’s limit” to fREF/10, and typically less than fREF/20 to suppress the reference spurs, thus failing to reduce the ring phase noise sufficiently.

The PLL architecture introduced here avoids Gardner’s limit, achieving a loopbandwidth of approximately fREF/2, and hence substantial reduction of the VCOphase noise. Shown in Fig. 25.7.1, the type-I synthesizer incorporates an XORgate as a phase detector (PD), a master-slave sampling filter (MSSF), a programmable harmonic trap, a three-stage ring VCO, and a pulse-swallow feedback divider. The divider employs a new topology to allow a wide divideratio, from 7 to 220, and hence operation with five octaves of VCO frequencyrange.

While the XOR PD is reminiscent of early type-I PLLs, it is the MSSF that accordsthis architecture two new properties. First, this filter transfer function exhibitsnotches at harmonics of the sampling frequency (= fREF in the locked condition),considerably attenuating the large disturbance produced by the XOR. This property vanishes in traditional type-I PLLs due to their use of a continuous-timefilter after the XOR. Second, the MSSF is clocked by the feedback signal, therebyproviding a bandwidth roughly equal to (C1/C2)(fVCO/N)/(2π). Since the filterbandwidth scales with the VCO frequency, the synthesizer achieves a wide capture range (which is ultimately limited by the VCO). Absent in traditional type-I PLLs, this property obviates the need for a frequency detection loop.

The above properties distinguish the MSSF from the sampling loop filters usedin [1] and [2], which employ a single sampler and are driven by PFD pulsesrather than by the feedback signal. Another important attribute of the proposedsynthesizer is that it eliminates the charge pump and its low-voltage design difficulties. While the ratio of C1 and C2 determines the loop bandwidth, the valueof C2 also plays a role in the performance; C2 (= 2pF) is chosen so that(kT/C2)/fREF contributes negligibly to the in-band phase noise as it is multipliedby N2/KPD

2.

In the presence of a ground bond-wire inductance in series with C1, the transientcurrent delivered by the XOR creates additional ripple on both C1 and C2, an errorthat is not removed by the nominal notch of the MSSF. To address this issue, thesynthesizer employs a “harmonic trap”, i.e., an impedance that approximates ashort circuit at fREF and 2fREF. The trap resonance frequencies are digitally tuned;a Δ-modulator monitors the ripple on the VCO control line and its output is full-wave rectified in the digital domain before adjusting the trap coefficients soas to minimize the ripple amplitude. The harmonic trap must exhibit a relativelysharp resonance so that it contributes both negligible phase shift and negligiblenoise at frequencies below fREF/2.

Figure 25.7.2 shows the ring oscillator implementation. According to extensivesimulations of various tuning mechanisms, varactor tuning poses the leastphase-noise penalty, a point evidently not previously recognized. The transistordimensions (W/L = 36μm/0.28μm for both NMOS and PMOS devices) are chosen so as to reduce their flicker noise to the point where the phase-lockedphase noise beyond a few hundred kilohertz offset is dominated by white noise.The free-running 2.4GHz VCO produces a phase noise of -121dBc/Hz at 10MHzoffset while consuming 3.1mW power.

The proposed architecture utilizes a Δ-modulator as a fast, low-power, and compact digitizer with an oversampling ratio of 30. Shown in Fig. 25.7.2, themodulator consists of a StrongArm comparator controlling a 1b DAC thatreturns a swing of ±ΔV around the input CM level, VCM. In contrast to conventional Δ-modulators, which return the entire output digital swing, thisimplementation saves considerable area for CD, for a given sensitivity. With ΔV = 25mV, CD is shrunk by a factor of 1V/50mV = 20. The Δ-modulator consumes 150uW.

The harmonic trap consists of two individual series-resonance branches at fREF

and 2fREF. Figure 25.7.3 depicts the implementation of one branch. Here, Gm1 andGm2 form a gyrator, rotating CL to create at X an equivalent inductance ofCL/(Gm1Gm2) = 70.8uH, which resonates with CS at fREF. The resonance frequencyis adjusted by a digitally controlled Gm2. With a Q of 15, this circuit requires sufficiently fine tuning steps, hence the need for a coarse control (the tail currents) and a fine control (the degeneration resistance).

The integer-N synthesizer has been fabricated in TSMC 45nm digital CMOS technology. Shown in Fig. 25.7.7 is the die micrograph, whose active area measures 100um × 150um. The prototype has been tested with a 1V supply andoperates from 2GHz to 3GHz, consuming 4mW at 2.4GHz. Plotted in Fig. 25.7.4,the measured phase noise reaches -114dBc/Hz within the loop bandwidth;Figure 25.7.5 shows the measured output spectrum with the harmonic trapsturned off and on. The 1st-order spur falls from -47dBc to -65dBc, and the 2nd-order spur from -55dBc to -68.5dBc. Integrated from 1kHz to 200MHz, theintegrated jitter is equal to 0.97psrms. These results far exceed the specificationsof wireless standards at 2.4GHz.

Figure 25.7.6 summarizes the performance of recently-reported synthesizers inthe frequency range of 2.3GHz to 3.1GHz. We note that the proposed designachieves, with a lower power, 16-to-20dB lower phase noise than do ring-basedtopologies. If adjusted for the 2X difference in reference frequencies, our designalso has a comparable phase noise to that of the LC-VCO-based PLL in [5] butat one-fourth of the power.

Acknowledgements:This research was supported by the Qualcomm Innovation Fellowship Programand Realtek Semiconductor. The authors are grateful to the TSMC UniversityShuttle Program for chip fabrication.

References:[1] S. E. Meninger et al., “A 1-MHz Bandwidth 3.6GHz 0.18-um CMOSFractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for ReducedBroadband Phase Noise.,” IEEE J. Solid-State Circuits, vol. 41, pp. 966-980,April 2006. [2] K. J. Wang et al., “Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL,” IEEE J. Solid-State Circuits, vol. 43, pp.2787-2797, Dec. 2008. [3] A. Sai et al., “A Digitally Stabilized Type-III PLL Using Ring VCO with1.01psrms Integrated Jitter in 65nm CMOS”, ISSCC Dig. Tech. Papers, pp. 248-249, Feb. 2012.[4] Y. C. Huang et al., “A 2.4GHz ADPLL with Digital-Regulated Supply-Noise-Insensitive and Temperature-Self-Compensated Ring DCO,” ISSCC Dig. Tech.Papers, pp. 270-271, Feb. 2014[5] P. C. Huang et al., “A 2.3GHz Fractional-N Dividerless Phase-Locked-Loopwith -112dBc/Hz In-Band Phase Noise,” ISSCC Dig. Tech. Papers, pp. 362-363,Feb. 2014.

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Figure 25.7.1: Proposed type-I synthesizer architecture. Figure 25.7.2: Ring oscillator and Δ-modulator implementations.

Figure 25.7.3: Implementation of one branch of the harmonic trap.

Figure 25.7.5: Measured output spectrum with harmonic traps turned off (top)and turned on (bottom). Figure 25.7.6: Performance summary and comparison with state-of-the-art.

Figure 25.7.4: Measured phase noise.

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25.8 A 2.4GHz VCO with FOM of 190dBc/Hz at 10kHz-to-2MHz Offset Frequencies in 0.13μm CMOS Using an ISF Manipulation Technique

Ali Mostajeran1,2, Mehrdad Sharif Bakhtiar1, Ehsan Afshari2

1Sharif University of Technology, Tehran, Iran, 2Cornell University, Ithaca, NY

For the last few decades, phase-noise (PN) improvement of VCOs has been anintriguing problem and remains as one of the challenges in transceiver design.PN in CMOS VCOs, especially close-in PN, greatly suffers from flicker noise. Theflicker noise can even degrade the PN at higher offset frequencies (~1MHz). Theclose-in PN is important in many communication applications. For instance, IEEE802.11a/b/g requires a very low PN at 10kHz offset frequency [1] and the PNperformance at 100kHz is critical in cellular and Wi-Fi MIMO applications. Inaddition to the PN performance, oscillators with lower power consumption andsmaller area are always on demand.

In conventional cross-coupled VCOs, the tail transistor has a large contributionto the PN, especially at close-in offset frequencies [2]. Many efforts have beenmade to suppress the tail noise. In [2], a trap is placed at the drain of the tailtransistor to block the tail noise around the second harmonic of the oscillationfrequency. This requires an extra inductor and also does not considerablydecrease the contribution of the flicker noise. In the Class-D VCO in [3], thoughthe tail transistor is removed, the PN is greatly affected by the flicker noise sincethe main transistor flicker noise is directly injected to the tank. Moreover, theoutput spur level is degraded. To the best of our knowledge, no specific methodto decrease the tail flicker noise is presented in the literature.

We use the Impulse Sensitivity Function (ISF) concept [4] to manipulate a cross-coupled oscillator and design a 2.4GHz VCO with a PN of -88.7dBc/Hz and-128.4dBc/Hz at 10kHz and 1MHz offset frequencies respectively, with no morepower consumption and area overhead. The proposed structure almost completely eliminates flicker noise contribution to the PN above 10kHz offset frequencies. To explain the proposed oscillator, let us consider the tail ISF (Γtail)waveform of a conventional cross-coupled oscillator in Fig. 25.8.1 (In this paperthe output voltage is considered as Acos(ϕ) where ϕ = ωot). ISF of a noisesource shows the sensitivity of output phase variation to the noise injection timein a period. Since the tail noise is stationary, its noise modulation function (NMF,α) is almost equal to 1. Hence, the effective tail ISF is almost the same as its ISF,[4] (Γtail,eff = Γtail × αtail ≃ Γtail). In order to improve PN, we need to lower the Γtail,eff

by manipulating both αtail and Γtail. In what follows we present a technique tolower both of these parameters.

To minimize Γtail,eff, we make αtail almost zero when the corresponding Γtail islarge. This can be achieved by turning off the tail transistor at the peaks of Γtail.Considering the Γtail waveform, switching off should be done at least twice ineach period. This is challenging as it requires extraction of second harmonic withproper phase shift which is not very efficient and reliable at RF frequencies. Abetter solution is to use two split current sources at the tail and switch them separately with a frequency of f0 (oscillation frequency). We can also separatethe two transistors, to individually turn on and off each branch. Schematic of thenew cross-coupled oscillator with a cyclo-stationary tail is shown in Fig. 25.8.2.Network, RC1, connects the gates of driver transistors to the output of the oscillator. Based on the oscillation frequency and the values of R and C1, one cancontrol the switching time to minimize αtail.

Next, we make Γtail smaller. As shown in Fig. 25.8.1, the tail noise has two different paths to flow. The first is through M1 (M2) to the output, which resultsin PN and the second path is through M3 to ground. The tail noise mostly tendsto flow in the first path since the impedance seen from source of M1 (M2) ismuch smaller than the drain of M3. To prevent the tail noise from flowing to theoutput, we create a low impedance path to the ground at the tail. This means thetail noise can directly be diverted to ground. Basically with a fixed noise powerat the tail, a smaller portion of it flows to the output, which means the outputphase is less sensitive to injection of a specific amount of noise power at the tail.This means the Γtail amplitude becomes smaller. As shown in Fig. 25.8.2, we cancreate a low impedance path to ground at the tail by replacing the tail transistorswith PMOS devices. Γtail of the proposed structure is shown in Fig. 25.8.2. Γtail,eff

of the proposed structure is compared with a conventional one in Fig. 25.8.3. Asshown, by manipulating ISF and NMF, the RMS value of Γtail,eff is significantlyreduced which results in much smaller contribution of tail noise to the PN.

In this structure we expect a great improvement of the PN at all offset frequencies. But there are three mechanisms that specifically improve the PN atclose-in offset frequencies: (i) Based on ISF theory [4], the nth Fourier seriescoefficient of ISF (cn) represents how much noise around the nth-harmonic ofoscillation contributes to the PN. So c0 represents the contribution of flickernoise to the PN. Based on Fourier series coefficients of Γtail,eff in Fig. 25.8.3, c0is much smaller in the proposed structure. The reason is that there is a lowimpedance path to the ground even at very low frequencies, which directlydiverts the flicker noise to the ground. (ii) Switching transistors on and off greatly helps with flicker noise suppression [5]. Basically the trap mechanismsthat cause flicker noise in CMOS are greatly suppressed by switching the deviceon and off. (iii) The PMOS transistors at the tail have lower flicker noise.

The contribution of the main transistor noise to the PN is also reduced.Considering the main transistor ISF (ΓM1) in Fig. 25.8.4, ΓM1 of the proposedstructure is much smaller than that of the conventional one. In the conventionalstructure, during current transitions the impedance at the common node of themain transistors is very small (almost ground) so noise of M1 directly injects tothe tank and its ISF is large. However, in the proposed structure the impedanceat the source of M1 is larger during transition times so we expect smaller ΓM1

during transitions. On the other hand, in the conventional topology when the tailcurrent is completely switched to one side, the corresponding main transistor issource degenerated and its noise circulates in the transistor and does not injectto the tank. So, ΓM1 is very small when M1 is completely on. In the proposedstructure the degeneration is still high enough during this time, which makes thenoise injection of M1 negligible. As shown, simulation of ΓM1 for both structuresalso verifies this claim.

A prototype of the proposed structure was fabricated in a 0.13μm CMOS processwith a center frequency of 2.4GHz. The inductor size is 2.1nH with a quality factor of 13. One pair of 200fF MOS varactors is used for fine frequency tuning.The VCO consumes 4.2mW from a 1.4V power supply. A reference conventionalcross-coupled VCO with the same center frequency and power consumption hasbeen implemented with constraint of best PN performance. Die sizes of bothVCOs are the same and each one is 0.27mm×0.34mm. The proposed structureis biased in Class-A, so there is no startup issue and the startup time can bemuch faster than Class-C oscillators. The bias network is designed to be independent of power supply and process variations as shown in Fig. 25.8.2.

PN is measured using an R&S FSU26 spectrum analyzer. A representative PNmeasurement for the proposed and conventional structures is shown in Fig.25.8.5. PN measurement beyond 2MHz is limited by the noise floor of the bufferand measurement equipment. According to measurement results an improvement of 8.2dB at 1MHz and 17dB at 10kHz offset frequencies isachieved. The proposed structure shows a decent FOM of -189.8dBc/Hz at 1MHzand a state-of-the-art FOM of -190.1dBc/Hz at 10kHz offset frequency. The PNvariation of the proposed and conventional VCOs vs. tuning voltage is shown inFig. 25.8.6. As measurements show, PN variation at close-in offset frequenciesis much smaller in the proposed structure. A performance comparison of measurement results with state-of-the-art CMOS VCOs is given in Fig. 25.8.6. Amicrograph of the fabricated VCOs is shown in Fig. 25.8.7.

Acknowledgement:We acknowledge the Army Research Lab for their support andSTMicroelectronics for silicon donation.

References:[1] D. Huang, et al, “A frequency synthesizer with optimally coupled QVCO andharmonic-rejection SSBmixer for multi-standard wireless receiver,” IEEE J.Solid-state Circuits, vol. 46, no. 6, pp. 1307-1320, June 2011.[2] E. Hegazi, et al, “A filtering technique to lower LC oscillator phase noise,”IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.[3] L. Fanori, P. Andreani. “A 2.5-to-3.3 GHz CMOS Class-D VCO,” ISSCC Dig.Tech. Papers, pp. 346-347. IEEE, Feb. 2013.[4] T. Lee, A. Hajimiri, “Oscillator Phase Noise: A Tutorial,” IEEE J. Solid-stateCircuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.[5] E. Klumperink, et al, “Reducing MOSFET 1/f noise and power consumptionby switched biasing,” IEEE J. Solid-State Circuits, vol. 35, no.7, pp. 994-1001,July 2000.

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Figure 25.8.1: A conventional cross-coupled oscillator and the tail noise paths(left); Output voltage, ISF, NMF, and effective ISF of the tail transistor (right).

Figure 25.8.2: The proposed structure and the biasing circuit (left); ISF, NMF,and effective ISF of the tail transistors (M3 and M4), (right).

Figure 25.8.3: Effective ISF waveform comparison of the tail transistors in theproposed and conventional structures (top); Fourier series coefficients of thecorresponding tail effective ISFs (bottom).

Figure 25.8.5: A phase-noise measurement of the proposed and conventionalcross-coupled oscillators.

Figure 25.8.6: Phase-noise variation of the proposed and conventional structures vs. tuning voltage (top); Performance comparison of the proposedstructure with state-of-the-art CMOS VCOs (bottom).

Figure 25.8.4: Main transistor ISF and normalized main transistor current(NMF) of the proposed and conventional structures.

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Figure 25.8.7: The die micrograph of the fabricated oscillators.



25.9 A ±3ppm 1.1mW FBAR Frequency Reference with 750MHz Output and 750mV Supply

Kannan A. Sankaragomathi1, Jabeom Koo1, Richard Ruby2, Brian P. Otis1

1University of Washington, Seattle, WA, 2Avago Technologies, San Jose, CA

Multiple emerging wireless applications (body-worn devices and IoT, for example) will demand previously impossible thin-film form factors and low system cost. One key enabling technology for this paradigm is a new class ofradios that offer cost/size approaching RFID while still maintaining peer-to-peer connectivity like more complex radios. These radios need to be cheap and thin,which means they should be fabricated using wafer-scale semiconductor processing. The existing paradigm (quartz crystals used as a frequency reference in radios) is a huge bottleneck in reducing cost and size of thesedevices. MEMS frequency references have replaced quartz crystals in someapplications [1-3]. For example, [1] reports a MEMS reference with 0.5ppm stability but the power consumption (~100mW) and supply voltage (1.8V) arenot suitable for low-voltage/low-power radios. [2] reports a 32kHz, 3ppm reference for mobile time-keeping applications, but is unsuitable for radio frequency synthesis due to its low output frequency. In this paper, we report athin-Film Bulk-Acoustic-Resonator (FBAR) frequency reference suitable for low-voltage/low-power radio applications. The reported FBAR reference achievesa stability of +/- 3ppm from 0 to 90C. We achieve this by using an electronic temperature compensation scheme to improve the intrinsic +/-50ppm stability ofan FBAR oscillator down to +/- 3ppm (Fig. 25.9.1). The core of the temperaturecompensation scheme is a temperature sensor that achieves a 1.75mK resolution at a 100mS sampling time.

Figure 25.9.1 shows the block diagram of the FBAR frequency reference.Transistors MP1 and MN1 form a Pierce oscillator. The oscillator in this workoperates at 750MHz, but the frequency can be changed to any frequency(>500MHz & <10GHz) at design time by using an appropriate FBAR. The oscillator operates from a 650mV regulated supply voltage generated using alow voltage bandgap reference and an LDO. A 6b thermometric MIM cap arrayis used to stabilize the oscillator frequency to the targeted value. The cap arrayhas a tuning range of 300ppm; sufficient to correct the frequency for temperature and process variations. The raw tuning resolution of the cap arrayis ~ 5ppm, and a 2nd-order ΔΣ modulator runs from a divided-by-4 clock anddithers the cap array, improving the resolution to <5ppb. A thermometric caparray and top-bit-dithering (dithering is dynamically pointed at the last bit in thearray) provide a monotonic frequency tuning without any abrupt frequencyjumps. A 0.75V digital temperature sensor generates a 19b word proportional toabsolute temperature. A calibrated polynomial computation engine (supports upto a 4th-order polynomial) converts the temperature sensor output to an appropriate frequency control word to stabilize the oscillator. A one-time calibration is needed to estimate the coefficients of the polynomial generator.The temperature sensor that forms the core of the temperature compensationscheme is described in detail below.

We introduce a new temperature sensor architecture that is motivated by the factthat the FBAR oscillator provides a very-high-quality (low-noise, low-drift) timereference. The 750MHz oscillator output is divided to lower frequencies to runthe ΔΣ modulator and the digital computation engine. These existing dividedclocks give us a very precise time domain DAC which is exploited to achieve alow-voltage operation. Figure 25.9.2 explains the basic principle of the temperature-sensing scheme. A Wheatstone bridge is constructed using twotypes of resistors RP (N-well) and RM (p-poly). RP has a positive temperaturecoefficient i.e RP = RP0(1 + αT) while RM has a negative temperature coefficienti.e. RM = RM0(1 - βT). RM is split into a fixed component RM,fixed and a variablecomponent RM,var whose average value is controlled by the duty cycle of CLKC. Afeedback loop using a zoom-ADC adjusts the average duty cycle, d of CLKC toensure a balanced bridge. The duty cycle under this condition is given by

This mechanism encodes the temperature in the time domain enabling us to fullyexploit the available accurate time reference and to achieve a low voltage opera-tion. A 10b digital-to-duty-cycle converter (DDC) uses divided clocks from theclean oscillator to generate CLKC with a 200kHz frequency and a variable dutycycle (see Fig. 25.9.3). The DDC, together with an integrator and comparatorforms a zoom ADC.

The zoom ADC operates in two phases: a SAR phase and a ΔΣ phase. In the SARphase the feedback loop digitizes d to a 7b coarse value and bounds its valuebetween two levels: dref1 and dref2. Then, the loop is rearranged to form a first-order ΔΣ loop that dithers the DDC control between dref1 and dref2, obtaininga finer 19b digital estimate of d. After offset and scaling, d provides the requiredambient temperature measurement. The integrator used in the zoom ADC isshown in Fig. 25.9.3 [5]. The integrator uses chopping to remove 1/f noise. Thezoom operation relaxes the swing required across the integrator to within100mV, leaving ~600mV headroom for the 4-transistor stack. All biases usebandgap-referenced feedback loops to ensure 150mV Vds for all transistorsacross process and temperature.

The FBAR frequency reference was fabricated in a 65nm TSMC process. Figure25.9.4 (top) shows the temperature stability of the compensated FBAR referencemeasured from 3 different chips. The oscillator achieves a stability of +/- 3ppmacross 0 to 90C. Figure 25.9.4 (bottom) shows the phase noise of the oscillatorwith and without the temperature compensation turned on. There is no significant phase noise degradation due to the temperature sensor or the ΔΣmodulator. Spurs present in the spectrum are due to on-chip 24kHz logic and a32× serializer running at 738kHz. In this chip 24kHz was used due to legacy reasons. In future iterations the logic clock frequency can be reduced to 10Hzpushing the spurs below the noise floor. The temperature-compensated frequency reference achieves an Allan deviation of 8ppb at a 100mS integrationtime which is competitive with current MEMS frequency references. The reported FBAR frequency reference consumes a total power of 1.1mW from a0.75V supply. The oscillator consumes 450μW, the temperature sensor consumes 15μW, and the rest is consumed by the buffers, dividers, ΔΣ modulator and the digital polynomial generator. Figure 25.9.5 presents measured results for the temperature sensor from a sample of 3 chips. After a4-point calibration, the temperature sensor achieves an accuracy of 0.2°C, sufficient to achieve a frequency stability of ±3ppm. The temperature sensorachieves a resolution of 1.75mK with a sampling time of 100ms. This corresponds to a resolution FOM of 4.6pJK2. (excluding power of the shaded digital blocks in Fig. 25.9.2 for fair comparison with previous works). This is a3× improvement over the state-of-the-art sub-1V temperature sensor presentedin [4] and is comparable to the state-of-the-art high-voltage temperature sensordescribed in [6]. Figure 25.9.5 (top) shows the frequency of the oscillator overa span of 11 hours. Figure 25.9.6 compares the reported temperature sensor tostate-of-the-art temperature sensors, and also compares the FBAR frequencyreference to other MEMS and quartz references. In contrast to previously reported MEMS references, this work presents an RF frequency reference withsufficient stability (+/-3ppm) and power (1.1mW) suitable for quartz-free standards-based wireless transceivers.

References:[1] Perrort. et. al. “A Temperature to digital converter for a MEMS based programmable oscillator with +/- 0.5 ppm stability and < 1ps jitter”, IEEEJ. Solid-State Circuits, vol.48, no.1, pp.276-291, Jan. 2013. [2] Asl et. al, “A 1.55x0.85mm2 3ppm 1.0μA 32.768kHz MEMS-BasedOscillator”, ISSCC Dig. Tech. Papers, pp. 226-227, Feb. 2014.[3] Wang. et. al, “A 1.8mW PLL-Free Channelized 2.4 GHz ZigBee Receiver UsingF Fixed LO Temperature-Compensated FBAR Resonator”, ISSCC Dig. Tech.Papers, pp. 372-373, Feb. 2014.[4] Souri et. al, “A 0.85V 600nW all CMOS Temperature Sensor with anInaccuracy of +/- 0.4C from -40 to 125C”, ISSCC Dig. Tech. Papers, pp. 222-223,Feb. 2014.[5] Shahmohammadi et. al, “A resistor based temperature sensor for MEMS frequency references,” European Solid-State Circuits Conference, ( ESSCIRC),pp. 225-228, Sept. 2013. [6] Heidary et. al, “A BJT-Based CMOS Temperature Sensor with a 3.6 pJK2

Resolution FOM”, ISSCC Dig. Tech. Papers, pp. 224-225, Feb. 2014.[7] TXC datasheet available online ‘www.txccrystal.com/images/pdf/8p.pdf’.

978-1-4799-6224-2/15/$31.00 ©2015 IEEE



Figure 25.9.1: Architecture of the FBAR frequency reference. Figure 25.9.2: Principle and architecture of the temperature sensor.

Figure 25.9.3: Integrator and the digital to duty cycle converter(box) used inthe Zoom ADC.

Figure 25.9.5: Measured frequency of the FBAR reference for 11 hours andmeasured error of temperature sensor (3 chips). Figure 25.9.6: Performance summary and comparison table.

Figure 25.9.4: Measured frequency drift across temperature (3 chips) andphase noise of the FBAR reference.

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Figure 25.9.7: Assembly of CMOS chip with FBAR die.

session 25 overview: rf frequency generation from ghz to thz

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