session seven
TRANSCRIPT
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Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud
Version 02 – October 2011
Session 7
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- Structural Description
- Generic Statements
- Packages
- Generate Statements
-For Generate
7 Contents
2
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Session 7
Structural description
3
the main objective here is to link
between many blocks to get
general block.
Block_1
Block_2
Block_3
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Structural description allows having multiple levels of
hierarchy in the design
Top- Down Design
define general block that has general
inputs and outputs after that we can write
the collection of the mini blocks inside it.
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Structural Description
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1) Component declaration
component <component_name>
port ( <port_names>: <mode> <type>;
<port_names>: <mode> <type>;
.
.
.
);
end component;
Session 7
Structural Description
5
Note that the definition of the component is like the definition
of the entity
Think as Hardware
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2) Component instantiation and Interconnections
instance_name: component_name
port map (signal1,
signal2,…);
each signal is written in the position that describe which port it belongs to
which means that the first signal written here represent the first port in the
component
very important note:
if you needn't use special output port you can write the key word open (that
mean this port will be unconnected).
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Think as Hardware
Structural Description
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7
Session 7
Example 28
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entity test is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; f : out STD_LOGIC); end test; architecture Behavioral of test is component or_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_or : out STD_LOGIC); end component ; component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC); end component; signal sig1,sig2 : std_logic; begin u1:and_gate port map (a,b,sig1); u2:and_gate port map (c,d,sig2); u3:or_gate port map (sig1,sig2,f); end Behavioral;
Session 7
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And gate
And gate
Or gate
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2) Component instantiation and Interconnections <instance_name>: <component_name >
port map(
<port_name> => <sig_name>,
<port_name> => <sig_name>,
.
.
.
<port_name> => <sig_name>
);
very important note:
if you needn't use special output port you can write the key word open (that
mean this port will be unconnected).
Session 7
Structural Description
9
Think as Hardware
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10
Session 7
Example 29
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Entity test is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; f : out STD_LOGIC); end test; Architecture Behavioral of test is component or_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_or : out STD_LOGIC); end component ; component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC); end component; signal sig1,sig2 : std_logic;
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begin
u1:and_gate
port map (in1 => a,
in2 => b,
out_and => sig1);
u2:and_gate
port map (in1 => c,
in2 => d,
out_and => sig2);
u3:or_gate
port map (in1 => sig1,
in2 => sig2,
out_or => f);
end Behavioral;
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Session 7
lab 14
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Entity comp4 is port ( a , b : in std_logic_vector(3 downto 0); eq : out std_logic ); End comp4 ; Architecture struct of comp4 is Component xnor_2 is port ( g , f : in std_logic ; y : out std_logic ); End component ; Component and_4 is port ( in1, in2, in3, in4 : in std_logic ; out : out std_logic ); End component ; Signal x : std_logic_vector ( 3 downto 0 ) ; Begin U1 : xnor_2 port map ( a(0) , b(0) , x(0) ) ; U2 : xnor_2 port map ( a(1) , b(1) , x(1) ) ; U3 : xnor_2 port map ( a(2) , b(2) , x(2) ) ; U4 : xnor_2 port map ( a(3) , b(3) , x(3) ) ; U5 : and_4 port map ( x(0) , x(1) , x(2) , x(3) , eq ) ; End struct ;
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Session 7
Generic
Statement
14
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VHDL provides an easy way to create generic design units that can
be used several times with different properties in the design
hierarchy
Session 7
Generic Statement
15
Think as Hardware
4-bit counter
8-bit counter
N-bit counter
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generic (
<identifier>: type [:= default_value];
<identifier>: type [:= default_value])
);
Session 7
Generic declaration
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Session 7
Example 30
• Generic AND Gate
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity generic_and is
generic (N : integer := 4 );
port(A, B: in std_logic_vector (N-1 downto 0);
Z : out std_logic_vector(N-1 downto 0) );
End entity;
Architecture behave of generic_and is
Begin
Z <= A and B;
End architecture
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Session 7
Example 31
• N-Bit Full Adder
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Entity F_adder is
Generic ( N : integer := 4 );
Port (
A, B : in std_logic_vector(N-1 downto 0) ;
C_in : in std_logic ;
Sum : out std_logic_vector(N-1 downto 0);
C_out : out std_logic
) ;
End F_adder ;
Session 7
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N bit
Full Adder
A
B
Sum
C_out
C_in
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Architecture struct of f_adder is Component n_adder
Generic ( N : integer := 4 ); Port ( A, B : in std_logic_vector(N-1 downto 0) ; C_in : in std_logic ; Sum : out std_logic_vector(N-1 downto 0); C_out : out std_logic ) ; End component ; Begin U1 : n_adder generic map (8) port map ( A => acc , B => b_reg , c_in => E , sum => result , c_out => carry_out ) ; End struct
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N bit
Full Adder
A
B
Sum
C_out
C_in
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Session 7
package
22
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Instead of declaring all components can declare all components in a
PACKAGE, and INCLUDE the package once
1) This makes the top-level entity code cleaner
2) It also allows that complete package to be used by another
designer
A package can contain
1) Components
2) Functions, Procedures
3) Types, Constants
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Session 7
Example 32
• Logic circuit by using package
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package logic_circuit is
component or_gate is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
out_or : out STD_LOGIC);
end component ;
component and_gate is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
out_and : out STD_LOGIC);
end component;
constant const1: STD_LOGIC_vector (3 downto 0) := "0011"; ---const definition
end logic_circuit;
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And gate
And gate
Or gate
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.logic_circuit.all; -----definition of the package entity test is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; out1: out STD_LOGIC_vector (3 downto 0); f : out STD_LOGIC); end test; architecture Behavioral of test is signal sig1,sig2 : std_logic; begin u1:and_gate port map ( in1 => a, in2 => b, out_and => sig1); u2:and_gate port map ( in1 => c, in2 => d, out_and => sig2); u3:or_gate port map ( in1 => sig1, in2 => sig2, out_or => f);
out1<= const1; ------- const using end Behavioral;
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And gate
And gate
Or gate
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Session 7
Generate
statement
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• The generate statement simplifies description of regular design structures.
Usually it is used to specify a group of identical components using just one
component specification and repeating it using the generate mechanism.
For generate declaration :
Label : for identifier IN range GENERATE
(concurrent assignments)
.
.
. END GENERATE;
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Session 7
Example 33
• SEREIS OF XOR GATES
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ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity;
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xor_out(1) <= parity_in(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); parity_out <= xor_out(6) XOR parity_in(7);
Session 7
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xor_out(1) xor_out(2)
xor_out(3) xor_out(4)
xor_out(5) xor_out(6)
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xor_out(0) <= parity_in(0); xor_out(1) <= xor_out(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); xor_out(7) <= xor_out(6) XOR parity_in(7); parity_out <= xor_out(7);
Session 7
32
xor_out(1) xor_out(2)
xor_out(3) xor_out(4)
xor_out(5) xor_out(6) xor_out(7)
xor_out(0)
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ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE G2; parity_out <= xor_out(7); END parity_dataflow;
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Session 7
Example 34
• N- BIT REGISTER
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Session 7
35
si so
z0 z1 z2 z3 z4
reset
clock
d si d d q q q q
r r r r
clk clk clk clk
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Next Session Evaluation Test
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Questions
Session-7
37
Session 7
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Take Your Notes Print the slides and take your notes here
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Session 7
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Take Your Notes Print the slides and take your notes here
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Session 7
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See You Next Session
Session 7
40