si80xx-1kv data sheet - silicon labs

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.comRev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 13, 2021

Si80xx-1kV

1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS

Features

Applications

Description

Skyworks’ family of low-power digital isolators are CMOS devices offeringsubstantial data rate, propagation delay, power, size, reliability, andexternal BOM advantages over legacy isolation technologies. Theoperating parameters of these products remain stable across widetemperature ranges and throughout device service life for ease of designand highly uniform performance. All device versions have Schmitt triggerinputs for high noise immunity and only require VDD bypass capacitors.Data rates up to 10 Mbps are supported, and all devices achievepropagation delays of less than 65 ns. Enable inputs provide a singlepoint control for enabling and disabling output drive. Ordering optionsinclude a choice of 1kVRMS isolation ratings.

High-speed operationDC to 10 Mbps

No start-up initialization required

Wide Operating Supply Voltage3.15 – 5.5 V

Up to 1000 VRMS isolation

High electromagnetic immunity

Low power consumption (typical)2.3 mA per channel at 10 Mbps

Tri-state outputs with ENABLE

Schmitt trigger inputs

Default low output

Precise timing (typical)40 ns propagation delay20 ns pulse width distortion100 ns minimum pulse width

Transient Immunity 50 kV/µs

AEC-Q100 qualification

Wide temperature range–40 to 125 °C

RoHS-compliant packagesQSOP-16

Industrial automation systems

Medical electronics

Hybrid electric vehicles

Isolated ADC, DAC

Power inverters

Communication systems

Ordering Information:

See page 17.

Si80xx-1kV

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 2Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 13, 2021

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4. Pin Descriptions (Si8030/35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125. Pin Descriptions (Si8040/45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136. Pin Descriptions (Si8050) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147. Pin Descriptions (Si8055) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158. Pin Descriptions (Si8065) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1710. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1811. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2012. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

12.1. Top Marking (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2112.2. Top Marking Explanation (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Si80xx-1kV


1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Ambient Operating Temperature* TA –40 25 125 ºC

Supply Voltage VDD1 3.15 — 5.5 V

VDD2 3.15 — 5.5 V

*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage.

Table 2. Electrical Characteristics(VDD1 = 3.15 to 5.5 V, VDD2 = 3.15 to 5.5 V, TA = –40 to 125 ºC)

Parameter Symbol Test Condition Min Typ Max Unit

VDD Undervoltage Threshold

VDDUV+ VDD1, VDD2 rising 2.65 2.80 3.05 V

VDD Undervoltage Threshold

VDDUV– VDD1, VDD2 falling 2.2 2.50 2.75 V

VDD Undervoltage Threshold Hysteresis

VDDHYS — 270 — mV

Positive-Going Input Threshold

VT+ All inputs rising 1.4 1.6 1.9 V

Negative-Going Input Threshold

VT– All inputs falling 1.0 1.2 1.4 V

Input Hysteresis VHYS — 0.40 — V

High Level Input Voltage VIH 2.0 — — V

Low Level input voltage VIL — — 0.8 V

High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4

4.8 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Input Leakage Current IL — — ±10 µA

Output Impedance1 ZO — 50 — W

Enable Input High Current IENH VENx = VIH — 2.0 — µA

Enable Input Low Current IENL VENx = VIL — 16 — µA

Supply Current (DC)VDD1VDD2

VI = 0, 1CL = 15 pF

——

4.47.5

7.510

mAmA

Notes:1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of

the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

Si80xx-1kV

4 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.comRev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 13, 2021

Figure 1. ENABLE Timing Diagram

Supply Current (10 Mbps)VDD1VDD2

VI = 5 MHzCL = 15 pF

——

4.49.4

7.512

mAmA

Maximum Data Rate 0 — 10 Mbps

Minimum Pulse Width — — 100 ns

Propagation Delay tPHL, tPLH See Figure 2 20 40 65 ns

Pulse Width Distortion|tPLH – tPHL|

PWD See Figure 2 — 20 30 ns

Propagation Delay Skew2 tPSK(P-P) — 20 30 ns

Channel-Channel Skew tPSK — 20 30 ns

Output Rise Time tr CL = 15 pFSee Figure 2

— 2.5 4.0 ns

Output Fall Time tf CL = 15 pFSee Figure 2

— 2.5 4.0 ns

Common ModeTransient Immunity

CMTI VI = VDD or 0 VVCM = 1500 V (see Figure 3)

35 50 — kV/µs

Enable to Data Valid ten1 See Figure 1 — 10 — ns

Enable to Data Tri-State ten2 See Figure 1 — 10 — ns

Start-up Time3 tSU — 40 — µs

Table 2. Electrical Characteristics (Continued)(VDD1 = 3.15 to 5.5 V, VDD2 = 3.15 to 5.5 V, TA = –40 to 125 ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of

the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

ENABLE

OUTPUTS

ten1 ten2

Si80xx-1kV


Figure 2. Propagation Delay Timing

Figure 3. Common Mode Transient Immunity Test Circuit

Typical Input

tPLH tPHL

Typical Output

tr tf

90%

10%

90%

10%

1.4 V

1.4 V

Oscilloscope

3.15 to 5.5 VIsolated Supply

Si80xxVDD2

OUTPUT

3.15 to 5.5 VSupply

High Voltage Surge Generator

Vcm SurgeOutput

High Voltage Differential

Probe

GND2GND1

VDD1

INPUT

Input SignalSwitch

InputOutput

Isolated Ground

Si80xx-1kV


Table 3. Thermal Characteristics

Parameter Symbol QSOP-16 Unit

IC Junction-to-Air Thermal Resistance JA 105 ºC/W

Max Junction Temperature TJ 130 ºC

Table 4. Absolute Maximum Ratings1

Parameter Symbol Min Typ Max Unit

Storage Temperature2 TSTG –65 — 150 ºC

Ambient Temperature Under Bias TA –40 — 125 ºC

Junction Temperature TJ — — 150 °C

Supply Voltage VDD1, VDD2 –0.5 — 7.0 V

Input Voltage VI –0.5 — VDD + 0.5 V

Output Voltage VO –0.5 — VDD + 0.5 V

Output Current Drive Channel IO — — 22 mA

Latchup Immunity3 — — 100 V/ns

Lead Solder Temperature (10 s) — — 260 ºC

Maximum Isolation (Input to Output) (1 sec)QSOP-16

— — 1500 VRMS

Notes:1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to conditions as specified in the operational sections of this data sheet.2. VDE certifies storage temperature from –40 to 150 °C.3. Latchup immunity specification is for slew rate applied across GND1 and GND2.

Si80xx-1kV


2. Functional Description

2.1. Theory of OperationThe Si80xx comprises a transmitter and a receiver separated by a semiconductor-based isolation barrier. TheSi80xx uses a high-frequency internal oscillator on the transmitter to modulate digital input signals across thecapacitive isolation barrier. On the receiver side, these signals are demodulated back to the corresponding digitaloutput signals that are galvanically isolated from the input. This simple and elegant architecture provides a robustdata path and requires no special considerations or initialization at start-up. A simplified block diagram for anSi80xx data channel is shown in Figure 4.

Figure 4. Simplified Channel Diagram

The transmitter consists of an input stage that latches in data from up to six asynchronous channels, followed by aserializer stage where the data is compressed into serial data packets that are then coupled across the capacitiveisolation barrier. The receiver consists of a demodulator block that converts the modulated signal back into serialdata packets that are then deserialized and latched to the output.

A BInput Latch

Input Selector

TransmitterSerializer Demodulator Deserializer

Receiver

Si80xx

High FrequencyOscillator

Modulator/Packet

Encoder

Output Latch

Packet Decoder

Clock Recovery and DemodulatorIs

ola

tion

Si80xx-1kV


3. Device Operation

Device behavior during start-up, normal operation, and shutdown is shown in Figure 5, where UVLO+ and UVLO-are the positive-going and negative-going thresholds respectively. Refer to Table 5 to determine outputs whenpower supply (VDD) is not present. Additionally, refer to Table 6 for logic conditions when enable pins are used.

Table 5. Si80xx Logic Operation

VI

Input1,2

EN

Input1,2,3,4VDDI

State1,5,6VDDO

State1,5,6VO Output1,2 Comments

H H or NC P P H Enabled, normal operation.

L H or NC P P L

X7 L P P Hi-Z8 Disabled.

X7 H or NC UP P L Upon transition of VDDI from unpowered to pow-ered, VO returns to the same state as VI after Start-up Time, tSU

X7 L UP P Hi-Z8 Disabled.

X7 X7 P UP Undetermined Upon transition of VDDO from unpowered to pow-ered, VO returns to the same state as VI after Start-up Time, tSU, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to pow-ered, VO returns to Hi-Z after Start-up Time, tSU, if EN is L.

Notes:1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN

is the enable control input located on the same output side.2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si80xx is

operating in noisy environments.4. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND.5. “Powered” state (P) is defined as 3.15 V < VDD < 5.5 V. 6. “Unpowered” state (UP) is defined as VDD = 0 V.7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is

disabled (EN = 0).

Si80xx-1kV


Table 6. Enable Input Truth1

P/N EN21,2 Operation

Si8030Si8040Si8050

H Outputs B1, B2, B3, B4, B5, B6 are enabled and follow input state.

L Outputs B1, B2, B3, B4, B5, B6 are disabled and Logic Low or in high impedance state.3

Si8035Si8045Si8055Si8065

— Outputs B1, B2, B3, B4, B5, B6 are enabled and follow input state.

Notes:1. Enable, EN, can be used for multiplexing, for clock sync, or other output control. EN is internally pulled-up to local VDD

by a 16 µA current source allowing it to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN if it is left floating. If EN is unused, it is recommended that it be connected to an external logic level, especially if the Si80xx is operating in a noisy environment.

2. X = not applicable; H = Logic High; L = Logic Low.3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is

disabled (EN = 0).

Si80xx-1kV


3.1. Device StartupOutputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Followingthis, the outputs follow the states of inputs.

3.2. Undervoltage LockoutUndervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown orwhen VDD is below its specified operating circuits range. Both Side A and Side B each have their ownundervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side Aunconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises aboveVDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply. See Figure 5 for more details.

Figure 5. Device Behavior during Normal Operation

INPUT

VDD1

UVLO-

VDD2

UVLO+

UVLO-UVLO+

OUTPUT

tSTART tSTART tSTARTtPHL tPLHtSD

Si80xx-1kV


3.3. Layout RecommendationsTo ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physicallyseparated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet thosecreepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating(commonly referred to as working voltage protection). Refer to the end-system specification (61010-1, 60950-1,60601-1, etc.) requirements before starting any design that uses a digital isolator.

3.3.1. Supply Bypass

The Si80xx family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. Thecapacitor should be placed as close as possible to the package. To enhance the robustness of a design, the usermay also include resistors (50–300 ) in series with the inputs and outputs if the system is excessively noisy.

3.3.2. Output Pin Termination

The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combinationof the value of the on-chip series termination resistor and channel resistance of the output driver FET. When drivingloads where transmission line effects will be a factor, output pins should be appropriately terminated with controlledimpedance PCB traces.

3.4. Fail-Safe Operating ModeThe default output state of Si80xx devices is logic low when the output supply is powered.

Si80xx-1kV


4. Pin Descriptions (Si8030/35)

Name Pin# Type Description

VDD1 1 Supply Side 1 power supply.

GND1 2 Ground Side 1 ground.

A1 3 Digital Input Side 1 digital input.



NC* 6 NA No Connect.




EN2/NC* 10 Digital Input Side 2 active high enable on Si8030. NC on Si8035.


B3 12 Digital Output Side 2 digital output.





*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.

VDD1

GND1

A1

A3

NC

NC

GND1

A2

VDD2

GND2

B2

B1

NC

B3

GND2

EN2/NC

Isolat ion

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

Si8030/35

Si80xx-1kV


5. Pin Descriptions (Si8040/45)











EN2/NC* 10 Digital Input Side 2 active high enable on Si8040. NC on Si8045.








VDD1

GND1

A1

A3

A4

NC

GND1

A2

VDD2

GND2

B2

B1

B4

B3

GND2

EN2/NC

Isolat ion

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

Si8040/45

Si80xx-1kV


6. Pin Descriptions (Si8050)








NC* 7 NA No connect.



EN2 10 Digital Input Side 2 active high enable on Si8050.








VDD1

A1

A3

A4

NC

GND1

A2

VDD2

B2

B1

B4

B3

GND2

EN2

Isolat ion

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

Si8050

A5

RFXMITR

RFRCVR

B5

Si80xx-1kV




















VDD1

A1

A3

A4

GND1

A2

VDD2

B2

B1

B4

B3

GND2

Isolat ion

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

Si8055

A5

RFXMITR

RFRCVR

B5

GND1 GND2

Si80xx-1kV




















VDD1

A1

A3

A4

A6

GND1

A2

VDD2

B2

B1

B4

B3

GND2

B6

Isolat ion

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

RFXMITR

RFRCVR

Si8065

A5

RFXMITR

RFRCVR

B5

RFXMITR

RFRCVR

RFXMITR

RFRCVR

Si80xx-1kV


9. Ordering Guide

Table 7. Ordering Guide for Valid OPNs1,2,3

Ordering Part Number (OPN)

Number of Inputs/Outputs

Default Output State

Output Enable Yes/No

Isolation Rating (kVrms)

Package

Si803x

Si8030AA-B-IU 3 Low Yes 1 QSOP-16

Si8035AA-B-IU 3 Low No 1 QSOP-16

Si804x



Si805x



Si806x


Notes:1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard

classifications and peak solder temperatures.2. “Si” and “SI” are used interchangeably.3. Add an “R” at the end of the device to denote tape and reel option.

Si80xx-1kV


10. Package Outline: 16-Pin QSOP

Figure 6 illustrates the package details for the Si80xx in a 16-pin QSOP package. Table 8 lists the values for thedimensions shown in the illustration.

Figure 6. 16-pin QSOP Package

Si80xx-1kV


Table 8. Package Diagram Dimensions

Dimension Min Max

A — 1.75

A1 0.10 0.25

A2 1.25 —

b 0.20 0.30

c 0.17 0.25

D 4.89 BSC

E 6.00 BSC

E1 3.90 BSC

e 0.635 BSC

L 0.40 1.27

L2 0.25 BSC

h 0.25 0.50

θ 0° 8°

aaa 0.10

bbb 0.20

ccc 0.10

ddd 0.25

Notes:1. All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.

Si80xx-1kV


11. Land Pattern: 16-Pin QSOP

Figure 7 illustrates the recommended land pattern details for the Si80xx in a 16-pin QSOP package. Table 9 liststhe values for the dimensions shown in the illustration.

Figure 7. 16-Pin QSOP PCB Land Pattern

Table 9. 16-Pin QSOP Land Pattern Dimensions

Dimension Feature (mm)

C1 Pad Column Spacing 5.40

E Pad Row Pitch 0.635

X1 Pad Width 0.40

Y1 Pad Length 1.55

Notes:1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for

Density Level B (Median Land Protrusion).2. All feature sizes shown are at Maximum Material Condition (MMC) and a card

fabrication tolerance of 0.05 mm is assumed.

Si80xx-1kV


12. Top Markings

12.1. Top Marking (16-Pin QSOP)

12.2. Top Marking Explanation (16-Pin QSOP)

Line 1 Marking: Base Part Number Ordering Options

(See Ordering Guide for more information).

80 = Isolator product seriesXY = Channel Configuration

X = # of data channels (6, 5, 4, 3)Y = # of reverse channels (0)*

S = operating mode:A = default output = low

V = Insulation ratingA = 1 kV

Line 2 Marking: RTTTTT = Mfg Code Manufacturing code from assembly house“R” indicates revision

Line 3 Marking: YY = YearWW = Work Week

Assigned by the Assembly House. Corresponds to the year and work week of the mold date.

*Note: Si8035/45/55/65 have 0 reverse channels.

80XYSVRTTTTTYYWW

Si80xx-1kV


REVISION HISTORY

Revision 1.1July, 2018

Removed references to default output high option. Updated “ Features” on front page.

Updated "3. Device Operation" on page 8.

Updated "3.4. Fail-Safe Operating Mode" on page 11.

Updated "9. Ordering Guide" on page 17.

Updated "12. Top Markings" on page 21.

Revision 1.0January, 2014

Revision 0.9October, 2013

Initial revision.

Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.

No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.

THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.

Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.

Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com, are incorporated by reference.

Portfoliowww.skyworksinc.com

Qualitywww.skyworksinc.com/quality

Support & Resourceswww.skyworksinc.com/support

Connecting Everyone

and Everything,

All the Time

Skyworks Solutions, Inc. | Nasdaq: SWKS | [email protected] | www.skyworksinc.comUSA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540 |

www.skyworksinc.com

www.skyworksinc.com/quality

www.skyworksinc.com/support

si80xx-1kv data sheet - silicon labs

Documents