[sic-en-2013-3] modeling and reduction of conducted emi of inverters with sic jfets on insulated...

7/28/2019 [SiC-En-2013-3] Modeling and Reduction of Conducted EMI of Inverters With SiC JFETs on Insulated Metal Substrate

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3138 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013

Modeling and Reduction of Conducted EMIof Inverters With SiC JFETs on Insulated

Metal SubstrateXun Gong , Member, IEEE , Ivan Josifovi c , Member, IEEE , and Jan Abraham Ferreira , Fellow, IEEE

Abstract This paper presents the suppression of conductedcommon-mode (CM) electromagnetic interference (EMI) in an in-verter for motor drive with discrete silicon carbide (SiC) JFETsattached on top of the insulated metal substrate (IMS). The EMCperformance of the IMS inverter is compared with that of a heatsink inverter in a similar circuit layout. Both are under the sameinuence of parasitic capacitive couplings between the SiC JFETdrains and the substrate base plate. It is found that although theapplication of conventional CM lters effectively suppresses theemitted noise in the low-frequency (LF) range, the inuence of

this capacitive coupling results in slight or no improvement in themiddle-frequency (MF) and high-frequency (HF) ranges. To dealwith this problem, a system CM equivalent circuit model withextracted parasitic parameters is proposed. The model is able toevaluate the lter insertion losses over a broad conducted EMIfrequency band, which is essential to achieve an optimized lterdesign balanced between performance and cost. The presented ex-perimental and calculated results form the step-by-step guidelinethat effectively suppresses the generated EMI to comply with thestandard prescribed by IEC61800-3 C2: Qp.

Index Terms Common mode (CM), electromagnetic interfer-ence (EMI), insulated metal substrate (IMS), motor drive, siliconcarbide (SiC).

I. INTRODUCTION

T HE high switching speed and temperature capabilities of silicon carbide (SiC) offer many signicant performanceimprovements for the switchingdevices in power electronics[1].New SiC JFETs increase the power efciency of converters, ac-celerate the miniaturization of power electronic systems, andenable them to operate under less stringent cooling require-ments [2]. To keep pace with the resulting power density in-crease, thermal management must be enhanced due to the re-duced magnetic component surface area available for cooling.Among those thermal managements for medium power convert-

ers, implementing the insulated metal substrate (IMS) is one of the most effective methods [3], [4]. On the other hand, IMSis also well known for its susceptibility to electromagnetic in-terference (EMI). Fig. 1(a) illustrates the typical structure of

Manuscript received May 29, 2012; revised July 31, 2012; accepted Septem-ber 20, 2012. Date of current version December 24, 2012. Recommended forpublication by Associate Editor P. Tenti.

The authors are with the Electrical Power Processing Group, Department of Electrical Engineering, Mathematics, and Computer Science, Delft Universityof Technology, 2628 CD, Delft, The Netherlands (e-mail: [email protected];[email protected]; [email protected]).

Color versions of one or more of the gures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identier 10.1109/TPEL.2012.2221747

Fig. 1. (a) Construction of the IMS. (b) Photograph of the investigated IMSinverter prototype. (c) Extensive capacitive couplings created due to the imple-mentation of the discrete SiC JFETs attached on top of the IMS.

IMS. It can be seen that because of the very thin dielectric layer(typically 40180 m) placed between the circuit copper foiland the metal (typically aluminum or copper) base plate, a largeamount of stray capacitance is formed, which creates a pathclosing a loop with considerable EMI propagations especiallyfor the high-frequency (HF) noise. This effect becomes muchmore critical when the IMS is used to cool active power de-vices, especially when SiC JFETs drain plates are attached ontop as illustrated in Fig. 1(b). The capacitive couplings, togetherwith the fast switching of SiC, result in signicant degradation

to the conducted/radiated EMC performance and also to the0885-8993/$31.00 2012 IEEE


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GONG et al. : MODELING AND REDUCTION OF CONDUCTED EMI OF INVERTERS WITH SiC JFETs ON INSULATED METAL SUBSTRATE 3139

circuit operation performance [5]. As a result, costly and in-creased ltering is needed to suppress the emitted noise belowthe stringent EMI standard. This has become the main barrier tothe increase in power density.

Additionally, EMC design methods that enable EMC perfor-mance evaluation over a broad frequency band have becomethe trend and are increasingly popular these years. It is possibleto predict the EMC and prevent the situation where noise issuppressed in some frequency range but is amplied in otherfrequency range. This is especially critical when dealing withthe increased HF noise of the inverters with SiC JFETs on topof the IMS. Filter designs targeting a restricted low-frequency(LF) band may become inadequate. In the past, many EMI l-ter design methods were developed to suppress the conductedEMI [6][10]. However, most of them fail to predict EMI andrequire a trial-and-error process for a certain HF range. Forexample, a common-mode (CM) input lter design procedureis introduced in [11] for a three-phase buck-type rectier. Atwo-stage CM lter is designed to suppress the conducted EMI

to comply with the standard. However, the suppression perfor-mance beyond 10 MHz is overlooked due to the oversimplica-tion of the model. A step-by-step design procedure is proposedin [12] and proved to be effective below 1 MHz, unfortunatelybeyond that frequency, the ltering performance prediction be-gins to deviate. In [13] and [14], lters are designed according tothe noise level at the start (150 kHz) or at the frequency requir-ing maximum attenuation in the conducted frequency range.However, other frequencies are not considered. A broadbandEMI lter design has been presented in [15]; however, the smallsignal-based methods require veryprecise measurements, whichare not easily obtained.

This paper investigates and proposes an equivalent circuitmodel to suppress the conducted EMI for a SiC JFET inverterfor motor drives. The inverter is implemented with discrete SiCJFETs and their corresponding external antiparallel diodes aredirectly attached on top of the IMS copper foil, which createsextensive capacitive coupling between the power device drainand the aluminum metal plate. A comprehensive and broadbandlter design is proposed to handle this problem. First, a sim-plied equivalent circuit model is established. The CM currentwaveforms of the system are obtained from simulation to verifythe inuence of the capacitive couplings. Theconducted EMI of the IMS inverter prototype is compared with a heat sink inverterfor similar circuit layout as both are under the same inuence of parasitic capacitive couplings. Second, the proposed model isfurther developed with theextraction of all theparasitic elementsto evaluate the lter performance.Thegroup of calculated inser-tion losses shows good agreement with the measurements overa broad conducted EMI range, making the proposed model sig-nicantly better in predicting and handling the increased EMIin the HF range. Third, different lter designs are comparedwith the model and the optimal lter design that results in thebest attenuation with respect to the IMS capacitive coupling isidentied. Finally, based on the modeling results, methods tosuppress the HF EMI are proposed. The emitted EMI of theIMS inverter driven motor system is effectively suppressed to

comply with the IEC61800-3 Qp standard.

Fig. 2. Capacitive couplings in the inverter bridge leg conguration.

II. CAPACITIVE COUPLING INFLUENCE OF THE IMS A. IMS Capacitive Coupling Inuence on CM

Fig. 2 illustrates the conguration of the IMS inverter bridgeleg that shows the capacitive coupling effects. Due to the verythin dielectric layer placed between the circuit copper foil andthemetal base plate, large amountof stray capacitance is formedbetween the signal layer and the metal plate. Due to safetyreasons when the metal plate is required to be connected tothe earth, those stray capacitors create extensive EMI couplingpaths, closing loops with considerable EMI noise propagations.To illustrate the effect, a simplied CM equivalent circuit model

for the IMSinverter driven motor systemis established as shownin Fig. 3(a), where V inv is the CM noise source. R 1 , C 1 , andL 1 are the equivalent impedance of LISN, L2 is the lumpedinductance between LISN and inverter switches, Y ca p is theadded lter capacitor, Lou t is the lumped inductance betweeninverter output and motor, R sf , C w f 1 , C w f 2 , and L gf are theequivalent impedance of the motor with cables, and I g is theearthcurrent. Thecriticalelementsare L3 , C 2 , L 4 ,and C 3 whichrepresent thecreated strayelementsnetworkbetween thecircuitfoil layer and the IMS base plate. The simulated waveforms of the CM current I g with and without the stray element network are shown in Fig. 3(b). A CM capacitor (also known as Y -capacitor) is applied at the inverter input. It can be seen thatthe CM parasitic oscillations and overshoots are signicantlyincreasedunder the inuence of the stray elements network. Theoscillation frequency becomes lower because of the increasedcapacitance at the inverter output side. The elements applied inthemodelaredeterminedbased on the followingconsiderations.

The photograph of the investigated IMS inverter prototype isshown in Fig. 4(a). The SiC JFET (SJEP120R100) is packagedin TO-247 with the drain of Al back plate and the surface areaAs = 20.3

15.3 = 310.59 mm 2 . The added antiparallel diode(C2D05120A) is in TO-220 package with the cathode surfacearea Ad = 9.65 14.3 = 138.0 mm 2 . The total surface areaAs + Ad causes parasitic capacitance C dh 1 and C dh 2 (see

Fig. 2). With 0.08-mm-thick Kapton dielectric layer (r = 5)


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Fig. 3. (a) Simplied CM equivalent circuit model of the IMS inverter systemfor CM current overshoot and oscillations. (b) Comparison of the simulatedwaveforms from the model with and without the capacitive couplings.

Fig. 4. Photographs of the SiC JFET inverters. (a) IMS inverter: very thindielectric layer between the SiC JFET drain plate and the aluminum base( 80 m) . (b) Heat sink inverter: SiC JFET drain and SiC diode cathodesare insulated by thermal Sil-pads from the aluminum heat sink ( 150 m) .

C dh 2 is calculated as C dh 2 = r 0 (As + Ad ) / l = 249 pF. C dh 3is the parasitic capacitance between the dc bus and the substrate.For a heat sink inverter with a power PCB, C dh 3 is much lowerthan one with the IMS due to its larger distance between thedc bus and the substrate. The thickness of the isolation pad isinversely proportional to the parasitic capacitance. In the three-phase inverter, all the top six power devices (SiC JFETs plusSiC diodes) are at the same potential as the dc + bus voltage;therefore, they all contribute to the equivalent value of C dh 1 .According to the PWM switching technique, pulsed dv / dts ap-pear between the node of bridge-leg output phase (summed areaof SiC JFET drain and diode cathode at the low side) and thesubstrate. In the model, the total capacitance of C 2 + C 3 inthe stray element network represents the coupled capacitance

which is 6. C dh 2 = 1494 pF. The lumped inductance of the

PCB traces is directly measured with an impedance analyzer(Aglient 4294A). The rest are extracted through curve ttingof the impedance-frequency characteristics. The details can befound in [16].

B. IMS Capacitive Coupling Inuence on DM

In addition to degradationof theEMCCM performanceby in-troducing extensive noise propagation paths, the IMS capacitivecouplings also greatly deteriorate the DM EMC performance.The rst reason is the interaction within one inverter leg thatconsists of two switches. As shown in Fig. 2, when IMS baseplate is oating, the parasitic capacitors C dh 1 , C dh 2 , and C dh 3are in Y -connection. Through Y transformation, the threecapacitors are equivalently added in parallel to the switch, ap-pearing as the increased values of parasitic capacitance C j p 1and C j p 2 . As a consequence, two degradation effects are pro-duced on DM performance: 1) slow down the switching speed,which potentially leads to the increased switching losses andprolonged switching transient time; and 2) increase the cur-rent overshoot at the switching transients. When one switch isswitched ON/OFF (e.g., J 2 in Fig. 2), the parasitic capacitorC j p 1 in parallel to the opposite switch determines the overshootmagnitude. Therefore with the increased capacitance in parallelto the switch, the parasitic overshoot magnitude and oscillationsare also increased. Moreover, the shoot-through problems arepotentially induced. It must be mentioned that these capacitivecouplings also have the effect of slowing down the switchingspeed of J 1 and J 2 , and consequently decreasing the values of switching dv/dts . This could be a benet from the EMC pointof view. However, because the parasitic capacitance value isrelatively small and it is dependent on the imposed voltage, thisimpact is majorly negative.

The second reason is the noise couplings among the threeinverter legs. According to thePWMswitching technique, whenthe upper switch in one inverter leg [e.g., J 1 in Fig. 1(c)] isswitchedON,whileat themean time, the lowerswitch in anotherinverter leg [e.g., J 4 in Fig. 1(c)] is at OFF state, pulsed voltage(dv/dt ) appears between these two inverter leg output nodes.As a result, the existing parasitic capacitors between the legoutput nodes and IMS base plate form a path that propagatesthe HF noise from one node to the other. Therefore, each of thethree inverter leg output nodes acts as a noise source, which isexpressed by E 1 , E 2 , and E 3 as shown in Fig. 1(c).

C. Experiment Conguration

The EMC performance of the IMS SiC JFET inverter proto-type is compared with a heat sink SiCJFETinverter with similarlayout as shown in Fig. 4(a) and (b), respectively. The differencein their layout designs is due to the following reasons: for IMSinverter, the drain plates of the SiC JFETs are soldered on topof the IMS copper coil directly to achieve better cooling effect.Therefore, the foil traces of the dc bus are soldered togetherwith the drain/cathode plate of the semiconductors. The compo-nents are placed closer to each other. However for the heat sink inverter, the thermal Sil-pads ( 150 m) must be inserted be-

tween to provide electrical insulation; therefore, thePCBis used


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Fig. 5. Experiment congurationof theIMS andheat sink SiCJFET inverters.

Fig. 6. Comparison of measured total noise spectra between the IMS SiCJFET inverter and the heat sink SiC JFET inverter.

and placed between the upper and lower switches. Although theaforementioned differences exist, the EMI levels from the twoinverters are comparable making it possible to characterize thecapacitive coupling inuence. Because both inverter prototypes

are implemented with the same type of discrete SiC JFETs andantiparallelexternalSiC diodesin thesamepackage on topof thesubstrates, the coupling mechanism is assumed to be the same.Their experiment conguration for EMI measurement is illus-trated in Fig. 5. The two inverters are placed in the same EMCtesting environment with the same measuring equipments. Theinverters are powered by a dc power supply at 550 V dc throughan LISN (Crange VN3-100S ). A 2.2-kW induction motor as theload is driven at 50 Hz modulation frequency by programmingthe driving signal source from a DSP. The inverter and motor aregrounded to the same copper plate.TheEMC spectrum analyzeris set for 9 kHz resolution bandwidth, 18 s sweep time, and peak

detection mode for measurement convenience.

D. EMI Comparison

Fig. 6 presents the measured EMI spectra of the two invertersystems. An identical and conventional purely capacitive lter(470 nF) is placed at the input of both inverter systems. Theschematic diagram of the lter is shown in Fig. 7(a). It can beseen that the emitted noise in an IMS inverter is signicantlyhigher than that in the heat sink inverter especially in the middlefrequency (MF) range (37 MHz), which is due to the higherHF current overshoot inuenced by the extensive capacitivecouplings as modeled in Fig. 3(b). Although the LF noise is

dramatically suppressed, this inuence results in no improved

HF performance since the HF noise level is even higher thanthat of the LF range. As a result, it is crucial to suppress theincreased noise level to comply with the standard IEC61800-3C2 Qp.Therefore for theIMSinverter,the addedcapacitor that isconventionally found in thelter must be carefully designed dueto the extensive capacitive coupling inuence. In the followingsections, this impact is explained with a CM equivalent circuitmodel and the lter insertion loss calculations. The lter designthat is able to suppress this inuence is presented.

III. BROAD BAND MODELING TO PREDICT THE FILTERINSERTION LOSSES

The treatment of the crucial HF noise in the IMS inverterrequires the applied method to predict the relative noise attenu-ation performance in a broad conducted EMC range. Therefore,the situation as shown in Fig. 6 where noise is suppressed in LFrange but increases in MF and HF ranges can be predicted andavoided. In the following sections, the model shown in Fig. 3(a)

is further rened by adding detailed parasitic elements. Thegoal is to provide a broadband prediction on the lter insertionloss, thereby selecting the optimal lter design that has betterperformance while requiring less ltering components. All thefollowing experiments are performed on the IMS inverter. Thisstudy focuses only on the CM noise which plays the predomi-nant role in total EMI spectrum of motor drive system [17], [18].The DM noise is not considered.

A. Creation of the Modeling Bases

The considered CM lter topologies are illustrated in Fig. 7,which are named C , LC , LCL , and LCLC , respectively. These

topologies are chosen because they are widely adopted as theCM lter for inverter driven motor systems. Among them, theeasy-to-implement topologies C and LC are used to createmodeling bases.

The conguration with only two pairs of DM capacitors po-sitioned in the dc bus (see Fig. 5) is taken as the case withoutCM lter. The noise emitted from this conguration is denedas the noise baseline. Fig. 8 shows the required lter insertionloss which is calculated according to the difference betweenthe IEC61800-3 C2 standard and the noise baseline. The mea-sured insertion loss of the applied C (470 nF) and LC (250 H470 nF) lters for the IMS inverter is illustrated in Fig. 9. It canbe seen that noise suppression in the MF range is not sufcientand greatly degraded. This is within the expectation due to theIMS capacitive couplings as analyzed in Section III-A. The val-ues of the inductor and capacitor are selected with reference totheactualEMI ltering componentvalues from commercial mo-tor drives. Additionally, the design of the inductor value avoidssaturation of the selected core.

B. Final Model for Filter Insertion Losses

With the insertion losses from the created experimental baseswith C and LC ltersas shown inFig. 9, the model of Fig.3(a) isfurther rened into the model shown in Fig. 10 which includes

the detailed parasitic elements. The values of stray elements


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Fig. 7. Considered lter topologies: (a) C , (b) LC , (c) LCL , and (d) LCLC .

Fig. 8. Required lter insertionlosscalculated from thenoise baseline withoutlter.

network is lowered in steps to capture the resonances that occuraround 4.5 MHz according to the measured insertion losses of Fig. 9. Extraction of the elements including the lter and themotor with cables will be introduced in Section III-C. The volt-age appearing across R 1 is the emitted noise voltage measuredby the spectrum analyzer.

The calculated insertion losses of the IMS inverter with C and LC lters are illustrated in Fig. 11(a). It can be seen thatthe modeled results of Fig. 11(a) agree well with the measure-ments of Fig. 9. The rst spike at 2.5 MHz is caused by theCM intrinsic resonance of the motor with cables. The secondspike at 4.5 MHz is caused by the resonance that occurs in thestray elements network which is fundamentally caused by the

capacitive coupling inuence of the IMS inverter.

Fig. 9. Measured lter insertion losses with the implemented CM lter of C (C = 470 nF) and LC (L = 250 H , C = 470 nF).

The calculated insertion losses with applied pure C lter(470 nF) at the input of both the IMS inverter and the heat sink inverter are shown in Fig. 11(b). When calculating the insertionloss for the heat sink inverter, the stray elements network in themodel is removed. It can be seen that the main difference occursat the second spike at 4.6 MHz. Additionally, the noise magni-tude of the IMS inverter in the LF range is around 6 dB higherthan that of heat sink inverter. The results agree well with theexperimental results of Fig. 6. Therefore, the established modelis proven to be capable of evaluating the lter performance overa broad conducted frequency band. The spike at 4.5 MHz ismainly caused by the capacitive couplings and is critical for the

lter design.


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Fig. 10. Final model with extracted elements.

Fig. 11. Comparison of the modeled lter insertion losses. (a) IMS inverter with the implemented CM lter of C (470 nF) and LC (250 H, 470 nF) (b) betweenthe heat sink inverter (without stray elements network of capacitive couplings) and the IMS inverter with C (470 nF) CM lter.

Fig. 12. Elements extraction for the motor with cables based on the curve tting of the CM impedance-frequency characteristic. (a) Experiment conguration.(b) Experimental result as opposed to calculated result.

C. Elements Extraction

The elements extraction method is based on curve tting of the equivalent circuits CM impedance-frequency characteristicfor each circuit portion in the system. In addition to the straycapacitance between the circuit copper foil and the substratebase plate, the other main parasitic components are determinedas follows.

Fig. 12(a) illustrates the experimental setup to measure

the CM impedance-frequency characteristic of the motor with

cables. The Agilent 4294A impedance analyzer is used as themeasurement tool. The test pins of the analyzer are connectedto the three-phase motor terminals and the motor PE cable, re-spectively. The measured and calculated results are illustratedin Fig. 12(b). The extracted elements are L ou t , Lw f , C w f 1 , Rsf ,C w f 2 , Rgf , and L gf as shown in Fig. 10. The total CM ca-pacitance C w f 1 + C w f 2 is derived from the LF slope k1 . Thecapacitance in thecircuit parallel branchwith fewercomponents(C w f 1) determines theslope of k2 in the MFrange. The summed


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Fig. 13. Model of the applied LCL lter [L 1 = 250 H, C 1 = 400 nF, L 2 =200 H shown in Fig. 7(c)] with extracted elements.

Fig. 14. Measured inductance-frequency characteristic of a 110 nH wire withand without being clamped by the current probe.

inductance of Lou t + L w f + L g f and capacitance C w f 2 create

the resonance of rst zero point Z 1 . Rsf determines the magni-tude of Z 1 . The summed inductance of Lou t + L g f and capac-itance C w f 2 create the resonance of f z 2 in the HF range. Moredetails of the model calculations are presented in [16].

Elements extraction for the lter is split into different or-ders of the inductor or capacitor, respectively. Each inductoror capacitor branch is measured and extracted separately. TheCM equivalent circuit model of the applied LCL lter is shownin Fig. 13, where the model branch of the third-order inductor(250 H) comprises R f 1 , C f 1 , and L f 1 , the model branch of the rst-order inductor (200 H) comprises R f 2 , C f 2 , and L f 2 ,and the model branch of the second-order capacitor (400 nF)comprises R f 3 , C f 3 , and L f 3 . Taking the CM capacitor par-asitics extraction as an example, R f 3 and L f 3 are the self equivalent series resistance (ESR) and the equivalent series in-ductance (ESL) of the capacitor, respectively. In the measuredimpedance-frequency characteristic of the capacitor, C f 3 is ex-tracted according to the slope in the LF range. The capacitorparasitic inductance L f 3 is calculated from the resonance oc-curring in the MF range. R f 3 is equal to the minimum value of the impedances.

Another important factor that needs to be considered is the in-uence of adding current probe to the parasitics during the mea-surements. This impact is determined according to themeasuredresults as shown in Fig. 14 which is the measured inductance-

frequencycharacteristicof a 110nH wire with andwithoutprobe

Fig. 15. Comparison of the calculated insertion losses with different appliedlters.

clamping. It can be seen that the connection of current probeintroduces an additional inductance of 7 nH at 5 MHz where the

main frequency is the concern. It hardly shows any effect in theHF range beyond 10 MHz. Because of the higher inductance inthe power cables (L 2 and L ou t as shown in Fig. 10), the currentprobe inductance is neglected in the model.

D. Evaluation of Different Filter Topologies

With the developed model, the calculated insertion losses of each lter ( C , LCL, and LCLC ) are compared against each otheras shown in Fig. 15. The selection of the component values isbased on four considerations. 1) The components should ful-ll the calculated lter attenuation to the level required by theinsertion loss as shown in Fig. 8. 2) The component values in

each order of the lter are the same; therefore, the selected ltertopologies as shown in Fig. 7 are comparable in volume. 3) Thecore saturation caused by both CM and DM leakage magneticelds must be avoided; therefore, the applied lter inductors isable to fulll their attenuation ability. It can be seen with refer-ence to the required insertion loss that the LCL lter exhibits thebest performance which effectively suppresses the noise spikein the MF range while still obtaining adequate attenuation abil-ity in the HF range. The results are illustrative of an optimizedEMI lter design with no excessive components involved. Al-though the LCLC lter utilizes more components, it does notgive better performance in suppressing the capacitive couplinginuence. The aforementioned benets can only be achieved bythe broadband modeling of the conducted EMI.

IV. TOWARD THE STANDARD COMPLIANCE

A. Implementation of the LCL Filter

Consequently, LCL CM lter is selected as the nal designand implemented in the IMS inverter driven motor system. Thecomponent values are the same as those in the calculated resultsshown in Fig. 15. The achieved EMI spectrum is compared withthat of the LCLC lter which is shown in Fig. 16. It can beseen that the measurements agree well with the calculations of Fig. 15. The noise spike caused by the capacitive couplings at

MF range (around 4.5 MHz) is effectively suppressed. However,


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Fig. 16. Comparison of the measured total noise spectra between the systemwith the LCLC (250 H, 400 nF, 200 H, 400 nH) lter and LCL (250 H,400 nF, 200 H) lter.

Fig. 17. Comparison of thecalculated LCL lter insertion lossbetween beforeand after optimization.

the noise at the initial frequency of 150 kHz and HF range still

fails to conform to the standard. This can, however, be achievedby a few adjustments which will be introduced in the followingsection.

B. Optimization

To further reduce the LF noise, the inductance of the rst-order lter [L 2 in Fig. 7(c)] is increased to 280 H. Reductionof the HF noise can be achieved with two solutions.

1) Decrease the grounding inductance ( L f 3 in Fig. 13) of theY -capacitors. The grounding inductance of Y -capacitorsis lowered by using copper strips instead of wires to con-nect the capacitor leads to the ground.

2) Increase the inductance which must be effective for HFnoise suppression between the inverter output phases andthe motor (L s 3 in Fig. 10). The HF effective inductanceof L s 3 is increased to 3 H by adding ferrite beads( ZCAT3035 TDK ) across the unshielded cables that con-nect the inverter and the motor. The equivalent circuitof the ferrite bead is a series connection of a frequency-dependent resistor and inductor, which damps and dissi-pates the HF oscillations.

Consequently, the calculated results are shown in Fig. 17,where the application of LCL (250 H 400 nF 200 H) shownin Fig. 15 corresponds to the case before optimization. Appli-

cation of the proposed HF improvement solutions corresponds

Fig. 18. Comparison of the measured total noise spectra before and afterapplying the improved approaches.

to the case after optimization. With the added ferrite beads, theinductance at the inverter output phases ( L s 3) is increased to

3 H.The comparison of the experimental results before and afterapplying the optimization solutions is shown in Fig. 18. It canbe seen that the HF noise is effectively reduced as predictedby the model. The LF noise reduction is resulted from the in-crease of the inductance of the rst-order lter. Combined withthe effects, the emitted EMI of the IMS inverter system is ef-fectively suppressed to comply with the standard prescribed byIEC61800-3 C2 Qp.

V. CONCLUSION

Applying IMS to improve thermal management of motordrives potentially deteriorates the EMC performance, even moreso when SiC power devices are used and attached directly ontop of the IMS. The extensive capacitive couplings betweenthe circuit copper foil and the IMS base plate result in the in-creased current overshoot and oscillations. It is shown that withconventional CM lters, the emitted noise in the IMS inverteris signicantly higher than that in the heat sink inverter whenthey are implemented in the same circuit layout. Although theLF noise is effectively suppressed, the inuence of capacitivecoupling results in little or even no improvement in the MFand HF noise ranges. In this paper, a CM equivalent circuitmodel which enables prediction of the lter performance overa broad conducted EMI frequency range is developed. Throughthe model, the optimal lter design is achieved through the in-sertion loss comparison of various lter topologies. It is foundthat for theIMSinverter, theperformance of the third-order lter LCL is much better than the others which include the fourth-order lter LCLC ; hence, the lter size and cost are reduced.Additionally, the methods to further improve HF performance,reducing the crucial parasitics and increasing the inductance atinverter output phases, are proposed according to the modelingresults. Consequently, the emitted EMI of the IMS inverter iseffectively suppressed to comply with the IEC61800-3 C2 Qp

standard.


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Xun Gong (M12) received the B.Sc. and M.Sc. de-grees in control theory and control engineering fromthe Dalian University of Technology, Dalian, China,in 2006 and 2009, respectively. During his masterthesis, he developed a soft-starter prototype for asyn-chronous electrical machines.

In 2008, he became a Ph.D. Researcher at Elec-trical Power Processing Group, Delft University of Technology, Delft, The Netherlands. His research in-terests include EMC strategies, high power densitydesign, and construction of motor drives. His current

research interests include power electronics, design and implementation of highpower density, and high efciency power converters.

Ivan Josifovi c (M09) was born in Kraljevo,Serbia, in 1982. He received the B.Sc. and M.Sc. de-greesfrom the Department of Power, Electronics, andTelecommunication fromthe University of Novi Sad,Serbia, Faculty of Technical Sciences, in 2005 and2007, respectively. In his master project, he realizeda dc motor drive and applied dSpace developmentsystem for implementation of a control algorithm.

He is currentlya Researcher with Electrical PowerProcessing (EPP) Group, Delft University of Tech-nology, Delft, The Netherlands. His research inter-

ests include high power density packaging and automated construction of power electronics. His work involves implementation of compact and efcientpower converters using wide-band gap semiconductors and innovative passivecomponents.

Jan Abraham Ferreira (M88SM01F05) wasborn in Pretoria, South Africa. He received theB.Sc.Eng. ( cum laude ), M.Sc..Eng. ( cum laude ), andPh.D. degrees in electricalengineering fromthe RandAfrikaans University, Johannesburg, South Africa.

In 1981, he did research on battery vehicles at theInstitute of Power Electronics and Electric Drives,Technical University of Aachen, and worked in in-dustry as a Systems Engineer at ESD (Pty) Ltd from1982 to 1985. From 1986 until 1997, he was at theFaculty of Engineering, Rand Afrikaans University,

where he held the Carl and Emily Fuchs Chair of Power Electronics in lateryears. In 1998, he became a Professor of Power Electronics and Electrical ma-chines at the Delft University of Technology, Delft, The Netherlands.

Dr. Ferreira was the Chairman of the South African Section of the IEEEduring 19931994. He is the Founding Chairman of the IEEE Joint IAS/PELSBenelux Chapter. He served in 19951996 as the Chairman of the IEEE IASPower Electronic Devices and Components committee. He is an Associate Edi-tor ofthe IEEET RANSACTIONS ON POWER ELECTRONICS and served as treasurerand vice president meetings of the IEEE PELS. He was the Chairman of theCIGRE SC14 National Committee of the Netherlands from 1999 to 2002 and isa member of the executive committee of the European Power Electronic Asso-ciation EPE Society (19992003; 2008present).

[sic-en-2013-3] modeling and reduction of conducted emi of inverters with sic jfets on insulated...

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