SICVERTER

By

Chaitanya Sindagi

Conner Bone

Joshua Powell

Final Report for ECE 445, Senior Design, Fall 2020

TA: Dean Biskup

8 December 2020

Project No. 4

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Abstract

For our project, we set out to design the foundation for an efficient, compact, 3-phase motor inverter using silicon-carbide MOSFETs, energy-dense film capacitors, and a dedicated Texas Instruments Digital Signal Processor (DSP). The design should be capable of operating at up to 600 V and 35 kW while outputting up to 62 Arms.

Our design incorporates two vertically stacked Printed Circuit Boards (PCBs) - a power stage PCB that handles DC-AC conversion and a control PCB that generates MOSFET switching signals and faults and external subsystem communication signals.

Testing with available equipment shows that our design should work as intended when operating at all extremes of power, voltage and current. However, more tests are required to determine performance and reliability before integration into an electric vehicle.

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Contents 1. Introduction .............................................................................................................................................. 1

1.1 Objective ............................................................................................................................................. 1

1.2 High-Level Requirements Met ............................................................................................................ 1

1.3 Summary ............................................................................................................................................. 2

2 Design ......................................................................................................................................................... 3

2.1 Power Stage ........................................................................................................................................ 4

2.1.1 DC Link Capacitors ........................................................................................................................ 4

2.1.2 Half-Bridges .................................................................................................................................. 4

2.1.3 Isolated Gate Drive and Power Supply ........................................................................................ 5

2.1.4 Current and Voltage Sense Amplifiers ......................................................................................... 5

2.2 Control Board ...................................................................................................................................... 6

2.2.1 Power Supplies – 12V Conversion ................................................................................................ 6

2.2.2 Texas Instruments TMS320F280049C Control Card .................................................................... 6

2.2.3 BiSS (Bidirectional/Serial/Synchronous) Interface IC ................................................................... 7

2.2.4 CAN (Controller Area Network) Interface IC(s) ............................................................................ 7

2.3 Software .............................................................................................................................................. 7

2.3.1 PWM (Pulse Width Modulation) Macro ...................................................................................... 7

2.3.2 Clarke Macro, Park Macro and IPark Macro ................................................................................ 8

2.3.3 Generated Clocks and Datalogging .............................................................................................. 9

2.3.4 General Purpose In/Out (I/O) Pin Assignments ........................................................................... 9

3. Design Verification .................................................................................................................................. 10

3.1 Power stage MOSFETs....................................................................................................................... 10

3.2 Capacitor Bank .................................................................................................................................. 11

3.3 Control Board Verifications ............................................................................................................... 11

3.3.1 12V Rail Conversion ................................................................................................................... 11

3.3.2 Communication Protocol Library ............................................................................................... 12

3.3.3 Control Card Pin Assignments .................................................................................................... 12

4. Costs ........................................................................................................................................................ 13

4.1 Parts .................................................................................................................................................. 13

4.2 Labor ................................................................................................................................................. 13

4.3 Total Costs ......................................................................................................................................... 13

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5. Conclusion ............................................................................................................................................... 14

5.1 Accomplishments .............................................................................................................................. 14

5.2 Uncertainties ..................................................................................................................................... 14

5.3 Ethical Considerations ....................................................................................................................... 14

5.4 Future Work ...................................................................................................................................... 14

References .................................................................................................................................................. 15

Appendix A Double Pulse Testing ............................................................................................................... 16

Appendix B Requirements and Verifications .............................................................................................. 17

Appendix C: Schematics and PCB Renders.................................................................................................. 19

Power Stage Schematics ..................................................................................................................... 19

Power Stage PCB Renders ................................................................................................................... 21

Control Board Schematics ................................................................................................................... 22

Control Board Renders ........................................................................................................................ 27

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1. Introduction This project has been done in collaboration and as a part of the Illini Formula Electric team which builds an electric race car every year. This 2020/21 school year, the race car being built is using 4 permanent magnet (PM) motors, one for each wheel of the car. These motors are driven by 3-phase AC power, so the vehicle’s 600 V battery pack’s DC output must be converted to 3-phase AC by a motor controller/inverter, one for each motor. Moreover, to achieve the maximum performance possible, each motor inverter must be capable of outputting 35 kW and 62 Arms to each of the motors.

1.1 Objective However, all commercially available motor controllers capable of driving 35 kW motors at 600 V were too expensive and/or too heavy to be useful in our electric race car. Therefore, the objective of this project was to create a motor controller that meets the specifications required for the car while being lightweight, efficient, compact, and affordable. To limit the scope of the project, a single inverter for a single motor has been developed over the course of the semester and was tested at low voltages and currents to validate its functionality.

To meet our design goals, we chose to use Silicon carbide MOSFETs, film capacitors and a Digital Signal Processor (DSP) from TI designed to function well in motor drive applications. It has been designed as a voltage source inverter with three phase legs and current sensing of all three phases for redundancy and noise immunity. A Field Oriented Control Algorithm is used to modulate the phase currents and maximize motor efficiency and performance. A motor resolver using a Bidirectional/Serial/Synchronous (BiSS)1 interface along with 2 Controller Area Networks (CAN)2 are used for noise immune communications on the vehicle.

To reduce system weight and complexity, all four inverters will be placed on a single large heatsink instead of the industry standard method of using a liquid-cooled cold plate. Our chosen heatsink is capable of dissipating up to 1.6 kW at peak operation, requiring each inverter at peak output power to dissipate less than 400 W.

1.2 High-Level Requirements Met As the physical design of the 2020/2021 car has been decided, the inverters need to fit in a predetermined space designed for them to go. One inverter module needed to fit within a 200 mm long x 100 mm wide x 40 mm tall space. Upon final assembly, our inverter is 194 mm long x 90 mm wide x 39 mm tall and should properly fit in the location it was designed for originally.

Finally, to remain competitive with other inverters on the market, our design needed to be as lightweight as possible to minimize the amount of mass the car needs to accelerate. Our initial target for weight was a total of less than 2.4 kg for four of these modules, so no more than 600 g per inverter. After full assembly, we found our constructed module to weigh 495 g, well within our weight target.

1 Described in Section 2.2.3 2 Described in Section 2.2.4

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As mentioned in Section 1.1, the inverters must be extremely efficient to meet the system’s design goals. This is primarily due to our choice of using an air-cooled heatsink. Therefore, our MOSFET losses must be kept low and overall inverter efficiency maximized. In Section 2.1.2 we cover how this design is expected to meet this requirement.

1.3 Summary In Section 2 the overall motor inverter design is covered with diagrams showcasing how the power stage PCB and control PCB interact with each other and other subsystems on the car to convert the car’s DC output to 3-phase AC. We explain our choices for components and algorithms used in our design.

Tests in Section 3 show our verification methods to ensure all components are within our design specification and in a safe operating range. While we were limited in our testing due to university labs not having the equipment necessary, the data we captured gives us a good indication that this motor inverter will perform safely and efficiently in the operation range expected. We have done calculations to show that while operating in these designed ranges, we will stay within our thermal targets in order to successfully cool these inverters with the chosen heatsink. Section 4 contains tables and equations that give a good picture on what the costs are of producing these inverters at scale, alongside the labor costs that must be considered for the design process of this product.

When our collected test data is extrapolated, we expect this inverter to operate within our needed specifications. Currently, further testing still needs to be done at these higher voltages and currents to fully determine if this inverter functions properly and safely as per our design.

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2 Design The overall vehicle design block diagram can be seen in Figure 1, and a detailed view of a motor controller from Figure 1 can be found in Figure 2. The 600 V battery pack supplies the four motor controllers with DC power through its protection relays. This power is converted into four sets of 3-phase power for each motor on the wheel. Each of these motors is rated for 40 kW but will only be operated at 35 kW for thermal reasons.

Figure 1 Block diagram of overall vehicle design

Figure 2 Block diagram of a single motor controller

The motor controller consists of two boards, the power stage and control board. The control board senses output current, bus voltage, faults, and motor position and along with the driver input from the CAN bus, it outputs six Pulse Width Modulation (PWM) signals to the power stage to switch its MOSFETs. The MOSFETs on the power stage, rapidly switch the voltage on the output phases of the motor, resulting in a controlled current waveform on each of the 3-phases. These waveforms are controlled to be sinusoidal and 120° out of phase with each other. We go into more detail of each board in the coming sections.

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2.1 Power Stage

Figure 3 Block diagram of the power stage component

The power stage in Figure 3 contains all high voltage and high current paths of the inverter. It is composed of 3-phase legs each drive one phase of the motor. It also contains a sensing circuit for the DC voltage of the battery, connectors for the battery input power and connectors to plug the control board into. Each phase leg consists of DC link capacitors, a Silicon Carbide (SiC) MOSFET half-bridge, isolated gate drivers, isolated power supplies, phase current sensing and module temperature sensing.

2.1.1 DC Link Capacitors The DC link capacitors provide the current pulses necessary to drive the switching waveforms demanded by the MOSFETs while allowing the battery to function as a constant DC supply with low ripple current. This is important to prevent battery heating and bus voltage oscillations. Fifteen B32774D8305K000 film capacitors in parallel were used to ensure low loop inductance and series resistance while maintaining a small capacitor volume. The total capacitance of this bank is 45 μF, which theoretically is sufficient to ensure a bus voltage ripple less than 43 V which is 10% of the minimum operating voltage.

2.1.2 Half-Bridges The half-bridges are two MOSFETs connected in series. We chose the FF11MR12W1M1B11BOMA1 for its low on-resistance of 11 mΩ resulting in low conduction losses. Moreover, since it is a Silicon Carbide device, it can switch very fast, resulting in low switching losses. These two are approximated in Equations 1, 2, 3 and 4.

𝑃𝑃𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = 3 × 𝑅𝑅𝐷𝐷𝐷𝐷(𝑐𝑐𝑐𝑐)(125∘𝐶𝐶) × 𝐼𝐼𝑟𝑟𝑟𝑟𝑟𝑟2 Eq. 1

𝑃𝑃𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = 3 × 14.8𝑚𝑚Ω × (62𝐴𝐴𝑟𝑟𝑟𝑟𝑟𝑟)2 = 171 𝑊𝑊 Eq. 2

Where Pcond is conduction losses and RDS(on) is the on-resistance of the MOSFETs at the specified temperature. This equation calculates the total power dissipation of each half bridge for simplicity.

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𝑃𝑃𝑟𝑟𝑠𝑠 = 6 × (𝐸𝐸𝑟𝑟𝑠𝑠(𝐼𝐼𝑐𝑐 = 88 𝐴𝐴 ) × 𝑓𝑓𝑟𝑟𝑠𝑠 × 0.637 × 0.5) Eq. 3

𝑃𝑃𝑟𝑟𝑠𝑠 = 6 × 1.852 × 10−3 × (50 × 103) × 0.637 × 0.5 = 177 𝑊𝑊 Eq. 4

Where Psw is switching losses, Esw is the switching energy of the MOSFETs at the specified switching current and fsw is the switching frequency. This equation is typically far more complicated, involving modulation index and motor power factor, however these were ignored for simplicity and the worst-case scenario was assumed.

Equation 5 calculates the total maximum losses expected from the inverter, Ptot which is shown to be below the 400 W limit imposed by the thermal design of the heatsink used.

𝑃𝑃𝑡𝑡𝑐𝑐𝑡𝑡 = 171 + 177 = 348𝑊𝑊 Eq. 5

In the worst case, a single MOSFET’s dissipation, Pdis(per MOSFET) can be calculated as shown in Equation 6.

𝑃𝑃𝑐𝑐𝑑𝑑𝑟𝑟(𝑝𝑝𝑝𝑝𝑟𝑟 𝑀𝑀𝑀𝑀𝐷𝐷𝑀𝑀𝑀𝑀𝑀𝑀) = 1713

+ 1776

= 86.5𝑊𝑊 Eq. 6

The temperature rise using the datasheet provided thermal resistance will therefore be 42 °C. This implies that the max heatsink temperature is 83 °C, well within the 75 °C that the heatsink is designed to maintain at nominal power output.

2.1.3 Isolated Gate Drive and Power Supply The isolated gate drive and power supply were chosen to be capable of driving the currents required for the MOSFETs. Further, we ensured they had a sufficient Common-Mode-Transient-Immunity (CMTI) so there were no glitches in the gate drive output even during the fastest voltage transient of the switching node. This is important since Silicon Carbide MOSFETs can switch faster than regular MOSFETs.

2.1.4 Current and Voltage Sense Amplifiers For current and voltage sensing, we chose to use sigma delta modulators to measure the analog signal on the isolated side and transmit a digital 1-bit stream to the microcontroller that represents the amplitude of the measured signal. This signal transmission technique is not as susceptible to electrical noise as analog sensors and can be filtered to a high accuracy using digital filters present in the microcontroller’s Sigma-Delta-Filter-Module (SDFM) bank. This technique also allows for more accurate control compared to a sample-hold ADC design since it samples across the entire switching interval and filters out all high frequency noise caused due to switching or otherwise [1]. These isolators were also chosen to have sufficiently high CMTI.

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2.2 Control Board

Figure 4 Block diagram of the control board component

The control board takes in all sensed inputs and throttle commands and outputs the necessary control signals to the power stage to ensure the output is what is required to generate the torque requested. The software being used to do this is described in Section 2.3.

It uses a Bidirectional/Serial/Synchronous (BiSS) interface to communicate with the motor resolver and get the motor shaft angle. It also uses a Controller Area Network (CAN) bus to get the throttle input from the driver pedal. Based on those inputs, as well as sensed signals from the power stage, it executes a Field Oriented Control (FOC) algorithm on a microcontroller at 50 kHz and ensures that all of this occurs safely. It also generates all the necessary voltage busses for the proper operation of the board. It will log all important parameters during operation and in fault conditions to the CAN bus.

2.2.1 Power Supplies – 12V Conversion We required 12 V, 5 V and 3.3 V busses for the different ICs on the board such as our gate drivers, isolated power supplies and interface controllers. However, we only have a 12 V supply to the board from the vehicle’s battery. Hence, the power supply section generates these additional two rails for low power components. To meet our performance requirements while keeping the design simple, we chose to use the RECOM R-78B DC-DC converters.

2.2.2 Texas Instruments TMS320F280049C Control Card The TMDSCNCD280049C daughter card is used to implement the FOC algorithm on the TMS320F280049C microcontroller. The algorithm will operate with at 100kHz to update a 50kHz PWM signal to each of the 6 MOSFETs twice every cycle. It takes in motor shaft position from the BiSS interface and current and voltage data from the power stage. Using the torque command from the CAN bus, the algorithm generates six PWM signals that are sent to the power stage to drive each MOSFET.

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2.2.3 BiSS (Bidirectional/Serial/Synchronous) Interface IC BiSS is an RS485 based signaling protocol designed for high-speed motor resolvers that is very noise immune and accurate. An RM44x resolver is placed on the motor shaft that interacts with the control board over this protocol. An RS485 Tx/Rx interface is used for this and has been implemented on the board using a circuit similar to Texas Instrument’s DesignDrive Development Kit [2].

2.2.4 CAN (Controller Area Network) Interface IC(s) The car uses multiple CAN busses to communicate various signals. The inverter will be connected to 2 CAN busses. Each CAN BUS has a transceiver to handle data transmission from the CAN bus that is accessed by other components on the car. One CAN bus will take in torque commands sent by the driver’s foot pedal and communicate them to the microcontroller. The other bus will be used to output data for the vehicle’s external datalogger to store critical parameters, status history, potential error codes and crashes.

2.3 Software

Figure 5 Block diagram of Texas Instruments' Sensored Field Oriented Control algorithm [3]

The software running on the control card from Texas Instruments is the only software programmed/used in the motor inverter. The control card as described in Section 2.2.4 executes a Field Oriented Control algorithm seen in Figure 5. Demo source code from Texas Instruments’ libraries of which implement this algorithm is used as the basis for our software [3] and a technical reference manual for the TMS320F280049C control card is used for pin assignments and register assignments [4].

2.3.1 PWM (Pulse Width Modulation) Macro The PWM macro generates six total PWMs each at 50 kHz denoted as PWM 1-3 (A/B). PWM (1A, 2A, 3A) are all sent to the high side of the isolated gate drivers and power supplies seen in Figure 3 of the power stage, and PWM (1B, 2B, 3B) are all sent to the low side of the isolated gate drivers and power supplies. These drive the MOSFETs and cause them to switch on and off.

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2.3.2 Clarke Macro, Park Macro and IPark Macro The Clarke and Park transformations are used specifically for vector-controlled architectures [5], which is what the permanent magnetic motors use, and these motors are driven by our 3-phase motor inverter. The Clarke transformation will take a three-phase reference frame and convert it into a two-axis orthogonal stationary reference frame as seen in Figure 6.

Figure 6 Clarke Transformation from three-phase reference frame to two-axis orthogonal stationary frame [5]

To do this transformation, the following equations are used in the Clarke Transformation algorithm to transform the reference frames. Equation 7 gives us our alpha (𝐼𝐼𝛼𝛼) axis and Equation 8 gives us our beta (𝐼𝐼β) axis for the orthogonal stationary frame.

𝐼𝐼𝛼𝛼 = 23

(𝐼𝐼𝑎𝑎) − 13

(𝐼𝐼𝑏𝑏 − 𝐼𝐼𝑐𝑐) Eq. 7

𝐼𝐼β = 2√3

(𝐼𝐼𝑏𝑏 − 𝐼𝐼𝑐𝑐) Eq. 8

Furthermore, the Park Transformation will change a two-axis stationary orthogonal reference frame into a rotating two-axis reference frame as seen in Figure 7.

Figure 7 Park Transformation from two-axis stationary orthogonal reference frame to two-axis rotating reference frame [5]

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The Park Transformation is done by using Equations 9 and 10 to transform reference frames.

𝐼𝐼𝑐𝑐  =  𝐼𝐼α × 𝑐𝑐os(θ)  +  𝐼𝐼β × 𝑠𝑠in(θ) Eq. 9

𝐼𝐼𝑞𝑞 = 𝐼𝐼𝛽𝛽 × 𝑐𝑐𝑐𝑐𝑠𝑠(𝜃𝜃) − 𝐼𝐼𝛼𝛼 × 𝑠𝑠𝑠𝑠𝑠𝑠(𝜃𝜃) Eq. 10

Lastly, the Inverse Park Transformation transforms a rotating two-axis frame back into the two-axis orthogonal stationary reference frame by using Equations 11 and 12.

𝐼𝐼𝛼𝛼 = 𝐼𝐼𝑐𝑐 × 𝑐𝑐𝑐𝑐𝑠𝑠(𝜃𝜃) − 𝐼𝐼𝑞𝑞 × 𝑠𝑠𝑠𝑠𝑠𝑠(𝜃𝜃) Eq. 11

𝐼𝐼𝛽𝛽 = 𝐼𝐼𝑞𝑞 × 𝑐𝑐𝑐𝑐𝑠𝑠(𝜃𝜃) + 𝐼𝐼𝑐𝑐 × 𝑠𝑠𝑠𝑠𝑠𝑠(𝜃𝜃) Eq. 12

2.3.3 Generated Clocks and Datalogging There are two generated clocks (CLK) signals for external devices we plan to implement in the future. Currently, the motor resolver is one of these components not implemented. The motor resolver is a magnetic rotary encoder, which receives a ~7.7 MHz clock and transmits motor position data back to the control card. Secondly, a 20 MHz clock is generated for an isolated sigma delta converter that is used to create a compact and noise free measurement of the DC bus and current from the 3-phase output. The bus voltage sensing and current sensing has not been implemented yet but is an upcoming feature in development.

2.3.4 General Purpose In/Out (I/O) Pin Assignments The types of GPIO pins that were used are known as push-pull output or floating input, and pull-up enable for input. The PWMs and clocks are setup with push-pull output and the inputs for faults and error reporting used a pull-up enabled input. The push-pull output two transistors where when the output is low the signal is pulled into the ground, and when the output is high the signal is pushed into VCC. Pull-up enable input is a type of pin that acts as a gate and uses a resistor connected to high.

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3. Design Verification We verified the board designs in three stages to minimize manufacturing cost and time. Firstly, we designed and tested a single-phase version of the power stage that was fully instrumented for ease of testing. We performed double-pulse testing [See Appendix A and Section 3.1] and power loop inductance measurement [See Section 3.2] with this board. A full power stage board was then designed and functionally verified to have no accidental errors. Lastly, the control board was assembled and briefly verified independently before being connected to the power stage and being tested together.

Some aspects of our verification plan such as bus voltage ripple, capacitor operating temperature, thermal resistance to heatsink and CAN bus were not completed since the lab equipment available were not capable of these tests. Therefore, they were replaced with alternative measurements, theoretical calculations, and different part choices to eliminate the need for them.

• Bus voltage ripple was verified by measuring the capacitance of the bank. • Capacitor operating temperature was verified using impedance measurement and a worst-case

assumption for ripple current. • By choosing an alternative MOSFET module that came with pre-applied thermal paste we were

able to use datasheet guidance for thermal resistance and not measure it ourselves. • CAN bus was verified with an oscilloscope to have the correct bit rate and bits manually.

3.1 Power stage MOSFETs To verify switching performance of the MOSFET half-bridges we performed a double pulse test [See Appendix A] while measuring power supply output voltages and switch node voltages. Power supply output voltages were stable at the highest transients we were able to achieve. Testing at the maximum expected transients was not possible due to lack of equipment. Figure 8 shows the results of switch node voltage overshoot and undershoot measured during these tests.

Figure 8 Overshoot and Undershoot vs Switching Voltage and Current

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From these graphs it is clear there is a correlation between undershoot and switching voltage and overshoot and switching current. Extrapolating these to 600 V and 88 A we have a maximum theoretical undershoot of 260 V and overshoot of 84 V. These are within are requirement of 300V and in the future, gives us room to reduce gate resistance and switching losses further.

3.2 Capacitor Bank The capacitor bank as had to be verified using alternative methods as mentioned in Section 3. These included capacitance measurement, impedance measurement and ESR measurement. The capacitance was measured with a multimeter to be 43.3 μF. Impedance was measured using a network analyzer operating in shunt-through mode. Figure 9 shows the results of this measurement.

Figure 9 Capacitor Impedance measurement

The resonant frequency is measured as 530 kHz with an amplitude of -68 dB. This corresponds to a power loop inductance of just 7 nH and an ESR of 19.9 mΩ. The ESR is higher than expect but likely due to AC resistance effects and poor soldering at the measurement frequency. ESR can be confirmed with an accurate LCR meter at low frequencies in the future.

3.3 Control Board Verifications

3.3.1 12V Rail Conversion When tested with a multimeter, the 5 V and 3.3 V power rails on the control board stayed within our designed specification of less than +/- 0.1 V ripple while sending signals to the power stage board. These rails were measured as 3.31V and 5.05V meeting our line regulation requirements and were observed to have noise levels below the available equipment’s noise floor.

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3.3.2 Communication Protocol Library As mentioned in Section 2.2, the motor resolver was a planned feature that measures the motor angle, but we were unable to implement it, so it has been planned for future implementation. The motor resolver was tested alone with an evaluation board and we were able to receive a data stream of bits while also sending it a 7.7 MHz clock, but when we attempted to communicate with the RM44 rotary magnetic encoder/motor resolver using our control board, we could not receive the data stream from the resolver. The problem is that the BiSS interface requires an acknowledge and start bit to be sent but the proprietary binary provided by Texas Instruments does not seem to initialize correctly and provide this start sequence to the resolver.

3.3.3 Control Card Pin Assignments Bit sequences programmed to be output to pins on the control card were viewed on the oscilloscope, and the correct signals were mapped to their respective pins on the headers connecting the power stage and control PCB’s. Pins assigned to be pulled low were measured as grounded, and pins set to be pulled high were measured at 3.3V. Faults, and other input signals coming from the power stage board were measured with the oscilloscope and the correct waveforms were observed.

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4. Costs

4.1 Parts Since the design is intended for the niche application of electric race cars, a bulk purchase volume of just 1000 units was used to determine the bulk price of manufacturing.

Table 1 Parts Costs Part Manufacturer Retail/Actual

Cost ($) Bulk

Purchase Cost ($)

DC Link Capacitors B32774D8305K000

EPCOS / TDK

$37.80 $19.35

Gate Driver - UCC21750DWR Texas Instruments $28.62 $13.44 Gate Supply - MGJ2D121505SC Murata $50.52 $37.56

Bus Voltage Sense AMC1336DWVR

Texas Instruments $6.68 $4.07

Phase Current Sense - AMC1306M05DWV

Texas Instruments $24.51 $9.00

Power Supply modules RECOM $19.58 $6.40 BiSS Interface ICs - $5.00 $2.00 CAN Interface ICs - $5.00 $2.00

Half Bridge x 3 FF11MR12W1M1B11BOMA1

Infineon $428.67 $362.25

TMS320F280049C Control Card Texas Instruments $99.00 $99.00 PCB PCBWAY $300.00 $10.00

Miscellaneous Passives N/A $50.00 $20.00 Housing + Heatsink - $200 $50

Total $1255.38 $635.07

4.2 Labor Development of this project took place over a period of 14 weeks, with an average time of 12hr/week/person. We estimate an hourly wage of $30 and that around 70% of the project has been completed. Further, a factor of 2.5 to account for equipment costs and overtime was added. The overall cost of Labor came out to $54,000 as seen in Equation 13.

3 × 14𝑠𝑠𝑝𝑝𝑝𝑝𝑤𝑤𝑟𝑟70%

× 30ℎ𝑟𝑟

× 12ℎ𝑟𝑟𝑠𝑠𝑝𝑝𝑝𝑝𝑤𝑤

× 2.5 = $54000 Eq. 13

4.3 Total Costs The total design and manufacturing cost of a single prototype is in Equation 14, whereas the bulk cost is in Equation 15.

$54000 + $1255.38 = $55255.38 Eq. 14

$540001000

+ $635.07 = $689.07 Eq. 15

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5. Conclusion

5.1 Accomplishments We successfully tested the electrical performance of the power stage at extremes where possible and used well-founded trends to determine the performance where test equipment was not available. The control board too was tested in its entirety and most issues with the design were identified and resolved.

5.2 Uncertainties The software for the TI control card does not include all safety checks and we have not been able to make it communicate correctly with the motor resolver. Moreover, due to the lack of high voltage testing, the effects of switching noise are unverifiable. We have not been able to test the capability of the inverter to operate at high output currents, however we do not expect any issues here, the thermal design has a large factor of safety.

5.3 Ethical Considerations A device used to power an electric vehicle at a high speed inherently is risky to the driver of the vehicle. A motor controller accidentally operating without the driver’s direct input is dangerous and should never happen. To mitigate such situations, the motor controller has multiple hardware fault detection stages, a hardware-based disable signal and is further backed up by relays on the vehicle battery pack that will disconnect if the driver is has lost control. All these measures together ensure that all situations that put the driver in harm’s way are avoided.

5.4 Future Work The software issues with communication mentioned in Section 3.3.2 need to be debugged and resolved. Additional hardware checks for overcurrent and over-temperature need to be implemented. Testing the design at maximum voltage and power must also be done to ensure satisfactory performance at these operating conditions. Thermal design must be verified during these maximum power tests as well.

Once all the tests have been completed, reliability testing with extended run times and artificially injected fault scenarios must be performed. After this, we believe it would be safe to put the inverter in the car and test the vehicle as a whole.

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References

[1] J. Sorensen, "Sigma Delta Conversion Used for Motor Control," [Online]. Available: https://www.analog.com/en/technical-articles/sigma-delta-conversion-used-for-motor-control.html. [Accessed 10 August 2020].

[2] "C2000 DesignDRIVE Development Kit for Industrial Motor Control," Texas Instruments, 2019. [Online]. Available: https://www.ti.com/tool/TMDXIDDK379D. [Accessed 18 August 2020].

[3] "Sensored Field Oriented Control of 3-Phase Permanent Magnet Synchronous Motors Using TMS320F2837x," Texas Instruments, 2016. [Online]. Available: https://www.ti.com/lit/an/sprabz0/sprabz0.pdf. [Accessed 4 September 2020].

[4] "TMS320F28004x Real-Time Microcontrollers Technical Reference Manual," 2020. [Online]. Available: https://www.ti.com/lit/an/sprabz0/sprabz0.pdf. [Accessed 1 October 2020].

[5] "Park, Inverse Park and Clarke, Inverse Clarke Transformations MSS Software Implementation," Microsemi, 2013. [Online]. Available: https://www.microsemi.com/document-portal/doc_view/132799-park-inverse-park-and-clarke-inverse-clarke-transformations-mss-software-implementation-user-guide. [Accessed 26 September 2020].

[6] J. Sylvestre, "Specter Engineering," 7 September 2019. [Online]. Available: https://www.specterengineering.com/blog/2019/9/7/dc-link-capacitor-selection-for-your-inverter.

[7] "Designing with Isolated Gate Drivers for HEV/EV Applications," Texas Instruments, 2018. [Online]. Available: https://training.ti.com/sites/default/files/docs/2018%20FAE%20Summit%20-%20Designing%20with%20Isolated%20Gate%20Drivers%20for%20HEVEV%20Applications_LI_0329_EXT.pdf. [Accessed 31 August 2020].

[8] G. Lakkas, "MOSFET power losses and how they affect power-supply efficiency," Texas Instruments, 2016. [Online]. Available: https://www.ti.com/lit/an/slyt664/slyt664.pdf. [Accessed 1 September 2020].

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Appendix A Double Pulse Testing

Double pulse testing is a method used to determine switching performance of a half bridge module at different levels of current. By using a large inductor connected between the switch node and DC+, a precise value of current can be conducted through the lower MOSFET (Device-Under-Test, DUT) in the half bridge by turning on the DUT for a fixed period of time. Then, the DUT is switched off and on before the inductor current decays, resulting in a measurement of a variety of parameters during the turn-on and turn-off events at a specified current. This schematic diagram is seen in Figure 10.

The high side MOSFET is held low while the DUT is turned on for a fixed period to raise the current to the necessary value. It is then turned off and back on within 2 μs and during this period the oscilloscope captures the necessary waveforms. The DUT is then turned off and the inductor discharges through the high side MOSFET’s body diode. These gate timings will be generated using a function generator to allow for precise control. A 19.5 μH inductor that theoretically saturated at 56.8 A was built for this using the largest available power iron core. Testing was not conducted above this current to prevent damage to the prototype. Figure 11 shows an example of the current through the entire test and Figure 12 shows the waveforms captured during testing. Switching voltages of 5-50 V and switching currents of 1-63 A were measured.

Figure 11 Double pulse full test waveform

Figure 12 Double pulse measurement waveform

Figure 10 Double pulse testing diagram

17

Appendix B Requirements and Verifications Table 2 Requirements and Verifications

Requirement Verification Verified? Y/N

DC bus ripple is under 10% of 440V, the minimum operational voltage of the vehicle battery.

This measurement will be done at a lower current and the resulting data will be extrapolated to 62Arms operation. When the complete power stage is being tested, the inverter is operated at 15.5Arms, and the DC bus voltage is measured with the oscilloscope. The peak-to-peak voltage is measured and must stay within 11V.

No

Operating temperature does not exceed 105°C, the datasheet specified maximum operating temperature. This is 70K above the assumed case internal temp of 45°C.

While operating the complete power stage as described above at 1/4th of peak power, capacitor case temperature rise over ambient is monitored with an IR thermometer. The temperature rise in these conditions must not exceed 17.5 Kelvin.

Yes

Supply output regulation within 0.5V at operational voltage transients of up to 50V/ns to maintain a stable gate drive supply

During double pulse testing as described in Appendix A, the power supply rails of the high side FET are monitored with a differential oscilloscope probe to ensure they stay within the 0.5V requirement even during the fast voltage transitions when switching.

Yes

Switch node voltage overshoot is under 300V to stay within MOSFET operating limits

During double pulse tests as described in Appendix A, switch node voltage is measured with high bandwidth and overshoot voltage is measured. The layout inductance, capacitor inductance and gate resistor must all be tuned to ensure the switch node voltage stays under 300V with a 100 VDC input. This does not scale predictably to 600 VDC operation, so this step will have to be repeated when testing at 600V later.

Yes, See Section

3.1

Thermal resistance to the heatsink is under 0.7K/W

The module temperature is measured using its built-in sensor and the heatsink temperature is measured with an IR thermometer. The difference is used to compute the thermal resistance and compared with the maximum allowable value. Verification could not be done due to manufacturing delays. The pre-applied thermal compound is rated for 0.48 K / W.

Yes

Voltage measurement must have 10-bit accuracy at 600V (0.6V)

The power supply voltage is set to various values between 0 and 100V and the measured voltage is compared to a measurement taken with a multimeter

No

18

at no load so there are no resistive voltage drops in the measurement.

3.3V bus and 5V bus have at least 5% output regulation and less than 100mV ripple to ensure proper functioning of all components on the bus.

During full power stage operation (See Appendix A), both bus voltages are measured with a multimeter to measure output regulation and an oscilloscope in AC coupling mode to measure output ripple under load.

Yes

Communication protocol library is functional.

The control card is wired to the RM44 resolver and angle measurements at the necessary update rate are performed and verified to approximately match with the motor shaft angle. The accuracy of this measurement is not verified since the product is rated to meet a certain specification with no additional steps or verification.

No

Both CAN busses operate up to 1Mbaud stably

CAN bus output through the IC is connected to a laptop using a USB-to-CAN adapter (PCAN-USB) and bidirectional communication is verified with a loopback program and a CAN bus viewer software (PCAN-View).

No

All communication pins are correctly mapped in software.

Each pin group is tested while testing each peripheral (CAN, BiSS, PWM etc.). As a result, no independent testing is necessary.

Yes

19

Appendix C: Schematics and PCB Renders Schematics and PCBs were designed using Altium Designer.

Power Stage Schematics

Figure 13

Figure 14

Figure 15

Figure 16

20

Figure 17

Figure 18

21

Figure 19

Power Stage PCB Renders

Figure 20 Power Stage PCB Top

22

Figure 21 Power Stage PCB Bottom

Control Board Schematics

Figure 22

Figure 23

23

Figure 24

Figure 25

Figure 26

24

Figure 27

Figure 28

Figure 29

25

Figure 30

26

Figure 31

27

Control Board Renders

Figure 32 Control Board PCB Top

Figure 33 Control Board PCB Bottom