sid - ba chapter talk - schuessler -v1 chapter/pdf and images... · sid - ba chapter talk -...

© 2008 National Semiconductor Corporation. All Rights Reserved.

Display Interfacing Managing the transitions and looking to the future

Jim Schuessler 6-January-2008


2

2004: Wide complex parallel interconnects

•  Sony-Ericsson Z1010 – typical of many


3

Poor electrical environment

•  Yet, using LV-CMOS I/O, it works!


4

Hitting the wall

•  Large number of signals –  Large internal volume –  Lower MTBF –  High cost of chips, boards, cables and

connectors •  Increasing power consumption •  Increasing EMI •  Longer design and system integration time

•  High speed serial interconnects reduce these problems

•  and… they are not just for displays!


5

Explosion of solutions

• Then the dust starts to settle: –  Most of the GSM world coalesces

around MIPI and DSI –  The dominance of Qualcomm

establishes MDDI in the CDMA world


6

Transition: Use of translator devices

•  Early proprietary serial interface from National Semiconductor –  Mobile Pixel Link


7

More efficient use of pins

•  400Kbps to ~400Mbps: Three orders of magnitude speed increase •  3 pins to 4 pins: 25% increase in pins


8

Dark ages of 2004

Module 2 Module 1

Application Processor

Display 1

Display 2

Display 3

Memory Bus

(CPU)

RGB, VS, HS, DE always

usually one or the other

or SPI, I2C


9

Transition Phase

Module 2 Module 1


Display 1

Display 2

Display 3

DSI RGB

SPI

Hub

CPU

•  Using DSI –  5:1 ratio savings in signals –  Lower EMI –  Multiple Displays – One

Interface •  Using MDDI, additionally

–  Audio, KB, intelligent touch can be supported (mouse)

MDDI


10

Module 2

Options on the Frame Buffer

Module 1

Application Processor Display 1 DSI

•  Opinions on the optimal locations of frame buffers continue to spark lively debate…

MDDI

FB FB


11

Module 2

Options on the Frame Buffer (2)

Module 1

Application Processor Display 1 DSI RGB Hub,

LCDC

•  Cost, power consumption and supply chain are the primary motivators

MDDI

FB FB

CPU


12

Mature serial display architectures

•  Many permutations of bridges and hubs during the adoption period

Module 2 Module 1


Display 1

Display 2

Display 3

DSI

DSI

SPI

Hub

FB


13

UniPro with D-Phy carries heterogeneous data

•  En.wikipedia.org/wiki/Unipro

Module 2 Module 1


Camera 1 GPU UniPort-D

Camera 2

CSI-2

CSI-2

Display 1

Display 2 Display Conversion

DSI

DSI DSI


14

A fully serial data architecture

•  MIPI UniPro underlies Network on Terminal Architecture (NoTA)

Module 2 Module 1


Camera 1 GPU UniPort-M

Camera 2

CSI-3

CSI-3

Display 1

Display 2 Display Conversion

DSI-2

DSI-2 DSI-2

Smart Sub-system (2nd Host)

WLAN

USB-3

Storage Sub-system

UniPort-D

UniPort-D

UniPort-D

UniPort-M

UniPort Switch UniPort-M


15

Network on Terminal? Isn’t it all a single chip?

• Yes – low cost “single chip” mobile terminals will continue to add functionality

• and…

• No – rapid terminal evolution requires multi-chip architectures –  Parallel busses are no longer tractable from a cost

standpoint: all but the most highly integrated die are I/O ring or “pad limited” verses being “core limited” in previous generations

–  Serial display and camera interfaces are a precursor to all high bandwidth data interfaces going serial


Thank You

Let’s continue the discussion…

sid - ba chapter talk - schuessler -v1 chapter/pdf and images... · sid - ba chapter talk -...

Documents